SG1577SZ_技术文档

April 2008

SG1577

Dual Synchronous DC/DC Controller

Features

Description

The SG1577 is a high-efficiency, voltage-mode, dual-

channel, synchronous DC/DC PWM controller for two

independent outputs. The two channels are operated

out of phase. The internal reference voltage is trimmed

to 0.7V±1.5%. It is connected to the error amplifier’s

positive terminal for voltage feedback regulation. The

soft-start circuit ensures the output voltage can be

gradually and smoothly increased from zero to its final

regulated value. The soft-start pin can also be used for

chip-enable function. When two soft-start pins are

grounded, the chip is disabled and the total operation

current can be reduced to under 0.55mA. The fixed-

frequency is programmable from 60kHz to 320kHz. The

Over-Current Protection (OCP) level can be

programmed by an external current sense resistor. It

has two integrated sets of internal MOSFET drivers.

SG1577 is available in 20-pin SOP and DIP packages.

Integrated Two Sets of MOSFET Drivers

Two Independent PWM Controllers

Constant Frequency Operation: Free-running Fixed

Frequency Oscillator Programmable: 60kHz to

320kHz

Wide Range Input Supply Voltage: 8~15V

Programmable Output as Low as 0.7V

Internal Error Amplifier Reference Voltage:

0.7V±1.5%

Two Soft-Start / EN Functions

Programmable Over-Current Protection (OCP)

30V HIGH Voltage Pin for Bootstrap Voltage

Output Over-Voltage Protection (OVP)

SOP and DIP 20-pin

Applications

CPU and GPU Vcore Power Supply

Power Supply Requiring Two Independent Outputs

Ordering Information

Operating

Temperature Range

Part Number

Package

Packing Method

SG1577SZ

SG1577DZ

-40°C to +85°C

20-pin Small Outline Package (SOP)

20-pin Dual In-Line Package (DIP)

Tape & Reel

Tube

-40°C to +85°C

All packages are lead free per JEDEC: J-STD-020B standard.

SG1577 • Rev. 1.0.1

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Application Diagram

Figure 1.

Typical Application

Internal Block Diagram

Figure 2.

Functional Block Diagram

SG1577 • Rev. 1.0.1

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2

Pin Configuration

Figure 3. SOP-20 and DIP-20 Pin Configuration (Top View)

Pin Definitions

Name

Pin #

Type

Description

Switching frequency programming pin. An external resistor connecting from

this pin to GND can program the switching frequency. The switching

frequency would be 60kHz when RT is open and become 320kHz when a

30kΩ RT resistor is connected.

RT

1

Frequency Select

Inverting input of the error amplifier. It is normally connected to the

switching power supply output through a resistor divider.

IN1

2

3

4

5

Feedback

Output of the error amplifier and input to the PWM comparator. It is used

for feedback loop compensation.

COMP1

SS1/ENB

CLP1

Compensation

Soft Start/Enable

A 10µA internal current source charging an external capacitor for soft start.

Pull down this pin and pin 17 can disable the chip.

Over Current

Protection

Over-current protection for high-side MOSFET. Connect a resistor from this

pin to the high-side supply voltage to program the OCP level.

BST1

DH1

6

7

Boost Supply

Supply for high-side driver. Connect to the internal bootstrap circuit.

High-Side Drive Channel 1, high-side MOSFET gate driver pin.

Switch-node connection to inductor. For channel 1 high-side driver’s

reference ground.

Low-Side Drive Low-side MOSFET gate driver pin.

CLN1

8

Switch Node

DL1

PGND

VCC

DL2

9

10

11

12

Driver Ground

Power Supply

Driver circuit GND supply. Connect to low-side MOSFET GND.

Supply voltage input.

Low-Side Drive Low-side MOSFET gate driver pin.

Switch-node connection to inductor. For channel 2, high-side driver’s

reference ground.

High-Side Drive Channel 2 high-side MOSFET gate driver pin.

CLN2

13

Switch Node

DH2

14

15

BST2

Boost Supply

Supply for high-side driver. Connect to the internal bootstrap circuit.

Over-Current

Protection

Over-current protection for the high-side MOSFET. Connect a resistor from

this pin to the high-side supply voltage to program the OCP level.

CLP2

16

17

18

A 10µA internal current source charging an external capacitor for soft start.

Pull down this pin and pin 4 can disable the chip.

SS2/ENB

COMP2

Soft-Start/Enable

Compensation

Feedback

Output of the error amplifier and input to the PWM comparator. It is used

for feedback-loop compensation.

Inverting input of the error amplifier. It is normally connected to the

switching power supply output through a resistor divider.

IN2

19

20

GND

Control Ground Control circuit GND supply.

SG1577 • Rev. 1.0.1

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3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are

given with respect to the network ground terminal. Stresses beyond those listed under "absolute maximum ratings"

may cause permanent damage to the device.

Symbol

Parameter

Supply voltage, VCC to GND

Min.

Max.

Unit

V_CC

16

V

BST1(or 2) -

CLN1(or 2)

BST1(2) to CLN1(2)

16

18

V

CLN1(or 2) -

GND

CLN1(2) to GND for 100ns Transient

-4

DH1(or 2) -

CLN1(or 2)

16

V

CLN1(or 2),

DL1(or 2)

-0.3

V_CC+0.3

PGND

Θ_JA

PGND to GND

± 1

90

V

°C/W

°C

Thermal Resistance, Junction-Air

Operating Junction Temperature

Storage Temperature Range

T_J

-40

-65

+125

+150

2.5

T_STG

°C

Electrostatic

Discharge Protection

Level

Human Body Model (HBM)

Charged Device Model (CDM)

kV

ESD

750

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol

V_CC

Parameter

Min.

+8

Max.

+15

Unit

V

Supply voltage

Operating Ambient Temperature

-40

T_A

+85

°C

SG1577 • Rev. 1.0.1

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4

Electrical Characteristics

V_CC=12V, T_A=25°C, unless otherwise noted.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

Oscillator

R_RT=OPEN

54

288

-10

85

60

66

352

10

Oscillator Frequency

f_osc

KHz

R_RT=GND

320

20kΩ＜R^RT

Total Accuracy

f_osc,rt

%

90

95

Maximum Duty Cycle

DON_MAX

Error Amplifier

Internal Reference Voltage

V_CC=8V,V_CC=15V

V_REF

A_VOL

0.6895 0.7000 0.7105

V

dB

Open-loop Voltage Gain

Unity Gain Bandwidth

Power Supply Rejection Ratio

Output Source Current

Output Sink Current

77

3.5

50

BW

MHz

dB

PSRR

I_SOURCE

I_SINK

IN1=IN2=0.6V

IN1=IN2=0.8V

IN1=IN2=0.6V

IN1=IN2=0.8V

60

80

500

5

100

µA

Output Voltage

V_{H COMP}

V_{L COMP}

V

100

mV

Soft Start

I_SOURCE

V

_CLP＜V_CLN

_CLP＞V_CLN

Soft-start Charge Current

8

10

12

µA

V

Soft-start Discharge Current

I_SINK

Protections

I_OSCET

0.8

1.0

1.2

90

120

150

20

150

125

4.0

µA

°C

%

OC Sink Current

V_CC=12V

T_OT

Over-Temperature

T_{OT_HYS}

V_OVP

Over-Temperature Hysteresis

112

1.0

10

Over-Voltage Protection of IN V_OVP/V_IN

Output

I_DH

1.7

3.3

1.7

3.1

40

A

Ω

A

High-side Current Source

High-side Sink Resistor

Low-side Current Source

Low-side Sink Resistor

Dead Time⁽¹⁾

V_BST- V_CLN=12V,V_DH- V_CLN=6V

R_DH

I_DL

V_BST- V_CLN=12V

V_CC=12V,V_DL=6V

V_CC=12V

R_DL

4

Ω

ns

T_DT

70

V_CC=12V, D_H& D_L=1000pF

Total Operating Current

I_{CC_OP}

3.3

4.3

5.3

mA

Operating Supply Current

Standby Current (Disabled)

V_CC=12V, No load

I_{CC_SBY}

0.55

1.00

SS1/ENB=SS2/ENB=0V

Note:

1. When V^DLfalls less than 2V relative to VDH rising to 2V.

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SG1577 • Rev. 1.0.1

5

Typical Performance Characteristics

Unless otherwise noted, values are for V_CC=12V, T_A=+25°C, and according to Figure 1.

Figure 4. V5p0 Power On with 1.6A Load

Figure 6. V5p0 Power On with 15A Load

Figure 8. V5p0 Power Off with 15A Load

Figure 5. V3p3 Power On with 3A Load

Figure 7. V3p3 Power On with 8A Load

Figure 9. V3p3 Power Off with 8A Load

SG1577 • Rev. 1.0.1

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6

Typical Performance Characteristics (Continued)

Unless otherwise noted, values are for V_CC=12V, T_A=+25°C, and according to Figure 1.

Figure 10. 3p3 & V5p0 Phase Shift with Light Load

Figure 12. Dead Time with Light Load (Rise Edge)

Figure 14. Dead Time with Heavy Load (Rise Edge)

Figure 11. V3p3 & V5p0 Phase Shift with Heavy Load

Figure 13. Dead Time with Light Load (Fall Edge)

Figure 15. Dead Time with Heavy Load (Fall Edge)

SG1577 • Rev. 1.0.1

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7

Typical Performance Characteristics (Continued)

Unless otherwise noted, values are for V_CC=12V, T_A=+25°C, and according to Figure 1.

Figure 16. Load Transient Response (Step-Up)

Figure 17. Load Transient Response (Step-Down)

20kΩ/22nF in Compensation Loop

Figure 18. Over-Current Protection (OCP)

Figure 19. Over-Current Protection (Hiccup Mode)

150

Iocset 1

140

Iocset 2

130

120

110

100

90

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃

Temperature (oC)

Figure 20. Over-Voltage Protection (OVP)

Figure 21. I_OCSETvs. Temperature

SG1577 • Rev. 1.0.1

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8

Functional Description

The SG1577 is a dual-channel voltage-mode PWM

controller. It has two sets of synchronous MOSFET

driving circuits. The two channels are running 180-

degrees out of phase. The following descriptions

highlight the advantages of the SG1577 design.

Oscillator Operation

The SG1577 has a frequency-programmable oscillator.

The oscillator is running at 60kHz when the RT pin is

floating. The oscillator frequency can be adjusted from

60kHz up to 320kHz by an external resistor R^RT

between RT pin and the ground. The oscillator

generates a sawtooth wave that has 90% rising duty.

Sawtooth wave voltage threshold is from 1.2V to 2.8V.

The frequency of oscillator can be programmed by the

following equation:

Soft Start

An internal start-up current (10µA) flows out of SS/EN

pin to charge an external capacitor. During the start-up

sequence, SG1577 isn’t enabled until the SS/ENB pin is

higher than 1.2V. From 1.2V to (1.2 + 1.6 x D_ON

/

D_{ON_MAX}) V, PWM duty cycle gradually increases

(3)

f_OSC, RT(kHz) = 60kHz + 8522 / R_RT(kΩ)

following SS/ENB pin voltage to bring output rising.

After (1.2 + 1.6 x D_ON/ D_{ON_MAX}) V, the soft-start period

ends and SS/ENB pin continually goes up to 4.8V.

When input power is abnormal, the external capacitor

on SS pin is shorted to ground and the chip is disabled.

Output Driver

The high-side gate drivers need an external

bootstrapping circuit to provide the required boost

voltage. The highest gate driver’s output (15V is the

allowed) on high-side and low-side MOSFETs forces

external MOSFETs to have the lowest R_DS(ON), which

results in higher efficiency.

(1)

T_SOFTSTART= C_SS/ENBx 1.6 x D_ON/ D_{ON_MAX}/ I_SOURCE

Over-Current Protection (OCP)

Over-current protection is implemented by sensing the

voltage drop across the drain and the source of external

high-side MOSFET. Over-current protection is triggered

when the voltage drop on external high-side MOSFET’s

R^DS(ON)is greater than the programmable current limit

voltage threshold. 120µA flowing through an external

resistor between input voltage and the CLP pin sets the

threshold of current limit voltage. When over-current

condition is true, the system is protected against the

cycle-by-cycle current limit. A counter counts a series of

over-current peak values to eight cycles; the soft-start

capacitor is discharged by a 1µA current until the

voltage on SS pin reaches 1.2V. During the discharge

period, the high-side driver is turned off and the low-

side driver is turned on. Once the voltage on SS/ENB

pin is under 1.2V, the normal soft-start sequence is

initiated and the 10µA current charges the soft-start

capacitor again.

Over-Temperature Protection (OTP)

The device is over-temperature protected. When chip

temperature is over 150^oC, the chip enters tri-state

(high-side driver is turned off). The hysteresis is 20^oC.

Type II Compensation Design

(for Output Capacitors with High ESR)

SG1577 is a voltage-mode controller; the control loop is

a single voltage feedback path, including an error

amplifier and PWM comparator, as shown in Figure 22.

To achieve fast transient response and accurate output

regulation, an adequate compensator design is

necessary. A stable control loop has a 0dB gain

crossing with -20dB/decade slope and a phase margin

greater than 45°.

I_L(OCP)= [(R_SENSEx I_OCSET+ V_OFFSET) / R_DS(ON)

(V_IN- V_OUT) x V_OUT/ (f_OSCx L_OUTx V_INx 2) ]

-

(2)

where, VOFFSET (≒10mV) is the offset voltage

contributed by the internal OCP comparator.

Error Amplifier

The IN1 and IN2 pins are connected to the

corresponding internal error amplifier’s inverting input

and the outputs of the error amplifiers are connected to

the corresponding COMP1 and COMP2 pins. The

COMP1 and COMP2 pins are available for control-loop

compensation externally. Non-inverting inputs are

internally tied to a fixed 0.7V ± 1.5% reference voltage.

Figure 22. Closed Loop

SG1577 • Rev. 1.0.1

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9

1. Modulator Frequency Equations

f_P1= 0

f_Z1

The modulator transfer function is the small-signal

transfer function of V_OUT/V_E/A. This transfer function is

dominated by a DC gain and the output filter (L_Oand

C_O) with a double-pole frequency at f_LCand a zero at

FESR. The DC gain of the modulator is the input

voltage (V_IN) divided by the peak-to-peak oscillator

voltage V_RAMP(=1.6V). The first step is to calculate the

complex conjugate poles contributed by the LC output

filter. The output LC filter introduces a double pole,

-40dB / decade gain slope above its corner resonant

frequency, and a total phase lag of 180 degrees. The

resonant frequency of the LC filter expressed as:

1

=

2π × R₂× C₂

(6)

1

f_P2

=

2π × R₂× (C₁//C₂)

Figure 24 shows the DC-DC converter gain vs.

frequency. The compensation gain uses external

impedance networks Z_Cand Z_fto provide a stable, high-

bandwidth loop.

High crossover frequency is desirable for fast transient

response, but often jeopardizes the system stability. To

cancel one of the LC filter poles, place the zero before

the LC filter resonant frequency. Place the zero at 75%

of the LC filter resonant frequency. Crossover frequency

should be higher than the ESR zero, but less than 1/5

of the switching frequency. The second pole should be

placed at half the switching frequency.

(4)

1

f

=

P(LC)

2π ×

L × C

O O

The next step of compensation design is to calculate

the ESR zero. The ESR zero is contributed by the ESR

associated with the output capacitance. Note that this

requires that the output capacitor should have enough

ESR to satisfy stability requirements. The ESR zero of

the output capacitor is expressed as:

1

(5)

f

=

Z(ESR)

2π × C × ESR

O

2. Compensation Frequency Equations

The compensation network consists of the error

amplifier and the impedance networks Z_Cand Z_f, as

Figure 23 shows.

Figure 24. Bode Plot

Figure 23. Compensation Loop

SG1577 • Rev. 1.0.1

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10

Layout Considerations

Layout is important in high-frequency switching converter

design. If designed improperly, PCB can radiate

excessive noise and contribute to converter instability.

(resistor divider), and compensation components

(between INx and COMPx pins). Position those

components close to their pins with a local, clear

GND connection or directly to the ground plane.

Place the PWM power stage components first. Mount

all the power components and connections in the top

layer with wide copper areas. The MOSFETs of buck,

inductor, and output capacitor should be as close to

each other as possible to reduce the radiation of EMI

due to the high-frequency current loop. If the output

capacitors are placed in parallel to reduce the ESR of

capacitor, equal sharing ripple current should be

considered. Place the input capacitor near the drain of

high-side MOSFET. In multi-layer PCB, use one layer

as power ground and have a separate control signal

ground as the reference for all signals. To avoid the

signal ground being affected by noise and have best

load regulation, it should be connected to the ground

terminal of output.

7

8

Place the bootstrap capacitor near the BSTx and

CLNx pins.

The resistor on the RT pin should be near this pin

and the GND return should be short and kept away

from the noisy MOSFET’s GND (which is short

together with IC’s PGND pin to GND plane on back

side of PCB).

9

Place the compensation components close to the

INx and COMPx pins.

10 The feedback resistors for both regulators should

be located as close as possible to the relevant INx

pin with vias tied straight to the ground plane as

required.

Follow the below guidelines for best performance:

11 Minimize the length of the connections between the

input capacitors, CIN, and the power switchers

(MOSFETs) by placing them nearby.

1

2

A two-layer printed circuit board is recommended.

Use the bottom layer of the PCB as a ground plane

and make all critical component ground

connections through vias to this layer.

12 Position both the ceramic and bulk input capacitors

as close to the upper MOSFET drain as possible

and make the GND returns (from the source of

lower MOSFET to V_INcapacitor GND) short.

3

4

5

Keep the metal running from the CLNx terminal to

the output inductor short.

13 Position the output inductor and output capacitors

between the upper MOSFET and lower MOSFET

and the load.

Use copper-filled polygons on the top (and bottom,

if two-layer PCB) circuit layers for the CLN node.

The small-signal wiring traces from the DLx and

DHx pins to the MOSFET gates should be kept

short and wide enough to easily handle the several

amps of drive current.

14 AGND should be on the clearer plane and kept

away from the noisy MOSFET GND.

15 PGND should be short, together with MOSFET

GND, then through vias to GND plane on the

bottom of PCB.

6

The critical, small-signal components include any

bypass capacitors (SMD-type of capacitors applied

at VCC and SSx/ENB pins), feedback components

SG1577 • Rev. 1.0.1

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11

Physical Dimensions

E

H

Detail

A

F

A

c

1

10

b

e

D

θ

L

A2

y

A1

Detail

A

Figure 25. 20-Lead Small Outline Package (SOP)

Dimensions

Millimeter

Inch

Typ.

Symbol

Min.

Typ.

Max.

2.642

0.305

2.337

Min.

0.093

0.004

0.089

Max.

0.104

0.012

0.092

A

A1

A2

b

2.362

0.101

2.260

0.406

0.203

0.016

0.008

c

D

E

12.598

7.391

12.903

7.595

0.496

0.291

0.508

0.299

e

1.270

0.050

H

L

10.007

0.406

10.643

1.270

0.394

0.016

0.419

0.050

F

0.508X45°

0.020X45°

y

0.101

0.004

θ°

0°

8°

0°

8°

SG1577 • Rev. 1.0.1

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12

Physical Dimensions (Continued)

θ

D

11

10

20

B

E1

e

E

1

A2

A

L

e

b1

A1

b

Figure 26. 20-Lead Dual In-line Package (DIP)

Dimensions

Millimeter

Inch

Typ.

Symbol

Min.

Typ.

Max.

Min.

Max.

A

A1

A2

b

5.334

0.210

0.381

3.175

0.015

0.125

3.302

1.524

0.457

26.162

7.620

6.350

2.540

3.302

9.017

7°

3.429

0.130

0.060

0.018

1.030

0.300

0.250

0.100

0.130

0.355

7°

0.135

b1

D

24.892

6.223

26.924

6.477

0.980

0.245

1.060

0.255

E

E1

e

L

2.921

8.509

0°

3.810

9.525

15°

0.115

0.335

0°

0.150

0.375

15°

e_B

θ°

SG1577 • Rev. 1.0.1

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13

SG1577 • Rev. 1.0.1

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14


型号：	SG1577SZ
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Dual Synchronous DC/DC Controller 双同步DC / DC控制器控制器
文件：	总14页 (文件大小：648K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SG1577SZ [FAIRCHILD]

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