SG1577SY_12 [FAIRCHILD]
Dual Synchronous DC/DC Controller; 双同步DC / DC控制器
| 型号： | SG1577SY_12 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual Synchronous DC/DC Controller |
| 文件： | 总14页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2012
SG1577
Dual Synchronous DC/DC Controller
Features
Description
The SG1577 is a high-efficiency, voltage-mode, dual-
channel, synchronous DC/DC PWM controller for two
independent outputs. The two channels are operated
out of phase. The internal reference voltage is trimmed
to 0.7 V ±1.5%. It is connected to the error amplifier’s
positive terminal for voltage feedback regulation. The
soft-start circuit ensures the output voltage can be
gradually and smoothly increased from zero to its final
regulated value. The soft-start pin can also be used for
chip-enable function. When two soft-start pins are
grounded, the chip is disabled and the total operation
current can be reduced to under 0.55 mA. The fixed-
frequency is programmable from 60 kHz to 320 kHz.
The Over-Current Protection (OCP) level can be
programmed by an external current sense resistor. It
has two integrated sets of internal MOSFET drivers.
SG1577 is available in the 20-pin SOP package.
.
.
.
Integrated Two Sets of MOSFET Drivers
Two Independent PWM Controllers
Constant Frequency Operation: Free-running Fixed
Frequency Oscillator Programmable: 60 kHz to
320 kHz
.
.
.
Wide Range Input Supply Voltage: 8~15 V
Programmable Output as Low as 0.7 V
Internal Error Amplifier Reference Voltage:
0.7 V ±1.5%
.
.
.
.
.
Two Soft-Start / EN Functions
Programmable Over-Current Protection (OCP)
30 V HIGH Voltage Pin for Bootstrap Voltage
Output Over-Voltage Protection (OVP)
SOP 20-Pin
Applications
.
.
CPU and GPU Vcore Power Supply
Power Supply Requiring Two Independent Outputs
Ordering Information
Operating
Temperature Range
Packing
Part Number
Package
Method
SG1577SY
-40°C to +85°C
20-Lead, Small Outline Package (SOP-20)
Tape & Reel
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
2
Marking Diagram
F: Fairchild Logo
Z: Plant Code
X: 1-Digit Year Code for SOP
Y: 1-Digit Week Code for SOP
TT: 2-Digit Die Run Code
T: Package Type (S = SOP)
P: Z=Lead Free + ROHS
Compatible
F ZXYTT
SG1577
TPM
Y=Green Package
M: Manufacture Flow Code
Figure 3. Top Mark
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
3
Pin Configuration
Figure 4. SOP-20 Pin Configuration (Top View)
Pin Definitions
Name
Pin #
Type
Description
Switching frequency programming pin. An external resistor connecting from
this pin to GND can program the switching frequency. The switching
frequency would be 60 kHz when RT is open and become 320 kHz when a
30 kΩ RT resistor is connected.
RT
1
Frequency Select
Inverting input of the error amplifier. It is normally connected to the
switching power supply output through a resistor divider.
IN1
2
3
4
5
Feedback
Output of the error amplifier and input to the PWM comparator. It is used
for feedback loop compensation.
COMP1
SS1/ENB
CLP1
Compensation
Soft Start/Enable
A 10 µA internal current source charging an external capacitor for soft start.
Pull down this pin and pin 17 can disable the chip.
Over Current
Protection
Over-current protection for high-side MOSFET. Connect a resistor from this
pin to the high-side supply voltage to program the OCP level.
BST1
DH1
6
7
Boost Supply
Supply for high-side driver. Connect to the internal bootstrap circuit.
High-Side Drive Channel 1, high-side MOSFET gate driver pin.
Switch-node connection to inductor. For channel 1 high-side driver’s
reference ground.
CLN1
8
Switch Node
DL1
PGND
VCC
DL2
9
Low-Side Drive
Driver Ground
Power Supply
Low-Side Drive
Low-side MOSFET gate driver pin.
Driver circuit GND supply. Connect to low-side MOSFET GND.
Supply voltage input.
10
11
12
Low-side MOSFET gate driver pin.
Switch-node connection to inductor. For channel 2, high-side driver’s
reference ground.
CLN2
13
Switch Node
DH2
14
15
High-Side Drive Channel 2 high-side MOSFET gate driver pin.
BST2
Boost Supply
Supply for high-side driver. Connect to the internal bootstrap circuit.
Over-Current
Protection
Over-current protection for the high-side MOSFET. Connect a resistor from
this pin to the high-side supply voltage to program the OCP level.
CLP2
16
17
18
A 10 µA internal current source charging an external capacitor for soft start.
Pull down this pin and pin 4 can disable the chip.
SS2/ENB
COMP2
Soft-Start/Enable
Compensation
Output of the error amplifier and input to the PWM comparator. It is used
for feedback-loop compensation.
Inverting input of the error amplifier. It is normally connected to the
switching power supply output through a resistor divider.
IN2
19
20
Feedback
GND
Control Ground
Control circuit GND supply.
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with
respect to the network ground terminal. Stresses beyond those listed under "absolute maximum ratings" may cause
permanent damage to the device.
Symbol
Parameter
Min.
Max.
16
Unit
V
VCC
Supply Voltage, VCC to GND
BST1(or 2) - CLN1(or 2) BST1(2) to CLN1(2)
16
V
CLN1(or 2) -GND
CLN1(2) to GND for 100 ns Transient
-4
18
V
BST1(or 2) - GND
BST1(2) to GND for 100 ns Transient
30
V
DH1(or 2) - CLN1(or 2)
16
V
CLN1(or 2), DL1(or 2)
-0.3
VCC+0.3
±1
V
PGND
ΘJA
PGND to GND
V
Thermal Resistance, Junction-to-Air
Operating Junction Temperature
Storage Temperature Range
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
90
°C/W
°C
°C
kV
V
TJ
-40
-65
+125
+150
2.5
TSTG
ESD
750
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
Parameter
Min.
+8
Max.
+15
Unit
V
Supply Voltage
-40
TA
Operating Ambient Temperature
+85
°C
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
5
Electrical Characteristics
VCC=12 V, TA =25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Oscillator
R
RT=OPEN
54
288
-10
85
60
66
352
10
Oscillator Frequency
fosc
KHz
RRT=GND
320
20 kΩ＜RRT
Total Accuracy
fosc,rt
%
%
90
95
Maximum Duty Cycle
DON_MAX
Error Amplifier
Internal Reference Voltage
VCC=8 V, VCC=15 V
TA=0~85°C
VREF
△VREF
AVOL
0.6895
0.7000
0.03
77
0.7105
V
mV/°C
dB
Temperature Coefficient(1)
Open-Loop Voltage Gain
Unity Gain Bandwidth
BW
3.5
MHz
dB
Power Supply Rejection Ratio
Output Source Current
Output Sink Current
PSRR
ISOURCE
ISINK
50
IN1=IN2=0.6 V
IN1=IN2=0.8 V
IN1=IN2=0.6 V
IN1=IN2=0.8 V
60
80
100
µA
500
µA
Output Voltage
Output Voltage
VH COMP
VL COMP
5
V
100
mV
Soft Start
ISOURCE
V
CLP＜VCLN
CLP＞VCLN
Soft-Start Charge Current
8
10
12
µA
µA
V
Soft-Start Discharge Current
ISINK
Protections
IOSCET
0.8
1.0
1.2
90
120
150
20
150
125
µA
°C
°C
%
OC Sink Current
VCC=12 V
TOT
Over-Temperature
TOT_hys
VOVP
Over-Temperature Hysteresis
Over-Voltage Protection of IN
112
1.0
VOVP/VIN
Output
VBST - VCLN=12 V,VDH
-
High-Side Current Source
IDH
1.7
A
VCLN=6 V
RDH
IDL
3.3
1.7
3.1
40
4.0
Ω
A
High-Side Sink Resistor
Low-Side Current Source
Low-Side Sink Resistor
Dead Time(2)
VBST - VCLN=12 V
VCC=12 V,VDL=6 V
VCC=12 V
1.0
10
RDL
tDT
4
Ω
70
ns
VCC=12 V, DH and DL=1000 pF
Total Operating Current
ICC_OP
3.3
4.3
5.3
mA
mA
Operating Supply Current
Standby Current (Disabled)
VCC=12 V, No Load
ICC_SBY
0.55
1.00
SS1/ENB=SS2/ENB=0 V
Notes:
1. Not test in production, 30 pcs sample.
2. When VDL falls less than 2 V relative to VDH rising to 2 V.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
SG1577 • Rev. 1.0.6
6
Typical Performance Characteristics
Unless otherwise noted, values are for VCC=12 V, TA=+25°C, and according to Figure 1.
Figure 5. V5p0 Power On with 1.6 A Load
Figure 7. V5p0 Power On with 15 A Load
Figure 9. V5p0 Power Off with 15 A Load
Figure 6. V3p3 Power On with 3 A Load
Figure 8. V3p3 Power On with 8 A Load
Figure 10. V3p3 Power Off with 8 A Load
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
Unless otherwise noted, values are for VCC=12 V, TA=+25°C, and according to Figure 1.
Figure 11. 3p3 and V5p0 Phase Shift with Light Load
Figure 12. V3p3 and V5p0 Phase Shift
with Heavy Load
Figure 13. Dead Time with Light Load (Rise Edge)
Figure 14. Dead Time with Light Load (Fall Edge)
Figure 15. Dead Time with Heavy Load (Rise Edge)
Figure 16. Dead Time with Heavy Load (Fall Edge)
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
Unless otherwise noted, values are for VCC=12 V, TA=+25°C, and according to Figure 1.
Figure 17. Load Transient Response (Step-Up)
Figure 18. Load Transient Response (Step-Down)
20k Ω/22 nF in Compensation Loop
20 kΩ/22 nF in Compensation Loop
Figure 19. Over-Current Protection (OCP)
Figure 20. Over-Current Protection (Hiccup Mode)
150
Iocset 1
140
Iocset 2
130
120
110
100
90
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃
Temperature (oC)
Figure 21. Over-Voltage Protection (OVP)
Figure 22. IOCSET vs. Temperature
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
9
Functional Description
The SG1577 is a dual-channel voltage-mode PWM
controller. It has two sets of synchronous MOSFET
driving circuits. The two channels are running 180-
degrees out of phase. The following descriptions
highlight the advantages of the SG1577 design.
Prevent CLN Noise in SG1577
To prevent noise/spike on CLN from affecting OCP
judgment, SG1577 internal has a 500 ns blanking time
to filter out this noise/spike on CLN at each turn-on
cycle and counts for eight cycles of CLP>CLN, then
OCP is asserted.
Soft-Start
An internal startup current (10 µA) flows out of SS/EN
pin to charge an external capacitor. During the startup
sequence, SG1577 isn’t enabled until the SS/ENB pin is
VOFFSET of OCP Comparator
240
220
200
180
160
140
120
100
80
higher than 1.2 V. From 1.2 V to (1.2 + 1.6 x DON
/
DON_MAX V, PWM duty cycle gradually increases
)
following SS/ENB pin voltage to bring output rising. After
(1.2 + 1.6 x DON / DON_MAX) V, the soft-start period ends
and SS/ENB pin continually goes up to 4.8 V. When
input power is abnormal, the external capacitor on SS
pin is shorted to ground and the chip is disabled.
60
40
20
0
TSOFTSTART = CSS/ENB x 1.6 x DON / DON_MAX / ISOURCE
(1)
4
6
8
10
12
14
16
VCC (V)
Figure 23. VOFFSET1/2 vs. VCC
Over-Current Protection (OCP)
Over-current protection is implemented by sensing the
voltage drop across the drain and the source of
external high-side MOSFET. Over-current protection is
triggered when the voltage drop on external high-side
MOSFET’s RDS(ON) is greater than the programmable
current limit voltage threshold. 120 µA flowing through
an external resistor between input voltage and the CLP
pin sets the threshold of current limit voltage. When
over-current condition is true, the system is protected
against the cycle-by-cycle current limit. A counter
counts a series of over-current peak values to eight
cycles; the soft-start capacitor is discharged by a 1 µA
current until the voltage on SS pin reaches 1.2 V.
During the discharge period, the high-side driver is
turned off and the low-side driver is turned on. Once
the voltage on SS/ENB pin is under 1.2 V, the normal
soft-start sequence is initiated and the 10 µA current
charges the soft-start capacitor again.
Error Amplifier
The IN1 and IN2 pins are connected to the
corresponding internal error amplifier’s inverting input
and the outputs of the error amplifiers are connected to
the corresponding COMP1 and COMP2 pins. The
COMP1 and COMP2 pins are available for control-loop
compensation externally. Non-inverting inputs are
internally tied to a fixed 0.7 V ±1.5% reference voltage.
Oscillator Operation
The SG1577 has a frequency-programmable oscillator.
The oscillator is running at 60 kHz when the RT pin is
floating. The oscillator frequency can be adjusted from
60 kHz up to 320 kHz by an external resistor RRT
between RT pin and the ground. The oscillator
generates a sawtooth wave that has 90% rising duty.
Sawtooth wave voltage threshold is from 1.2 V to 2.8 V.
The frequency of oscillator can be programmed by the
following equation:
IL(OCP)= [(RSENSE x IOCSET + VOFFSET) / RDS(ON)
(VIN - VOUT) x VOUT / (fOSC x LOUT x VIN x 2) ]
-
(2)
where, VOFFSET (=10 mV) is the offset voltage
contributed by the internal OCP comparator.
fOSC, RT(kHz) = 60kHz + 8522 / RRT(kΩ)
(3)
Design Notes
Output Driver
VCC noise/spike affects the offset voltage of the OCP
comparator Figure 23 shows the VOFFSET1/2 vs. VCC
variation curve, which is a simulation result by IC
internal circuitry. Calculate the OCP variation between
The high-side gate drivers need an external
bootstrapping circuit to provide the required boost
voltage. The highest gate driver’s output (15 V is the
allowed) on high-side and low-side MOSFETs forces
external MOSFETs to have the lowest RDS(ON), which
results in higher efficiency.
VCC=12 V and VCC=4 V. For Ch1 or Ch2, VOFFSET
/
RDS(ON) = 172 mV / 9 mΩ = 19 A is affected. VCC>10 V is
the recommended range; lower, and the comparator’s
offset voltage is large.
Over-Temperature Protection (OTP)
The device is over-temperature protected. When chip
temperature is over 150°C, the chip enters tri-state
(high-side driver is turned off). The hysteresis is 20°C.
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
10
Type II Compensation Design
(for Output Capacitors with High ESR)
2. Compensation Frequency Equations
The compensation network consists of the error
amplifier and the impedance networks ZC and Zf, as
Figure 24 shows.
SG1577 is a voltage-mode controller; the control loop is
a single voltage feedback path, including an error
amplifier and PWM comparator, as shown in Figure 24.
To achieve fast transient response and accurate output
regulation, an adequate compensator design is
necessary. A stable control loop has a 0 dB gain
crossing with -20 dB/decade slope and a phase margin
greater than 45°.
Figure 25. Compensation Loop
fP1 = 0
1
fZ1
=
(6)
2π × R2 × C2
1
fP2
=
2π × R2 × (C1 //C2)
Figure 24. Closed Loop
Figure 26 shows the DC-DC converter gain vs.
frequency. The compensation gain uses external
impedance networks ZC and Zf to provide a stable,
high-bandwidth loop.
1. Modulator Frequency Equations
The modulator transfer function is the small-signal
transfer function of VOUT/VE/A. This transfer function is
dominated by a DC gain and the output filter (LO and CO)
with a double-pole frequency at fLC and a zero at FESR.
The DC gain of the modulator is the input voltage (VIN)
divided by the peak-to-peak oscillator voltage
High crossover frequency is desirable for fast transient
response, but often jeopardizes the system stability. To
cancel one of the LC filter poles, place the zero before
the LC filter resonant frequency. Place the zero at 75%
of the LC filter resonant frequency. Crossover frequency
should be higher than the ESR zero, but less than 1/5 of
the switching frequency. The second pole should be
placed at half the switching frequency.
V
RAMP(=1.6 V). The first step is to calculate the complex
conjugate poles contributed by the LC output filter. The
output LC filter introduces double pole,
a
-40 dB / decade gain slope above its corner resonant
frequency, and a total phase lag of 180°. The resonant
frequency of the LC filter expressed as:
1
f
=
P(LC)
(4)
2π ×
L × C
O O
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough
ESR to satisfy stability requirements. The ESR zero of
the output capacitor is expressed as:
1
fZ(ESR)
=
(5)
2π × CO × ESR
Figure 26. Bode Plot
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
11
Layout Considerations
Layout is important in high-frequency switching converter
design. If designed improperly, PCB can radiate
excessive noise and contribute to converter instability.
components close to their pins with a local, clear
GND connection or directly to the ground plane.
7
8
Place the bootstrap capacitor near the BSTx and
CLNx pins.
Place the PWM power stage components first. Mount all
the power components and connections in the top layer
with wide copper areas. The MOSFETs of buck,
inductor, and output capacitor should be as close to
each other as possible to reduce the radiation of EMI
due to the high-frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
capacitor, equal sharing ripple current should be
considered. Place the input capacitor near the drain of
high-side MOSFET. In multi-layer PCB, use one layer as
power ground and have a separate control signal ground
as the reference for all signals. To avoid the signal
ground being affected by noise and have best load
regulation, it should be connected to the ground terminal
of output.
The resistor on the RT pin should be near this pin
and the GND return should be short and kept away
from the noisy MOSFET’s GND (which is short
together with IC’s PGND pin to GND plane on back
side of PCB).
9
Place the compensation components close to the
INx and COMPx pins.
10 The feedback resistors for both regulators should
be located as close as possible to the relevant INx
pin with vias tied straight to the ground plane as
required.
11 Minimize the length of the connections between the
input capacitors, CIN, and the power switchers
(MOSFETs) by placing them nearby.
Follow the below guidelines for best performance:
1
2
A two-layer printed circuit board is recommended.
12 Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible
and make the GND returns (from the source of
lower MOSFET to VIN capacitor GND) short.
Use the bottom layer of the PCB as a ground plane
and make all critical component ground connections
through vias to this layer.
3
4
5
Keep the metal running from the CLNx terminal to
the output inductor short.
13 Position the output inductor and output capacitors
between the upper MOSFET and lower MOSFET
and the load.
Use copper-filled polygons on the top (and bottom,
if two-layer PCB) circuit layers for the CLN node.
14 AGND should be on the clearer plane and kept
away from the noisy MOSFET GND.
The small-signal wiring traces from the DLx and
DHx pins to the MOSFET gates should be kept
short and wide enough to easily handle the several
amps of drive current.
15 PGND should be short, together with MOSFET
GND, then through vias to GND plane on the
bottom of PCB.
6
The critical, small-signal components include any
bypass capacitors (SMD-type of capacitors applied
at VCC and SSx/ENB pins), feedback components
(resistor divider), and compensation components
(between INx and COMPx pins). Position those
16 Prevent spike happen on CLN pin a proper snubber
circuit for CLN and GND is recommend.
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
12
Physical Dimensions
12.80±0.20
11.430
A
11.930
11.430
20
11
B
7.50±0.10
10.325
10.922
8.422
1
PIN ONE
INDICATOR
10
1.27
C B A
0.50 TYP
0.51
1.25 TYP
0.35
1.27 TYP
M
0.25
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.20±0.10
SEATING PLANE
PIN#1 IDENTIFICATION OPTIONS
20
0.75
0.25
X 45°
20
20
(R0.10)
(R0.10)
GAGE PLANE
0.25
8°
0°
SEATING PLANE
0.40~1.27
(1.40)
PIN #1
INDICATOR
DETAIL A
SCALE: 2:1
PIN #1
INDICATOR
PIN #1
INDICATOR
1
1
1
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC MS-013.
OPTION 2
OPTION 1
OPTION 3
PIN 1 ONLY
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
HALF MOON & PIN 1
HALF MOON ONLY
D) LANDPATTERN RECOMMENDATION IS FSC DESIGN
E) FILENAME AND REVISION: M20BREV4
Figure 27. 20-Lead, Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
13
© 2009 Fairchild Semiconductor Corporation
SG1577 • Rev. 1.0.6
www.fairchildsemi.com
14
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