SCAN1837TSSC [FAIRCHILD]
Transparent Latch with 3-STATE Outputs; 透明锁存器带3态输出
| 型号： | SCAN1837TSSC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Transparent Latch with 3-STATE Outputs |
| 文件： | 总12页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1991
Revised May 2000
SCAN18373T
Transparent Latch with 3-STATE Outputs
General Description
Features
The SCAN18373T is a high speed, low-power transparent
latch featuring separate data inputs organized into dual 9-
bit bytes with byte-oriented latch enable and output enable
control signals. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architec-
ture with the incorporation of the defined boundary-scan
test logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).
■ IEEE 1149.1 (JTAG) Compliant
■ Buffered active-low latch enable
■ 3-STATE outputs for bus-oriented applications
■ 9-bit data busses for parity applications
■ Reduced-swing outputs source 32 mA/sink 64 mA
■ Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
■ TTL compatible inputs
■ 25 mil pitch SSOP (Shrink Small Outline Package)
■ Includes CLAMP and HIGHZ instructions
■ Member of Fairchild’s SCAN Products
Ordering Code:
Order Number Package Number
Package Description
SCAN1837TSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
AI(0–8), BI(0–8)
ALE, BLE
Description
Data Inputs
Latch Enable Inputs
AOE1, BOE1
AO(0–8), BO(0–8)
3-STATE Output Enable Inputs
3-STATE Latch Outputs
Truth Tables
Inputs
AOE1
AO(0–8)
AI(0–8)
ALE
X
H
L
L
L
X
L
Z
L
H
H
H
X
H
L
AO0
Inputs
BO(0–8)
BOE1
BI(0–8)
BLE
X
H
L
L
L
X
L
Z
L
H
H
H
X
H
L
BO0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
AO0 = Previous AO before H-to-L transition of ALE
BO0 = Previous BO before H-to-L transition of BLE
© 2000 Fairchild Semiconductor Corporation
DS010962
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Functional Description
The SCAN18373T consists of two sets of nine D-type
latches with 3-STATE standard outputs. When the Latch
Enable (ALE or BLE) input is HIGH, data on the inputs
(AI(0–8) or BI(0–8)) enters the latches. In this condition the
the inputs a set-up time preceding the HIGH-to-LOW tran-
sition of the Latch Enable. The 3-STATE standard outputs
are controlled by the Output Enable (AOE1 or BOE1) input.
When Output Enable is LOW, the standard outputs are in
the 2-state mode. When Output Enable is HIGH, the stan-
dard outputs are in the high impedance mode, but this
does not interfere with entering new data into the latches.
latches are transparent, i.e., a latch output will change
state each time its input changes. When Latch Enable is
LOW, the latches store the information that was present on
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Block Diagrams
Byte-A
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2
Block Diagrams (Continued)
Tap Controller
Byte-B
Note: BSR stands for Boundary Scan Register.
3
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Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data.
to the SCAN18373T device. SCAN CMOS Test Access
Logic devices do not include the IEEE 1149.1 optional
identification register. Therefore, this unique captured
value can be used as a “pseudo ID” code to confirm that
the correct device is placed in the appropriate location in
the boundary scan chain.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti-
vate their respective outputs by loading a logic high.
Instruction Register Scan Chain Definition
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition Logic 0
MSB → LSB
Instruction Code
00000000
Instruction
EXTEST
10000001
10000010
00000011
All Others
SAMPLE/PRELOAD
CLAMP
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
HIGHZ
BYPASS
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
Scan Cell TYPE1
Scan Cell TYPE2
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4
Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register
Scan Chain Definition (42 Bits in Length)
5
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Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register Definition Index
Bit No.
Pin Name
41 AOE1
Pin No.
Pin Type
Scan Cell Type
TYPE1
3
Input
Input
40 ACP
39 AOE
38 BOE1
37 BCP
36 BOE
35 AI0
34 AI1
33 AI2
32 AI3
31 AI4
30 AI5
29 AI6
28 AI7
27 AI8
26 BI0
25 BI1
24 BI2
23 BI3
22 BI4
21 BI5
20 BI6
19 BI7
18 BI8
17 AO0
16 AO1
15 AO2
14 AO3
13 AO4
12 AO5
11 AO6
10 AO7
9 AO8
8 BO0
7 BO1
6 BO2
5 BO3
4 BO4
3 BO5
2 BO6
1 BO7
0 BO8
54
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
Internal
Input
Control
Signals
26
31
Input
Internal
Input
55
53
52
50
49
47
46
44
43
42
41
39
38
36
35
33
32
30
2
Input
Input
Input
Input
A–in
Input
Input
Input
Input
Input
Input
Input
Input
Input
B–in
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
4
5
7
8
A–out
10
11
13
14
15
16
18
19
21
22
24
25
27
B–out
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6
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
SCAN Products
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
VIN from 0.8V to 2.0V
−40°C to +85°C
125 mV/ns
O = VCC +0.5V
DC Output Voltage (VO)
−0.5V to VCC + 0.5V
±70 mA
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
Per Output Pin
V
CC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of SCAN circuits outside databook specifications.
±70 mA
Junction Temperature
SSOP
+140°C
−65°C to +150°C
2000V
Storage Temperature
ESD (Min)
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
V
Conditions
VOUT = 0.1V
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
1.5
1.5
1.5
Guaranteed Limits
Minimum HIGH
2.0
2.0
2.0
0.8
0.8
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
(Note 2)
2.0
0.8
0.8
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
VIL
V
VOH
3.15
4.15
2.4
3.15
4.15
2.4
V
IOUT = −50 µA
V
IN = VIL or VIH
OH = −32 mA
VIN = VIL or VIH
V
2.4
2.4
I
2.4
V
2.4
I
OH = −24 mA
VOL
Maximum LOW
Output Voltage
(Note 2)
0.1
0.1
0.1
V
I
OUT = 50 µA
0.1
0.55
0.55
0.55
0.55
0.55
0.55
V
IN = VIL or VIH
OL = 64 mA
IN = VIL or VIH
OL = 48 mA
V
I
V
V
I
IIN
Maximum Input
Leakage Current
Maximum Input
Leakage
5.5
5.5
±0.1
±1.0
µA
VI = VCC, GND
IIN
2.8
−385
−160
94
3.6
−385
−160
94
µA
µA
VI = VCC
VI = GND
VI = GND
TDI, TMS
Minimum Input Leakage
Minimum Dynamic
Output Current (Note 3)
Maximum Output
Leakage Current
Output Short
5.5
5.5
µA
IOLD
IOHD
IOZ
mA
mA
VOLD = 0.8V Max
−40
−40
VOHD = 2.0V Min
5.5
±0.5
±5.0
µA
VI (OE) = VIL, VIH
IOS
mA
Min
µA
5.5
5.5
−100
−100
VO = 0V
Circuit Current
ICC
Maximum Quiescent
Supply Current
16.0
88
VO = Open
TDI, TMS = VCC
VO = Open
5.5
750
820
µA
TDI, TMS = GND
7
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DC Electrical Characteristics (Continued)
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
ICCt
Parameter
Units
Conditions
(V)
Typ
Guaranteed Limits
Maximum ICC per Input
5.5
2.0
2.0
mA
VI = VCC − 2.1V
VI = VCC − 2.1V
TDI/TMS Pin,
5.5
2.15
2.15
mA
Test One with the
Other Floating
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Noise Specifications
VCC
T
A = +25°C
T
A = −40°C to +85°C
Symbol
VOLP
Parameter
Units
(V)
Typ
Guaranteed Limits
Maximum HIGH Output Noise
(Note 4)(Note 5)
5.0
1.0
1.5
V
V
V
V
V
V
VOLV
VOHP
VOHV
VIHD
VILD
Minimum LOW Output Noise
(Note 4)(Note 5)
5.0
5.0
5.0
5.5
5.5
−0.6
−1.2
OH + 1.5
OH − 1.8
2.0
Maximum Overshoot
V
OH + 1.0
OH − 1.0
1.6
V
(Note 5)(Note 6)
Minimum VCC Droop
V
V
(Note 5)(Note 6)
Minimum HIGH Dynamic Input Voltage Level
(Note 6)(Note 7)
2.0
0.8
Maximum LOW Dynamic Input Voltage Level
(Note 6)(Note 7)
1.4
0.8
Note 4: Maximum number of outputs that can switch simultaneously is n. (n−1) outputs are switched LOW and one output held LOW.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n−1) outputs are switched HIGH and one output held HIGH.
Note 6: Worst case package.
Note 7: Maximum number of data inputs (n) switching. (n−1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD).
AC Electrical Characteristics
Normal Operation
VCC
T
A= +25°C
T
A= −40°C to +85°C
L = 50 pF
Max
Symbol
Parameter
C
L = 50 pF
C
Units
(V)
(Note 8)
5.0
Min
2.5
2.5
2.5
2.5
1.5
1.5
2.0
2.0
Typ
Max
9.0
Min
tPLH
,
,
Propagation
Delay, D to Q
Propagation
Delay, LE to Q
Disable Time
2.5
2.5
2.5
2.5
1.5
1.5
2.0
2.0
9.8
9.8
ns
ns
ns
ns
tPHL
tPLH
tPHL
9.0
5.0
5.0
5.0
10.0
10.5
9.0
10.5
11.3
9.5
tPLZ
tPHZ
tPZL
tPZH
,
9.5
10.0
11.9
9.7
,
Enable Time
10.9
9.0
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
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8
AC Operating Requirements
Normal Operation
VCC
T
A = +25°C
L = 50 pF
Guaranteed Minimum
T
A = −40°C to +85°C
Symbol
Parameter
C
CL = 50 pF
Units
(V)
(Note 9)
tS
Setup Time, H or L
Data to LE
5.0
3.0
3.0
ns
tH
Hold Time, H or L
LE to Data
5.0
5.0
1.5
5.0
1.5
5.0
ns
ns
tW
LE Pulse Width
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Electrical Characteristics
Scan Test Operation
VCC
TA= +25°C
T
A = −40°C to +85°C
Symbol
Parameter
C
L = 50 pF
C
L = 50 pF
Units
(V)
(Note 10)
5.0
Min
3.5
3.5
2.5
2.5
3.0
3.0
5.0
5.0
Typ
Max
13.2
13.2
11.5
11.5
14.5
14.5
18.0
18.0
Min Max
tPLH
tPHL
tPLZ
tPHZ
tPZL
tPZH
tPLH
tPHL
,
Propagation Delay
3.5
3.5
2.5
2.5
3.0
3.0
5.0
5.0
14.5
14.5
11.9
11.9
15.8
15.8
19.8
19.8
ns
ns
ns
TCK to TDO
,
Disable Time
5.0
5.0
TCK to TDO
,
Enable Time
TCK to TDO
,
Propagation Delay
TCK to Data Out
during Update-DR State
Propagation Delay
TCK to Data Out
during Update-IR State
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
5.0
5.0
ns
ns
ns
tPLH
,
5.0
5.0
18.6
18.6
5.0
5.0
20.2
20.2
tPHL
tPLH
,
5.5
5.5
19.9
19.9
5.5
5.5
21.5
21.5
tPHL
5.0
tPLZ
,
Propagation Delay
TCK to Data Out
during Update-DR State
Propagation Delay
TCK to Data Out
during Update-IR State
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
4.0
4.0
16.4
16.4
4.0
4.0
18.2
18.2
tPHZ
5.0
5.0
5.0
ns
ns
ns
tPLZ
,
5.0
5.0
19.5
19.5
5.0
5.0
20.8
20.8
tPHZ
tPLZ
,
5.0
5.0
19.9
19.9
5.0
5.0
21.5
21.5
tPHZ
tPZL
,
Propagation Delay
TCK to Data Out
during Update-DR State
Propagation Delay
TCK to Data Out
during Update-IR State
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
5.0
5.0
18.9
18.9
5.0
5.0
20.9
20.9
tPZH
5.0
5.0
5.0
ns
ns
ns
tPZL
,
6.5
6.5
22.4
22.4
6.5
6.5
24.2
24.2
tPZH
tPZL
,
7.0
7.0
23.8
23.8
7.0
7.0
25.7
25.7
tPZH
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V.
Note: All propagation delays involving TCK are measured from the falling edge of TCK.
9
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AC Operating Requirements
Scan Test Operation
VCC
T
A = +25°C
L = 50 pF
Guaranteed Minimum
T
A = −40°C to +85°C
Symbol
Parameter
C
C
L = 50 pF
Units
(V)
(Note 11)
tS
Setup Time,
5.0
5.0
5.0
5.0
3.0
3.0
4.5
3.0
4.5
ns
ns
ns
ns
Data to TCK (Note 12)
Hold Time,
tH
tS
tH
tS
4.5
3.0
4.5
TCK to Data (Note 12)
Setup Time, H or L
AOE1, BOE1 to TCK (Note 13)
Hold Time, H or L
TCK to AOE1, BOE1 (Note 13)
Setup Time, H or L
Internal AOE, BOE,
to TCK (Note 14)
Hold Time, H or L
TCK to Internal
5.0
5.0
3.0
3.0
3.0
3.0
ns
ns
tH
AOE, BOE (Note 14)
Setup Time
tS
tH
tS
tH
tS
tH
tW
5.0
5.0
5.0
5.0
5.0
3.0
3.5
8.0
2.0
4.0
4.5
3.0
3.5
8.0
2.0
4.0
4.5
ns
ns
ns
ns
ns
ns
ALE, BLE (Note 15) to TCK
Hold Time
TCK to ALE, BLE (Note 15)
Setup Time, H or L
TMS to TCK
Hold Time, H or L
TCK to TMS
Setup Time, H or L
TDI to TCK
Hold Time, H or L
TCK to TDI
5.0
5.0
Pulse Width TCK
H
L
15.0
5.0
15.0
5.0
ns
fMAX
Maximum TCK
5.0
25
25
MHz
Clock Frequency
Tpu
Tdn
Wait Time, Power Up to TCK
Power Down Delay
5.0
0.0
100
100
100
100
ns
ms
Note 11: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 12: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35.
Note 13: Timing pertains to BSR 38 and 41 only.
Note 14: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 15: Timing pertains to BSR 37 and 40 only.
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
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Extended AC Electrical Characteristics
T
A = 25°C
VCC = 5.0V
L = 50 pF
C
T
A = −40°C to +85°C
CC = 5.0V ± 0.5V
L = 250 pF
(Note 17)
Min
Symbol
Parameter
Units
V
18 Outputs
C
Switching
(Note 16)
Typ
Min
3.0
3.0
3.0
3.0
2.5
2.5
2.0
2.0
Max
12.0
12.8
11.5
11.5
10.5
12.5
10.5
10.5
Max
13.5
16.0
13.0
14.5
tPLH
Propagation Delay
4.0
4.0
4.0
4.0
ns
ns
ns
ns
ns
ns
tPHL
Latch Enable to Output
Propagation Delay
Data to Output
tPLH
tPHL
tPZH
Output Enable Time
(Note 18)
tPZL
tPHZ
Output Disable Time
(Note 19)
tPLZ
tOSHL
(Note 20)
tOSLH
(Note 20)
Pin to Pin Skew
HL Data to Output
Pin to Pin Skew
LH Data to Output
0.5
0.5
1.0
1.0
1.0
1.0
Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 17: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 18: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 19: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 20: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH.
Capacitance
Symbol
CIN
Parameter
Input Pin Capacitance
Typ
4.0
Units
pF
Conditions
VCC = 5.0V
VCC = 5.0V
VCC = 5.0V
COUT
CPD
Output Pin Capacitance
13.0
34.0
pF
Power Dissipation Capacitance
pF
11
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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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12
相关型号：
SCAN18540TFMQB
Boundary Scan Bus Driver, SCAN/JTAG/3J Series, 2-Func, 9-Bit, Inverted Output, CMOS, CDFP56, 0.025 INCH PITCH, CERAMIC, FP-56
FAIRCHILD
SCAN18540TMDA
IC SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN DRIVER, INVERTED OUTPUT, UUC56, DIE, Bus Driver/Transceiver
NSC
SCAN18540TSSCX_NL
Boundary Scan Bus Driver, SCAN/JTAG/3J Series, 2-Func, 9-Bit, Inverted Output, CMOS, PDSO56, 0.300 INCH, 0.025 INCH PITCH, SSOP-56
FAIRCHILD
SCAN18541TFM
SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, CDFP56, 0.635 MM PITCH, CERPACK-56
TI
SCAN18541TFMQB
SERIALLY CONTROLLED ACCESS NETWORK NON-INVERTING LINE DRIVER WITH TRI-STATE OUTPUTS
NSC
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