SCAN18540TSSCX [FAIRCHILD]
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| 型号： | SCAN18540TSSCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 驱动器 |
| 文件： | 总11页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1991
Revised May 2000
SCAN18540T
Inverting Line Driver with 3-STATE Outputs
General Description
Features
The SCAN18540T is a high speed, low-power line driver
featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented paired output enable control sig-
nals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture with the
incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), and Test Clock
(TCK).
■ IEEE 1149.1 (JTAG) compliant
■ Dual output enable signals per byte
■ 3-STATE outputs for bus-oriented applications
■ 9-bit data busses for parity applications
■ Reduced-swing outputs source 32 mA/sink 64 mA
■ Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
■ TTL compatible inputs
■ 25 mil pitch SSOP (Shrink Small Outline Package)
■ Includes CLAMP and HIGHZ instructions
■ Member of Fairchild’s SCAN products
Ordering Code:
Order Number Package Number
Package Description
SCAN18540TSSC
MS54A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Connection Diagram
Pin Descriptions
Pin Names
AI(0–8)
BI(0–8)
Description
Input pins, A side
Input pins, B side
AOE1, AOE2 3-STATE Output Enable Input pins, A side
BOE1, BOE2 3-STATE Output Enable Input pins, B side
AO(0–8)
BO(0–8)
Output pins, A side
Output pins, B side
Truth Tables
Inputs
AO(0–8)
AOE1
AOE2
AI(0–8)
L
H
X
L
L
X
H
L
H
X
X
L
L
Z
Z
H
Inputs
BO(0–8)
BOE1
BOE2
BI(0–8)
L
H
X
L
L
X
H
L
H
X
X
L
L
Z
Z
H
H = HIGH Voltage Level X = Immaterial
L = LOW Voltage Level Z = High Impedance
© 2000 Fairchild Semiconductor Corporation
DS010964
www.fairchildsemi.com
Block Diagrams
Byte-A
Tap Controller
Byte-B
Note: BSR stands for Boundary Scan Register
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2
Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data.
Std 1149.1. The upper six bits are unique to the
SCAN18540T device. SCAN CMOS Test Access Logic
devices do not include the IEEE 1149.1 optional identifica-
tion register. Therefore, this unique captured value can be
used as a “pseudo ID” code to confirm that the correct
device is placed in the appropriate location in the boundary
scan chain.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti-
vate their respective outputs by loading a logic high.
Instruction Register Scan Chain Definition
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
MSB→LSB
Bypass Register Scan Chain Definition
Logic 0
Instruction Code
00000000
Instruction
EXTEST
10000001
SAMPLE/PRELOAD
CLAMP
10000010
The INSTRUCTION register is an 8-bit register which cap-
tures the default value of 01001101. The two least signifi-
cant bits of this captured value (01) are required by IEEE
00000011
HIGH-Z
All Others
BYPASS
Scan Cell TYPE1
Scan Cell TYPE2
3
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BOUNDARY-SCAN Register
Scan Chain Definition (42 Bits in Length)
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4
BOUNDARY-SCAN Register Definition Index
Bit No.
Pin Name
Pin No.
Pin Type
Scan Cell Type
TYPE1
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
AOE1
AOE2
AOE
BOE1
BOE2
BOE
AI0
3
Input
Input
54
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
Internal
Input
Control
Signals
26
31
Input
Internal
Input
55
53
52
50
49
47
46
44
43
42
41
39
38
36
35
33
32
30
2
AI1
Input
AI2
Input
AI3
Input
AI4
Input
A–in
AI5
Input
AI6
Input
AI7
Input
AI8
Input
BI0
Input
BI1
Input
BI2
Input
BI3
Input
BI4
Input
B–in
BI5
Input
BI6
Input
BI7
Input
BI8
Input
AO0
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
BO0
BO1
BO2
BO3
BO4
BO5
BO6
BO7
BO8
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
4
5
7
8
A–out
10
11
13
14
15
16
18
19
21
22
24
25
27
8
7
6
5
4
B–in
3
2
1
0
5
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
SCAN Products
4.5V to 5.5V
0V to VCC
VI = VCC +0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
VIN from 0.8V to 2.0V
−40°C to +85°C
125 mV/ns
O = VCC +0.5V
DC Output Voltage (VO)
−0.5V to VCC +0.5V
±70 mA
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
Per Output Pin
V
CC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of SCAN circuits outside databook specifications.
±70 mA
Junction Temperature
SSOP
+140°C
−65°C to +150°C
2000V
Storage Temperature
ESD (Min)
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
V
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
1.5
1.5
1.5
Guaranteed Limits
Minimum HIGH
2.0
2.0
2.0
0.8
0.8
V
OUT = 0.1V
or VCC −0.1V
OUT = 0.1V
or VCC −0.1V
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
(Note 2)
2.0
0.8
0.8
VIL
V
V
VOH
3.15
4.15
2.4
3.15
4.15
2.4
V
IOUT = −50 µA
V
IN = VIL or VIH
OH = −32 mA
VIN = VIL or VIH
V
2.4
2.4
I
2.4
V
2.4
I
OH = −24 mA
VOL
Maximum LOW
Output Voltage
(Note 2)
0.1
0.1
0.1
V
I
OUT = 50 µA
0.1
0.55
0.55
0.55
0.55
0.55
0.55
V
IN = VIL or VIH
OL = 64 mA
IN = VIL or VIH
OL = 48 mA
V
I
V
V
I
IIN
Maximum Input
Leakage Current
Maximum Input
Leakage
5.5
5.5
±0.1
±1.0
µA
VI = VCC, GND
IIN
2.8
3.6
µA
µA
VI = VCC
TDI, TMS
−385
−385
VI = GND
Minimum Input
Leakage
5.5
5.5
−160
−160
µA
VI = GND
IOLD
IOHD
IOZ
Minimum Dynamic
Output Current (Note 3)
Maximum Output
Leakage Current
Output Short
94
94
mA
mA
V
OLD = 0.8V Max
OHD = 2.0V Min
−40
−40
V
5.5
5.5
5.5
5.5
±0.5
−100
16.0
750
±5.0
−100
88
µA
mA Min
µA
VI (OE) = VIL, VIH
IOS
VO = 0V
Circuit Current
Maximum Quiescent
Supply Current
ICC
VO = Open
TDI, TMS = VCC
O = Open
TDI, TMS = GND
V
820
µA
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6
DC Electrical Characteristics (Continued)
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
ICCt
Parameter
Units
Conditions
VI = VCC–2.1V
(V)
Typ
Guaranteed Limits
Maximum ICC Per Input
5.5
2.0
2.0
mA
VI = VCC–2.1V
TDI/TMS Pin, Test
One with the
5.5
2.15
2.15
mA
other Floating
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Noise Specifications
VCC
(V)
T
A = +25°C
T
A = −40°C to +85°C
Symbol
VOLP
Parameter
Maximum HIGH Output Noise
Units
Typ
Guaranteed Limits
5.0
5.0
5.0
5.0
5.5
5.5
1.0
1.5
V
V
V
V
V
V
(Note 4)(Note 5)
VOLV
VOHP
VOHV
Minimum LOW Output Noise
(Note 4)(Note 5)
−0.6
OH+1.0
OH−1.0
1.6
−1.2
OH+1.5
OH−1.8
2.0
Maximum Overshoot
V
V
V
V
(Note 5)(Note 6)
Minimum VCC Droop
(Note 6)(Note 5)
Minimum HIGH Dynamic Input Voltage Level
(Note 6)(Note 7)
2.0
0.8
VIHD
VILD
Maximum LOW Dynamic Input Voltage Level
(Note 6)(Note 7)
1.4
0.8
Note 4: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH.
Note 6: Worst case package.
Note 7: Maximum number of data inputs (n) switching. (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD).
AC Electrical Characteristics
Normal Operation:
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
Symbol
Parameter
C
L = 50 pF
C
Units
(V)
(Note 8)
5.0
Min
2.5
2.5
1.5
1.5
2.0
2.0
Typ
Max
9.0
Min
tPLH
tPHL
tPLZ
tPHZ
tPZL
tPZH
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
,
Propagation Delay
2.5
2.5
1.5
1.5
2.0
2.0
9.8
9.8
ns
ns
ns
Data to Q
9.0
,
Disable Time
5.0
5.0
10.2
10.2
11.8
9.5
10.7
10.7
12.8
10.5
,
Enable Time
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
7
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AC Electrical Characteristics
Scan Test Operation:
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
Symbol
Parameter
C
L = 50 pF
C
Units
(V)
(Note 9)
5.0
Min
3.5
3.5
2.5
2.5
3.0
3.0
Typ
Max
13.2
13.2
11.5
11.5
14.5
14.5
Min
tPLH
tPHL
tPLZ
tPHZ
tPZL
tPZH
tPLH
tPHL
,
Propagation Delay
3.5
3.5
2.5
2.5
3.0
3.0
14.5
14.5
11.9
11.9
15.8
15.8
ns
ns
ns
TCK to TDO
,
Disable Time
5.0
5.0
TCK to TDO
,
Enable Time
TCK to TDO
,
Propagation Delay
TCK to Data Out
During Update-
-DR State
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
18.0
18.0
5.0
5.0
19.8
19.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPLH
,
,
Propagation Delay
TCK to Data Out
During Update-
IR State
tPHL
5.0
5.0
18.6
18.6
5.0
5.0
20.2
20.2
tPLH
tPHL
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.5
5.5
19.9
19.9
5.5
5.5
21.5
21.5
tPLZ
,
Propagation Delay
TCK to Data Out
During Update-
DR State
tPHZ
4.0
4.0
16.4
16.4
4.0
4.0
18.2
18.2
tPLZ
,
Propagation Delay
TCK to Data Out
During Update-
IR State
tPHZ
5.0
5.0
19.5
19.5
5.0
5.0
20.8
20.8
tPLZ
,
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
tPHZ
5.0
5.0
19.9
19.9
5.0
5.0
21.5
21.5
tPZL
,
Propagation Delay
TCK to Data Out
During Update-
DR State
tPZH
5.0
5.0
18.9
18.9
5.0
5.0
20.9
20.9
5.0
5.0
tPZL
,
Propagation Delay
TCK to Data Out
During Update-
IR State
tPZH
6.5
6.5
22.4
22.4
6.5
6.5
24.2
24.2
tPZL
,
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
tPZH
5.0
7.0
7.0
23.8
23.8
7.0
7.0
25.7
25.7
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
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8
AC Operating Requirements
Scan Test Operation:
VCC
T
A = +25°C
L = 50 pF
Guaranteed Minimum
T
A = −40°C to +85°C
Symbol
Parameter
C
CL = 50 pF
Units
(V)
(Note 10)
tS
Setup Time, H or L
Data to TCK (Note 11)
Hold Time, H or L
TCK to Data (Note 11)
Setup Time, H or L
AOEn, BOEn
5.0
5.0
3.0
3.0
4.5
ns
ns
tH
4.5
3.0
tS
5.0
5.0
5.0
5.0
3.0
4.5
3.0
3.0
ns
ns
ns
ns
to TCK (Note 12)
Hold Time, H or L
TCK to AOEn,
tH
tS
tH
4.5
3.0
3.0
BOEn (Note 12)
Setup Time, H or L
Internal AOE, BOE,
to TCK (Note 13)
Hold Time, H or L
TCK to Internal
AOE, BOE (Note 13)
Setup Time, H or L
TMS to TCK
tS
tH
tS
tH
tW
5.0
5.0
5.0
8.0
2.0
4.0
4.5
8.0
2.0
4.0
4.5
ns
ns
ns
ns
Hold Time, H or L
TCK to TMS
Setup Time, H or L
TDI to TCK
Hold Time, H or L
TCK to TDI
5.0
5.0
Pulse Width TCK
H
L
15.0
5.0
15.0
5.0
ns
fMAX
TPU
TDN
Maximum TCK
Clock Frequency
Wait Time,
5.0
25
25
MHz
5.0
0.0
100
100
100
100
ns
Power Up to TCK
Power Down Delay
ms
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 11: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26, and 27-35.
Note 12: Timing pertains to BSR 37, 38, 40 and 41.
Note 13: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
9
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Extended AC Electrical Characteristics
T
A = 25°C
CC = 5.0V
L = 50 pF
V
C
T
A = −40°C to +85°C
CC = 5.0V ± 0.5V
L = 250 pF
(Note 15)
Min
Symbol
Parameter
Units
V
18 Outputs
C
Switching
(Note 14)
Typ
Min
3.0
3.0
2.5
2.5
2.0
2.0
Max
11.0
11.0
11.5
14.0
11.5
11.5
Max
13.0
15.0
tPLH
tPHL
,
Propagation Delay
Data to Output
4.0
4.0
ns
ns
ns
ns
ns
tPZH
tPZL
tPHZ
tPLZ
,
,
Output Enable Time
(Note 16)
Output Disable Time
(Note 17)
tOSHL
Pin to Pin Skew
HL Data to Output
Pin to Pin Skew
LH Data to Output
0.5
0.5
1.0
1.0
1.0
1.0
(Note 18)
tOSLH
(Note 18)
Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW etc.).
Note 15: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 16: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 17: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 18: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination LOW-to-HIGH and/or HIGH-to-LOW.
Capacitance
Symbol
CIN
Parameter
Input Pin Capacitance
Typ
4.0
Units
pF
Conditions
VCC = 5.0V
VCC = 5.0V
VCC = 5.0V
COUT
CPD
Output Pin Capacitance
13.0
34.0
pF
Power Dissipation Capacitance
pF
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10
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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