SCAN18540T [NSC]
Inverting Line Driver with TRI-STATE Outputs; 与三态输出反相线路驱动器
| 型号： | SCAN18540T |
| 厂家： | 
National Semiconductor |
| 描述： | Inverting Line Driver with TRI-STATE Outputs |
| 文件： | 总14页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1998
SCAN18540T
Inverting Line Driver with TRI-STATE® Outputs
General Description
Features
n IEEE 1149.1 (JTAG) compliant
n Dual output enable signals per byte
The SCAN18540T is a high speed, low-power line driver fea-
turing separate data inputs organized into dual 9-bit bytes
with byte-oriented paired output enable control signals. This
device is compliant with IEEE 1149.1 Standard Test Access
Port and Boundary Scan Architecture with the incorporation
of the defined boundary-scan test logic and test access port
consisting of Test Data Input (TDI), Test Data Out (TDO),
Test Mode Select (TMS), and Test Clock (TCK).
n TRI-STATE outputs for bus-oriented applications
n 9-bit data busses for parity applications
n Reduced-swing outputs source 24 mA/sink 48 mA (Mil)
n Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
n TTL compatible inputs
n 25 mil pitch Cerpack packaging
n Includes CLAMP and HIGHZ instructions
n Standard Microcircuit Drawing (SMD) 5962-9312701
Connection Diagram
Pin Names
Description
AOE1, AOE2
TRI-STATE Output Enable Input pins,
A side
BOE1, BOE2
TRI-STATE Output Enable Input pins,
B side
AO(0–8)
BO(0–8)
Output pins, A side
Output pins, B side
DS100323-1
Pin Names
AI(0–8)
BI(0–8)
Description
Input pins, A side
Input pins, B side
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100323
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Truth Tables
Inputs
AOE2
AO (0–8)
AOE1
AI (0–8)
L
H
X
L
L
X
H
L
H
X
X
L
L
Z
Z
H
Inputs
BO (0–8)
BOE1
BOE2
BI (0–8)
L
H
X
L
L
X
H
L
H
X
X
L
L
Z
Z
H
=
=
=
=
H
X
L
HIGH Voltage Level
Immaterial
LOW Voltage Level
High Impedance
Z
Block Diagrams
Byte-A
DS100323-2
Tap Controller
DS100323-3
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2
Block Diagrams (Continued)
Byte-B
DS100323-4
Note: BSR stands for Boundary Scan Register
3
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Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location.
Scan cell TYPE1 is intended to solely observe system data,
while TYPE2 has the additional ability to control system
data. (See IEEE Standard 1149.1 Figure 10–11 for a further
description of scan cell TYPE1 and Figure 10–12 for a fur-
ther description of scan cell TYPE2.)
clude the IEEE 1149.1 optional identification register. There-
fore, this unique captured value can be used as a “pseudo
ID” code to confirm that the correct device is placed in the
appropriate location in the boundary scan chain.
Instruction Register Scan Chain Definition
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as well
as at each of the two internal active-high output enable sig-
nals. AOE controls the activity of the A-outputs while BOE
controls the activity of the B-outputs. Each will activate their
respective outputs by loading a logic high.
DS100323-10
→
MSB LSB
The BYPASS register is a single bit shift register stage iden-
tical to scan cell TYPE1. It captures a fixed logic low.
Instruction Code
Instruction
EXTEST
00000000
10000001
10000010
00000011
All Others
Bypass Register Scan Chain Definition
Logic 0
SAMPLE/PRELOAD
CLAMP
HIGH-Z
BYPASS
DS100323-9
The INSTRUCTION register is an 8-bit register which cap-
tures the default value of 01001101. The two least significant
bits of this captured value (01) are required by IEEE Std
1149.1. The upper six bits are unique to the SCAN18540T
device. SCAN CMOS Test Access Logic devices do not in-
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4
Description of BOUNDARY-SCAN Circuitry (Continued)
Scan Cell TYPE1
DS100323-7
Scan Cell TYPE2
DS100323-8
5
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Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register
Scan Chain Definition (42 Bits in Length)
DS100323-23
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6
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index
Bit No.
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Pin Name
AOE1
AOE2
AOE
BOE1
BOE2
BOE
AI0
Pin No.
Pin Type
Input
Scan Cell Type
TYPE1
3
54
Input
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
Internal
Input
Control
Signals
26
31
Input
Internal
Input
55
53
52
50
49
47
46
44
43
42
41
39
38
36
35
33
32
30
2
AI1
Input
AI2
Input
AI3
Input
AI4
Input
A–in
AI5
Input
AI6
Input
AI7
Input
AI8
Input
BI0
Input
BI1
Input
BI2
Input
BI3
Input
BI4
Input
B–in
BI5
Input
BI6
Input
BI7
Input
BI8
Input
AO0
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
BO0
BO1
BO2
BO3
BO4
BO5
BO6
BO7
BO8
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
4
5
7
8
A–out
10
11
13
14
15
16
18
19
21
22
24
25
27
8
7
6
5
4
B–in
3
2
1
0
7
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Absolute Maximum Ratings (Note 1)
ESD (Min)
2000V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
Supply Voltage (VCC
)
DC Input Diode Current (IIK
)
SCAN Products
4.5V to 5.5V
0V to VCC
0V to VCC
=
VI −0.5V
−20 mA
+20 mA
Input Voltage (VI)
=
VI VCC +0.5V
DC Output Diode Current (IOK
Output Voltage (VO
)
)
Operating Temperature (TA)
Military
=
VO −0.5V
−20 mA
+20 mA
−55˚C to +125˚C
125 mV/ns
=
VO VCC +0.5V
Minimum Input Edge Rate dV/dt
VIN from 0.8V to 2.0V
DC Output Voltage (VO
)
−0.5V to VCC +0.5V
±
DC Output Source/Sink Current (IO
DC VCC or Ground Current
Per Output Pin
)
70 mA
@
VCC 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of SCAN circuits outside databook specifications.
±
70 mA
Junction Temperature
Cerpack
+175˚C
Storage Temperature
−65˚C to +150˚C
DC Electrical Characteristics
Symbol
Parameter
VCC
Military
Units
Conditions
(V)
=
TA −55˚C to +125˚C
Guaranteed Limits
=
VIH
VIL
Minimum High
Input Voltage
Maximum Low
Input Voltage
Minimum High
Output Voltage
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
2.0
2.0
V
V
V
V
V
VOUT 0.1V
or VCC −0.1V
=
0.8
VOUT 0.1V
0.8
or VCC −0.1V
=
IOUT −50 µA
VOH
3.15
4.15
2.4
=
VIN VIL or VIH
=
IOH −24 mA
2.4
=
IOUT 50 µA
VOL
Maximum Low
Output Voltage
0.1
0.1
=
VIN VIL or VIH
0.55
0.55
=
IOL 48 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum Input
Leakage
1.0
µA
VI VCC, GND
=
VI VCC
IIN
5.5
5.5
5.5
3.7
µA
µA
µA
=
VI GND
TDI,
TMS
−385
−160
=
VI GND
Minimum Input
Leakage
=
VOLD 0.8V Max
IOLD
IOHD
Minimum Dynamic
63
mA
mA
=
Output Current
(Note 2)
−27
VOHD 2.0V Min
=
±
IOZ
IOS
ICC
Maximum Output
Leakage Current
Output Short
5.5
5.5
5.5
5.5
10.0
−100
168
µA
VI (OE) VIL, VIH
=
VO 0V
mA Min
µA
Circuit Current
=
VO Open
Maximum Quiescent
Supply Current
=
TDI, TMS VCC
=
VO Open
930
µA
=
TDI, TMS GND
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8
DC Electrical Characteristics (Continued)
Symbol
Parameter
VCC
(V)
Military
Units
Conditions
=
TA −55˚C to +125˚C
Guaranteed Limits
2.0
=
VI VCC–2.1V
ICCt
Maximum ICC Per
Input
5.5
5.5
mA
mA
=
VI VCC–2.1V
2.15
TDI/TMS Pin, Test
One with the
other Floating
Note 2: Maximum test duration 2.0 ms, one output loaded at a time.
Note 3: All outputs loaded; thresholds associated with output under test.
Noise Specifications
Symbol
Parameter
VCC
(V)
Military
Units
=
TA −55˚C to +125˚C
Guaranteed Limits
0.8
VOLP
Maximum High
Output Noise
(Notes 4, 5)
5.0
5.0
V
V
VOLV
Minimum Low
Output Noise
(Notes 4, 5)
-0.8
Note 4: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH.
AC Electrical Characteristics
Normal Operation
Symbol
Parameter
VCC
(V)
(Note 7)
Military
Units
=
TA −55˚C
to +125˚C
=
CL 50 pF
Min
2.5
2.5
1.5
1.5
2.0
2.0
Max
10.5
11.0
11.2
11.2
14.0
12.0
tPLH
tPHL
tPLZ
tPHZ
tPZL
tPZH
,
Propagation Delay
Data to Q
5.0
5.0
5.0
ns
ns
ns
,
Disable Time
,
Enable Time
AC Electrical Characteristics
Scan Test Operation
Symbol
Parameter
VCC
(V)
(Note 7)
Military
Units
=
TA −55˚C to
+125˚C
=
CL 50 pF
Min
3.5
3.5
2.5
2.5
Max
15.8
15.8
12.8
12.8
tPLH
tPHL
tPLZ
tPHZ
,
Propagation Delay
TCK to TDO
5.0
5.0
ns
ns
,
Disable Time
TCK to TDO
9
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AC Electrical Characteristics (Continued)
Scan Test Operation
Symbol
Parameter
VCC
(V)
(Note 7)
Military
Units
=
TA −55˚C to
+125˚C
=
CL 50 pF
Min
3.0
3.0
Max
16.7
16.7
tPZL
tPZH
tPLH
tPHL
,
Enable Time
5.0
5.0
ns
ns
TCK to TDO
,
Propagation Delay
TCK to Data Out
During Update-
-DR State
5.0
5.0
21.7
21.7
tPLH
,
,
Propagation Delay
TCK to Data Out
During Update-
IR State
tPHL
5.0
5.0
5.0
5.0
5.0
5.0
5.0
21.2
21.2
ns
ns
ns
ns
ns
ns
ns
ns
tPLH
tPHL
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.5
5.5
23.0
23.0
tPLZ
,
Propagation Delay
TCK to Data Out
During Update-
DR State
tPHZ
4.0
4.0
19.6
19.6
tPLZ
,
Propagation Delay
TCK to Data Out
During Update-
IR State
tPHZ
5.0
5.0
22.4
22.4
tPLZ
,
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
tPHZ
5.0
5.0
23.3
23.3
tPZL
,
Propagation Delay
TCK to Data Out
During Update-
DR State
tPZH
5.0
5.0
22.6
22.6
5.0
5.0
tPZL
,
Propagation Delay
TCK to Data Out
During Update-
IR State
tPZH
6.5
6.5
26.2
26.2
tPZL
,
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
tPZH
5.0
7.0
7.0
27.4
27.4
Note 6: All Propagation Delays involving TCK are measured from the falling edge of TCK.
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10
AC Operating Requirements
Scan Test Operation
Symbol
Parameter
VCC
(V)
(Note 7)
Military
TA −55˚C to +125˚C
Units
=
=
CL 50 pF
Guaranteed Minimum
tS
tH
tS
Setup Time, H or L
Data to TCK (Note 8)
Hold Time, H or L
TCK to Data (Note 8)
Setup Time, H or L
AOEn, BOEn
5.0
5.0
3.0
ns
ns
5.5
3.0
4.5
3.0
5.0
5.0
5.0
ns
ns
ns
to TCK (Note 10)
Hold Time, H or L
TCK to AOEn,
tH
tS
tH
BOEn (Note 10)
Setup Time, H or L
Internal AOE, BOE,
to TCK (Note 9)
Hold Time, H or L
TCK to Internal
5.0
5.0
5.0
5.0
5.0
5.0
3.0
8.0
2.0
4.0
4.5
ns
ns
ns
ns
ns
AOE, BOE (Note 9)
Setup Time, H or L
TMS to TCK
tS
tH
tS
tH
tW
Hold Time, H or L
TCK to TMS
Setup Time, H or L
TDI to TCK
Hold Time, H or L
TCK to TDI
Pulse Width TCK
H
12.0
5.0
25
ns
MHz
ns
L
fmax
TPU
TDN
Maximum TCK
Clock Frequency
Wait Time,
5.0
5.0
0.0
100
100
Power Up to TCK
Power Down Delay
ms
±
Note 7: Voltage Range 5.0 is 5.0V 0.5V.
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 8: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26, and 27-35.
Note 9: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 10: Timing pertains to BSR 37, 38, 40 and 41.
11
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Capacitance
Symbol
CIN
Parameter
Input Pin Capacitance
Output Pin Capacitance
Power Dissipation
Capacitance
Typ
4.0
Units
pF
Conditions
=
VCC 5.0V
=
VCC 5.0V
COUT
CPD
13.0
34.0
pF
=
VCC 5.0V
pF
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12
13
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Ceramic Flatpak (F)
NS Package Number WA56A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Corporation
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Tel: 1-800-272-9959
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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