FDI3632 [FAIRCHILD]
N-Channel PowerTrench MOSFET 100V, 80A, 9mз; N沟道PowerTrench MOSFET的100V ， 80A ， 9mз
| 型号： | FDI3632 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | N-Channel PowerTrench MOSFET 100V, 80A, 9mз |
| 文件： | 总11页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2003
FDB3632 / FDP3632 / FDI3632
N-Channel PowerTrench® MOSFET
100V, 80A, 9mΩ
Features
Applications
•
•
•
•
•
•
rDS(ON) = 7.5mΩ (Typ.), VGS = 10V, ID = 80A
Qg(tot) = 84nC (Typ.), VGS = 10V
Low Miller Charge
•
•
•
•
•
•
•
DC/DC converters and Off-Line UPS
Distributed Power Architectures and VRMs
Primary Switch for 24V and 48V Systems
High Voltage Synchronous Rectifier
Direct Injection / Diesel Injection Systems
42V Automotive Load Control
Low QRR Body Diode
UIS Capability (Single Pulse and Repetitive Pulse)
Qualified to AEC Q101
Formerly developmental type 82784
Electronic Valve Train Systems
D
DRAIN
(FLANGE)
SOURCE
DRAIN
(FLANGE)
DRAIN
SOURCE
DRAIN
GATE
GATE
GATE
G
SOURCE
TO-220AB
FDP SERIES
DRAIN
(FLANGE)
TO-262AB
FDI SERIES
TO-263AB
FDB SERIES
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
VGS
Parameter
Ratings
100
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
V
V
±20
Continuous (TC < 111oC, VGS = 10V)
Continuous (Tamb = 25oC, VGS = 10V, RθJA = 43oC/W)
Pulsed
80
12
A
A
ID
Figure 4
393
A
EAS
Single Pulse Avalanche Energy (Note 1)
Power dissipation
Derate above 25oC
mJ
W
W/oC
oC
310
PD
2.07
TJ, TSTG
Operating and Storage Temperature
-55 to 175
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-220, TO-263, TO-262
Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2)
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
0.48
62
oC/W
oC/W
oC/W
43
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
Package Marking and Ordering Information
Device Marking
FDB3632
Device
FDB3632
FDP3632
FDI3632
Package
TO-263AB
TO-220AB
TO-262AA
Reel Size
330mm
Tube
Tape Width
24mm
N/A
Quantity
800 units
50 units
50 units
FDP3632
FDI3632
Tube
N/A
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
100
-
-
-
-
-
V
V
DS = 80V
-
-
-
1
IDSS
µA
nA
VGS = 0V
TC= 150oC
250
±100
IGSS
VGS = ±20V
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250µA
ID=80A, VGS=10V
2
-
-
4
V
0.0075 0.009
0.009 0.015
0.018 0.022
rDS(ON)
Drain to Source On Resistance
ID =40A, VGS = 6V,
ID=80A, VGS=10V, TC=175oC
-
Ω
-
Dynamic Characteristics
CISS
Input Capacitance
-
-
-
-
-
-
-
-
6000
820
200
84
-
pF
pF
pF
nC
nC
nC
nC
nC
VDS = 25V, VGS = 0V,
f = 1MHz
COSS
CRSS
Qg(TOT)
Qg(TH)
Qgs
Output Capacitance
-
Reverse Transfer Capacitance
Total Gate Charge at 10V
Threshold Gate Charge
-
110
14
-
VGS = 0V to 10V
VGS = 0V to 2V
11
VDD = 50V
D = 80A
Ig = 1.0mA
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
I
30
Qgs2
20
-
Qgd
20
-
Resistive Switching Characteristics (VGS = 10V)
tON
td(ON)
tr
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
102
ns
ns
ns
ns
ns
ns
30
39
96
46
-
-
-
V
V
DD = 50V, ID = 80A
GS = 10V, RGS = 3.6Ω
td(OFF)
tf
Turn-Off Delay Time
Fall Time
-
-
tOFF
Turn-Off Time
213
Drain-Source Diode Characteristics
I
SD = 80A
-
-
-
-
-
-
-
-
1.25
1.0
64
V
V
VSD
Source to Drain Diode Voltage
ISD = 40A
trr
Reverse Recovery Time
ISD = 75A, dISD/dt= 100A/µs
ISD = 75A, dISD/dt= 100A/µs
ns
nC
QRR
Reverse Recovered Charge
120
Notes:
1: Starting T = 25°C, L = 0.12mH, I = 75A.
J
AS
2: Pulse Width = 100s
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
Typical Characteristics TA = 25°C unless otherwise noted
1.2
125
CURRENT LIMITED
BY PACKAGE
1.0
100
0.8
75
V
= 10V
GS
0.6
0.4
0.2
0
50
25
0
150
0
25
50
75
100
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
C
T
, CASE TEMPERATURE ( C)
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
x Z
x R
+ T
J
DM
θJC
θJC C
0.01
10
-5
-4
-3
-2
-1
0
1
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
1000
o
T
= 25 C
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
150
C
V
= 10V
I = I
GS
25
100
50
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
Typical Characteristics TA = 25°C unless otherwise noted
400
100
200
If R = 0
10µs
t
AV
= (L)(I )/(1.3*RATED BV
- V
DD
)
AS
DSS
If R ≠ 0
t
AV
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DD
AS
DSS
100
100µs
o
STARTING T = 25 C
J
OPERATION IN THIS
AREA MAY BE
10
1
LIMITED BY r
DS(ON)
1ms
o
STARTING T = 150 C
J
10ms
DC
SINGLE PULSE
T
T
= MAX RATED
= 25 C
J
o
C
10
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
0.01
0.1
1
10
V
t , TIME IN AVALANCHE (ms)
DS
AV
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 5. Forward Bias Safe Operating Area
150
150
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 6V
GS
V
= 10V
GS
V
= 15V
V
= 5.5V
DD
GS
120
90
60
30
0
120
90
60
30
0
o
T
= 175 C
J
V
= 5V
GS
o
T
= 25 C
J
o
o
T
= 25 C
T
= -55 C
C
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
1
2
3
4
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
10
9
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 6V
GS
2.0
8
1.5
1.0
0.5
V
= 10V
GS
7
V
= 10V, I =80A
D
GS
6
-80
-40
0
40
80
120
160
200
0
20
40
I , DRAIN CURRENT (A)
62
80
o
T , JUNCTION TEMPERATURE ( C)
D
J
Figure 9. Drain to Source On Resistance vs Drain
Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
Typical Characteristics TA = 25°C unless otherwise noted
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.2
1.1
1.0
0.9
V
= V , I = 250µA
DS D
I
= 250µA
GS
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10000
10
V
= 50V
DD
C
= C + C
GS GD
ISS
8
6
4
2
0
C
C
+ C
GD
OSS
DS
1000
C
= C
RSS
GD
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 80A
= 40A
D
D
V
= 0V, f = 1MHz
1
GS
100
0.1
10
100
0
20
40
60
80
100
V
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
DS
g
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
0
AS
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
DS
L
V
= 10V
GS
V
GS
+
V
DD
V
GS
-
V
= 2V
DUT
GS
Q
gs2
0
I
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
0
DS
90%
90%
+
V
GS
V
DD
10%
10%
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
80
60
40
20
R
= 26.51+ 19.84/(0.262+Area) EQ.2
θJA
R
= 26.51+ 128/(1.69+Area) EQ.3
θJA
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
JM
A
(EQ. 1)
P
= -----------------------------
DM
Rθ JA
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
0.1
(0.645)
1
10
(6.45)
(64.5)
2
2
AREA, TOP COPPER AREA in (cm )
Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
19.84
(0.262 + Area)
R
= 26.51 + ------------------------------------
(EQ. 2)
θ JA
θ JA
Area in Inches Squared
128
= 26.51 + ---------------------------------
(1.69 + Area)
R
(EQ. 3)
Area in Centimeters Squared
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
PSPICE Electrical Model
.SUBCKT FDB3632 2 1 3 ;
CA 12 8 1.7e-9
rev May 2002
Cb 15 14 2.5e-9
Cin 6 8 6.0e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
Ebreak 11 7 17 18 102.5
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
-
+
50
-
17
DBODY
RDRAIN
6
8
EBREAK 18
-
ESG
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
6
+
-
18
22
It 8 17 1
MMED
9
20
MSTRO
8
RLGATE
Lgate 1 9 5.61e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.7e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 27
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
-
S1B
S2B
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 3.8e-3
Rgate 9 20 1.1
-
-
8
22
RVTHRES
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 2.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*350),3))}
.MODEL DbodyMOD D (IS=5.9E-11 N=1.07 RS=2.3e-3 TRS1=3.0e-3 TRS2=1.0e-6
+ CJO=4e-9 M=0.58 TT=4.8e-8 XTI=4.2)
.MODEL DbreakMOD D (RS=0.17 TRS1=3.0e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=15e-10 IS=1.0e-30 N=10 M=0.6)
.MODEL MstroMOD NMOS (VTO=4.1 KP=200 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=3.4 KP=10.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.1)
.MODEL MweakMOD NMOS (VTO=2.75 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.1e+1 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.0e-3 TC2=-1.7e-6)
.MODEL RdrainMOD RES (TC1=8.5e-3 TC2=2.8e-5)
.MODEL RSLCMOD RES (TC1=2.0e-3 TC2=2.0e-6)
.MODEL RsourceMOD RES (TC1=4e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.0e-3 TC2=-1.8e-5)
.MODEL RvtempMOD RES (TC1=-4.4e-3 TC2=2.2e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=0.4)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.4 VOFF=-0.8)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
SABER Electrical Model
REV May 2002
template FDB3632 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=5.9e-11,nl=1.07,rs=2.3e-3,trs1=3.0e-3,trs2=1.0e-6,cjo=4e-9,m=0.58,tt=4.8e-8,xti=4.2)
dp..model dbreakmod = (rs=0.17,trs1=3.0e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=15e-10,isl=10.0e-30,nl=10,m=0.6)
m..model mstrongmod = (type=_n,vto=4.1,kp=200,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=3.4,kp=10.0,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.75,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2)
LDRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.4)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.4,voff=-0.8)
c.ca n12 n8 = 1.7e-9
c.cb n15 n14 = 2.5e-9
c.cin n6 n8 = 6.0e-9
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
DBREAK
11
50
-
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
16
21
+
-
19
8
spe.ebreak n11 n7 n17 n18 = 102.5
MWEAK
LGATE
EVTEMP
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
RGATE
GATE
1
6
+
-
18
22
EBREAK
+
MMED
9
20
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
i.it n8 n17 = 1
RLSOURCE
S1A
S2A
l.lgate n1 n9 = 5.61e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.7e-9
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 27
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
22
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.0e-3,tc2=-1.7e-6
res.rdrain n50 n16 = 3.8e-3, tc1=8.5e-3,tc2=2.8e-5
res.rgate n9 n20 = 1.1
res.rslc1 n5 n51 = 1.0e-6, tc1=2.0e-3,tc2=2.0e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 2.5e-3, tc1=4e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.0e-3,tc2=-1.8e-5
res.rvtemp n18 n19 = 1, tc1=-4.4e-3,tc2=2.2e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/350))** 3))
}
}
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
SPICE Thermal Model
JUNCTION
th
REV May 2002
FDB3632
CTHERM1 TH 6 7.5e-3
CTHERM2 6 5 8.0e-3
CTHERM3 5 4 9.0e-3
CTHERM4 4 3 2.4e-2
CTHERM5 3 2 3.4e-2
CTHERM6 2 TL 6.5e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 TH 6 3.1e-4
RTHERM2 6 5 2.5e-3
RTHERM3 5 4 2.2e-2
RTHERM4 4 3 8.1e-2
RTHERM5 3 2 1.35e-1
RTHERM6 2 TL 1.5e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model FDB3632
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =7.5e-3
ctherm.ctherm2 6 5 =8.0e-3
ctherm.ctherm3 5 4 =9.0e-3
ctherm.ctherm4 4 3 =2.4e-2
ctherm.ctherm5 3 2 =3.4e-2
ctherm.ctherm6 2 tl =6.5e-2
4
3
2
rtherm.rtherm1 th 6 =3.1e-4
rtherm.rtherm2 6 5 =2.5e-3
rtherm.rtherm3 5 4 =2.2e-2
rtherm.rtherm4 4 3 =8.1e-2
rtherm.rtherm5 3 2 =1.35e-1
rtherm.rtherm6 2 tl =1.5e-1
}
tl
CASE
©2003 Fairchild Semiconductor Corporation
FDB3632 / FDP3632 / FDI3632 Rev. B1
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Rev. I2
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