FAN5903BUCX_技术文档

June 2013

FAN5903

Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs

Features

Description

.

2.7 V to 5.5 V Input Voltage Range

V_OUTRange from 0.4 V to 3.5 V (or V_IN)

Small Form Factor Inductor

FAN5903 is a high-efficiency, low-noise, synchronous,

step-down, DC-DC converter designed for powering

3G / 3.5G / 4G RF Power Amplifiers (PAs) in handsets

and other mobile applications.

o

2012 470 nH or 540 nH for Minimal PCB Area

2520 1.0 µH for Higher Efficiency

The output voltage may be dynamically varied from

0.40 V to 3.50 V, proportional to an analog input V_CON

,

ranging from 0.16 V to 1.40 V provided by an external

DAC. This allows the PA to be supplied with the voltage

that enables maximum power-added efficiency.

.

Bypass Dropout at 500 mA, 60 mV Typical

100% Duty Cycle for Low Dropout Operation

Input Under-Voltage Lockout / Thermal Shutdown

An integrated bypass FET automatically switches on

when battery voltage drops close to the desired output

voltage (V_OUT= V_BAT- 200 mV). The DC-DC switches

back to Synchronous Mode when the voltage dropout

exceeds 375 mV. The integrated bypass FET is also

enabled when V_CONis nominally greater than to 1.5 V.

1.34 mm x 1.29 mm, 9-Bump, 0.4 mm-Pitch,

Wafer-Level Chip-Scale Package (WLCSP)

.

3 MHz / 6 MHz Selectable Switching Frequency to

Facilitate System Optimization

.

High-Efficiency PFM Operation at Low Power

Sleep Mode for Very Low I_QOperation

The FAN5903 offers fast transition times, enabling

changes to the output voltage in less than 10 µs for

power transitions. Moreover, a Current-Mode control

loop with fast transient response ensures excellent line

and load regulation.

Up to 96% Efficient Synchronous Operation at

High-Power Conditions

.

10 µs Output Voltage Step Response for Early

Power Loop Settling

Light-load efficiency is optimized by operating in PFM

Mode for load currents typically less than 100 mA.

The switching frequency may be set to 3 MHz or

6 MHz, enabling further optimization of system

performance. The FAN5903 typically uses a single,

small-form-factor inductor of 470 nH or 540 nH.

Efficiency may be further optimized using a 1.0 µH

inductor when running at 3 MHz.

Applications

.

Dynamic Supply Bias for 3G/3.5G and 4G PAs

Power Supply for WCDMA/LTE PAs

Resources

When output regulation is not required, the FAN5903

may be placed in Sleep Mode by setting V_CONnominally

to 50 mV. This ensures a very low I_Q(<70 µA) while

For more information or a full copy of this datasheet,

please contact a Fairchild representative.

enabling

a fast return to output regulation. The

FAN5903 enables significant current reduction and

increased talk time and is available in a 1.34 mm x

1.29 mm, 9-bump, 0.40 mm-pitch, WLCSP package.

Ordering Information

Operating

Part Number

Package

Packing Method

Temperature Range

1.34 mm x 1.29 mm, 9-bump, 0.4 mm Pitch,

Wafer-Level Chip-Scale Package (WLCSP)

FAN5903UCX

-40 to +85°C

Tape and Reel

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FAN5903 • Rev. 1.0.9

Application Diagrams

V_OUT

470nH

L1

PVIN

SW

FB

C_IN

10 µF

C_OUT

4.7 µF

EN

FAN5903

FSEL

PGND

AGND

3/6 MHz DC-DC

From

External

DAC

VCON

Figure 1. Application Circuit

C_PA

FAN5903

Bypass

Controller

PA

PVIN

V_IN

2.7V – 4.5V

UMTS BAND 1, … ,13

C_IN

FB

0.4Vto 3.4V

Up to

800mArms

Switcher

Optional

GPIO

L1

V_OUT

BPEN

FSEL

EN

PFM/PWM

Controller

SW

C_OUT

PGND

DAC/GPIO

VCON

Reference

AGND

CHIPSET

Bandgap

PA

UMTS BAND 1, … ,13

C_PA

Figure 2. Typical Application with a 5-Band WCDMA / HSPA PA System

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FAN5903 • Rev. 1.0.9

2

Pin Configuration

VCON

AGND

PGND

AGND

VCON

A1

A2

A3

A2

A1

4

.

4

.

EN

FSEL

SW

FSEL

EN

0

m

9

m

9

B1

B2

B3

B2

B1

2

.

2

.

1

BPEN

FB

PVIN

FB

BPEN

C1

C2

C3

C2

C1

0.4

1.34 mm

Figure 3. Top-Through View, Bumps Face Down

Figure 4. Top-Through View, Bumps Face Up

Pin Definitions

Pin # Name

Description

A1

A2

VCON Analog control pin. Shield signal routing against noise.

AGND Analog ground, reference ground for the IC. Follow PCB routing notes for connecting this pin.

Power ground of the internal MOSFET switches. Follow routing notes for connections between

PGND and AGND.

A3

B1

B2

PGND

EN

FSEL

SW

Enables switching when HIGH, Shutdown Mode when LOW. This pin should not be left floating.

Switching frequency select. When FSEL is LOW, the DC-DC operates at 6 MHz. When FSEL is

HIGH, the DC-DC operates at 3 MHz. This pin should not be left floating.

B3

C1

C2

Switching node of the internal MOSFET switches. Connect to output inductor.

BPEN Force bypass transistor when HIGH; auto-bypass when LOW. This pin should not be left floating.

FB Output voltage-sense pin. Connect to VOUT to establish feedback path for regulation point.

PVIN Supply voltage input to the internal MOSFET switches; connect to input power source.

C3

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FAN5903 • Rev. 1.0.9

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Min.

-0.3

-40

Max.

6.0

Unit

PVIN

V_IN

V

Voltage On Any Other Pin

Junction Temperature

Storage Temperature

PV_IN+ 0.3

+125

T_J

T_STG

T_L

°C

-65

+150

Lead Soldering Temperature (10 Seconds)

+260

Human Body Model, JESD22-A114

Charged Device Model, JESD22-C101

2.0

1.5

Electrostatic Discharge

Protection

ESD

kV

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_IN

Parameter

Min.

2.7

Typ.

Max.

5.5

Unit

V

Supply Voltage Range

Output Voltage Range

V_OUT

0.35

<V_IN

2.4

V

I_{OUT_BYP}Output Current (Bypass Mode)

I_{OUT_DCDC}Output Current (DCDC Mode)

A

1.0

A

470

540

1.00

10

f_SW= 6 MHz

f_SW= 3 MHz

nH

L1

Inductor

µH

µF

°C

C_IN

C_OUT

T_A

Input Capacitor⁽¹⁾

Output Capacitor

2.2

-40

4.7

Operating Ambient Temperature Range

Operating Junction Temperature Range

+85

T_J

+125

Note:

1. A large enough input capacitor value is required for limiting the input voltage drop during bursts, bypass

transitions, or during large output voltage transitions. Ensure the input capacitor value is greater than the output

capacitor’s. See the inrush current specifications below.

Dissipation Ratings

Symbol

Parameter

Min.

Typ.

Max.

Unit

Junction-to-Ambient Thermal Resistance⁽²

110

°C/W

)

Θ_JA

Note:

2. Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with

four-layer 2s2p boards in accordance to JESD51- JEDEC standard. Special attention must be paid not to exceed

junction temperature T_J(max)at a given ambient temperate T_A.

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FAN5903 • Rev. 1.0.9

4

Electrical Characteristics

V_IN= V_OUT+ 0.6 V, I_OUT= 200 mA, EN = V_IN, T_A= -40°C to +85°C, unless otherwise noted. Typical values are at

T_A= +25°C, V_IN= 3.7 V.

Symbol

Parameter

Condition

Min.

Typ. Max. Unit

Power Supplies

V_IN

I_SD

I_Q

Input Voltage Range

I_OUT≤ 800 mA

2.7

5.5

3

V

µA

V

Shutdown Supply Current

Quiescent Current

EN = 0 V

1

Sleep Enabled

V_INRising

70

2.30

1.2

2.45

175

2.60

V_UVLO

Under Voltage Lockout Threshold

Hysteresis

mV

V

V_IH

Input HIGH Threshold

Input LOW Threshold

EN = V_INor GND

Logic Threshold Voltage: EN,

FSEL and BPEN

V_IL

I_EN

0.5

V

EN Input Bias Current

0.01

1.00

µA

Oscillator

f_SW

Average Oscillator Frequency

FSEL = 0

FSEL = 1

5.4

2.7

6.0

3.0

6.6

3.3

MHz

f_SW

DC-DC Mode

PMOS On Resistance⁽³⁾

NMOS On Resistance⁽³⁾

P-Channel Current Limit

N-Channel Current Limit

Minimum Output Voltage

V_IN= V_GS= 3.7 V

230

150

1.5

mΩ

A

R_DSON

I_LIMp

I_LIMn

1.2

0.8

1.8

1.4

1.1

A

V_{OUT_MIN}

V_CON= 0.16 V

V_CON= 1.40 V

0.35

3.45

0.40

3.50

0.45

3.55

V

V_{OUT_MAX}Maximum Output Voltage

V

Gain in Control Range 0.16V to

1.40V

Gain

2.5

V_{OUT_ACC}V_OUTAccuracy

Ideal = 2.5 x V_CON

V_IN= V_GS= 3.7 V

-50

+50

mV

Bypass Mode

R_FET

Bypass FET Resistance⁽⁴⁾

210

60

mΩ

Bypass Mode Output Voltage Drop I_OUT= 500 mA

mV

V_{OUT_BP}

Output Regulation

V_{OUT_RLine}

V_{OUT_RL}



V_OUTLine Regulation

V_OUTLoad Regulation

+5

mV



I_OUT≤ 800 mA

+25

V_CONVoltage that Forces Very

Low I_QSleep Mode

V_{CON_SL_EN} V_CONSleep Mode Enter

V_{CON_SL_EX} V_CONSleep Mode Exit

50

mV

V

V_CONVoltage that Exits Sleep

Mode

135

1.4

V_CONVoltage that Forces

Bypass, V_IN= 2.70 V – 4.75 V

V_{CON_BP_EN} V_CONForced Bypass Mode Enter

1.6

V_CONVoltage that Exits

Forced; Bypass,

V_IN= 2.70 V – 4.75 V

V_{CON_BP_EX} V_CONForced Bypass Mode Exit

V

Voltage Threshold to Enter Bypass

Mode

V_{BP_ThH}

V_{BP_ThL}

T_OTP



V_IN– V_OUT

160

320

200

375

240

440

mV

Voltage Threshold to Exit Bypass

Mode



Rising Temperature

Hysteresis

+150

+20



Over-Temperature Protection

°C

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FAN5903 • Rev. 1.0.9

5

Electrical Characteristics

V_IN= V_OUT+ 0.6 V, I_OUT= 200 mA, EN = V_IN, T_A= -40°C to +85°C, unless otherwise noted. Typical values are at

T_A= +25°C, V_IN= 3.7 V.

Symbol

Timings

Parameter

Condition

Min.

Typ. Max. Unit

V_IN= 3.7 V, V_OUTfrom 0 V to

3.1 V, C_OUT= 4.7 µF, 10 V,

X5R

t_SS



Startup Time

30

40

µs

t_{SP_en}



Sleep Mode Enter Time

Sleep Mode Exit Time

V_CON< 50 mV

40

11

µs

t_{SP_ex}



V_CON≥ 135 mV

V_OUTfrom 5% to 95%,

V_OUT< 2 V (1.4 V – 3.4 V) ,

R_LOAD≤ 7 

t_{DC-DC_TR}



V_OUTStep Response Rise Time⁽³⁾

10

12

µs

V_OUTfrom 95% to 5%,

V_OUT< 2 V (3.4 V – 1.4 V),

R_LOAD≤ 7 

t_{DC-DC_TF}



V_OUTStep Response Fall Time⁽³⁾

Maximum Allowed Time for

Consecutive Current Limits⁽⁵⁾

t_{DC-DC_CL}

40

µs

Consecutive Current Limit

Recovery Time⁽³⁾

t_{DCDC_CLR}

180

Notes:

3. Guaranteed by design; not tested in production.

4. Bypass FET resistance does not include the PFET R_DSONand inductor DCR in parallel with the bypass FET in

Bypass Mode.

5. Protects part under short circuit conditions. After 40 µs, operation halts and restarts after 180 µs. Under heavy

capacitive loads, V_CONslew rate may be reduced to avoid consecutive current limits. Under typical conditions for

a 3 V change at the output, a capacitive only load of up to 40 µF is supported, assuming a step at the V_CONinput.

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FAN5903 • Rev. 1.0.9

6

Typical Characteristics

Unless otherwise noted, V_IN= EN = 3.7 V, L1 = 1.0 µH, C_LOAD= 4.7 µF, and T_A= +25°C.

100%

90%

80%

70%

60%

50%

40%

100%

90%

80%

70%

60%

50%

40%

VIN = 2.7V

VIN = 3.7V

VIN = 4.2V

VIN = 5.5V

VIN = 2.7V

VIN = 3.7V

VIN = 4.2V

VIN = 5.5V

0

100

200

300

400

500

0

100

200

300

400

OutputCurrent(mA)

Figure 5. Efficiency vs. Output Current vs. Input

Figure 6. Efficiency vs. Output Current vs. Input

Voltage, f_SW= 6 MHz, R_PA= 7 

Voltage, f_SW= 6 MHz, R_PA= 10 

100%

90%

80%

70%

100%

90%

80%

70%

VIN = 2.7V

VIN = 3.7V

VIN = 4.2V

VIN = 5.5V

60%

VIN = 3.7V

VIN = 4.2V

50%

40%

VIN = 5.5V

40%

0

1

2

3

4

0

1

2

3

4

OutputVoltage (V)

Figure 7. Efficiency vs. Output Voltage vs. Input

Figure 8. Efficiency vs. Output Voltage vs. Input

Voltage, f_SW= 6 MHz, R_PA= 7 

Voltage, f_SW= 6 MHz, R_PA= 10 

100%

90%

80%

70%

100%

90%

80%

70%

VIN = 2.7V

VIN = 3.7V

VIN = 4.2V

VIN = 5.5V

60%

50%

40%

VIN = 3.7V

VIN = 4.2V

50%

VIN = 5.5V

40%

0

100

200

300

400

0

100

200

300

400

500

OutputCurrent(mA)

Figure 9. Efficiency vs. Output Current vs. Input

Figure 10. Efficiency vs. Output Current vs. Input

Voltage, f_SW= 3 MHz, R_PA= 7 

Voltage, f_SW= 3 MHz, R_PA= 10 

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FAN5903 • Rev. 1.0.9

7

Typical Characteristics

Unless otherwise noted, V_IN= EN = 3.7 V, L1 = 1.0 µH, C_LOAD= 4.7 µF, and T_A= +25°C.

100%

90%

80%

70%

60%

50%

40%

100%

90%

80%

70%

60%

50%

40%

VIN = 2.7V

VIN = 3.7V

VIN = 4.2V

VIN = 5.5V

VIN = 2.7V

VIN = 3.7V

VIN = 4.2V

VIN = 5.5V

0

1

2

3

4

0

1

2

3

4

OutputVoltage (V)

Figure 11. Efficiency vs. Output Voltage vs. Input

Figure 12. Efficiency vs. Output Voltage vs. Input

Voltage, f_SW= 3 MHz, R_PA= 7 

Voltage, f_SW= 3 MHz, R_PA= 10 

100

90

3.30

2.80

2.30

1.80

80

70

-40°C

1.30

-40°C

+25°C

60

0.80

+85°C

50

0.30

2.5

3.5

4.5

5.5

2.5

3.5

4.5

5.5

InputVoltage (V)

Figure 13. Shutdown Current vs. Input Voltage

vs. Temperature

Figure 14. Sleep Mode Current vs. Input Voltage

vs. Temperature

Figure 15. Rise Times for 300 mV, 500 mV, and

Figure 16. Rise Times for 300 mV, 500 mV, and

2 V V_OUT(V_IN= 3.7 V)

FAN5903 • Rev. 1.0.9

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8

Typical Characteristics

Unless otherwise noted, V_IN= EN = 3.7 V, L1 = 1.0 µH, C_LOAD= 4.7 µF, and T_A= +25°C.

Figure 17. Line Transient V_IN= 3.7 V to 4.2 V,

Figure 18. Line Transient V_IN= 3.7 V to 4.2 V,

V_OUT= 2.5 V, 10  Load, 50 µs/div.

V_OUT= 1.0 V, 10  Load, 50 µs/div.

Figure 19. Load Transient, 0 mA to 400 mA,

V_OUT= 1.0 V

Figure 20. Load Transient, 200 mA to 800 mA,

V_OUT= 1.0 V

Figure 21. Load Transient, 0 mA to 400 mA,

V_OUT= 2.5 V

Figure 22. Load Transient, 200 mA to 800 mA,

V_OUT= 2.5 V

FAN5903 • Rev. 1.0.9

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9

Typical Characteristics

Unless otherwise noted, V_IN= EN = 3.7 V, L1 = 1.0 µH, C_LOAD= 4.7 µF, and T_A= +25°C.

Figure 23. Switching Waveforms, PFM Mode,

I_LOAD= 10 mA (Light Load)

Figure 24. Switching Waveforms, PWM Mode,

f_SW= 6 MHz, I_LOAD= 300 mA (Heavy Load)

Figure 25. V_OUTRising Transition 0.5 V to 2.5 V,

V_IN= 3.7 V

Figure 26. V_OUTFalling Transition 2.5 V to 0.5 V,

V_IN= 3.7 V

Figure 27. V_OUTTransient Response V_OUT= 3 V

Figure 28. V_OUTTransient and Bypass Response V_OUT

> 3 V, V_CONStepped Above 1.5 V

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FAN5903 • Rev. 1.0.9

10

Typical Characteristics

Unless otherwise noted, V_IN= EN = 3.7 V, L1 = 1.0 µH, C_LOAD= 4.7 µF, and T_A= +25°C.

I_LIM

Figure 29. Soft-Start Transient Response from

0 mA to 100 mA

Figure 30. Cold-Start Transient Response from

0 mA to 100 mA

Figure 31. Soft-Start Transient Response from

0 mA to 800 mA

Figure 32. Cold-Start Transient Response from

0 mA to 800 mA

Figure 33. Shutdown Transient Response

FAN5903 • Rev. 1.0.9

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11

Block Diagram

FB

Bypass

Controller

PVIN

Positive

Current Limit

C_IN

PWM

VCON

FSEL

Controller

SW

L1

0 : Div 1

1 : Div 2

3 MHz OSC

C_OUT

To PWM CTL

Negative

PGND

Current Limit

EN

BPEN

AGND

Figure 34. Block Diagram

Operating Mode Description

The FAN5903 is a high-efficiency synchronous step-

down DC-DC converter operating with a Current-Mode

control. It adjusts the output voltage, V_OUT, depending

on the set voltage V_CONprovided by an external DAC.

monitored. A current sense flags when the P-channel

transistor current exceeds the current limit and the

switcher is turned off to decrease the inductor current and

prevent magnetic saturation. Similarly, the current sense

flags when the N-channel transistor current exceeds the

current limit and re-directs discharging current through

the inductor back to the battery.

Regulated V_OUTis set to 2.5 times input voltage V_CON

.

The DC-DC operates in PWM Mode or PFM Mode,

depending on the output voltage and load current.

Bypass Mode is supported where the output voltage is

shorted to the input voltage via a low on-state resistance

bypass FET.

In Pulse Frequency Modulation (PFM) Mode, at low

output voltages and load currents, typically less than

100 mA; the DC-DC operates in a constant On-Time

Mode. In the on-state, the P-channel is turned on during a

well-defined on-time before switching to the off state,

whereby the N-channel switch is turned on and the

inductor current is decreased to 0 A. The switcher output

is put into high-resistance state until the new regulation

cycle starts.

The FAN5903 supports a wide range of load currents.

High-current applications, up to a DC output of 800 mA,

mandated by 3G / 3.5G and 4G applications, for

example, are supported. System performance may be

optimized by enabling the DC-DC to run at either a

3 MHz or 6 MHz switching rate.

PFM Mode realizes high efficiency while maintaining RF

system performance down to low load currents.

Auto Mode

In Pulse Width Modulation (PWM) Mode, regulation

starts with an on-state where a P-channel transistor is

turned on and the inductor current is ramped up until the

off state begins. In the off state, the P-channel is switched

off and an N-channel transistor is turned on. The inductor

current decreases to maintain an average value equal to

the DC load current. The inductor current is continuously

Bypass Mode

In Bypass Mode, the FAN5903 operates at 100% duty

cycle with the bypass FET turned on. This enables a very

low voltage dropout with up to 2.4 A DC load current. In

applications with 3G / 3.5G and 4G PAs, the Bypass

Mode typically handles 800 mA.

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FAN5903 • Rev. 1.0.9

12

Table 1. Mode Descriptions

Conditions

#

Mode

Mode Description

FSEL BPEN EN VCON

1

2

Shutdown Mode

Sleep Mode

The whole IC is disabled.

X

0

The DC-DC is in Sleep Mode and consumes less than

70 µA of current.

X

1

0

3

4

6 MHz Auto Mode

3 MHz Auto Mode

The DC-DC is in Auto Mode and switches at 6 MHz.^(6,7)

0

1

0

1

The DC-DC is in Auto Mode and switches at 3 MHz.

The bypass FET is forced ON. The DC-DC is set to 100%

duty cycle.

5

Bypass Mode

X

1

Notes:

6. When V_OUTexceeds V_IN– 200 mV, the bypass FET is enabled and the DC-DC goes to 100% duty cycle. When

V_OUT≤ V_IN– 375 mV, the bypass FET is disabled and the DC-DC goes to Auto Mode.

7. When the load current is smaller than PFM current threshold, the DC-DC changes to PFM Mode.

DC Output Voltage

Bypass Mode

The output voltage of the DC-DC is determined by V_CON,

provided by an external DAC or voltage reference:

The trigger to enter Bypass Mode is based on the

voltage difference between the battery voltage (sensed

through the PVIN pin) and the internally generated

reference voltage, V_REF, as depicted in Figure 36. The

DC-DC enters Bypass Mode when V_IN= V_OUT+ 200 mV.

It then turns into 100% duty cycle and the low-R_DSON

bypass FET is turned on. As V_OUTapproaches V_IN; the

DC-DC operates in a constant off-time mode, the

frequency is decreased to achieve a high duty cycle,

and the system continues to run in a regulated mode

until the bypass condition is satisfied.

(1)

V_OUT 2.5V_CON

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

As noted above, Bypass Mode is also entered when

V_CONexceeds 1.5 V.

Sleep Mode

FB

1.0

PVIN

DCDC Mode

0.5

Bypass Mode

-

Bypass Slew

Controller

0.0

250mV

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

+

-

VCON

V_CON(V)

V_REF

Figure 35. Output Voltage vs. Control Voltage

SW

VREF

PWM

Controller

DC-DC

Switcher

L1

VREF ranges from 0.4 V to3.4V

when V_INis higher than 3.4V

The DC-DC is able to provide a regulated V_OUTonly if

V_CONis between 0.16 V to 1.40 V. This allows V_OUTto

be adjusted between 0.40 V and 3.50 V. If V_CONis below

this range, V_OUTis clamped to 0.40 V as minimum and

enters bypass for V_CON> 1.50 V. If V_CONis less than

50 mV, FAN5903 enters a non-regulated Sleep Mode.

This reduces current consumption to less than 70 µA

while allowing for a rapid return to regulation.

Figure 36. Enabling Bypass Transistor Circuit

The bypass FET is turned on progressively using a slew

rate controller to limit the inrush current. The inrush

current is expressed as a function of the specified slew

rate as follows:

V_OUT

t

FAN5903 automatically switches between PFM, PWM,

and Bypass Modes.

(2)

I_INRUSH C_OUT

 C_OUTV_{BP_SLEW}

The DC-DC is able to provide a regulated V_OUTonly if

The slew rate controller is not used when releasing the

Bypass Mode.

the battery voltage is 200 mV greater than V_OUT

.

www.fairchildsemi.com

FAN5903 • Rev. 1.0.9

13

V_OUTNegative Step

Switching Frequency Selection (FSEL)

After a V_CONnegative step, the DC-DC enters Current-

Limit Mode, where V_OUTis reduced with a constant slew

rate dictated by the output capacitor and the current limit.

In some cases, it may be desirable to change the DC-

DC’s switching frequency from 6 MHz (FSEL = 0) to

3 MHz (FSEL = 1). At 3 MHz operation the DC-DC’s

efficiency is generally higher than that at 6 MHz. The

primary tradeoff with this is increased voltage ripple at

the lower frequency. A 1.0 µH inductor may be used in

3 MHz operation to optimize efficiency and ripple.

V_OUTTransition to or from Bypass Mode

The transition to or from Bypass Mode requires the

bypass conditions be met. The FAN5903 performs

detection of the bypass conditions 2 µs after V_CON

transition and enables the required charging

discharging circuit to realize a transition time of 10 µs.

/

The FAN5903 is designed to have minimal impact on

the RF output spectrum at either switching frequency.

V_OUTTransition at Startup

At startup, after EN rising edge is detected, the system

requires 40 µs to enable all internal voltage references

and amplifiers before enabling the DC-DC function.

Dynamic Output Voltage Transitions

The FAN5903 has

a complex voltage transition

controller that realizes less than 10 µs transition times

with a large output capacitor and output voltage ranges.

V_OUTTransition After BPEN

When BPEN goes HIGH, the controller dismisses the

internal bypass flags and sensors and enables

Bypass Mode. However, the transition is managed

with the same current limit and slew rate used during

regular transitions.

The transition controller manages five transitions:

.

V_OUTpositive step

V_OUTnegative step

V_OUTtransition to or from Bypass Mode

V_OUTtransition at startup

V_OUTtransition after BPEN

Thermal Protection

If the junction temperature exceeds the maximum

specified junction temperature, the FAN5903 enters

Power-Down Mode (except the thermal detection circuit).

In most cases, sharp V_CONtransitions and letting the

transition controller optimize the output voltage slew rate

are recommended.

Sleep Mode

The FAN5903 offers a Sleep mode to minimize current,

while also enabling a rapid return to regulation. Sleep

Mode is entered when V_CONis held below 50 mV for at

least 40 µs. In this mode, current consumption is

reduced to under 70 µA. Sleep Mode is exited after

approximately 12 µs when V_CONis set above 135 mV.

V_OUTPositive Step

After a V_CONpositive step, the DC-DC enters a Current-

Limit Mode, where V_OUTramps with a constant slew rate

dictated by the output capacitor and the current limit.

Typical Voltage Transitions

Figure 37. Rise and Fall Times for 300 mV, 500 mV,

Figure 38. Rise Times for 300 mV, 500 mV, and 2 V

and 2 V V_OUT(V_IN= 3.7 V)

V_OUT(V_IN= 3.7 V)

www.fairchildsemi.com

FAN5903 • Rev. 1.0.9

14

Application Information

Figure 39 illustrates an application of the FAN5903 in a 3G / 4G transmitter. The FAN5903 is designed for driving

multiple PAs. Figure 40 presents a timing diagram designed to meet WCDMA specifications. The FAN5903 supports

voltage transients less than 10 µs.

FB

PVIN

C_IN

10µF

0.4V to V_BAT

Up to 800mA DC

540nH

L1

FAN5903

SW

FSEL

BPEN

EN

C_OUT

4.7µF

PGND

V_IN

Power

Ground

Plane

From

DAC

VCON

AGND

Analog

Ground

Plane

V_OUT

1000pF

100pF

1000pF

100pF

1000pF

100pF

PA

RF

Ground

Plane

RF

Ground

Plane

RF

Ground

Plane

Figure 39. Typical Application Diagram of FAN5903 Supplying Power to Three 3G or 4G PAs

30µs

DC-DC_EN

VCON

8µs

-

DC DC V_OUT

PA Supply

10ms

2.5 x V_CON

10ms

RF Power

Figure 40. Timing Diagram for 3G/4G Transmitters

www.fairchildsemi.com

FAN5903 • Rev. 1.0.9

15

Application Information

Inductor Selection

Follow these guidelines:

.

Use a low noise source or a driver with good

PSRR to generate V_CON

The FAN5903 is able to operate at 3 MHz or 6 MHz

switching frequency, so 470 nH (or 540 nH) or 1.0 µH

inductors can be used, respectively. To achieve

optimum efficiency, it is recommended that the

FAN5903 switch at 3 MHz (FSEL = HIGH), using a

1.0 µH inductor. For applications that require the

smallest possible PCB area, the FAN5903 should be

configured for 6 MHz operation (FSEL = LOW) to allow

use of a 470 nH or 540 nH 2012 inductor.

.

The V_CONdriver must be referenced to AGND.

V_CONrouting must be protected against PVIN,

SW, PGND signals, and other noisy signals. Use

AGND shielding for better isolation.

.

Be sure the DAC output can drive the 470 pF

capacitor on VCON. It may be necessary to insert

a low value resistor to ensure DAC stability

without slowing V_CONfast transition times.

Table 2. Recommended Inductors

No Floating Inputs

Inductor f_SW

Description

The FAN5903 does not have internal pull-down resistors

on its inputs. Therefore, unused inputs should not be left

floating and should be pulled HIGH or LOW.

470 nH, ±20%, 1100 mA, 2012

(metric)

Murata: LQM21PNR47MC0

470 nH, ±30%, 1200 mA, 2012

(metric)

PCB Layout & Component Placement

6 MHz

L1

Panasonic: ELGTEAR47NA

.

Make sure the FAN5903, C_IN, and C_OUTare all tied

to the same power ground (PGND). This minimizes

the parasitic inductance of the switching loop paths.

540 nH, ±20%, 1300 mA, 2012

(metric)

Murata: LQM21PNR54MG0

.

Place PGND on the top layer and connect it to the

AGND ground plane next to C_OUTusing several vias.

1.0 µH, ±20%, 2500 mA, 3030

(metric)

3 MHz

Ensure that the routing loop, PVIN – PGND –

VOUT is the shortest possible.

Coilcraft: XFL3010-102ME

Place the inductor away from the FB connection to

prevent unpredictable loop behavior.

Capacitor Selection

Use the application circuit layout in Figure 41

whenever possible. The performance of this layout

has been verified.

The minimum required output capacitor C_OUTis 4.7 µF,

6.3 V, X5R with an ESR of 10 m or lower and an ESL

of 0.3 nH or lower. Larger case sizes result in increased

loop parasitic inductance and higher noise.

.

Review the layout guidelines for the IC package.

This is especially important for the WLCSP

package. Refer to “Surface Mount Assembly of

Amkor’s Eutectic and Lead-Free CSPnl™ Wafer-

Level Chip-Scale Package” available from the

Amkor website.

A 0.1 µF capacitor may be added in parallel with C_OUTto

reduce the effect of the capacitor’s parasitic inductance.

Table 3. Recommended Capacitor Values

Capacitor

C_IN

Description

.

PVIN and PGND must be routed with the widest

and shortest traces possible. It is acceptable for the

traces connecting the inductor to be long rather

than having long PVIN or PGND traces. The SW

node is a source of electrical switching noise. Do

not route it near sensitive analog signals.

10 µF, ±20%, X5R, 10 V

4.7 µF, ±20%, X5R, 6.3 V

C_OUT

C on V_CON470 pF, ±20%, X5R

.

Two small vias are used to connect the SW node to

the inductor L1. Use solder-filled vias if available.

Filter VCON

VCON is the analog control pin of the DC-DC and

should be connected to an external Digital-to-Analog

Converter (DAC). It is recommended to place up to

470 pF decoupling capacitance between VCON and

AGND to filter the DAC noise. This capacitor also helps

protect the DAC from the DC-DC high-frequency

switching noise coupled through the VCON pin.

The connection from C_OUTto FB should be wide to

minimize the Bypass mode voltage drop and the

series inductance. Even if the current in Bypass

Mode is small, keep this trace short and at least

5mm wide.

.

The ground plane should be not be broken into

pieces. Ground currents must have a direct, wide

path from input to output.

Any noise on the V_CONinput is transferred to V_OUTwith a

gain of two and a half (2.5). If the DAC output is noisy, a

series resistor may be inserted between the DAC output

and the capacitor to form an RC filter.

www.fairchildsemi.com

FAN5903 • Rev. 1.0.9

16

Assembly

.

Each capacitor should have at least two dedicated

ground vias. Place vias within 0.1 mm of the

capacitors.

.

Use metal-filled or solder-filled vias if available.

Poor soldering can cause low DC-DC conversion

efficiency. If the efficiency is low, X-ray the solder

connections to verify their integrity.

.

Ensure the traces are wide enough to handle the

maximum current value, especially in Bypass Mode.

Ensure the vias are able to handle the current

density. Use metal-filled vias if available.

L1

C_OUT

C_IN

Figure 41. Recommended PCB Layout

www.fairchildsemi.com

FAN5903 • Rev. 1.0.9

17

Physical Dimensions

F

0.03 C

A

E

2X

0.40

A1

B

D

Ø0.20

Cu Pad

0.40

PIN A1

INDEX AREA

Ø0.30

Solder Mask

0.03 C

2X

LAND PATTERN RECOMMENDATION

(NSMD PAD TYPE)

TOP VIEW

0.06 C

0.292±0.018

0.208±0.021

0.539

0.461

0.05 C

E

C

SEATING PLANE

D

SIDE VIEWS

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

Ø0.260±0.020

9X

0.40

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 1994.

C

B

A

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

(Y)±0.018

0.40

E. PACKAGE NOMINAL HEIGHT IS 500 MICRONS

±39 MICRONS (461-539 MICRONS).

F

1

2 3

(X)±0.018

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

BOTTOM VIEW

G. DRAWING FILNAME: MKT-UC009AErev1

Product

D

E

X

Y

Unit

FAN5903UCX

1.292 ± 0.030

1.342 ± 0.030

0.271

0.246

mm

Figure 42. 1.34 x 1.29 mm, 9-Bump, 0.4 mm-Pitch WLCSP

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

www.fairchildsemi.com

FAN5903 • Rev. 1.0.9

18

www.fairchildsemi.com

FAN5903 • Rev. 1.0.9

19


型号：	FAN5903BUCX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Switching Regulator 开关
文件：	总19页 (文件大小：2159K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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