FAN3223CMPX [FAIRCHILD]
Dual 4A High-Speed, Low-Side Gate Drivers; 双4A高速,低侧栅极驱动器型号: | FAN3223CMPX |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Dual 4A High-Speed, Low-Side Gate Drivers |
文件: | 总24页 (文件大小:1355K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
May 2008
FAN3223 / FAN3224 / FAN3225
Dual 4A High-Speed, Low-Side Gate Drivers
Features
Description
The FAN3223-25 family of dual 4A gate drivers is
designed to drive N-channel enhancement-mode
MOSFETs in low-side switching applications by
providing high peak current pulses during the short
switching intervals. The driver is available with either
TTL or CMOS input thresholds. Internal circuitry
provides an under-voltage lockout function by holding
the output LOW until the supply voltage is within the
operating range. In addition, the drivers feature
matched internal propagation delays between A and B
channels for applications requiring dual gate drives with
critical timing, such as synchronous rectifiers. This also
enables connecting two drivers in parallel to effectively
double the current capability driving a single MOSFET.
Industry-Standard Pinouts
4.5 to 18V Operating Range
5A Peak Sink/Source at VDD = 12V
4.3A Sink / 2.8A Source at VOUT = 6V
Choice of TTL or CMOS Input Thresholds
Three Versions of Dual Independent Drivers:
-
-
-
Dual Inverting + Enable (FAN3223)
Dual Non-Inverting + Enable (FAN3224)
Dual-Inputs (FAN3225)
Internal Resistors Turn Driver Off If No Inputs
MillerDrive™ Technology
The FAN322X drivers incorporate MillerDrive™
architecture for the final output stage. This bipolar-
MOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize switching loss, while providing rail-
to-rail voltage swing and reverse current capability.
12ns / 9ns Typical Rise/Fall Times with 2.2nF Load
Typical Propagation Delay Under 20ns Matched
within 1ns to the Other Channel
Double Current Capability by Paralleling Channels
8-Lead 3x3mm MLP or 8-Lead SOIC Package
Rated from –40°C to +125°C Ambient
The FAN3223 offers two inverting drivers and the
FAN3224 offers two non-inverting drivers. Each device
has dual independent enable pins that default to ON if
not connected. In the FAN3225, each channel has dual
inputs of opposite polarity, which allows configuration
as non-inverting or inverting with an optional enable
function using the second input. If one or both inputs
are left unconnected, internal resistors bias the inputs
such that the output is pulled LOW to hold the power
MOSFET OFF.
Applications
Switch-Mode Power Supplies
High-Efficiency MOSFET Switching
Synchronous Rectifier Circuits
DC-to-DC Converters
Motor Control
FAN3223
FAN3224
FAN3225
Figure 1. Pin Configurations
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
Ordering Information
Input
Threshold
Packing
Method
Quantity
per Reel
Part Number
Logic
Package
FAN3223CMPX
FAN3223CMX
3x3mm MLP-8
SOIC-8
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
CMOS
TTL
Dual Inverting Channels + Dual Enable
FAN3223TMPX
FAN3223TMX
FAN3224CMPX
FAN3224CMX
FAN3224TMPX
FAN3224TMX
FAN3225CMPX
FAN3225CMX
FAN3225TMPX
FAN3225TMX
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
CMOS
TTL
Dual Non-Inverting Channels + Dual
Enable
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
CMOS
TTL
Dual Channels of Two-Input / One-
Output Drivers
3x3mm MLP-8
SOIC-8
All standard Fairchild Semiconductor products are RoHS compliant and many are also “GREEN” or going green. For Fairchild’s
definition of “green” please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Package Outlines
Figure 2. 3x3mm MLP-8 (Top View)
Figure 3. SOIC-8 (Top View)
Thermal Characteristics(1)
(2)
(3)
(4)
(5)
(6)
Package
Units
°C/W
ΘJL
ΘJT
ΘJA
ΨJB
ΨJT
1.2
64
42
2.8
0.7
8-Lead 3x3mm Molded Leadless Package (MLP)
8-Pin Small Outline Integrated Circuit (SOIC)
Notes:
38
29
87
41
2.3
°C/W
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
3. Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
4. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and
JESD51-7, as appropriate.
5. Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
6. Psi_JT (ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 4.
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
2
FAN3223
FAN3224
FAN3225
Figure 4. Pin Assignments (Repeated)
Pin Definitions
Name
Pin Description
Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
ENA
Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
ENB
GND
INA
Ground. Common ground reference for input and output circuits.
Input to Channel A.
INA+ Non-Inverting Input to Channel A. Connect to VDD to enable output.
INA-
INB
Inverting Input to Channel A. Connect to GND to enable output.
Input to Channel B.
INB+ Non-Inverting Input to Channel B. Connect to VDD to enable output.
INB-
Inverting Input to Channel B. Connect to GND to enable output.
OUTA Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
OUTB Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is
OUTA
above UVLO threshold.
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
OUTB
Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current.
P1
VDD
Supply Voltage. Provides power to the IC.
Output Logic
FAN3223 (x=A or B)
FAN3224 (x=A or B)
FAN3225 (x=A or B)
ENx
INx
ENx
INx
OUTx
INx+
INx−
OUTx
OUTx
0
0
1(7)
0
0
1
0
0
0(7)
0
0
0
1
0(7)
0(7)
1
0
1(7)
0
0
1
0
0
0
1
1(7)
1(7)
0
1(7)
1(7)
1(7)
0(7)
1
0
1(7)
1
Note:
7. Default input signal if no external connection is made.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
3
Block Diagrams
Figure 5. FAN3223 Block Diagram
Figure 6. FAN3224 Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
4
Block Diagrams
Figure 7. FAN3225 Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
5
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD
Parameter
Min.
Max.
Unit
V
VDD to PGND
-0.3
20.0
VEN
ENA and ENB to GND
GND - 0.3 VDD + 0.3
GND - 0.3 VDD + 0.3
GND - 0.3 VDD + 0.3
+260
V
VIN
INA, INA+, INA–, INB, INB+ and INB– to GND
OUTA and OUTB to GND
V
VOUT
TL
V
Lead Soldering Temperature (10 Seconds)
Junction Temperature
ºC
ºC
ºC
kV
kV
TJ
-55
-65
4
+150
+150
TSTG
Storage Temperature
Human Body Model, JEDEC JESD22-A114
Charged Device Model, JEDEC JESD22-C101
Electrostatic Discharge
Protection Level
ESD
1
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VDD
Parameter
Min.
4.5
0
Max.
18.0
VDD
Unit
V
Supply Voltage Range
VEN
Enable Voltage ENA and ENB
V
VIN
Input Voltage INA, INA+, INA–, INB, INB+ and INB–
Operating Ambient Temperature
0
VDD
V
TA
-40
+125
ºC
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
6
Electrical Characteristics
Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Supply
VDD
Parameter
Conditions
Min. Typ. Max. Unit
Operating Range
4.5
18.0
0.70 0.95
0.21 0.35
V
mA
mA
V
All except FAN3225C
FAN3225C(8)
Supply Current,
Inputs / EN Not Connected
IDD
VON
Turn-On Voltage
Turn-Off Voltage
INA=ENA=VDD, INB=ENB=0V
INA=ENA=VDD, INB=ENB=0V
3.5
3.3
3.9
3.7
4.3
4.1
VOFF
V
Inputs (FAN322xT)(9)
VIL_T
VIH_T
IIN+
INx Logic Low Threshold
0.8
1.2
1.6
V
V
INx Logic High Threshold
Non-inverting Input
2.0
175.0
1.5
IN from 0 to VDD
IN from 0 to VDD
-1.5
-175.0
0.2
µA
µA
V
IIN-
Inverting Input
VHYS_T
TTL Logic Hysteresis Voltage
0.4
0.8
Inputs (FAN322xC)(9)
VIL_C
VIH_C
IINL
INx Logic Low Threshold
30
38
55
%VDD
%VDD
µA
INx Logic High Threshold
IN Current, Low
70
175
1
IN from 0 to VDD
IN from 0 to VDD
-1
IINH
IN Current, High
-175
µA
VHYS_C CMOS Logic Hysteresis Voltage
ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T)
17
%VDD
VENL
VENH
VHYS_T
RPU
Enable Logic Low Threshold
Enable Logic High Threshold
TTL Logic Hysteresis Voltage(10)
Enable Pull-up Resistance(10)
EN from 5V to 0V
EN from 0V to 5V
0.8
1.2
1.6
0.4
100
17
V
V
2.0
V
kΩ
ns
ns
tD1, tD2 Propagation Delay, EN Rising(11)
tD1, tD2 Propagation Delay, EN Falling(11)
0 - 5VIN, 1V/ns Slew Rate
0 - 5VIN, 1V/ns Slew Rate
9
26
28
11
18
Continued on the following page…
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
7
Electrical Characteristics (Continued)
Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Output
Parameter
Conditions
Min. Typ. Max. Unit
OUT at VDD/2,
CLOAD=0.22µF, f=1kHz
ISINK
OUT Current, Mid-Voltage, Sinking(10)
4.3
A
A
OUT at VDD/2,
CLOAD=0.22µF, f=1kHz
ISOURCE
IPK_SINK
OUT Current, Mid-Voltage, Sourcing(10)
OUT Current, Peak, Sinking(10)
-2.8
CLOAD=0.22µF, f=1kHz
CLOAD=0.22µF, f=1kHz
CLOAD=2200pF
5
-5
12
9
A
A
IPK_SOURCE OUT Current, Peak, Sourcing(10)
tRISE
tFALL
Output Rise Time(11)
Output Fall Time(11)
20
17
ns
ns
CLOAD=2200pF
Output Propagation Delay, CMOS
Inputs(11)
Output Propagation Delay, TTL Inputs(11) 0 - 5VIN, 1V/ns Slew Rate
tD1, tD2
tD1, tD2
0 - 12VIN, 1V/ns Slew Rate
10
9
18
17
2
29
29
4
ns
ns
Propagation Matching Between
Channels
INA=INB, OUTA and OUTB
at 50% point
ns
IRVS
Output Reverse Current Withstand(10)
500
mA
Notes:
8. Lower supply current due to inactive TTL circuitry.
9. EN inputs have TTL thresholds; refer to the ENABLE section
10. Not tested in production.
11. See Timing Diagrams of Figure 8 and Figure 9.
Timing Diagrams
Figure 8. Non-inverting
Figure 9. Inverting
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
8
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 10. IDD (Static) vs. Supply Voltage(12)
Figure 11. IDD (Static) vs. Supply Voltage(12)
Figure 12. IDD (Static) vs. Supply Voltage(12)
Figure 13. IDD (No-Load) vs. Frequency
Figure 14. IDD (No-Load) vs. Frequency
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
9
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 15. IDD (2.2nF Load) vs. Frequency
Figure 16. IDD (2.2nF Load) vs. Frequency
Figure 17. IDD (Static) vs. Temperature(12)
Figure 18. IDD (Static) vs. Temperature(12)
Figure 19. IDD (Static) vs. Temperature(12)
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
10
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 20. Input Thresholds vs. Supply Voltage
Figure 21. Input Thresholds vs. Supply Voltage
Figure 22. Input Threshold % vs. Supply Voltage
Figure 23. Input Thresholds vs. Temperature
Figure 24. Input Thresholds vs. Temperature
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
11
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 25. UVLO Thresholds vs. Temperature
Figure 27. Propagation Delay vs. Supply Voltage
Figure 29. Propagation Delay vs. Supply Voltage
Figure 26. UVLO Threshold vs. Temperature
Figure 28. Propagation Delay vs. Supply Voltage
Figure 30. Propagation Delay vs. Supply Voltage
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
12
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 31. Propagation Delays vs. Temperature
Figure 32. Propagation Delays vs. Temperature
Figure 33. Propagation Delays vs. Temperature
Figure 34. Propagation Delays vs. Temperature
Figure 35. Fall Time vs. Supply Voltage
Figure 36.
Rise Time vs. Supply Voltage
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
13
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 37.
Rise and Fall Times vs. Temperature
Figure 38. Rise/Fall Waveforms with 2.2nF Load
Figure 39. Rise/Fall Waveforms with 10nF Load
Figure 40. Quasi-Static Source Current
with VDD=12V(13)
Figure 41. Quasi-Static Sink Current with VDD=12V(13)
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
14
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 42. Quasi-Static Source Current
Figure 43. Quasi-Static Sink Current with VDD=8V(13)
with VDD=8V(13)
Notes:
12. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static IDD increases
by the current flowing through the corresponding pull-up/down resistor shown in the block diagram.
13. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the
current-measurement loop.
Test Circuit
Figure 44. Quasi-Static IOUT / VOUT Test Circuit
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
15
Applications Information
Input Thresholds
MillerDrive™ Gate Drive Technology
Each member of the FAN322x driver family consists of
two identical channels that may be used independently
at rated current or connected in parallel to double the
individual current capacity. In the FAN3223 and
FAN3224, channels A and B can be enabled or
disabled independently using ENA or ENB, respectively.
The EN pin has TTL thresholds for parts with either
CMOS or TTL input thresholds. If ENA and ENB are not
connected, an internal pull-up resistor enables the
driver channels by default. ENA and ENB have TTL
thresholds in parts with either TTL or CMOS INx
threshold. If the channel A and channel B inputs and
outputs are connected in parallel to increase the driver
current capacity, ENA and ENB should be connected
and driven together.
FAN322x gate drivers incorporate the MillerDrive™
architecture shown in Figure 45. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT swings between 1/3 to 2/3
VDD and the MOS devices pull the output to the HIGH or
LOW rail.
The purpose of the MillerDrive™ architecture is to
speed up switching by providing high current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
For applications that have zero voltage switching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast switching even
though the Miller plateau is not present. This situation
often occurs in synchronous rectifier applications
because the body diode is generally conducting before
the MOSFET is switched ON.
The FAN322x family offers versions in either TTL or
CMOS input thresholds. In the FAN322xT, the input
thresholds meet industry-standard TTL-logic thresholds
independent of the VDD voltage, and there is a
hysteresis voltage of approximately 0.4V. These levels
permit the inputs to be driven from a range of input logic
signal levels for which a voltage over 2V is considered
logic HIGH. The driving signal for the TTL inputs should
have fast rising and falling edges with a slew rate of
6V/µs or faster, so a rise time from 0 to 3.3V should be
550ns or less. With reduced slew rate, circuit noise
could cause the driver input voltage to exceed the
hysteresis voltage and retrigger the driver input,
causing erratic operation.
The output pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slower rise or fall
time at the MOSFET gate is needed.
In the FAN322xC, the logic input thresholds are
dependent on the VDD level and, with VDD of 12V, the
logic rising edge threshold is approximately 55% of VDD
and the input falling edge threshold is approximately
38% of VDD. The CMOS input configuration offers a
hysteresis voltage of approximately 17% of VDD. The
CMOS inputs can be used with relatively slow edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
window. This allows setting precise timing intervals by
fitting an R-C circuit between the controlling signal and
the IN pin of the driver. The slow rising edge at the IN
pin of the driver introduces a delay between the
controlling signal and the OUT pin of the driver.
Figure 45. MillerDrive™ Output Architecture
Under-Voltage Lockout
The FAN322x start-up logic is optimized to drive
ground-referenced N-channel MOSFETs with an under-
voltage lockout (UVLO) function to ensure that the IC
starts up in an orderly fashion. When VDD is rising, yet
below the 3.9V operational level, this circuit holds the
output LOW, regardless of the status of the input pins.
After the part is active, the supply voltage must drop
0.2V before the part shuts down. This hysteresis helps
prevent chatter when low VDD supply voltages have
noise from the power switching. This configuration is not
suitable for driving high-side P-channel MOSFETs
because the low output voltage of the driver would turn
the P-channel MOSFET ON with VDD below 3.9V.
Static Supply Current
In the IDD (static) typical performance characteristics
(Figure 10 - Figure 12 and Figure 17 - Figure 19), the
curve is produced with all inputs/enables floating (OUT
is low) and indicates the lowest static IDD current for the
tested configuration. For other states, additional current
flows through the 100kΩ resistors on the inputs and
outputs shown in the block diagram of each part (see
Figure 5 - Figure 7). In these cases, the actual static IDD
current is the value obtained from the curves plus this
additional current.
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
16
best results, make connections to all pins as short
and direct as possible.
VDD Bypass Capacitor Guidelines
To enable this IC to turn a device ON quickly, a local
high-frequency bypass capacitor CBYP with low ESR and
ESL should be connected between the VDD and GND
pins with minimal trace length. This capacitor is in
addition to bulk electrolytic capacitance of 10µF to 47µF
commonly found on driver and controller bias circuits.
The FAN322x is compatible with many other
industry-standard drivers. In single input parts with
enable pins, there is an internal 100kΩ resistor tied
to VDD to enable the driver by default; this should
be considered in the PCB layout.
The turn-on and turn-off current paths should be
minimized, as discussed in the following section.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply to ≤5%. This
is often achieved with a value ≥20 times the equivalent
Figure 46 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn
the MOSFET ON. The current is supplied from the local
bypass capacitor, CBYP, and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance
in the path should be minimized. The localized CBYP
acts to contain the high peak current pulses within this
driver-MOSFET circuit, preventing them from disturbing
the sensitive analog circuitry in the PWM controller.
load capacitance CEQV, defined here as QGATE/VDD
.
Ceramic capacitors of 0.1µF to 1µF or larger are
common choices, as are dielectrics, such as X5R and
X7R with good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV, or
CBYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10nF mounted
closest to the VDD and GND pins to carry the higher
frequency components of the current pulses. The
bypass capacitor must provide the pulsed current from
both of the driver channels and, if the drivers are
switching simultaneously, the combined peak current
sourced from the CBYP would be twice as large as when
a single channel is switching.
Layout and Connection Guidelines
The FAN3223-25 family of gate drivers incorporates
fast-reacting input circuits, short propagation delays,
and powerful output stages capable of delivering
current peaks over 4A to facilitate voltage transition
times from under 10ns to over 150ns. The following
layout and connection guidelines are strongly
recommended:
Figure 46. Current Path for MOSFET Turn-on
Keep high-current output and power ground paths
separate logic and enable input signals and signal
ground paths. This is especially critical when
dealing with TTL-level logic thresholds at driver
inputs and enable pins.
Figure 47 shows the current path when the gate driver
turns the MOSFET OFF. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and
surrounding circuitry.
If the inputs to a channel are not externally
connected, the internal 100kΩ resistors indicated
on block diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of
an unused channel to VDD or GND using short
traces to prevent noise from causing spurious
output switching.
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
triggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts with long input, enable, or output leads. For
Figure 47. Current Path for MOSFET Turn-off
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
17
Truth Table of Logic Operation
Operational Waveforms
The FAN3225 truth table indicates the operational states
using the dual-input configuration. In a non-inverting
driver configuration, the IN- pin should be a logic LOW
signal. If the IN- pin is connected to logic HIGH, a disable
function is realized, and the driver output remains LOW
regardless of the state of the IN+ pin.
At power-up, the driver output remains LOW until the
VDD voltage reaches the turn-on threshold. The
magnitude of the OUT pulses rises with VDD until
steady-state VDD is reached. The non-inverting
operation illustrated in Figure 50 shows that the output
remains LOW until the UVLO threshold is reached, then
the output is in-phase with the input.
IN+
0
IN-
0
OUT
0
0
1
0
0
1
1
0
1
1
In the non-inverting driver configuration in Figure 48,
the IN- pin is tied to ground and the input signal (PWM)
is applied to IN+ pin. The IN- pin can be connected to
logic HIGH to disable the driver and the output remains
LOW, regardless of the state of the IN+ pin.
VDD
IN+
PWM
OUT
FAN3225
IN-
GND
Figure 50. Non-Inverting Start-Up Waveforms
For the inverting configuration of Figure 49, start-up
waveforms are shown in Figure 51. With IN+ tied to
VDD and the input signal applied to IN–, the OUT
pulses are inverted with respect to the input. At power-
up, the inverted output remains LOW until the VDD
voltage reaches the turn-on threshold, then it follows
the input with inverted phase.
Figure 48. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver application in Figure 49, the IN+
pin is tied HIGH. Pulling the IN+ pin to GND forces the
output LOW, regardless of the state of the IN- pin.
VDD
Turn-on threshold
VDD
IN+
IN-
OUT
FAN3225
IN-
PWM
IN+
(VDD)
GND
Figure 49. Dual-Input Driver Enabled,
Inverting Configuration
OUT
Figure 51. Inverting Start-Up Waveforms
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
18
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure that the part is operating within
acceptable temperature limits.
To give a numerical example, if the synchronous
rectifier switches in the forward converter of Figure 52
are FDMS8660S, the datasheet gives a total gate
charge of 60nC at VGS = 7V, so two devices in parallel
would have 120nC gate charge. At
a switching
frequency of 300kHz, the total power dissipation is:
PGATE = 120nC • 7V • 300kHz • 2 = 0.5W
PDYNAMIC = 1.5mA • 7V • 2 = 0.021W
PTOTAL = 0.52W
The total power dissipation in a gate driver is the sum of
(5)
(6)
(7)
two components, PGATE and PDYNAMIC
:
PTOTAL = PGATE + PDYNAMIC
(1)
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit
time) to switch the load MOSFET ON and OFF at
the switching frequency. The power dissipation that
results from driving a MOSFET at a specified gate-
source voltage, VGS, with gate charge, QG, at
switching frequency, FSW, is determined by:
The SOIC-8 has
characterization parameter of
a
junction-to-board thermal
ψJB
= 42°C/W. In a
system application, the localized temperature around
the device is a function of the layout and construction of
the PCB along with airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; with 80%
derating, TJ would be limited to 120°C. Rearranging
Equation 4 determines the board temperature required
to maintain the junction temperature below 120°C:
PGATE = QG • VGS • FSW • n
(2)
n is the number of driver channels in use (1 or 2).
Dynamic Pre-drive / Shoot-through Current: A
power loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-down resistors, can be
obtained using the “IDD (No-Load) vs. Frequency”
graphs in Typical Performance Characteristics to
determine the current IDYNAMIC drawn from VDD
under actual operating conditions:
ψ
TB,MAX = TJ - PTOTAL
•
(8)
(9)
JB
TB,MAX = 120°C – 0.52W • 42°C/W = 98°C
For comparison, replace the SOIC-8 used in the
previous example with the 3x3mm MLP package with
ψJB
= 2.8°C/W. The 3x3mm MLP package could
operate at PCB temperature of 118°C, while
a
PDYNAMIC = IDYNAMIC • VDD • n
(3)
maintaining the junction temperature below 120°C. This
illustrates that the physically smaller MLP package with
thermal pad offers a more conductive path to remove
the heat from the driver. Consider tradeoffs between
reducing overall circuit size with junction temperature
reduction for increased reliability.
Once the power dissipated in the driver is determined,
the driver junction rise with respect to circuit board can
be evaluated using the following thermal equation,
ψJB
assuming
was determined for a similar thermal
design (heat sinking and air flow):
ψ
TJ
= PTOTAL
•
JB + TB
(4)
where:
TJ
= driver junction temperature
ψJB
= (psi) thermal characterization parameter relating
temperature rise to total power dissipation
TB = board temperature in location as defined in
the Thermal Characteristics table.
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
19
Typical Application Diagrams
Figure 52. High Current Forward Converter
with Synchronous Rectification
Figure 53.
Center-tapped Bridge Output with
Synchronous Rectifiers
Vin
QC
QD
QA
QB
FAN3224
PWM-A
FAN3227
SR-1
Secondary
Phase Shift
Controller
PWM-B
PWM-C
SR-2
FAN3227
PWM-D
Figure 54. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous Rectifiers
(Simplified)
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
20
Table 1.
Related Products
Gate
Part
Number
Input
Threshold
Type
Drive(14)
Logic
Package
(Sink/Src)
FAN3100C Single 2A +2.5A / -1.8A CMOS
FAN3100T Single 2A +2.5A / -1.8A TTL
Single Channel of Two-Input/One-Output
Single Channel of Two-Input/One-Output
Dual Inverting Channels + Dual Enable
SOT23-5, MLP6
SOT23-5, MLP6
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
FAN3226C Dual 2A
FAN3226T Dual 2A
FAN3227C Dual 2A
FAN3227T Dual 2A
FAN3228C Dual 2A
FAN3228T Dual 2A
FAN3229C Dual 2A
FAN3229T Dual 2A
FAN3223C Dual 4A
FAN3223T Dual 4A
FAN3224C Dual 4A
FAN3224T Dual 4A
FAN3225C Dual 4A
+2.4A / -1.6A CMOS
+2.4A / -1.6A TTL
+2.4A / -1.6A CMOS
+2.4A / -1.6A TTL
+2.4A / -1.6A CMOS
+2.4A / -1.6A TTL
+2.4A / -1.6A CMOS
+2.4A / -1.6A TTL
+4.3A / -2.8A CMOS
+4.3A / -2.8A TTL
+4.3A / -2.8A CMOS
+4.3A / -2.8A TTL
+4.3A / -2.8A CMOS
+4.3A / -2.8A TTL
Dual Inverting Channels + Dual Enable
Dual Non-Inverting Channels + Dual Enable
Dual Non-Inverting Channels + Dual Enable
Dual Channels of Two-Input/One-Output, Pin Config.1
Dual Channels of Two-Input/One-Output, Pin Config.1
Dual Channels of Two-Input/One-Output, Pin Config.2
Dual Channels of Two-Input/One-Output, Pin Config.2
Dual Inverting Channels + Dual Enable
Dual Inverting Channels + Dual Enable
Dual Non-Inverting Channels + Dual Enable
Dual Non-Inverting Channels + Dual Enable
Dual Channels of Two-Input/One-Output
Dual Channels of Two-Input/One-Output
FAN3225T Dual 4A
Note:
14. Typical currents with OUT at 6V and VDD = 12V.
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
21
Physical Dimensions
2X
0.8 MAX
2X
RECOMMENDED LAND PATTERN
0.05
0.00
SEATING
PLANE
A. CONFORMS TO JEDEC REGISTRATION MO-229,
VARIATION VEEC, DATED 11/2001
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. FILENAME: MKT-MLP08Drev2
Figure 55. 3x3mm, 8-Lead Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
22
Physical Dimensions (Continued)
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 56. 8-Lead SOIC
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
23
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
24
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