FAN3223CMX_12_技术文档

August 2012

FAN3223 / FAN3224 / FAN3225_F085

Dual 4A High-Speed, Low-Side Gate Drivers

Features

Description

The FAN3223-25 family of dual 4A gate drivers is

designed to drive N-channel enhancement-mode

MOSFETs in low-side switching applications by

providing high peak current pulses during the short

switching intervals. The driver is available with either

TTL or CMOS input thresholds. Internal circuitry

provides an under-voltage lockout function by holding

the output LOW until the supply voltage is within the

operating range. In addition, the drivers feature matched

internal propagation delays between A and B channels

for applications requiring dual gate drives with critical

timing, such as synchronous rectifiers. This also

enables connecting two drivers in parallel to effectively

double the current capability driving a single MOSFET.

Qualified to AEC Q-100

4.5 to 18V Operating Range

5A Peak Sink/Source at V_DD= 12V

4.3A Sink / 2.8A Source at V_OUT= 6V

Choice of TTL or CMOS Input Thresholds

Three Versions of Dual Independent Drivers:

-

Dual Inverting + Enable (FAN3223)

Dual Non-Inverting + Enable (FAN3224)

Dual-Inputs (FAN3225)

Internal Resistors Turn Driver Off If No Inputs

MillerDrive™ Technology

The FAN322X drivers incorporate MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize switching loss, while providing rail-

to-rail voltage swing and reverse current capability.

12ns / 9ns Typical Rise/Fall Times with 2.2nF Load

Typical Propagation Delay Under 20ns Matched

within 1ns to the Other Channel

Double Current Capability by Paralleling Channels

8-Lead SOIC Package

The FAN3223 offers two inverting drivers and the

FAN3224 offers two non-inverting drivers. Each device

has dual independent enable pins that default to ON if

not connected. In the FAN3225, each channel has dual

inputs of opposite polarity, which allows configuration as

non-inverting or inverting with an optional enable

function using the second input. If one or both inputs are

left unconnected, internal resistors bias the inputs such

that the output is pulled LOW to hold the power

MOSFET OFF.

Rated from –40°C to +125°C Ambient

Applications

Switch-Mode Power Supplies

High-Efficiency MOSFET Switching

Synchronous Rectifier Circuits

DC-to-DC Converters

Motor Control

Related Resources

AN-6069: Application Review and Comparative

Evaluation of Low-Side Gate Drivers

FAN3223

FAN3224

FAN3225

Figure 1. Pin Configurations

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

Ordering Information

Input

Threshold

Packing

Method

Quantity

per Reel

Eco

Status

Part Number

Logic

Package

FAN3223CMX_F085

FAN3223TMX_F085

FAN3224CMX_F085

FAN3224TMX_F085

FAN3225CMX_F085

FAN3225TMX_F085

CMOS

TTL

SOIC-8

RoHS

Tape & Reel

2,500

Dual Inverting Channels +

Dual Enable

CMOS

TTL

Dual Non-Inverting Channels

+ Dual Enable

CMOS

TTL

Dual Channels of Two-Input /

One-Output Drivers

For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

Package Outline

Figure 2. SOIC-8 (Top View)

Thermal Characteristics⁽¹⁾

(2)

(3)

(4)

(5)

(6)

Package

Units

Θ_JL

Θ_JT

Θ_JA

Ψ_JB

Ψ_JT

38

29

87

41

2.3

°C/W

8-Pin Small Outline Integrated Circuit (SOIC)

Notes:

1. Estimates derived from thermal simulation; actual values depend on the application.

2. Theta_JL ( _JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any

thermal pad) that are typically soldered to a PCB.

Θ

3. Theta_JT (

Θ

_JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is

held at a uniform temperature by a top-side heatsink.

4. Theta_JA (Θ_JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.

The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,

JESD51-5, and JESD51-7, as appropriate.

5. Psi_JB (Ψ_JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an

application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board

reference is defined as the PCB copper adjacent to pin 6.

6. Psi_JT (

Ψ_JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and

the center of the top of the package for the thermal environment defined in Note 4.

FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

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2

FAN3223

FAN3224

FAN3225

Figure 3. Pin Assignments (Repeated)

Pin Definitions

Name

Pin Description

Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and

CMOS INx threshold.

ENA

Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and

CMOS INx threshold.

ENB

GND Ground. Common ground reference for input and output circuits.

INA

Input to Channel A.

INA+ Non-Inverting Input to Channel A. Connect to VDD to enable output.

INA-

INB

Inverting Input to Channel A. Connect to GND to enable output.

Input to Channel B.

INB+ Non-Inverting Input to Channel B. Connect to VDD to enable output.

INB-

Inverting Input to Channel B. Connect to GND to enable output.

OUTA Gate Drive Output A: Held LOW unless required input(s) are present and V_DDis above UVLO threshold.

OUTB Gate Drive Output B: Held LOW unless required input(s) are present and V_DDis above UVLO threshold.

Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V_DDis

OUTA

above UVLO threshold.

Gate Drive Output B (inverted from the input): Held LOW unless required input is present and V_DDis

above UVLO threshold.

OUTB

VDD

Supply Voltage. Provides power to the IC.

Output Logic

FAN3223 (x=A or B)

FAN3224 (x=A or B)

FAN3225 (x=A or B)

ENx

INx

ENx

INx

OUTx

INx+

INx−

OUTx

0

1⁽⁷⁾

0

1

0

0⁽⁷⁾

0

1

0⁽⁷⁾

1

0

1⁽⁷⁾

0

1

0

1

1⁽⁷⁾

0⁽⁷⁾

1

0

1⁽⁷⁾

1

Note:

7. Default input signal if no external connection is made.

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

3

Block Diagrams

Figure 4. FAN3223 Block Diagram

Figure 5. FAN3224 Block Diagram

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

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Block Diagrams

Figure 6. FAN3225 Block Diagram

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

5

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_DD

Parameter

Min.

Max.

Unit

V

VDD to PGND

-0.3

20.0

V_EN

ENA and ENB to GND

GND - 0.3 V_DD+ 0.3

+260

V

V_IN

INA, INA+, INA–, INB, INB+ and INB– to GND

OUTA and OUTB to GND

V

V_OUT

T_L

V

Lead Soldering Temperature (10 Seconds)

Junction Temperature

ºC

kV

T_J

-55

-65

+150

3

T_STG

ESD

Storage Temperature

Human Body Model, JEDEC JESD22-A114

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DD

Parameter

Min.

4.5

0

Max.

18.0

V_DD

Unit

V

Supply Voltage Range

V_EN

Enable Voltage ENA and ENB

V

V_IN

Input Voltage INA, INA+, INA–, INB, INB+ and INB–

Operating Ambient Temperature

0

V_DD

V

T_A

-40

+125

ºC

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

6

Electrical Characteristics

Unless otherwise noted, V_DD=12V, T_J=-40°C to +125°C. Currents are defined as positive into the device and negative

out of the device.

Symbol

Supply

V_DD

Parameter

Conditions

Min. Typ. Max. Unit

Operating Range

4.5

18.0

0.95

0.35

4.5

V

mA

V

All except FAN3225C

0.70

0.21

3.9

Supply Current,

Inputs / EN Not Connected

I_DD

FAN3225C⁽⁸⁾

V_ON

Turn-On Voltage

Turn-Off Voltage

INA=ENA=VDD, INB=ENB=0V

3.4

3.2

V_OFF

3.7

4.3

V

Inputs (FAN322xT)⁽⁹⁾

V_{INL_T}

V_{INH_T}

I_{INx_T}

INx Logic Low Threshold

0.8

1.2

1.6

V

INx Logic High Threshold

Non-inverting Input Current

Inverting Input Current

2.0

1.5

IN = 0V

IN = V_DD

IN = 0V

IN = V_DD

-1.5

90

µA

V

120 175.0

-175.0 -120

-1.5

-90

1.5

1.0

Inverting Input Current

V_{HYS_T}TTL Logic Hysteresis Voltage

0.4

0.7

Inputs (FAN322xC)⁽⁹⁾

V_{INL_C}

INx Logic Low Threshold

30

38

55

%V_DD

V_{INH_C}

I_{INx_C}

INx Logic High Threshold

Non-Inverting Input Current

Inverting Input Current

70

1.5

175

-90

1.5

%V_DD

µA

IN = 0V

IN = V_DD

IN = 0V

IN = V_DD

-1.5

90

120

µA

-175

-1.5

-120

µA

Inverting Input Current

µA

V_{HYS_C}CMOS Logic Hysteresis Voltage

ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T)

17

%V_DD

V_ENL

V_ENH

Enable Logic Low Threshold

Enable Logic High Threshold

EN from 5V to 0V

EN from 0V to 5V

0.8

1.2

1.6

0.4

100

17

V

2.0

V_{HYS_T}TTL Logic Hysteresis Voltage⁽¹⁰⁾

V

R_PU

t_D3

Enable Pull-up Resistance⁽¹⁰⁾

kΩ

ns

EN to Output Propagation Delay ⁽¹¹⁾

0V to 5V EN, 1V/ns Slew Rate

5V to 0V EN, 1V/ns Slew Rate

9

29

31

t_D4

18

Continued on the following page…

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

7

Electrical Characteristics (Continued)

Unless otherwise noted, V_DD=12V, T_J=-40°C to +125°C. Currents are defined as positive into the device and negative

out of the device.

Symbol

Output

Parameter

Conditions

Min. Typ. Max. Unit

OUT at V_DD/2,

C_LOAD=0.22µF, f=1kHz

I_SINK

OUT Current, Mid-Voltage, Sinking⁽¹⁰⁾

4.3

A

OUT at V_DD/2,

C_LOAD=0.22µF, f=1kHz

I_SOURCE

I_{PK_SINK}

OUT Current, Mid-Voltage, Sourcing⁽¹⁰⁾

OUT Current, Peak, Sinking⁽¹⁰⁾

-2.8

C_LOAD=0.22µF, f=1kHz

5

A

I_{PK_SOURCE}OUT Current, Peak, Sourcing⁽¹⁰⁾

-5

V_OH

High Level Output Voltage

15

35

mV

V^OH= VDD – VOUT, IOUT = –1mA

V_OL

t_RISE

t_FALL

Low Level Output Voltage

Output Rise Time⁽¹¹⁾

Output Fall Time⁽¹¹⁾

IOUT = 1mA

10

12

9

25

20

17

mV

ns

C_LOAD=2200pF

ns

Output Propagation Delay, CMOS

Inputs⁽¹²⁾

t_D1, t_D2

0 - 12V_IN, 1V/ns Slew Rate

9

18

17

2

34

29

4

ns

Output Propagation Delay, TTL Inputs⁽¹²⁾0 - 5V_IN, 1V/ns Slew Rate

INA=INB, OUTA and OUTB

at 50% point

T_DEL.MATCHPropagation Matching Between Channels

ns

I_RVS

Output Reverse Current Withstand⁽¹⁰⁾

500

mA

Notes:

8. Lower supply current due to inactive TTL circuitry.

9. EN inputs have TTL thresholds; refer to the ENABLE section

10. Not tested in production.

11. See Timing Diagrams of Figure 9 and Figure 10.

12. See Timing Diagrams of Figure 7 and Figure 8.

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

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Timing Diagrams

90%

Output

10%

V_INH

Input

V_INL

t_D1

t_D2

t_FALL

Figure 7. Non-Inverting (EN HIGH or Floating)

t_RISE

Figure 8. Inverting (EN HIGH or Floating)

Figure 9. Non-Inverting (IN HIGH)

Figure 10. Inverting (IN LOW)

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 11. I_DD(Static) vs. Supply Voltage⁽¹³⁾

Figure 12. I_DD(Static) vs. Supply Voltage⁽¹³⁾

Figure 13. I_DD(Static) vs. Supply Voltage⁽¹³⁾

Figure 14. I_DD(No-Load) vs. Frequency

Figure 15. I_DD(No-Load) vs. Frequency

FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

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10

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 16. I_DD(2.2nF Load) vs. Frequency

Figure 17. I_DD(2.2nF Load) vs. Frequency

Figure 18. I_DD(Static) vs. Temperature⁽¹³⁾

Figure 19. I_DD(Static) vs. Temperature⁽¹³⁾

Figure 20. I_DD(Static) vs. Temperature⁽¹³⁾

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

11

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 21. Input Thresholds vs. Supply Voltage

Figure 22. Input Thresholds vs. Supply Voltage

Figure 23. Input Threshold % vs. Supply Voltage

Figure 24. Input Thresholds vs. Temperature

Figure 25. Input Thresholds vs. Temperature

FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

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12

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 26. UVLO Thresholds vs. Temperature

Figure 28. Propagation Delay vs. Supply Voltage

Figure 30. Propagation Delay vs. Supply Voltage

Figure 27. UVLO Threshold vs. Temperature

Figure 29. Propagation Delay vs. Supply Voltage

Figure 31. Propagation Delay vs. Supply Voltage

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

13

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 32. Propagation Delays vs. Temperature

Figure 33. Propagation Delays vs. Temperature

Figure 34. Propagation Delays vs. Temperature

Figure 35. Propagation Delays vs. Temperature

Figure 36. Fall Time vs. Supply Voltage

Figure 37.

Rise Time vs. Supply Voltage

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

14

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 38.

Rise and Fall Times vs. Temperature

Figure 39. Rise/Fall Waveforms with 2.2nF Load

Figure 40. Rise/Fall Waveforms with 10nF Load

Figure 41. Quasi-Static Source Current

with V_DD=12V⁽¹⁴⁾

Figure 42. Quasi-Static Sink Current with V_DD=12V⁽¹⁴⁾

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

15

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 43. Quasi-Static Source Current

Figure 44. Quasi-Static Sink Current with V_DD=8V⁽¹⁴⁾

with V_DD=8V⁽¹⁴⁾

Notes:

13. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static I_DDincreases by

the current flowing through the corresponding pull-up/down resistor shown in the block diagram.

14. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the

current-measurement loop.

Test Circuit

Figure 45. Quasi-Static I_OUT/ V_OUTTest Circuit

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

16

Applications Information

Input Thresholds

MillerDrive™ Gate Drive Technology

FAN322x gate drivers incorporate the MillerDrive™

architecture shown in Figure 46. For the output stage, a

combination of bipolar and MOS devices provide large

currents over a wide range of supply voltage and

temperature variations. The bipolar devices carry the

bulk of the current as OUT swings between 1/3 to 2/3

Each member of the FAN322x driver family consists of

two identical channels that may be used independently

at rated current or connected in parallel to double the

individual current capacity. In the FAN3223 and

FAN3224, channels A and B can be enabled or disabled

independently using ENA or ENB, respectively. The EN

pin has TTL thresholds for parts with either CMOS or

TTL input thresholds. If ENA and ENB are not

connected, an internal pull-up resistor enables the driver

channels by default. ENA and ENB have TTL thresholds

in parts with either TTL or CMOS INx threshold. If the

channel A and channel B inputs and outputs are

connected in parallel to increase the driver current

capacity, ENA and ENB should be connected and

driven together.

V_DDand the MOS devices pull the output to the HIGH or

LOW rail.

The purpose of the MillerDrive™ architecture is to

speed up switching by providing high current during the

Miller plateau region when the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

For applications that have zero voltage switching during

the MOSFET turn-on or turn-off interval, the driver

supplies high peak current for fast switching even

though the Miller plateau is not present. This situation

often occurs in synchronous rectifier applications

because the body diode is generally conducting before

the MOSFET is switched ON.

The FAN322x family offers versions in either TTL or

CMOS input thresholds. In the FAN322xT, the input

thresholds meet industry-standard TTL-logic thresholds

independent of the V_DDvoltage, and there is

a

hysteresis voltage of approximately 0.4V. These levels

permit the inputs to be driven from a range of input logic

signal levels for which a voltage over 2V is considered

logic HIGH. The driving signal for the TTL inputs should

have fast rising and falling edges with a slew rate of

6V/µs or faster, so a rise time from 0 to 3.3V should be

550ns or less. With reduced slew rate, circuit noise

could cause the driver input voltage to exceed the

hysteresis voltage and retrigger the driver input, causing

erratic operation.

The output pin slew rate is determined by V_DDvoltage

and the load on the output. It is not user adjustable, but

a series resistor can be added if a slower rise or fall time

at the MOSFET gate is needed.

V_DD

In the FAN322xC, the logic input thresholds are

dependent on the V_DDlevel and, with V_DDof 12V, the

logic rising edge threshold is approximately 55% of V_DD

and the input falling edge threshold is approximately

38% of V_DD. The CMOS input configuration offers a

hysteresis voltage of approximately 17% of V_DD. The

CMOS inputs can be used with relatively slow edges

(approaching DC) if good decoupling and bypass

techniques are incorporated in the system design to

prevent noise from violating the input voltage hysteresis

window. This allows setting precise timing intervals by

fitting an R-C circuit between the controlling signal and

the IN pin of the driver. The slow rising edge at the IN

pin of the driver introduces a delay between the

controlling signal and the OUT pin of the driver.

Input

stage

V_OUT

Figure 46. MillerDrive™ Output Architecture

Under-Voltage Lockout

The FAN322x start-up logic is optimized to drive

ground-referenced N-channel MOSFETs with an under-

voltage lockout (UVLO) function to ensure that the IC

starts up in an orderly fashion. When V_DDis rising, yet

below the 3.9V operational level, this circuit holds the

output LOW, regardless of the status of the input pins.

After the part is active, the supply voltage must drop

0.2V before the part shuts down. This hysteresis helps

prevent chatter when low V_DDsupply voltages have

noise from the power switching. This configuration is not

suitable for driving high-side P-channel MOSFETs

because the low output voltage of the driver would turn

the P-channel MOSFET ON with V_DDbelow 3.9V.

Static Supply Current

In the I_DD(static) typical performance characteristics

(Figure 11 - Figure 13 and Figure 18 - Figure 20), the

curve is produced with all inputs/enables floating (OUT

is low) and indicates the lowest static I_DDcurrent for the

tested configuration. For other states, additional current

flows through the 100kΩ resistors on the inputs and

outputs shown in the block diagram of each part (see -

Figure 6). In these cases, the actual static I_DDcurrent is

the value obtained from the curves plus this additional

current.

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

17

VDD Bypass Capacitor Guidelines

The FAN322x is compatible with many other

industry-standard drivers. In single input parts with

enable pins, there is an internal 100kΩ resistor tied

to VDD to enable the driver by default; this should

be considered in the PCB layout.

To enable this IC to turn a device ON quickly, a local

high-frequency bypass capacitor C_BYPwith low ESR and

ESL should be connected between the VDD and GND

pins with minimal trace length. This capacitor is in

addition to bulk electrolytic capacitance of 10µF to 47µF

commonly found on driver and controller bias circuits.

The turn-on and turn-off current paths should be

minimized, as discussed in the following section.

A typical criterion for choosing the value of C_BYPis to

keep the ripple voltage on the V_DDsupply to ≤5%. This

is often achieved with a value ≥20 times the equivalent

Figure 47 shows the pulsed gate drive current path

when the gate driver is supplying gate charge to turn the

MOSFET ON. The current is supplied from the local

bypass capacitor, C_BYP, and flows through the driver to

the MOSFET gate and to ground. To reach the high

peak currents possible, the resistance and inductance in

the path should be minimized. The localized C_BYPacts

to contain the high peak current pulses within this driver-

MOSFET circuit, preventing them from disturbing the

sensitive analog circuitry in the PWM controller.

load capacitance C_EQV, defined here as Q_GATE/V_DD

.

Ceramic capacitors of 0.1µF to 1µF or larger are

common choices, as are dielectrics, such as X5R and

X7R with good temperature characteristics and high

pulse current capability.

If circuit noise affects normal operation, the value of

C_BYPmay be increased to 50-100 times the C_EQV, or

C_BYPmay be split into two capacitors. One should be a

larger value, based on equivalent load capacitance, and

the other a smaller value, such as 1-10nF mounted

closest to the VDD and GND pins to carry the higher

frequency components of the current pulses. The

bypass capacitor must provide the pulsed current from

both of the driver channels and, if the drivers are

switching simultaneously, the combined peak current

sourced from the C_BYPwould be twice as large as when

a single channel is switching.

Layout and Connection Guidelines

The FAN3223-25 family of gate drivers incorporates

fast-reacting input circuits, short propagation delays,

and powerful output stages capable of delivering current

peaks over 4A to facilitate voltage transition times from

under 10ns to over 150ns. The following layout and

connection guidelines are strongly recommended:

Figure 47. Current Path for MOSFET Turn-on

Figure 48 shows the current path when the gate driver

turns the MOSFET OFF. Ideally, the driver shunts the

current directly to the source of the MOSFET in a small

circuit loop. For fast turn-off times, the resistance and

inductance in this path should be minimized.

Keep high-current output and power ground paths

separate logic and enable input signals and signal

ground paths. This is especially critical when

dealing with TTL-level logic thresholds at driver

inputs and enable pins.

Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed switching, while reducing the loop area that

can radiate EMI to the driver inputs and

surrounding circuitry.

If the inputs to a channel are not externally

connected, the internal 100kΩ resistors indicated

on block diagrams command a low output. In noisy

environments, it may be necessary to tie inputs of

an unused channel to VDD or GND using short

traces to prevent noise from causing spurious

output switching.

Figure 48. Current Path for MOSFET Turn-off

Many high-speed power circuits can be susceptible

to noise injected from their own output or other

external sources, possibly causing output re-

triggering. These effects can be obvious if the

circuit is tested in breadboard or non-optimal circuit

layouts with long input, enable, or output leads. For

best results, make connections to all pins as short

and direct as possible.

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

18

Truth Table of Logic Operation

Operational Waveforms

The FAN3225 truth table indicates the operational states

using the dual-input configuration. In a non-inverting

driver configuration, the IN- pin should be a logic LOW

signal. If the IN- pin is connected to logic HIGH, a disable

function is realized, and the driver output remains LOW

regardless of the state of the IN+ pin.

At power-up, the driver output remains LOW until the

V_DDvoltage reaches the turn-on threshold. The

magnitude of the OUT pulses rises with V_DDuntil

steady-state V_DDis reached. The non-inverting

operation illustrated in Figure 51 shows that the output

remains LOW until the UVLO threshold is reached, then

the output is in-phase with the input.

IN+

0

IN-

0

OUT

0

1

0

1

0

1

In the non-inverting driver configuration in Figure 49, the

IN- pin is tied to ground and the input signal (PWM) is

applied to IN+ pin. The IN- pin can be connected to logic

HIGH to disable the driver and the output remains LOW,

regardless of the state of the IN+ pin.

Figure 51. Non-Inverting Start-Up Waveforms

For the inverting configuration of Figure 50, start-up

waveforms are shown in Figure 52. With IN+ tied to

VDD and the input signal applied to IN–, the OUT

pulses are inverted with respect to the input. At power-

up, the inverted output remains LOW until the V_DD

voltage reaches the turn-on threshold, then it follows the

input with inverted phase.

Figure 49. Dual-Input Driver Enabled,

Non-Inverting Configuration

In the inverting driver application in Figure 50, the IN+

pin is tied HIGH. Pulling the IN+ pin to GND forces the

output LOW, regardless of the state of the IN- pin.

Figure 50. Dual-Input Driver Enabled,

Inverting Configuration

Figure 52. Inverting Start-Up Waveforms

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FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

19

Thermal Guidelines

Gate drivers used to switch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

power. It is important to determine the driver power

dissipation and the resulting junction temperature in the

application to ensure that the part is operating within

acceptable temperature limits.

To give a numerical example, if the synchronous

rectifier switches in the forward converter of Figure 53

are FDMS8660S, the datasheet gives a total gate

charge of 60nC at V_GS= 7V, so two devices in parallel

would have 120nC gate charge. At

a switching

frequency of 300kHz, the total power dissipation is:

The total power dissipation in a gate driver is the sum of

P_GATE= 120nC • 7V • 300kHz • 2 = 0.504W

(5)

(6)

(7)

two components, P_GATEand P_DYNAMIC

:

P

_DYNAMIC= 1.5mA • 7V • 2 = 0.021W

_TOTAL= 0.525W

P_TOTAL= P_GATE+ P_DYNAMIC

(1)

P

Gate Driving Loss: The most significant power loss

results from supplying gate current (charge per unit

time) to switch the load MOSFET ON and OFF at

the switching frequency. The power dissipation that

results from driving a MOSFET at a specified gate-

source voltage, V_GS, with gate charge, Q_G, at

switching frequency, F_SW, is determined by:

The SOIC-8 has

characterization parameter of

a

junction-to-board thermal

ψ_JB

= 42°C/W. In a

system application, the localized temperature around

the device is a function of the layout and construction of

the PCB along with airflow across the surfaces. To

ensure reliable operation, the maximum junction

temperature of the device must be prevented from

exceeding the maximum rating of 150°C; with 80%

derating, T_Jwould be limited to 120°C. Rearranging

Equation 4 determines the board temperature required

to maintain the junction temperature below 120°C:

P_GATE= Q_G• V_GS• F_SW• n

(2)

n is the number of driver channels in use (1 or 2).

Dynamic Pre-drive / Shoot-through Current: A

power loss resulting from internal current

consumption under dynamic operating conditions,

including pin pull-up / pull-down resistors, can be

obtained using the “I_DD(No-Load) vs. Frequency”

graphs in Typical Performance Characteristics to

determine the current I_DYNAMICdrawn from V_DD

under actual operating conditions:

ψ

T_B,MAX= T_J- P_TOTAL

•

(8)

(9)

JB

T_B,MAX= 120°C – 0.525W • 42°C/W = 98°C

P_DYNAMIC= I_DYNAMIC• V_DD• n

(3)

Once the power dissipated in the driver is determined,

the driver junction rise with respect to circuit board can

be evaluated using the following thermal equation,

ψ_JB

assuming

was determined for a similar thermal

design (heat sinking and air flow):

ψ

T_J

= P_TOTAL

•

_JB+ T_B

(4)

where:

T_J

= driver junction temperature

ψ_JB

= (psi) thermal characterization parameter

relating temperature rise to total power

dissipation

T_B= board temperature in location as defined in

the Thermal Characteristics table.

www.fairchildsemi.com

FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

20

Typical Application Diagrams

FAN3224

8

7

6

5

1

2

3

4

ENA

ENB

A

B

GND

VDD

Figure 53. High Current Forward Converter

with Synchronous Rectification

Figure 54.

Center-tapped Bridge Output with

Synchronous Rectifiers

Figure 55. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous Rectifiers

(Simplified)

FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0

www.fairchildsemi.com

21

Table 1.


型号：	FAN3223CMX_12
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Dual 4A High-Speed, Low-Side Gate Drivers 双4A高速，低侧栅极驱动器驱动器栅极栅极驱动
文件：	总24页 (文件大小：1729K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN3223CMX_12 [FAIRCHILD]

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