FAN3223TMX_技术文档

FAN3223 /FAN3224 /FAN3225

Dual 4-A High-Speed, Low-SideGate Drivers

Features

Description

The FA N3223-25 family of dual 4 A gate drivers is

designed to drive N-channel enhancement-mode

MOSFETs in low -side sw itching applications by

providing high peak current pulses during the short

sw itching intervals. The driver is available w ith either

TTL or CMOS input thresholds. Internal circuitry

provides an under-voltage lockout function by holding

the output LOW until the supply voltage is w ithin the

operating range. In addition, the drivers feature matched

internal propagation delays betw een A and B channels

for applications requiring dual gate drives w ith critical

timing, such as synchronous rectifiers. This also

enables connecting tw o drivers in parallel to effectively

double the current capability driving a single MOSFET.

.

Industry-Standard Pinouts

4.5-V to 18-V Operating Range

5-A Peak Sink/Source at V_DD=12 V

4.3-A Sink / 2.8-A Source at V_OUT=6 V

Choice of TTL or CMOS Input Thresholds

Three Versions of Dual Independent Drivers:

-

Dual Inverting + Enable (FAN3223)

Dual Non-Inverting + Enable (FAN3224)

Dual-Inputs (FAN3225)

.

Internal Resistors Turn Driver Off If No Inputs

MillerDrive™ Technology

The FAN322X drivers incorporate MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize sw itching loss, w hile providing rail-

to-rail voltage sw ing and reverse current capability.

12-ns / 9-ns Typical Rise/Fall Times (2.2-nF Load)

Under 20-ns Typical Propagation Delay Matched

w ithin 1 ns to the Other Channel

.

Double Current Capability by Paralleling Channels

8-Lead 3x3 mm MLP or 8-Lead SOIC Package

Rated from –40°C to +125°C Ambient

The FAN3223 offers two inverting drivers and the

FAN3224 offers tw o non-inverting drivers. Each device

has dual independent enable pins that default to ON if

not connected. In the FAN3225, each channel has dual

inputs of opposite polarity, w hich allow s configuration as

non-inverting or inverting w ith an optional enable

function using the second input. If one or both inputs are

left unconnected, internal resistors bias the inputs such

that the output is pulled LOW to hold the pow er

MOSFET OFF.

Automotive Qualified to AEC-Q100 (F085 Version)

Applications

.

Sw itch-Mode Pow er Supplies

High-Efficiency MOSFET Sw itching

Synchronous Rectifier Circuits

DC-to-DC Converters

Motor Control

Automotive-Qualified Systems (F085 version)

ENA

1

8

ENA

1

8

1

8

ENB

INA+

INA-

+

-

INA

GND

INB

2

3

4

7

6

5

OUTA

VDD

INA

GND

INB

2

3

4

7

6

5

OUTA

VDD

INB+

GND

2

3

4

7

6

5

OUTA

VDD

A

B

A

B

A

B

+

-

OUTB

INB-

FAN3223

FAN3224

FAN3225

Figure 1.

Pin Configurations

December-2017, Rev. 2

Publication Order Number

FAN3224/D

Ordering Information

Input

Threshold

Packing Quantity

Part Number

Logic

Package

Method

per Reel

FAN3223CMPX

3x3 mm MLP-8

SOIC-8

Tape & Reel

3,000

2,500

3,000

2,500

3,000

2,500

3,000

2,500

FAN3223CMX

FAN3223CMX-F085⁽¹⁾

CMOS

TTL

Dual Inverting

Channels + Dual

Enable

SOIC-8

FAN3223TMPX

3x3 mm MLP-8

SOIC-8

FAN3223TMX

FAN3223TMX-F085⁽¹⁾

SOIC-8

3x3 mm MLP-8

SOIC-8

FAN3224CMPX

FAN3224CMX

FAN3224CMX-F085⁽¹⁾

CMOS

SOIC-8

Dual Non-Inverting

Channels + Dual

Enable

3x3 mm MLP-8

SOIC-8

FAN3224TMPX

FAN3224TMX

TTL

FAN3224TMX-F085⁽¹⁾

FAN3224TUMX-F085⁽²⁾

FAN3225CMPX

2,500

3,000

2,500

3,000

2,500

SOIC-8

3x3 mm MLP-8

SOIC-8

FAN3225CMX

FAN3225CMX-F085⁽¹⁾

CMOS

TTL

Dual Channels of Tw o-

Input / One-Output

Drivers

SOIC-8

FAN3225TMPX

3x3 mm MLP-8

SOIC-8

FAN3225TMX

FAN3225TMX-F085⁽¹⁾

SOIC-8

Note s:

1. Qualified to AEC-Q100.

2. Modified UVLO thresholds.

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2

Package Outlines

1

2

3

8

7

6

1

2

3

4

8

7

6

5

4

5

Figure 2.

3x3 mm MLP-8 (Top View)

Figure 3.

SOIC-8 (Top View)

Thermal Characteristics⁽³⁾

(4)

(5)

(6)

(7)

(8)

Package

Θ_JL

Θ_JT

Θ_JA

Ψ_JB

Ψ_JT

Unit

°C/W

1.2

64

42

2.8

0.7

8-Lead 3x3 mm Molded Leadless Package (MLP)

8-Pin Small Outline Integrated Circuit (SOIC)

38

29

87

41

2.3

Notes:

3. Estimatesderived from thermal simulation; actual valuesdependon the application.

4. Theta_JL (Θ ): Thermal resistance betweenthe semiconductor junction andthe bottom surface of all the leads(including any

JL

thermal pad) that are typically solderedto a PCB.

5. Theta_JT (Θ ): Thermal resistance betweenthe semiconductor junction andthe top surface of the package,assuming it is

JT

held at a uniform temperature by a top-side heatsink.

6. Theta_JA (Θ_JA): Thermal resistance betweenjunction andambient,dependenton the PCB design, heat sinking, and airflow.

The value given isfor natural convection with noheatsinkusing a 2S2P board, asspecifiedin JEDEC standardsJESD51-2,

JESD51-5, and JESD51-7, asappropriate.

7. Psi _JB (Ψ_JB): Thermal characterizationparameter providingcorrelation betweensemiconductor junctiontemperature andan

application circuit board referencepoint for the thermal environment definedin Note 6. For the MLP-8package, the board

reference isdefined asthe PCB copper connectedto the thermal pad andprotrudingfrom either end of the package.For the

SOIC-8 package, the board reference isdefinedasthe PCB copper adjacent to pin 6.

8. Psi _JT (Ψ_JT): Thermal characterizationparameter providingcorrelation betweenthe semiconductor junction temperature and

the center of the top of the package for the thermal environmentdefined in Note6.

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3

ENA

1

8

ENA

1

8

1

8

ENB

INA+

INA-

+

-

INA

GND

INB

2

3

4

7

6

5

OUTA

VDD

INA

GND

INB

2

3

4

7

6

5

OUTA

VDD

INB+

GND

2

3

4

7

6

5

OUTA

VDD

A

B

A

B

A

B

+

-

OUTB

INB

-

FAN3223

FAN3224

FAN3225

Figure 4.

Pin Assignments (Repeated)

Pin Definitions

Name

Pin Description

Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and

CMOS INx threshold.

ENA

ENB

Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and

CMOS INx threshold.

GND

INA

Ground. Common ground reference for input and output circuits.

Input to Channel A.

INA+

INA-

INB

Non-Inverting Input to Channel A. Connect to VDD to enable output.

Inverting Input to Channel A. Connect to GND to enable output.

Input to Channel B.

INB+

INB-

Non-Inverting Input to Channel B. Connect to VDD to enable output.

Inverting Input to Channel B. Connect to GND to enable output.

OUTA Gate Drive Output A: Held LOW unless required input(s) are present and V_DDis above UVLO threshold.

OUTB Gate Drive Output B: Held LOW unless required input(s) are present and V_DDis above UVLO threshold.

Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V_DDis

OUTA

above UVLO threshold.

Gate Drive Output B (inverted from the input): Held LOW unless required input is present and V_DDis

above UVLO threshold.

OUTB

Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected

to GND; NOT suitable for carrying current.

P1

VDD

Supply Voltage. Provides pow er to the IC.

Output Logic

FAN3223 (x=A or B)

FAN3224 (x=A or B)

FAN3225 (x=A or B)

ENx

INx

ENx

INx

OUTx

INx+

INx−

OUTx

0

1⁽⁹⁾

0

1⁽⁹⁾

0

1

0

1⁽⁹⁾

0⁽⁹⁾

0

1

0⁽⁹⁾

1

0

1⁽⁹⁾

0

1

0

1

0⁽⁹⁾

1

1⁽⁹⁾

1

1⁽⁹⁾

Note:

9. Default input signal if no external connection is made.

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Block Diagrams

V_DD

100kΩ

ENA

1

8

ENB

V_DD

INA

2

3

OUTA

VDD

7

6

100kΩ

GND

UVLO

V_{DD_OK}

V_DD

100kΩ

OUTB

5

INB

4

100kΩ

Figure 5.

FAN3223 Block Diagram

V_DD

100kΩ

ENA

1

8

ENB

INA

2

7

6

OUTA

VDD

100kΩ

UVLO

GND

3

4

V_{DD_OK}

INB

5

OUTB

100kΩ

Figure 6.

FAN3224 Block Diagram

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5

Block Diagrams

V_DD

INA+

INA-

8

1

100kΩ

OUTA

VDD

7

6

100kΩ

V_{DD_OK}

GND

INB+

3

2

UVLO

V_DD

100kΩ

OUTB

5

INB-

4

100kΩ

Figure 7.

FAN3225 Block Diagram

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6

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_DD

V_EN

Parameter

Min.

Max. Unit

VDD to PGND

-0.3

20.0

V

ENA and ENB to GND

GND - 0.3 V_DD+ 0.3

+260

V_IN

INA, INA+, INA–, INB, INB+ and INB– to GND

OUTA and OUTB to GND DC

V

V_OUT

T_L

V

Lead Soldering Temperature (10 Seconds)

Junction Temperature

ºC

T_J

-55

-65

+150

T_STG

Storage Temperature

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. ON does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DD

Parameter

Min.

4.5

9.5

0

Max. Unit

Supply Voltage Range

18.0

V

V_DD

Supply Voltage Range (FAN3224TU only)

Enable Voltage ENA and ENB

V_EN

V_DD

V

V_IN

Input Voltage INA, INA+, INA–, INB, INB+ and INB–

0

V_DD

V

V_OUT

T_A

OUTA and OUTB to GND

Repetitive Pulse < 200 ns

-2.0

-40

V_DD+ 0.3

+125

V

Operating Ambient Temperature

ºC

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Electrical Characteristics

Unless otherw ise noted, V_DD=12 V, T_J=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Supply

V_DD

Operating Range

4.5

18.0

0.95

0.35

4.3

V

mA

V

All except FAN3225C

0.70

0.21

3.9

Supply Current, Inputs / EN Not

Connected

I_DD

(10)

FAN3225C

V_ON

Turn-On Voltage

Turn-Off Voltage

INA=ENA=V_DD, INB=ENB=0 V

3.5

3.3

V_OFF

3.7

4.1

V

FAN322xTMX-F085, FAN322xCMX-F085 (Automotive-Qualified Versions)

V_DD

Operating Range

4.5

18.0

1.20

0.35

4.5

V

mA

V

All Except FAN3225C

0.70

0.21

3.9

Supply Current, Inputs / EN Not

Connected⁽¹⁵⁾

I_DD

(10)

FAN3225C

Turn-On Voltage⁽¹⁵⁾

Turn-Off Voltage⁽¹⁵⁾

V_ON

INA=ENA=V_DD, INB=ENB=0 V

3.4

3.2

V_OFF

3.7

4.3

V

FAN3224TUMX-F085 (Modified UVLO Version)

Operating Range

V_DD

I_DD

9.5

18.0

1.20

V

Supply Current, Inputs / EN Not

Connected⁽¹⁵⁾

0.70

mA

V_ON

Turn-On Voltage⁽¹⁵⁾

Turn-Off Voltage⁽¹⁵⁾

INA=ENA=V_DD, INB=ENB=0 V

8.0

7.0

9.1

8.2

10.2

9.3

V

V_OFF

Inputs(FAN322xT)⁽¹¹⁾

V_{INL_T}

V_{INH_T}

V_{HYS_T}TTL Logic Hysteresis Voltage

INx Logic LOW Threshold

0.8

1.2

1.6

0.4

V

INx Logic HIGH Threshold

2.0

0.2

-1

0.8

175

1

V

I

Non-Inverting Input Current

Inverting Input Current

IN from 0 to V_DD

µA

IN+

I

IN-

-175

FAN322xTMX-F085, FAN3224TUMX-F085 (Automotive-Qualified Versions)

V_{INL_T}

V_{INH_T}

INx Logic LOW Threshold

INx Logic HIGH Threshold

0.8

1.2

1.6

0.4

V

2.0

0.9

1.5

175

-90

1.5

V_{HYS_T}TTL Logic Hysteresis Voltage

0.1

-1.5

80

V

I

Non-inverting Input Current⁽¹⁵⁾

Inverting Input Current⁽¹⁵⁾

IN=0 V

IN=V_DD

IN=0 V

IN=V_DD

µA

INx_T

I

120

INx_T

I

-175

-1.5

-120

INx_T

I

INx_T

Inputs(FAN322xC)⁽¹¹⁾

V_{INL_C}

INx Logic Low Threshold

30

-1

38

55

17

%V_DD

V_{INH_C}INx Logic High Threshold

V_{HYS_C}CMOS Logic Hysteresis Voltage

70

%V_DD

µA

I

Non-Inverting Input Current

IN from 0 to V_DD

175

IN+

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8

Electrical Characteristics

Unless otherw ise noted, V_DD=12 V, T_J=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

I

IN-

Inverting Input Current

IN f rom 0 to V_DD

-175

1

µA

FAN322xCMX-F085 (Automotive-Qualified Versions)

V_{INL_C}INx Logic Low Threshold

30

38

55

17

%V_DD

µA

V_{INH_C}INx Logic High Threshold

70

V_{HYS_C}CMOS Logic Hysteresis Voltage

I

Non-Inverting Input Current⁽¹⁵⁾

Inverting Input Current⁽¹⁵⁾

IN=0 V

IN=V_DD

IN=0 V

IN=V_DD

-1.5

90

1.5

175

-90

1.5

INx_T

I

120

µA

INx_T

I

-175

-1.5

-120

µA

INx_T

I

Inverting Input Current⁽¹⁵⁾

µA

INx_T

ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T)

V_ENL

Enable Logic Low Threshold

EN f rom 5 V to 0 V

0.8

1.2

1.6

0.4

100

V

V_ENH

Enable Logic High Threshold

EN f rom 0 V to 5 V

2.0

V_{HYS_T}TTL Logic Hysteresis Voltage⁽¹²⁾

V

R_PU

t_D3

Enable Pull-Up Resistance⁽¹²⁾

kΩ

0 V to 5 V EN, 1 V/ns Slew

Rate

9

17

18

26

28

ns

EN to Output Propagation Delay⁽¹³⁾

5 V to 0 V EN, 1 V/ns Slew

Rate

t_D4

11

FAN3223C-TMX-F085, FAN3224C-TMX-F085, FAN3224TUMX-F085 (Automotive-Qualified Versions)

V_ENL

V_ENH

Enable Logic Low Threshold

Enable Logic High Threshold

EN f rom 5 V to 0 V

EN f rom 0 V to 5 V

0.8

1.2

1.6

0.4

100

V

2.0

V_{HYS_T}TTL Logic Hysteresis Voltage⁽¹²⁾

V

R_PU

t_D3

Enable Pull-Up Resistance⁽¹²⁾

kΩ

0 V to 5V EN, 1 V/ns Slew

Rate

6

17

19

34

31

ns

EN to Output Propagation Delay^(13,15)

5 V to 0V EN, 1 V/ns Slew

Rate

t_D4

Outputs

OUT at V_DD/2, C_LOAD=0.22 µF,

f=1 kHz

I_SINK

OUT Current, Mid-Voltage, Sinking⁽¹²⁾

4.3

A

OUT Current, Mid-Voltage,

Sourcing⁽¹²⁾

OUT at V_DD/2, C_LOAD=0.22 µF,

f=1 kHz

I_SOURCE

-2.8

I_{PK_SINK}OUT Current, Peak, Sinking⁽¹²⁾

I_{PK_SOURCE}OUT Current, Peak, Sourcing⁽¹²⁾

C_LOAD=0.22 µF, f=1 kHz

C_LOAD=2200 pF

5

-5

12

9

A

t_RISE

t_FALL

Output Rise Time⁽¹⁴⁾

Output Fall Time⁽¹⁴⁾

20

17

ns

C_LOAD=2200 pF

Propagation Matching Betw een

Channels

Output Reverse Current Withstand⁽¹²⁾

INA=INB, OUTA and OUTB at

50% Point

t_DEL.MATCH

I_RVS

2

4

ns

mA

ns

500

18

Output Propagation Delay, CMOS

Inputs⁽¹⁴⁾

t_D1,t_D2

0 – 12 V_IN, 1 V/ns Slew Rate

0 – 5 V_IN, 1 V/ns Slew Rate

10

9

29

Output Propagation Delay, TTL

Inputs⁽¹⁴⁾

t_D1,t_D2

17

ns

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9

Electrical Characteristics

Unless otherw ise noted, V_DD=12 V, T_J=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

All Except for FAN3225C-TMX-F085 (Automotive-Qualified Versions)

t_RISE

t_FALL

Output Rise Time⁽¹⁴⁾

Output Fall Time⁽¹⁴⁾

C_LOAD=2200 pF

12

9

20

17

ns

Propagation Matching Betw een

Channels

Output Reverse Current Withstand⁽¹²⁾

INA=INB, OUTA and OUTB at

50% Point

t_DEL.MATCH

I_RVS

2

4

ns

mA

ns

500

18

Output Propagation Delay, CMOS

Inputs^(14,15)

t_D1,t_D2

0 – 12 V_IN, 1 V/ns Slew Rate

0 – 5 V_IN, 1 V/ns Slew Rate

9

6

34

30

Output Propagation Delay, TTL

Inputs^(14,15)

t_D1,t_D2

16

ns

V_OH

V_OL

High Level Output Voltage⁽¹⁵⁾

Low Level Output Voltage⁽¹⁵⁾

15

10

35

25

mV

V_OH=V_DD–V_OUT, I_OUT=–1 mA

I_OUT= 1 mA

FAN3225C_TMX_F085 (Automotive-Qualificed Versions)

t_RISE

t_FALL

Output Rise Time⁽¹⁴⁾

Output Fall Time⁽¹⁴⁾

C_LOAD=2200 pF

12

9

28

26

ns

V_OH

High Level Output Voltage⁽¹⁵⁾

Low Level Output Voltage⁽¹⁵⁾

15

10

37

25

mV

V_OH=V_DD–V_OUT, I_OUT=–1 mA

V_OL

I_OUT= 1 mA

Notes:

10. Low er supply current due to inactive TTL circuitry.

11. EN inputs have TTL thresholds; refer to the ENABLE section.

12. Not tested in production.

13. See Timing Diagrams of Figure 10 and Figure 11.

14. See Timing Diagrams of Figure 8 and Figure 9.

15. Applies only to _F085 versions.

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10

Timing Diagrams

V_INH

V_INL

Input

V_INL

t_D1

t_D2

t_D1

t_D2

t_RISE

t_FALL

t_RISE

t_FALL

90%

10%

90%

10%

Output

Figure 8.

Non-Inverting (EN HIGH or Floating)

Figure 9.

Inverting (EN HIGH or Floating)

HIGH

LOW

Input

LOW

V

ENH

Enable

V

ENH

V

ENL

Enable

V

ENL

t_D3

t_D4

D3

D4

t

t_FALL

t_RISE

t_FALL

t_RISE

90%

10%

90%

10%

Output

Figure 10. Non-Inverting (IN HIGH)

Figure 11. Inverting (IN LOW)

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11

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 12.

I_DD(Static) vs. Supply Voltage⁽¹⁶⁾

Figure 13.

I_DD(Static) vs. Supply Voltage⁽¹⁶⁾

Figure 14.

I_DD(Static) vs. Supply Voltage⁽¹⁶⁾

Figure 15.

I_DD(No-Load) vs. Frequency

Figure 16.

I_DD(No-Load) vs. Frequency

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12

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 17.

I_DD(2.2 nF Load) vs. Frequency

Figure 18.

I_DD(2.2 nF Load) vs. Frequency

Figure 19.

I_DD(Static) vs. Temperature⁽¹⁶⁾

Figure 20.

I_DD(Static) vs. Temperature⁽¹⁶⁾

Figure 21.

I_DD(Static) vs. Temperature⁽¹⁶⁾

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13

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 22.

Input Thresholds vs. Supply Voltage Figure 23.

Input Thresholds vs. Supply Voltage

Figure 24.

Input Threshold % vs. Supply Voltage

Figure 25.

Input Thresholds vs. Temperature

Figure 26.

Input Thresholds vs. Temperature

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14

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 27.

UVLO Thresholds vs. Temperature

Figure 28. UVLO Threshold vs. Temperature

Figure 29. UVLO Thresholds vs. Temperature

Figure 30. Propagation Delay vs. Supply

Voltage

Figure 31. Propagation Delay vs. Supply

Voltage

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 32. Propagation Delay vs. Supply

Voltage

Figure 33. Propagation Delay vs. Supply

Voltage

Figure 34. Propagation Delays vs. Temperature

Figure 35. Propagation Delays vs. Temperature

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16

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 36. Propagation Delays vs. Temperature

Figure 37. Propagation Delays vs. Temperature

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 38.

Fall Time vs. Supply Voltage

Figure 39. Rise Time vs. Supply Voltage

Figure 40.

Rise and Fall Times vs. Temperature

www.onsemi.com

17

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 41.

Rise/Fall Waveforms with 2.2 nF

Load

Figure 42.

Rise/Fall Waveforms with 10 nF

Load

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18

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 43.

Quasi-Static Source Current

with V_DD=12 V⁽¹⁷⁾

Figure 44.

Quasi-Static Sink Current with

V_DD=12 V⁽¹⁷⁾

Figure 45.

Notes:

Quasi-Static Source Current

with V_DD=8 V⁽¹⁷⁾

Figure 46.

Quasi-Static Sink Current with

V_DD=8 V⁽¹⁷⁾

16. For any inverting inputs pulled low , non-inverting inputs pulled high, or outputs driven high, static I_DDincreases by

the current flow ing through the corresponding pull-up/dow n resistor show n in the block diagram.

17. The initial spike in each current w aveformis a measurement artifact caused by the stray inductance of the

current-measurement loop.

www.onsemi.com

19

Test Circuit

V_DD

470 µF

Al. El.

4.7 µF

ceramic

Current Probe

LECROY AP015

I_OUT

IN

1 kHz

1 µF

ceramic

C_LOAD

0.22 µF

V_OUT

Figure 47. Quasi-Static I_OUT/ V_OUTTest Circuit

www.onsemi.com

20

Applications Information

Input Thresholds

MillerDrive™ Gate Drive Technology

Each member of the FAN322x driver family consists of

tw o identical channels that may be used independently

at rated current or connected in parallel to double the

individual current capacity. In the FAN3223 and

FAN3224, channels A and B can be enabled or disabled

independently using ENA or ENB, respectively. The EN

pin has TTL thresholds for parts w ith either CMOS or

TTL input thresholds. If ENA and ENB are not

connected, an internal pull-up resistor enables the driver

channels by default. ENA and ENB have TTL thresholds

in parts w ith either TTL or CMOS INx threshold. If the

channel A and channel B inputs and outputs are

connected in parallel to increase the driver current

capacity, ENA and ENB should be connected and

driven together.

FAN322x gate drivers incorporate the MillerDrive™

architecture show n in Figure 48. For the output stage, a

combination of bipolar and MOS devices provide large

currents over a w ide range of supply voltage and

temperature variations. The bipolar devices carry the

bulk of the current as OUT sw ings betw een 1/3 to 2/3

V_DDand the MOS devices pull the output to the HIGH or

LOW rail.

The purpose of the MillerDrive™ architecture is to

speed up sw itching by providing high current during the

Miller plateau region w hen the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

For applications that have zero voltage sw itching during

the MOSFET turn-on or turn-off interval, the driver

supplies high peak current for fast sw itching even

though the Miller plateau is not present. This situation

often occurs in synchronous rectifier applications

because the body diode is generally conducting before

the MOSFET is sw itched ON.

The FAN322x family offers versions in either TTL or

CMOS input thresholds. In the FAN322xT, the input

thresholds meet industry-standard TTL-logic thresholds

independent of the V_DDvoltage, and there is

a

hysteresis voltage of approximately 0.4 V. These levels

permit the inputs to be driven from a range of input logic

signal levels for w hich a voltage over 2 V is considered

logic HIGH. The driving signal for the TTL inputs should

have fast rising and falling edges w ith a slew rate of

6 V/µs or faster, so a rise time from 0 to 3.3 V should be

550 ns or less. With reduced slew rate, circuit noise

could cause the driver input voltage to exceed the

hysteresis voltage and retrigger the driver input, causing

erratic operation.

The output pin slew rate is determined by V_DDvoltage

and the load on the output. It is not user adjustable, but

a series resistor can be added if a slow er rise or fall time

at the MOSFET gate is needed.

V_DD

In the FAN322xC, the logic input thresholds are

dependent on the V_DDlevel and, w ith V_DDof 12V, the

logic rising edge threshold is approximately 55% of V_DD

and the input falling edge threshold is approximately

38% of V_DD. The CMOS input configuration offers a

hysteresis voltage of approximately 17% of V_DD. The

CMOS inputs can be used w ith relatively slow edges

(approaching DC) if good decoupling and bypass

techniques are incorporated in the system design to

prevent noise from violating the input voltage hysteresis

w indow . This allow s setting precise timing intervals by

fitting an R-C circuit betw een the controlling signal and

the IN pin of the driver. The slow rising edge at the IN

pin of the driver introduces a delay betw een the

controlling signal and the OUT pin of the driver.

Input

stage

V_OUT

Figure 48. MillerDrive™ Output Architecture

Under-Voltage Lockout

The FAN322x startup logic is optimized to drive ground-

referenced N-channel MOSFETs w ith an under-voltage

lockout (UVLO) function to ensure that the IC starts up

in an orderly fashion. When V_DDis rising, yet below the

UVLO level, this circuit holds the output LOW,

regardless of the status of the input pins. After the part

is active, the supply voltage must drop 0.2 V before the

part shuts dow n. This hysteresis helps prevent chatter

when low V_DDsupply voltages have noise from the

pow er sw itching. This configuration is not suitable for

driving high-side P-channel MOSFETs because the low

output voltage of the driver w ould turn the P-channel

MOSFET ON w ith V_DDbelow the UVLO level.

Static SupplyCurrent

In the I_DD(static) typical performance characteristics

(Figure 12 - Figure 14 and Figure 19 - Figure 21), the

curve is produced w ith all inputs/enables floating (OUT

is low ) and indicates the low est static I_DDcurrent for the

tested configuration. For other states, additional current

flow s through the 100 kΩ resistors on the inputs and

outputs show n in the block diagram of each part (see

Figure 5 - Figure 7). In these cases, the actual static I_DD

current is the value obtained from the curves plus this

additional current.

www.onsemi.com

21

For best results, make connections to all pins as

short and direct as possible.

V_DDBypass Capacitor Guidelines

To enable this IC to turn a device ON quickly, a local

high-frequency bypass capacitor, C_BYP, w ith low ESR

and ESL should be connected betw een the VDD and

GND pins w ith minimal trace length. This capacitor is

in addition to the bulk electrolytic capacitance of 10 µF

to 47 µF commonly found on the driver and controller

bias circuits.

.

The FAN322x is compatible w ith many other

industry-standard drivers. In single input parts w ith

enable pins, there is an internal 100 kΩ resistor tied

to VDD to enable the driver by default; this should

be considered in the PCB layout.

The turn-on and turn-off current paths should be

minimized, as discussed in the follow ing section.

A typical criterion for choosing the value of C_BYPis to

keep the ripple voltage on the V_DDsupply to ≤5%. This

is often achieved w ith a value ≥20 times the equivalent

load capacitance C_EQV, defined here as Q_GATE/V_DD

Ceramic capacitors of 0.1 µF to 1 µF or larger are

common choices, as are dielectrics, such as X5R and

X7R w ith good temperature characteristics and high

pulse current capability.

Figure 49 show s the pulsed gate drive current path

when the gate driver is supplying gate charge to turn the

MOSFET ON. The current is supplied from the local

bypass capacitor, C_BYP, and flow s through the driver to

the MOSFET gate and to ground. To reach the high

peak currents possible, the resistance and inductance in

the path should be minimized. The localized C_BYPacts

to contain the high peak current pulses w ithin this driver-

MOSFET circuit, preventing them from disturbing the

sensitive analog circuitry in the PWM controller.

.

If circuit noise affects normal operation, the value of

C_BYPmay be increased to 50-100 times the C_EQV, or

C_BYPmay be split into tw o capacitors. One should be a

larger value, based on equivalent load capacitance, and

the other a smaller value, such as 1-10 nF mounted

closest to the VDD and GND pins to carry the higher

frequency components of the current pulses. The

bypass capacitor must provide the pulsed current from

both of the driver channels and, if the drivers are

sw itching simultaneously, the combined peak current

sourced from the C_BYPw ould be tw ice as large as w hen

a single channel is sw itching.

V_DD

V_DS

C_BYP

FAN322x

Layout and Connection Guidelines

PWM

The FA N3223-25 family of gate drivers incorporates

fast-reacting input circuits, short propagation delays,

and pow erful output stages capable of delivering current

peaks over 4 A to facilitate voltage transition times from

under 10 ns to over 150 ns. The follow ing layout and

connection guidelines are strongly recommended:

Figure 49. Current Path for MOSFET Turn-On

Figure 50 show s the current path w hen the gate driver

turns the MOSFET OFF. Ideally, the driver shunts the

current directly to the source of the MOSFET in a s mall

circuit loop. For fast turn-off times, the resistance and

inductance in this path should be minimized.

.

Keep high-current output and pow er ground paths

separate logic and enable input signals and signal

ground paths. This is espec ially critical w hen

dealing w ith TTL-level logic thresholds at driver

inputs and enable pins.

V_DD

V_DS

.

Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed sw itching, w hile reducing the loop area that

can radiate EMI to the driver inputs and

surrounding circuitry.

C_BYP

FAN322x

.

If the inputs to a channel are not externally

connected, the internal 100 kΩ resistors indicated

on block diagrams command a low output. In noisy

environments, it may be necessary to tie inputs of

an unused channel to VDD or GND using short

traces to prevent noise from causing spurious

output sw itching.

PWM

Figure 50. Current Path for MOSFET Turn-Off

Many high-speed pow er circuits can be susceptible

to noise injected from their ow n output or other

external sources, possibly causing output re-

triggering. These effects can be obvious if the

circuit is tested in breadboard or non-optimal circuit

layouts w ith long input, enable, or output leads.

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22

Truth Table of Logic Operation

OperationalWaveforms

The FAN3225 truth table indicates the operational states

using the dual-input configuration. In a non-inverting

driver configuration, the IN- pin should be a logic LOW

signal. If the IN- pin is connected to logic HIGH, a disable

function is realized, and the driver output remains LOW

regardless of the state of the IN+ pin.

At pow er-up, the driver output remains LOW until the

V_DDvoltage reaches the turn-on threshold. The

magnitude of the OUT pulses rises w ith V_DDuntil

steady-state V_DDis reached. The non-inverting

operation illustrated in Figure 53 shows that the output

remains LOW until the UVLO threshold is reached, then

the output is in-phase w ith the input.

IN+

0

IN-

0

OUT

0

1

0

VDD

0

1

Turn-on threshold

1

0

1

In the non-inverting driver configuration in Figure 51, the

IN- pin is tied to ground and the input signal (PWM) is

applied to IN+ pin. The IN- pin can be connected to logic

HIGH to disable the driver and the output remains LOW,

regardless of the state of the IN+ pin.

IN-

IN+

VDD

IN+

PWM

OUT

FAN3225

IN-

OUT

GND

Figure 53. Non-Inverting Startup Waveforms

For the inverting configuration of Figure 52, startup

waveforms are show n in Figure 54. With IN+ tied to

VDD and the input signal applied to IN–, the OUT

pulses are inverted w ith respect to the input. At pow er-

up, the inverted output remains LOW until the V_DD

voltage reaches the turn-on threshold, then it follows the

input w ith inverted phase.

Figure 51. Dual-Input Driver Enabled,

Non-Inverting Configuration

In the inverting driver application in Figure 52, the IN+

pin is tied HIGH. Pulling the IN+ pin to GND forces the

output LOW, regardless of the state of the IN- pin.

VDD

Turn-on threshold

IN+

IN-

OUT

FAN3225

IN-

PWM

GND

IN+

(VDD)

Figure 52. Dual-Input Driver Enabled,

Inverting Configuration

OUT

Figure 54. Inverting Startup Waveforms

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23

Thermal Guidelines

Gate drivers used to sw itch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

pow er. It is important to determine the driver pow er

dissipation and the resulting junction temperature in the

application to ensure that the part is operating w ithin

acceptable temperature limits.

To give a numerical example, assume for a 12 V V_DD

(V_BIAS) system, the synchronous rectifier sw itches of

Figure 55 have a total gate charge of 60 nC at

V_GS= 7 V. Therefore, tw o devices in parallel w ould have

120 nC gate charge. At a sw itching frequency of

300 kHz, the total pow er dissipation is:

The total pow er dissipation in a gate driver is the sum of

P_GATE= 120 nC • 7 V • 300 kHz • 2 = 0.504 W

P_DYNAMIC= 3.0 mA • 12 V • 1 = 0.036 W

P_TOTAL= 0.540 W

(5)

(6)

(7)

tw o components, P_GATEand P_DYNAMIC

:

P_TOTAL= P_GATE+ P_DYNAMIC

(1)

P_GATE(Gate Driving Loss): The most significant pow er

loss results from supplying gate current (charge per

unit time) to sw itch the load MOSFET on and off at

the sw itching frequency. The pow er dissipation that

results from driving a MOSFET at a specified gate-

source voltage, V_GS, w ith gate charge, Q_G, at

sw itching frequency, f_SW, is determined by:

The SOIC-8 has

characterization parameter of

a

junction-to-board thermal

ψ_JB

= 42°C/W. In a

system application, the localized temperature around

the device is a function of the layout and construction of

the PCB along w ith airflow across the surfaces. To

ensure reliable operation, the maximum junction

temperature of the device must be prevented from

exceeding the maximum rating of 150°C; w ith 80%

derating, T_Jw ould be limited to 120°C. Rearranging

Equation 4 determines the board temperature required

to maintain the junction temperature below 120°C:

P_GATE= Q_G• V_GS• f_SW• n

w here n is the number of driver channels in use (1 or 2).

P_DYNAMIC(Dynamic Pre-Drive Shoot-through

(2)

/

Current): A pow er loss resulting from internal current

consumption under dynamic operating conditions,

including pin pull-up / pull-dow n resistors. The internal

current consumption (I_DYNAMIC) can be estimated using

the graphs in Figure 15 and Figure 16 of the Typical

Performance Characteristics to determine the current

I_DYNAMICdraw n from V_DDunder actual operating

conditions:

ψ

•

(8)

(9)

T_B,MAX= T_J- P_TOTAL

JB

T_B,MAX= 120°C – 0.54 W • 42°C/W = 97°C

P_DYNAMIC= I_DYNAMIC• V_DD• n

(3)

where n is the number of driver ICs in use. Note that n is

usually be one IC even if the IC has tw o channels,

unless two or more.driver ICs are in parallel to driv e a

large load.

Once the pow er dissipated in the driver is determined,

the driver junction rise w ith respect to circuit board can

be evaluated using the follow ing thermal equation,

ψ_JB

assuming

w as determined for a similar thermal

design (heat sinking and air flow ):

ψ

_JB+ T_B

(4)

T_J= P_TOTAL

•

w here:

T_J

= driver junction temperature;

ψ_JB

= (psi) thermal characterization parameter

relating temperature rise to total pow er

dissipation; and

T_B

= board temperature in location as defined in

the Thermal Characteristics table.

www.onsemi.com

24

Typical Application Diagrams

V_IN

V_OUT

PWM

1

2

3

4

8

7

6

5

FAN3224

8

7

6

5

1

2

3

4

ENA

ENB

Vbias

Timing/

Isolation

A

B

GND

VDD

FAN3224

Figure 55. High Current Forward Converter

with Synchronous Rectification

Figure 56.

Center-Tapped Bridge Output with

Synchronous Rectifiers

Vin

QC

QA

QD

QB

FAN3224

PWM-A

FAN3225

SR-1

SR-2

Secondary

Phase Shift

Controller

PWM-B

PWM-C

FAN3225

PWM-D

Figure 57. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous

Rectifiers (Simplified)

www.onsemi.com

25

Table 1.

Type

RelatedProducts

Gate

Part

Input

Threshold

Drive⁽¹⁸⁾

(Sink/Src)

Logic

Package

Number

Single 1 A FAN3111C +1.1 A / -0.9 A

CMOS

Single Channel of Dual-Input/Single-Output

SOT23-5, MLP6

Single 1 A FAN3111E +1.1 A / -0.9 A External⁽¹⁹⁾Single Non-Inverting Channel withExternal Reference SOT23-5, MLP6

Single 2 A FAN3100C +2.5 A / -1.8 A

Single 2 A FAN3100T +2.5 A / -1.8 A

Single 2 A FAN3180 +2.4 A / -1.6 A

CMOS

TTL

Single Channel of Two-Input/One-Output

Single Non-Inverting Channel + 3.3-V LDO

Dual Inverting Channels

SOT23-5, MLP6

SOT23-5

TTL

Dual 2 A

FAN3216T +2.4 A / -1.6 A

FAN3217T +2.4 A / -1.6 A

FAN3226C +2.4 A / -1.6 A

FAN3226T +2.4 A / -1.6 A

FAN3227C +2.4 A / -1.6 A

FAN3227T +2.4 A / -1.6 A

FAN3228C +2.4 A / -1.6 A

FAN3228T +2.4 A / -1.6 A

FAN3229C +2.4 A / -1.6 A

FAN3229T +2.4 A / -1.6 A

TTL

SOIC8

TTL

Dual Non-InvertingChannels

SOIC8

CMOS

TTL

Dual Inverting Channels+ Dual Enable

Dual Non-InvertingChannels+ Dual Enable

SOIC8, MLP8

CMOS

TTL

CMOS

TTL

Dual Channelsof Two-Input/One-Output, Pin Config.1 SOIC8, MLP8

Dual Channelsof Two-Input/One-Output, Pin Config.2 SOIC8, MLP8

CMOS

TTL

20 V Non-Inverting Channel (NMOS) and Inverting

SOIC8

Dual 2 A

FAN3268T +2.4 A / -1.6 A

FAN3278T +2.4 A / -1.6 A

TTL

Channel (PMOS) + Dual Enables

30 V Non-Inverting Channel (NMOS) and Inverting

SOIC8

Channel (PMOS) + Dual Enables

Dual 4 A

FAN3213T +4.3 A / -2.8 A

FAN3214T +4.3 A / -2.8 A

TTL

Dual Inverting Channels

SOIC8

Dual Non-InvertingChannels

Dual 4 A

FAN3223C +4.3 A / -2.8 A

FAN3223T +4.3 A / -2.8 A

FAN3224C +4.3 A / -2.8 A

FAN3224T +4.3 A / -2.8 A

FAN3225C +4.3 A / -2.8 A

FAN3225T +4.3 A / -2.8 A

CMOS

TTL

Dual Inverting Channels + Dual Enable

Dual Non-Inverting Channels + Dual Enable

Dual Channels of Two-Input/One-Output

Single Inverting Channel + Enable

SOIC8, MLP8

SOIC8

CMOS

TTL

CMOS

TTL

Single 9 A FAN3121C +9.7 A / -7.1 A

Single 9 A FAN3121T +9.7 A / -7.1 A

Single 9 A FAN3122T +9.7 A / -7.1 A

Single 9 A FAN3122C +9.7 A / -7.1 A

CMOS

TTL

Single Inverting Channel + Enable

CMOS

TTL

Single Non-Inverting Channel + Enable

Dual-Coil Relay Driver, TimingConfig. 0

Dual-Coil Relay Driver, TimingConfig. 1

Dual 12 A FAN3240

Dual 12 A FAN3241

Notes:

+12.0 A

TTL

SOIC8

18. Typical currents w ith OUTx at 6 V and V_DD=12 V.

19. Thresholds proportional to an externally supplied reference voltage.

www.onsemi.com

26

Physical Dimensions

0.10 C

2.37

3.00

A

B

5

8

2X

1.99

3.30

1.42

3.00

(0.65)

PIN #1 IDENT

0.10 C

1

4

0.42 TYP

TOP VIEW

2X

0.65 TYP

RECOMMENDED LAND PATTERN

0.80 MAX

0.10 C

0.08 C

(0.20)

0.05

0.00

C

NOTES:

FRONT VIEW

SEATING

PLANE

A. CONFORMS TO JEDEC REGISTRATION MO-229,

VARIATION VEEC, DATED 11/2001.

0.45

0.20

B. DIMENSIONS ARE IN MILLIMETERS.

2.25MAX

4

1

C. DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 2009.

PIN #1 IDENT

D. LAND PATTERN RECOMMENDATION IS

EXISTING INDUSTRY LAND PATTERN.

1.30MAX

E. DRAWING FILENAME: MKT-MLP08Drev3

5

8

0.25

0.35

0.10

0.65

C

A B

1.95

0.05

BOTTOM VIEW

Figure 58. 3x3 mm, 8-Lead Molded Leadless Package (MLP)

www.onsemi.com

27

Physical Dimensions (Continued)

A

4.90±0.10

0.65

(0.635)

8

5

B

1.75

6.00±0.20

5.60

3.90±0.10

1

4

PIN ONE

INDICATOR

1.27

LAND PATTERN RECOMMENDATION

0.25

C B A

SEE DETAIL A

0.175±0.075

0.22±0.03

C

1.75 MAX

0.10

0.42±0.09

(0.86)

OPTION A - BEVEL EDGE

x 45°

R0.10

GAGE PLANE

OPTION B - NO BEVEL EDGE

0.36

NOTES:

8°

0°

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

SEATING PLANE

0.65±0.25

(1.04)

D) LANDPATTERN STANDARD: SOIC127P600X175-8M

E) DRAWING FILENAME: M08Arev16

DETAIL A

SCALE: 2:1

Figure 59. 8-Lead Small Outline Integrated Circuit (SOIC)

www.onsemi.com

28

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29


型号：	FAN3223TMX
厂家：	ONSEMI
描述：	Dual 4-A High-Speed, Low-Side Gate Drivers 栅
文件：	总29页 (文件大小：1974K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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