FAN3217TMX_12_技术文档

May 2012

FAN3216 / FAN3217_F085

Dual-2A, High-Speed, Low-Side Gate Drivers

Features

Description

.

Qualified to AEC Q-100

The FAN3216 and FAN3217 dual 2A gate drivers are

designed to drive N-channel enhancement-mode

MOSFETs in low-side switching applications by

providing high peak current pulses during the short

switching intervals. They are both available with TTL

input thresholds. Internal circuitry provides an under-

voltage lockout function by holding the output LOW until

the supply voltage is within the operating range. In

addition, the drivers feature matched internal

propagation delays between A and B channels for

applications requiring dual gate drives with critical

timing, such as synchronous rectifiers. This also

enables connecting two drivers in parallel to effectively

double the current capability driving a single MOSFET.

4.5 to 18V Operating Range

3A Peak Sink/Source at V_DD= 12V

2.4A Sink / 1.6A Source at V_OUT= 6V

TTL Input Thresholds

Two Versions of Dual Independent Drivers:

-

Dual Inverting (FAN3216)

Dual Non-Inverting (FAN3217)

.

Internal Resistors Turn Driver Off If No Inputs

MillerDrive™ Technology

12ns / 9ns Typical Rise/Fall Times with 1nF Load

The FAN3216/17 drivers incorporate MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize switching loss, while providing rail-

to-rail voltage swing and reverse current capability.

Typical Propagation Delay Under 20ns Matched

within 1ns to the Other Channel

.

Double Current Capability by Paralleling Channels

Standard SOIC-8 Package

Rated from –40°C to +125°C Ambient

The FAN3216 offers two inverting drivers and the

FAN3217 offers two non-inverting drivers. Both are

offered in a standard 8-pin SOIC package.

Applications

.

Switch-Mode Power Supplies

High-Efficiency MOSFET Switching

Synchronous Rectifier Circuits

DC-to-DC Converters

Motor Control

FAN3216

FAN3217

Figure 1. Pin Configurations

Ordering Information

Input

Threshold

Packing

Method

Quantity

per Reel

Eco

Status

Part Number

Logic

Package

Tape &

Reel

FAN3216TMX_F085 Dual Inverting Channels

TTL

SOIC-8

RoHS

2,500

Dual Non-Inverting

FAN3217TMX_F085

Tape &

Reel

Channels

For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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Package Outline

Figure 2. SOIC-8 (Top View)

Thermal Characteristics⁽¹⁾

(2)

(3)

(4)

(5)

(6)

Package

Units

_JL

_JT

_JA

_JB

_JT

40

31

89

43

3.0

°C/W

8-Pin Small Outline Integrated Circuit (SOIC)

Notes:

1. Estimates derived from thermal simulation; actual values depend on the application.

2. Theta_JL (_JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any

thermal pad) that are typically soldered to a PCB.

3. Theta_JT (_JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is

held at a uniform temperature by a top-side heatsink.

4. Theta_JA (Θ_JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.

The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,

JESD51-5, and JESD51-7, as appropriate.

5. Psi_JB (_JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an

application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board

reference is defined as the PCB copper adjacent to pin 6.

6. Psi_JT (_JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and

the center of the top of the package for the thermal environment defined in Note 4.

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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2

Pin Configurations

FAN3216

FAN3217

Figure 3. Pin Configurations (Repeated)

Pin Definitions

1

Name

NC

Pin Description

No Connect. This pin can be grounded or left floating.

Input to Channel A.

2

INA

2

INA

Input to Channel A.

3

GND

INB

Ground. Common ground reference for input and output circuits.

Input to Channel B.

4

INB

Input to Channel B.

5

Gate Drive Output B (inverted from the input): Held LOW unless required input is

present and V_DDis above UVLO threshold.

OUTB

(FAN3216)

5

Gate Drive Output B: Held LOW unless required input(s) are present and V_DDis above

UVLO threshold.

OUTB

VDD

(FAN3217)

6

Supply Voltage. Provides power to the IC.

7

Gate Drive Output A (inverted from the input): Held LOW unless required input is

present and V_DDis above UVLO threshold.

OUTA

(FAN3216)

7

Gate Drive Output A: Held LOW unless required input(s) are present and V_DDis above

UVLO threshold.

OUTA

NC

(FAN3217)

8

No Connect. This pin can be grounded or left floating.

Output Logic

FAN3216 (x=A or B)

FAN3217 (x=A or B)

INx

0⁽⁷⁾

1

OUTx

1

0

1

1⁽⁷⁾

Note:

7. Default input signal if no external connection is made.

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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3

Block Diagrams

Figure 4. FAN3216 Block Diagram

Figure 5. FAN3217 Block Diagram

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_DD

Parameter

Min.

Max.

Unit

V

VDD to PGND

-0.3

20.0

V_IN

INA and INB to GND

OUTA and OUTB to GND

GND - 0.3 V_DD+ 0.3

+260

V

V_OUT

T_L

V

Lead Soldering Temperature (10 Seconds)

Junction Temperature

ºC

T_J

-55

-65

+150

T_STG

Storage Temperature

ESD

Human Body Model, JEDEC JESD22-A114

3

kV

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DD

Parameter

Min.

4.5

0

Max.

18.0

V_DD

Unit

V

Supply Voltage Range

V_IN

Input Voltage INA and INB

V

T_A

Operating Ambient Temperature

-40

+125

ºC

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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5

Electrical Characteristics

Unless otherwise noted, V_DD=12V, T_J=-40°C to +125°C. Currents are defined as positive into the device and negative

out of the device.

Symbol

Supply

V_DD

Parameter

Conditions

Min. Typ. Max. Unit

Operating Range

4.5

18.0

1.20

4.60

4.30

V

mA

V

I_DD

Supply Current, Inputs Not Connected

Turn-On Voltage

0.75

3.90

3.70

V_ON

INA = V_DD, INB = 0V

3.40

3.20

V_OFF

Turn-Off Voltage

V

Inputs

V_{IL_T}

INx Logic Low Threshold

0.8

1.2

1.6

V

V_{IH_T}

I_{INx_T}

V_{HYS_T}

INx Logic High Threshold

Non-Inverting Input Current

Inverting Input Current

2.0

1.5

175

-90

1.5

0.8

V

IN = 0V

IN = V_DD

IN = 0V

IN = V_DD

-1.5

90

µA

V

120

-175

-1.5

0.15

-120

Inverting Input Current

TTL Logic Hysteresis Voltage

0.4

Output

OUTx at V_DD/2, C_LOAD=0.22µF,

f=1kHz

I_SINK

OUT Current, Mid-Voltage, Sinking⁽⁸⁾

2.4

A

OUTx at V_DD/2,

C_LOAD=0.1µF, f=1kHz

I_SOURCE

I_{PK_SINK}

OUT Current, Mid-Voltage, Sourcing⁽⁸⁾

OUT Current, Peak, Sinking⁽⁸⁾

-1.6

C_LOAD=0.1µF, f=1kHz

3

A

I_{PK_SOURCE}OUT Current, Peak, Sourcing⁽⁸⁾

-3

V_OH

High Level Output Voltage

15

35

mV

V^OH= VDD – VOUT, IOUT = –1mA

V_OL

t_RISE

Low Level Output Voltage

Output Rise Time⁽⁹⁾

IOUT = 1mA

10

12

9

25

22

17

34

mV

ns

C_LOAD=1000pF

t_FALL

Output Fall Time⁽⁹⁾

C_LOAD=1000pF

ns

t_D1, t_D2

Output Propagation Delay, TTL Inputs⁽⁹⁾

0 - 5V_IN, 1V/ns Slew Rate

4.5

19

ns

INA=INB, OUTA and OUTB at 50%

Point

Propagation Matching Between Channels

Output Reverse Current Withstand⁽⁸⁾

2

4

ns

I_RVS

500

mA

Notes:

8. Not tested in production.

9. See Timing Diagrams of Figure 6 and Figure 7.

Figure 6. Non-Inverting Timing Diagram

Figure 7. Inverting Timing Diagram

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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6

Typical Performance Characteristics

Typical characteristics are provided at T_A=25°C and V_DD=12V unless otherwise noted.

Figure 8. I_DD(Static) vs. Supply Voltage⁽¹⁰⁾

Figure 9. I_DD(Static) vs. Temperature⁽¹⁰⁾

Figure 10. I_DD(No-Load) vs. Frequency

Figure 11. I_DD(1nF Load) vs. Frequency

Figure 12. Input Thresholds vs. Supply Voltage

Figure 13. Input Thresholds vs. Temperature

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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7

Typical Performance Characteristics

Typical characteristics are provided at T_A=25°C and V_DD=12V unless otherwise noted.

Figure 14. UVLO Threshold vs. Temperature

Figure 15. Propagation Delay vs. Supply Voltage

Figure 16. Propagation Delay vs. Supply Voltage

Figure 17. Propagation Delays vs. Temperature

Figure 18. Propagation Delays vs. Temperature

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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8

Typical Performance Characteristics

Typical characteristics are provided at T_A=25°C and V_DD=12V unless otherwise noted.

Figure 19. Fall Time vs. Supply Voltage

Figure 20. Rise Time vs. Supply Voltage

Figure 21. Rise and Fall Times vs. Temperature

Figure 22. Rise/Fall Waveforms with 2.2nF Load

Figure 23. Rise/Fall Waveforms with 10nF Load

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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9

Typical Performance Characteristics

Typical characteristics are provided at T_A=25°C and V_DD=12V unless otherwise noted.

Figure 24. Quasi-Static Source Current

Figure 25. Quasi-Static Sink Current with V_DD=12V⁽¹¹⁾

with V_DD=12V⁽¹¹⁾

Figure 26. Quasi-Static Source Current

with V_DD=8V⁽¹¹⁾

Figure 27. Quasi-Static Sink Current with V_DD=8V⁽¹¹⁾

Notes:

10. For any inverting inputs pulled LOW, non-inverting inputs pulled HIGH, or outputs driven HIGH; static I_DD

increases by the current flowing through the corresponding pull-up/down resistor shown in Figure 4 and Figure 5.

11. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the

current-measurement loop.

Test Circuit

Figure 28. Quasi-Static I_OUT/ V_OUTTest Circuit

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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10

Applications Information

Input Thresholds

The FAN3216 and the FAN3217 drivers consist of two

identical channels that may be used independently at

rated current or connected in parallel to double the

individual current capacity.

The input thresholds meet industry-standard TTL-logic

thresholds independent of the V_DDvoltage, and there is

a hysteresis voltage of approximately 0.4V. These levels

permit the inputs to be driven from a range of input logic

signal levels for which a voltage over 2V is considered

logic HIGH. The driving signal for the TTL inputs should

have fast rising and falling edges with a slew rate of

6V/µs or faster, so a rise time from 0 to 3.3V should be

550ns or less. With reduced slew rate, circuit noise

could cause the driver input voltage to exceed the

hysteresis voltage and retrigger the driver input, causing

erratic operation.

Figure 29. MillerDrive™ Output Architecture

Under-Voltage Lockout

The FAN321x startup logic is optimized to drive ground-

referenced N-channel MOSFETs with an under-voltage

lockout (UVLO) function to ensure that the IC starts up

in an orderly fashion. When V_DDis rising, yet below the

3.9V operational level, this circuit holds the output LOW,

regardless of the status of the input pins. After the part

is active, the supply voltage must drop 0.2V before the

part shuts down. This hysteresis helps prevent chatter

when low V_DDsupply voltages have noise from the

power switching. This configuration is not suitable for

driving high-side P-channel MOSFETs because the low

output voltage of the driver would turn the P-channel

MOSFET on with V_DDbelow 3.9V.

Static Supply Current

In the I_DD(static) typical performance characteristics

shown in Figure 8 and Figure 9, each curve is produced

with both inputs floating and both outputs LOW to

indicate the lowest static I_DDcurrent. For other states,

additional current flows through the 100k resistors on

the inputs and outputs shown in the block diagram of

each part (see Figure 4 and Figure 5). In these cases,

the actual static I_DDcurrent is the value obtained from

the curves plus this additional current.

MillerDrive™ Gate Drive Technology

FAN3216 and FAN3217 gate drivers incorporate the

MillerDrive™ architecture shown in Figure 29. For the

output stage, a combination of bipolar and MOS devices

provide large currents over a wide range of supply

voltage and temperature variations. The bipolar devices

carry the bulk of the current as OUT swings between 1/3

to 2/3 V_DDand the MOS devices pull the output to the

HIGH or LOW rail.

V_DDBypass Capacitor Guidelines

To enable this IC to turn a device ON quickly, a local

high-frequency bypass capacitor, C_BYP, with low ESR

and ESL should be connected between the VDD and

GND pins with minimal trace length. This capacitor is in

addition to bulk electrolytic capacitance of 10µF to 47µF

commonly found on driver and controller bias circuits.

A typical criterion for choosing the value of C_BYPis to

keep the ripple voltage on the V_DDsupply to ≤ 5%. This

is often achieved with a value ≥ 20 times the equivalent

The purpose of the MillerDrive™ architecture is to

speed up switching by providing high current during the

Miller plateau region when the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

load capacitance C_EQV, defined here as Q_GATE/V_DD

.

Ceramic capacitors of 0.1µF to 1µF or larger are

common choices, as are dielectrics, such as X5R and

X7R, with good temperature characteristics and high

pulse current capability.

For applications with zero voltage switching during the

MOSFET turn-on or turn-off interval, the driver supplies

high peak current for fast switching even though the

Miller plateau is not present. This situation often occurs

in synchronous rectifier applications because the body

diode is generally conducting before the MOSFET is

switched ON.

If circuit noise affects normal operation, the value of

C_BYPmay be increased, to 50-100 times the C_EQV, or

C_BYPmay be split into two capacitors. One should be a

larger value, based on equivalent load capacitance, and

the other a smaller value, such as 1-10nF mounted

closest to the VDD and GND pins to carry the higher-

frequency components of the current pulses. The

bypass capacitor must provide the pulsed current from

both of the driver channels and, if the drivers are

switching simultaneously, the combined peak current

sourced from the C_BYPwould be twice as large as when

a single channel is switching.

The output pin slew rate is determined by V_DDvoltage

and the load on the output. It is not user adjustable, but

a series resistor can be added if a slower rise or fall time

at the MOSFET gate is needed.

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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11

Layout and Connection Guidelines

The FAN3216 and FAN3217 gate drivers incorporate

fast-reacting input circuits, short propagation delays,

and powerful output stages capable of delivering current

peaks over 2A to facilitate voltage transition times from

under 10ns to over 150ns. The following layout and

connection guidelines are strongly recommended:

Figure 31 shows the current path when the gate driver

turns the MOSFET OFF. Ideally, the driver shunts the

current directly to the source of the MOSFET in a small

circuit loop. For fast turn-off times, the resistance and

inductance in this path should be minimized.

.

Keep high-current output and power ground paths

separate from logic input signals and signal ground

paths. This is especially critical for TTL-level logic

thresholds at driver input pins.

.

Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed switching, while reducing the loop area that

can radiate EMI to the driver inputs and

surrounding circuitry.

.

If the inputs to a channel are not externally

connected, the internal 100k resistors indicated

on block diagrams command a low output. In noisy

environments, it may be necessary to tie inputs of

an unused channel to VDD or GND using short

traces to prevent noise from causing spurious

output switching.

Figure 31. Current Path for MOSFET Turn-Off

Many high-speed power circuits can be susceptible

to noise injected from their own output or other

external sources, possibly causing output re-

triggering. These effects can be obvious if the

circuit is tested in breadboard or non-optimal circuit

layouts with long input or output leads. For best

results, make connections to all pins as short and

direct as possible.

.

FAN3216 and FAN3217 are pin-compatible with

many other industry-standard drivers.

The turn-on and turn-off current paths should be

minimized, as discussed in the following section.

Figure 30 shows the pulsed gate drive current path

when the gate driver is supplying gate charge to turn the

MOSFET on. The current is supplied from the local

bypass capacitor, C_BYP, and flows through the driver to

the MOSFET gate and to ground. To reach the high

peak currents possible, the resistance and inductance in

the path should be minimized. The localized C_BYPacts

to contain the high peak current pulses within this driver-

MOSFET circuit, preventing them from disturbing the

sensitive analog circuitry in the PWM controller.

Figure 30. Current Path for MOSFET Turn-On

FAN3216 / FAN3217 • Rev. 1.0.0

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12

Operational Waveforms

At power-up, the driver output remains LOW until the

V_DDvoltage reaches the turn-on threshold. The

magnitude of the OUT pulses rises with V_DDuntil

steady-state V_DDis reached. The non-inverting

operation illustrated in Figure 32 shows that the output

remains LOW until the UVLO threshold is reached, then

the output is in-phase with the input.

The inverting configuration of startup waveforms are

shown in Figure 33. With IN+ tied to VDD and the input

signal applied to IN–, the OUT pulses are inverted with

respect to the input. At power-up, the inverted output

remains LOW until the V_DDvoltage reaches the turn-on

threshold, then it follows the input with inverted phase.

Figure 33. Inverting Startup Waveforms

Figure 32. Non-Inverting Startup Waveforms

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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13

Thermal Guidelines

Gate drivers used to switch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

power. It is important to determine the driver power

dissipation and the resulting junction temperature in the

application to ensure that the part is operating within

acceptable temperature limits.

In the forward converter with synchronous rectifier

shown in the typical application diagrams, the

FDMS8660S is a reasonable MOSFET selection. The

gate charge for each SR MOSFET would be 60nC with

V_GS= V_DD= 7V. At a switching frequency of 500kHz, the

total power dissipation is:

The total power dissipation in a gate driver is the sum of

P_GATE= 60nC • 7V • 500kHz • 2 = 0.42W

P_DYNAMIC= 3mA • 7V • 2 = 0.042W

P_TOTAL= 0.46W

(5)

(6)

(7)

two components, P_GATEand P_DYNAMIC

:

P_TOTAL= P_GATE+ P_DYNAMIC

(1)

Gate Driving Loss: The most significant power loss

results from supplying gate current (charge per unit

time) to switch the load MOSFET on and off at the

switching frequency. The power dissipation that

results from driving a MOSFET at a specified gate-

The SOIC-8 has

characterization parameter of

a

junction-to-board thermal

_JB

= 43°C/W. In a

system application, the localized temperature around

the device is a function of the layout and construction of

the PCB along with airflow across the surfaces. To

ensure reliable operation, the maximum junction

temperature of the device must be prevented from

exceeding the maximum rating of 150°C; with 80%

derating, T_Jwould be limited to 120°C. Rearranging

Equation 4 determines the board temperature required

to maintain the junction temperature below 120°C:

source voltage, V_GS

, with gate charge, Q_G, at

switching frequency, f_SW, is determined by:

P_GATE= Q_G• V_GS• f_SW• n

(2)

where n is the number of driver channels in use (1 or 2).

Dynamic Pre-Drive / Shoot-through Current: A power

loss resulting from internal current consumption under

dynamic operating conditions, including pin pull-up /

pull-down resistors, can be obtained using the graphs

in Typical Performance Characteristics to determine

the current I_DYNAMICdrawn from V_DDunder actual

operating conditions:



T_B= T_J- P_TOTAL

•

(8)

(9)

JB

T_B= 120°C – 0.46W • 43°C/W = 100°C

P_DYNAMIC= I_DYNAMIC• V_DD• n

(3)

Once the power dissipated in the driver is determined,

the driver junction rise with respect to circuit board can

be evaluated using the following thermal equation,

_JB

assuming

was determined for a similar thermal

design (heat sinking and air flow):



T_J

= P_TOTAL

•

_JB+ T_B

(4)

where:

T_J

= driver junction temperature;

_JB

= (psi) thermal characterization parameter

relating temperature rise to total power

dissipation; and

T_B

= board temperature in location as defined in

the Thermal Characteristics table.

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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14

Typical Application Diagrams

Figure 34. Forward Converter

with Synchronous Rectification

Figure 35.

Primary-side Dual Driver

in a Push-pull Converter

Figure 36. Phase-shifted Full-bridge with Two Gate Drive Transformers (Simplified)

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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15

Table 1. Related Products

Part

Number

Gate Drive⁽¹²⁾

(Sink/Src) Threshold

Input

Type

Logic

Package

SOT23-5

Single 1A FAN3111C +1.1A / -0.9A

Single 1A FAN3111E +1.1A / -0.9A

Single 2A FAN3100C +2.5A / -1.8A

Single 2A FAN3100T +2.5A / -1.8A

CMOS

Single Channel of Dual-Input/Single-Output

External⁽¹³⁾Single Non-Inverting Channel with External Reference SOT23-5

CMOS

TTL

Single Channel of Two-Input/One-Output

Dual Inverting Channels

SOT23-5

SOIC8

Dual 2A

FAN3216T +2.4A / -1.6A

FAN3217T +2.4A / -1.6A

FAN3226C +2.4A / -1.6A

FAN3226T +2.4A / -1.6A

FAN3227C +2.4A / -1.6A

FAN3227T +2.4A / -1.6A

FAN3228C +2.4A / -1.6A

FAN3228T +2.4A / -1.6A

FAN3229C +2.4A / -1.6A

FAN3229T +2.4A / -1.6A

TTL

Dual Non-Inverting Channels

CMOS

TTL

Dual Inverting Channels + Dual Enable

Dual Non-Inverting Channels + Dual Enable

CMOS

TTL

CMOS

TTL

Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8

Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8

CMOS

TTL

20V Non-Inverting Channel (NMOS) and Inverting

SOIC8

Dual 2A

FAN3268T +2.4A / -1.6A

FAN3278T +2.4A / -1.6A

TTL

Channel (PMOS) + Dual Enables

30V Non-Inverting Channel (NMOS) and Inverting

SOIC8

Channel (PMOS) + Dual Enables

Dual 4A

FAN3213T +2.5A / -1.8A

FAN3214T +2.5A / -1.8A

FAN3223C +4.3A / -2.8A

FAN3223T +4.3A / -2.8A

FAN3224C +4.3A / -2.8A

FAN3224T +4.3A / -2.8A

FAN3225C +4.3A / -2.8A

FAN3225T +4.3A / -2.8A

TTL

Dual Inverting Channels

SOIC8

TTL

Dual Non-Inverting Channels

CMOS

TTL

Dual Inverting Channels + Dual Enable

Dual Non-Inverting Channels + Dual Enable

Dual Channels of Two-Input/One-Output

Single Inverting Channel + Enable

Single Non-Inverting Channel + Enable

CMOS

TTL

CMOS

TTL

Single 9A FAN3121C +9.7A / -7.1A

Single 9A FAN3121T +9.7A / -7.1A

Single 9A FAN3122T +9.7A / -7.1A

Single 9A FAN3122C +9.7A / -7.1A

Notes:

CMOS

TTL

CMOS

TTL

12. Typical currents with OUTx at 6V and V_DD=12V.

13. Thresholds proportional to an externally supplied reference voltage.

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FAN3216 / FAN3217_F085 • Rev. 1.0.0

16

Physical Dimensions

5.00

4.80

A

0.65

3.81

8

5

B

1.75

6.20

5.80

4.00

3.80

5.60

1

4

PIN ONE

INDICATOR

1.27

(0.33)

M

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.10

0.25

0.19

C

1.75 MAX

0.10

C

0.51

0.33

OPTION A - BEVEL EDGE

0.50

0.25

x 45

R0.10

GAGE PLANE

OPTION B - NO BEVEL EDGE

0.36

NOTES: UNLESS OTHERWISE SPECIFIED

8ٛ

0ٛ

0.90

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

SEATING PLANE

(1.04)

0.406

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

DETAIL A

SCALE: 2:1

Figure 37. 8-Lead Small Outline Integrated Circuit (SOIC)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN3216 / FAN3217_F085 • Rev. 1.0.0

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17

FAN3216 / FAN3217_F085 • Rev. 1.0.0

www.fairchildsemi.com

18


型号：	FAN3217TMX_12
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Dual-2A, High-Speed, Low-Side Gate Drivers 双2A ，高速，低侧栅极驱动器驱动器栅极栅极驱动
文件：	总18页 (文件大小：1309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN3217TMX_12 [FAIRCHILD]

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