74LVX86SJ_08 [FAIRCHILD]
Low Voltage Quad 2-Input Exclusive-OR Gate; 低电压四2输入异或门型号: | 74LVX86SJ_08 |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Low Voltage Quad 2-Input Exclusive-OR Gate |
文件: | 总8页 (文件大小:306K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
February 2008
74LVX86
Low Voltage Quad 2-Input Exclusive-OR Gate
Features
General Description
■ Input voltage level translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
The LVX86 contains four 2-input exclusive-OR gates.
The inputs tolerate voltages up to 7V allowing the inter-
face of 5V systems to 3V systems.
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Information
Order
Number
Package
Number
Package Description
74LVX86M
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX86SJ
74LVX86MTC
MTC14
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
Description
A –A
Inputs
Inputs
Outputs
0
3
3
B –B
0
O –O
0
3
©1993 Fairchild Semiconductor Corporation
74LVX86 Rev. 1.4.0
www.fairchildsemi.com
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
I
Supply Voltage
–0.5V to +7.0V
CC
IK
DC Input Diode Current, V = –0.5V
–20mA
I
V
DC Input Voltage
–0.5V to 7V
I
I
DC Output Diode Current
OK
V
= –0.5V
–20mA
+20mA
O
V
= V + 0.5V
CC
O
V
DC Output Voltage
–0.5V to V + 0.5V
O
CC
I
DC Output Source or Sink Current
25mA
50mA
O
I
or I
DC V or Ground Current
CC
GND
CC
T
Storage Temperature
Power Dissipation
–65°C to +150°C
180mW
STG
P
(1)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
2.0V to 3.6V
0V to 5.5V
0V to V
CC
V
Input Voltage
I
V
Output Voltage
O
CC
T
Operating Temperature
Input Rise and Fall Time
–40°C to +85°C
0ns/V to 100ns/V
A
∆t / ∆V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74LVX86 Rev. 1.4.0
www.fairchildsemi.com
2
DC Electrical Characteristics
T = –40°C to
A
T = +25°C
+85°C
A
Symbol
Parameter
V
Conditions
Min. Typ. Max. Min.
Max. Units
CC
V
HIGH Level Input
Voltage
2.0
3.0
3.6
2.0
3.0
3.6
2.0
1.5
2.0
2.4
1.5
2.0
2.4
V
IH
V
LOW Level Input
Voltage
0.5
0.8
0.8
0.5
0.8
0.8
V
V
IL
V
HIGH Level Output
Voltage
V
= V or V ,
= –50µA
1.9
2.9
2.0
3.0
1.9
2.9
OH
IN
IL
IH
I
OH
3.0
V
= V or V ,
IN
IL
IH
I
= –50µA
OH
V
= V or V ,
2.58
2.48
IN
IL
IH
I
= –4mA
OH
V
LOW Level Output
Voltage
2.0
3.0
V
= V or V ,
= 50µA
0.0
0.0
0.1
0.1
0.1
0.1
V
OL
IN
IL
IH
I
OL
V
= V or V ,
IN
IL
IH
I
= 50µA
OL
V
= V or V ,
= 4mA
0.36
0.1
0.44
1.0
IN
IL
IH
I
OL
I
Input Leakage
Current
3.6
3.6
µA
µA
V
V
= 5.5V or GND
IN
IN
IN
I
Quiescent Supply
Current
= V or GND
2.0
20.0
CC
CC
(2)
Noise Characteristics
T = 25°C
A
Symbol
Parameter
V
(V)
C (pF)
Typ.
Limit
Units
CC
L
V
Quiet Output Maximum Dynamic V
3.3
50
50
50
50
0.3
0.5
–0.5
2.0
V
V
V
V
OLP
OL
V
Quiet Output Minimum Dynamic V
3.3
3.3
3.3
–0.3
OLV
OL
V
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
IHD
V
0.8
ILD
Note:
2. Input t = t = 3ns
r
f
©1993 Fairchild Semiconductor Corporation
74LVX86 Rev. 1.4.0
www.fairchildsemi.com
3
AC Electrical Characteristics
T = –40°C to
A
T = +25°C
+85°C
A
Symbol
Parameter
V
(V) C (pF) Min. Typ. Max. Min. Max. Units
CC L
t
, t
Propagation Delay Time
2.7
15
50
15
50
50
7.5
10.0
5.8
14.5
18.0
9.3
1.0
1.0
1.0
1.0
17.5
21.0
11.0
14.5
1.5
ns
ns
PLH PHL
3.3 0.3
8.3
12.8
1.5
(3)
t
, t
Output to Output Skew
2.7
3.3
OSLH OSHL
1.5
1.5
Note:
3. Parameter guaranteed by design t
= |t
–t
|, t
= |t
–t
|
OSLH
PLHm PLHn OSHL
PHLm PHLn
Capacitance
T = –40°C to
A
T = +25°C
+85°C
A
Symbol
Parameter
Min.
Typ.
4
Max.
Min.
Max. Units
C
Input Capacitance
Power Dissipation Capacitance
10
10
pF
pF
IN
(4)
C
18
PD
Note:
4. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current
PD
consumption without load.
CPD × VCC × fIN × ICC
---------------------------------------------------------
4 (per, Gate)
Average operating current can be obtained by the eqation: I
=
CC(opr.)
©1993 Fairchild Semiconductor Corporation
74LVX86 Rev. 1.4.0
www.fairchildsemi.com
4
Physical Dimensions
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
1.70
1.27
1
7
PIN ONE
INDICATOR
0.51
0.35
1.27
(0.33)
LAND PATTERN RECOMMENDATION
M
0.25
C B A
1.75 MAX
SEE DETAIL A
1.50
1.25
0.25
0.19
0.25
0.10
C
0.10
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.50
0.25
X 45°
R0.10
R0.10
GAGE PLANE
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.36
8°
0°
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1993 Fairchild Semiconductor Corporation
74LVX86 Rev. 1.4.0
www.fairchildsemi.com
5
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1993 Fairchild Semiconductor Corporation
74LVX86 Rev. 1.4.0
www.fairchildsemi.com
6
Physical Dimensions (Continued)
0.43 TYP
0.65
1.65
6.10
0.45
12.00°
TOP & BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
R0.09min
1.00
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1993 Fairchild Semiconductor Corporation
74LVX86 Rev. 1.4.0
www.fairchildsemi.com
7
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
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No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
©1993 Fairchild Semiconductor Corporation
74LVX86 Rev. 1.4.0
www.fairchildsemi.com
8
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