74LVTH322374 [FAIRCHILD]
Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs and 25з Series Resistors in the Outputs (Preliminary); 低电压32位D型触发器带3态输出和25з系列电阻的输出（初步）
| 型号： | 74LVTH322374 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs and 25з Series Resistors in the Outputs (Preliminary) |
| 文件： | 总6页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
February 2001
Revised August 2001
74LVTH322374
Low Voltage 32-Bit D-Type Flip-Flop
with 3-STATE Outputs
and 25Ω Series Resistors in the Outputs (Preliminary)
General Description
Features
■ Input and output interface capability to systems at
The LVTH322374 contains thirty-two non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 32-bit opera-
tion.
5V VCC
■ Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs
■ Live insertion/extraction permitted
■ Power Up/Power Down high impedance provides glitch-
free bus loading
The LVTH322374 is designed with equivalent 25Ω series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
■ Outputs include equivalent series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
■ ESD performance:
The LVTH322374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
Human-body model > 2000V
Machine model > 200V
These flip-flops are designed for low voltage (3.3V) VCC
Charged-device model > 1000V
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH322374 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Ordering Code:
Order Number
Package Number
Package Description
74LVTH322374GX
(Note 1)
BGA96A
(Preliminary)
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS500429
www.fairchildsemi.com
Preliminary
Pin Descriptions for FBGA
Connection Diagram
Pin Names
OEn
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
CPn
I0–I31
O0–O31
3-STATE Outputs
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
O1
O3
O0
O2
OE1
CP1
I0
I2
I1
I3
GND
GND
O5
O4
VCC1 VCC1
I4
I5
O7
O6
GND
GND
GND
GND
I6
I7
O9
O8
I8
I9
O11
O13
O10
O12
VCC1 VCC1
I10
I12
I11
I13
G
GND
OE2
GND
CP2
H
O14
O15
I15
I14
J
K
L
O17
O19
O21
O23
O25
O27
O29
O16
O18
O20
O22
O24
O26
O28
OE3
CP3
I16
I18
I20
I22
I24
I26
I28
I17
I19
I21
I23
I25
I27
I29
(Top Thru View)
GND
GND
VCC2 VCC2
M
N
P
R
GND
GND
GND
GND
VCC2 VCC2
GND
OE4
GND
CP4
T
O30
O31
I31
I30
Truth Tables
Inputs
Outputs
O0–O7
Inputs
OE2
Outputs
O8–O15
CP1
OE1
I0–I7
CP2
I8–I15
L
L
H
L
H
L
L
L
H
L
H
L
L
L
X
X
Oo
Z
L
L
X
X
Oo
Z
X
H
X
H
Inputs
OE3
Outputs
O16–O23
Inputs
OE4
Outputs
O24–O31
CP3
I16–I23
CP4
I24–I31
L
L
H
L
H
L
L
L
H
L
H
L
L
L
X
X
Oo
Z
L
L
X
X
Oo
Z
X
H
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
o = Previous Oo before HIGH-to-LOW of CP
O
Functional Description
The LVTH322374 consists of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs.
The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be
shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common to all
flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their indi-
vidual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the
Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to
the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
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2
Preliminary
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
VCC1 is associated with Bytes 1 and 2.
VCC2 is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.
3
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Preliminary
Absolute Maximum Ratings(Note 2)
Symbol
VCC
VI
Parameter
Supply Voltage
Value
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−50
Conditions
Units
V
V
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
Output in HIGH or LOW State (Note 3)
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
VI < GND
mA
mA
−50
V
V
V
O < GND
64
O > VCC Output at HIGH State
O > VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±64
mA
mA
°C
IGND
TSTG
±128
−65 to +150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
−32
64
Units
Supply Voltage
Input Voltage
V
V
VI
IOH
IOL
TA
HIGH Level Output Current
mA
mA
°C
LOW Level Output Current
Free-Air Operating Temperature
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
−40
85
∆t/∆V
0
10
ns/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
VCC
T
A = −40°C to +85°C
Symbol
Parameter
Units
Conditions
II = −18 mA
(V)
2.7
Min
Max
VIK
Input Clamp Diode Voltage
−1.2
V
V
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
2.7–3.6
2.7–3.6
2.7–3.6
3.0
2.0
V
V
O ≤ 0.1V or
O ≥ VCC − 0.1V
0.8
VOH
V
CC − 0.2
I
I
I
I
OH = −100 µA
OH = −12 mA
OL = 100 µA
OL = 12 mA
V
V
2.0
VOL
Output LOW Voltage
2.7
0.2
0.8
3.0
II(HOLD)
II(OD)
II
Bushold Input Minimum Drive
75
−75
VI = 0.8V
3.0
3.0
µA
µA
VI = 2.0V
Bushold Input Over-Drive
Current to Change State
Input Current
500
(Note 4)
−500
(Note 5)
3.6
3.6
10
±1
VI = 5.5V
Control Pins
Data Pins
VI = 0V or VCC
VI = 0V
µA
−5
3.6
0
1
VI = VCC
IOFF
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
±100
µA
µA
0V ≤ VI or VO ≤ 5.5V
IPU/PD
V
O = 0.5V to 3.0V
0–1.5V
±100
VI = GND or VCC
IOZL
IOZH
IOZH
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
3.6
3.6
−5
5
µA
µA
V
V
V
O = 0.5V
O = 3.0V
+
10
µA
CC < VO ≤ 5.5V
ICCH
ICCL
ICCZ
(VCC1 or VCC2
)
)
)
0.19
5
mA
mA
mA
Outputs HIGH
Outputs LOW
Power Supply Current
(VCC1 or VCC2
(VCC1 or VCC2
Power Supply Current
0.19
Outputs Disabled
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4
Preliminary
DC Electrical Characteristics (Continued)
VCC
T A = −40°C to +85°C
Symbol
ICCZ
Parameter
Units
Conditions
(V)
Min
Max
+
Power Supply Current
(VCC1 or VCC2
)
3.6
0.19
mA
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
∆ICC
Increase in Power Supply Current (VCC1 or VCC2
(Note 6)
)
3.6
0.2
mA
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 7)
VCC
T
A = 25°C
Conditions
Symbol
Parameter
Units
C
L = 50 pF, RL = 500Ω
(V)
3.3
3.3
Min
Typ
0.8
Max
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
V
V
(Note 8)
(Note 8)
−0.8
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A = −40°C to +85°C, CL = 50 pF, RL = 500Ω
CC = 3.3V ± 0.3V CC = 2.7V
Max
Symbol
Parameter
V
V
Units
Min
Max
Min
fMAX
Maximum Clock Frequency
Propagation Delay
CP to On
160
2.2
2.0
1.8
1.8
2.0
2.4
1.8
0.8
3.0
160
2.2
2.0
1.8
1.8
2.0
2.4
2.0
0.1
3.0
MHz
ns
tPHL
tPLH
tPZL
tPZH
tPLZ
tPHZ
tS
4.9
5.3
4.9
5.6
5.0
5.4
5.1
6.2
6.0
6.9
5.1
5.7
Output Enable Time
ns
ns
Output Disable Time
Setup Time
Hold Time
ns
ns
ns
tH
tW
Pulse Width
Capacitance (Note 9)
Symbol
CIN
COUT
Parameter
Conditions
CC = OPEN, VI = 0V or VCC
CC = 3.0V, VO = 0V or VCC
Typical
Units
Input Capacitance
Output Capacitance
V
V
4
8
pF
pF
Note 9: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
5
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Preliminary
Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA96A
Preliminary
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
相关型号：
74LVTH322374GX
Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs and 25з Series Resistors in the Outputs (Preliminary)
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