74LVTH322374ZKER [TI]
3.3V ABT 32 BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS; 3.3V ABT 32位边沿触发的D型触发器具有三态输出
| 型号： | 74LVTH322374ZKER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V ABT 32 BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS |
| 文件： | 总9页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
D
D
Member of the Texas Instruments
Widebus+ Family
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
D
D
D
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
D
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
Flow-Through Architecture Optimizes PCB
Layout
3.3-V V
)
CC
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
D
D
Supports Unregulated Battery Operation
Down to 2.7 V
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
I
and Power-Up 3-State Support Hot
off
Insertion
GKE OR ZKE PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
A
B
C
D
E
F
1Q2
1Q4
1Q6
1Q8
2Q2
2Q4
2Q6
2Q7
3Q2
3Q4
3Q6
3Q8
4Q2
4Q4
4Q6
4Q7
1Q1
1Q3
1Q5
1Q7
2Q1
2Q3
2Q5
2Q8
3Q1
3Q3
3Q5
3Q7
4Q1
4Q3
4Q5
4Q8
1OE
GND
1CLK
GND
1D1
1D3
1D5
1D7
2D1
2D3
2D5
2D8
3D1
3D3
3D5
3D7
4D1
4D3
4D5
4D8
1D2
1D4
1D6
1D8
2D2
2D4
2D6
2D7
3D2
3D4
3D6
3D8
4D2
4D4
4D6
4D7
V
CC
V
CC
GND
GND
GND
GND
E
F
G
H
J
V
CC
V
CC
G
H
J
GND
2OE
3OE
GND
GND
2CLK
3CLK
GND
K
L
K
L
V
CC
V
CC
M
N
P
R
T
GND
GND
GND
GND
M
N
P
R
T
V
CC
V
CC
GND
4OE
GND
4CLK
NC − No internal connection
description/ordering information
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74LVTH322374KR
74LVTH322374ZKER
LFBGA − GKE
LFBGA − ZKE (Pb-free)
−40°C to 85°C
Tape and reel
HW374
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢉꢈ ꢂꢃ
ꢈꢊ ꢈꢋꢅ ꢌ ꢍ ꢆ ꢈ ꢉꢋ ꢍꢎ ꢆ ꢏ ꢐꢑ ꢏꢋꢆ ꢒꢎ ꢑꢑ ꢏꢒ ꢏꢐ ꢐ ꢋꢆꢓ ꢔꢏ ꢕ ꢄꢎ ꢔꢋꢕ ꢄ ꢖ ꢔ
ꢗꢎ ꢆ ꢇ ꢈ ꢋꢀꢆꢌꢆ ꢏ ꢖꢘꢆ ꢔꢘ ꢆꢀ
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The SN74LVTH322374 is a 32-bit edge-triggered D-type flip-flop with 3-state outputs designed for low-voltage
(3.3-V) V operation, but with the capability to provide a TTL interface to a 5-V system environment. It is
CC
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive
transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each 8-bit flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗ ꢎꢆ ꢇ ꢈ ꢋꢀꢆꢌꢆ ꢏ ꢖ ꢘꢆ ꢔꢘ ꢆ
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
A3
H3
H4
2OE
1OE
A4
2CLK
2D1
1CLK
C1
1D
C1
A2
E2
2Q1
1Q1
A5
E5
1D1
1D
To Seven Other Channels
To Seven Other Channels
J3
J4
T3
T4
4OE
3OE
4CLK
3CLK
C1
1D
C1
1D
J2
N2
4Q1
3Q1
J5
N5
4D1
3D1
To Seven Other Channels
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗꢎ ꢆ ꢇ ꢈ ꢋꢀꢆꢌꢆ ꢏ ꢖꢘꢆ ꢔꢘ ꢆꢀ
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
MIN
2.7
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
5.5
−12
12
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
200
−40
CC
T
A
Operating free-air temperature
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 2.7 V,
= 3 V,
I = −18 mA
−1.2
V
V
V
IK
CC
CC
CC
CC
CC
I
I
I
= −12 mA
= 12 mA
2
OH
OL
OH
= 3 V,
0.8
10
1
OL
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
Control inputs
Data inputs
V = V
or GND
I
CC
I
I
I
µA
µA
µA
I
V = V
1
I
CC
V
= 3.6 V
= 0,
CC
CC
V = 0
I
−5
100
V
V or V = 0 to 4.5 V
off
I
O
V = 0.8 V
I
75
V
V
= 3 V
CC
V = 2 V
I
−75
Data inputs
I(hold)
500
−750
‡
= 3.6 V ,
V = 0 to 3.6 V
I
CC
I
I
I
V
CC
V
CC
V
CC
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
−5
µA
µA
µA
OZH
O
= 0.5 V
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V, OE = don’t care
O
100
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V, OE = don’t care
O
100
0.38
10
µA
I
CC
OZPD
Outputs high
V
CC
= 3.6 V, I = 0,
O
Outputs low
I
mA
CC
V = V
CC
or GND
I
Outputs disabled
0.38
V
= 3 V to 3.6 V, One input at V − 0.6 V,
CC
CC
Other inputs at V
§
0.2
mA
∆I
CC
or GND
CC
C
C
V = 3 V or 0
3
9
pF
pF
i
I
V
O
= 3 V or 0
o
†
‡
§
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗ ꢎꢆ ꢇ ꢈ ꢋꢀꢆꢌꢆ ꢏ ꢖ ꢘꢆ ꢔꢘ ꢆ
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V = 3.3 V
CC
0.3 V
V
CC
= 2.7 V
UNIT
MIN MAX
160
MIN
MAX
f
t
t
t
Clock frequency
160
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
3
1.8
0.8
3
2
w
High or low
High or low
ns
su
h
0.1
ns
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 3.3 V
CC
0.3 V
V
= 2.7 V
MAX
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
t
160
160
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
2
2.2
1.8
1.8
2.4
2
3.4
3.3
3.5
3.5
4.2
3.8
5.3
4.9
5.6
4.9
5.4
5
6.2
5.1
6.9
6
CLK
OE
Q
Q
Q
ns
5.7
5.1
ns
ns
OE
0.5
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢉꢈ ꢂꢃ
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ꢗꢎ ꢆ ꢇ ꢈ ꢋꢀꢆꢌꢆ ꢏ ꢖꢘꢆ ꢔꢘ ꢆꢀ
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
S1
Open
GND
500 Ω
TEST
/t
S1
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
L
500 Ω
t
/t
GND
(see Note A)
PHZ PZH
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
Output
1.5 V
1.5 V
1.5 V
1.5 V
t
V
+ 0.3 V
OL
V
OL
(see Note B)
OL
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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