74LCXZ162244MTX [FAIRCHILD]
Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs/Outputs and 26з Series Resistors in the Outputs; 低电压16位缓冲器/线路与5V容限输入/输出和26з系列电阻的输出驱动器
| 型号： | 74LCXZ162244MTX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs/Outputs and 26з Series Resistors in the Outputs |
| 文件： | 总8页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2000
Revised September 2000
74LCXZ162244
Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant
Inputs/Outputs and 26Ω Series Resistors in the Outputs
General Description
Features
■ 5V tolerant inputs and outputs
The LCXZ162244 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
■ Guaranteed power up/down high impedance
■ Supports live insertion/withdrawal
■ Outputs have equivalent 26Ω series resistors
■ 2.7V–3.6V VCC specifications provided
When VCC is between 0 and 1.5V, the LCXZ162244 is in
■ 5.3 ns tPD max (VCC = 3.0V), 20 µA ICC max
■ ±12 mA output drive (VCC = 3.0V)
the high impedance state during power up or power down.
this places the outputs in the high impedance (Z) state pre-
venting intermittent low impedance loading or glitching in
bus oriented applications.
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The LCXZ162244 is designed for low voltage (2.7V or
3.3V) VCC applications with capability of interfacing to a 5V
Human body model > 2000V
signal environment.
Machine model > 200V
In addition the outputs include 26Ω (nominal) series resis-
tors to reduce overshoot and undershoot and are designed
to sink/source 12 mA at VCC = 3.0V.
The LCXZ162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Code:
Package
Order Number
Package Description
Number
74LCXZ162244MEA
MS48A
MS48A
MTD48
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TUBES]
74LCXZ162244MEX
(Note 1)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TAPE and REEL]
74LCXZ162244MTD
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74LCXZ162244MTX
(Note 1)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
© 2000 Fairchild Semiconductor Corporation
DS500251
www.fairchildsemi.com
Connection Diagram
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
I0–I15
O0–O15
Inputs
Outputs
Truth Tables
Inputs
Outputs
O0–O3
Inputs
Outputs
O8–O11
OE1
I0–I3
OE3
I8–I11
L
L
L
H
X
L
H
Z
L
L
L
H
X
L
H
Z
H
H
Inputs
Outputs
O4–O7
Inputs
Outputs
O12–O15
OE2
I4–I7
OE4
I12–I15
L
L
L
H
X
L
H
Z
L
L
L
H
X
L
H
Z
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Functional Description
Logic Diagram
The LCXZ162244 contains sixteen non-inverting buffers
with 3-STATE standard outputs. The device is nibble
(4 bits) controlled with each nibble functioning identically,
but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The
3-STATE outputs are controlled by an Output Enable (OEn)
input for each nibble. When OEn is LOW, the outputs are in
2-state mode. When OEn is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
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2
Absolute Maximum Ratings(Note 2)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE or VCC = 0–1.5V
V
−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 3)
IIK
DC Input Diode Current
DC Output Diode Current
−50
−50
VI < GND
mA
mA
IOK
V
V
O < GND
O > VCC
+50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 4)
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
VCC
5.5
±12
±8
Units
Supply Voltage
Input Voltage
Output Voltage
Operating
V
V
VI
VO
HIGH or LOW State
3-STATE
0
V
0
IOH/IOL
Output Current
V
V
CC = 3.0V − 3.6V
CC = 2.7V − 3.0V
mA
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
Parameter
Conditions
Units
(V)
2.7 − 3.6
2.7 − 3.6
2.7 − 3.6
2.7
Min
Max
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
2.0
V
V
VIL
0.8
VOH
I
I
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −4 mA
OH = −6 mA
OH = −8 mA
OH = −12 mA
OL = 100 µA
OL = 4 mA
V
CC − 0.2
2.2
3.0
2.4
V
V
2.7
3.0
2.0
VOL
LOW Level Output Voltage
2.7 − 3.6
2.7
0.2
0.4
OL = 6 mA
3.0
0.55
0.6
OL = 8 mA
2.7
OL = 12 mA
3.0
0.8
II
Input Leakage Current
0 ≤ VI ≤ 5.5V
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
2.7 − 3.6
±5.0
µA
µA
µA
µA
IOZ
3-STATE Output Leakage
2.7 − 3.6
0
±5.0
10
IOFF
Power-Off Leakage Current
Power Up/Down
VI or VO = 5.5V
VO = 0.5V to VCC
IPU/PD
0 − 1.5
±5.0
3-STATE Output Current
Quiescent Supply Current
VI = GND or VCC
ICC
VI = VCC or GND
2.7 − 3.6
2.7 − 3.6
2.7 − 3.6
225
±225
500
µA
µA
3.6V ≤ VI, VO ≤ 5.5V (Note 5)
∆ICC
Increase in ICC per Input
VIH = VCC −0.6V
3
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DC Electrical Characteristics (Continued)
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500 Ω
CC = 3.3V ± 0.3V CC = 2.7V
L = 50 pF L = 50 pF
Max Max
V
V
Symbol
Parameter
Units
C
C
Min
Min
tPHL
tPLH
tPZL
tPZH
tPLZ
Propagation Delay
Data to Output
1.0
1.0
1.0
1.0
1.0
1.0
5.3
5.3
6.3
6.3
5.4
5.4
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
6.0
6.0
7.1
7.1
5.7
5.7
ns
ns
ns
ns
Output Enable Time
Output Disable Time
tPHZ
tOSHL
tOSLH
Output to Output Skew (Note 6)
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
Parameter
Conditions
Units
(V)
3.3
3.3
Typical
0.8
VOLP
VOLV
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 50 pF, VIH = 3.3V, VIL = 0V
V
V
C
−0.8
Capacitance
Symbol
Parameter
Conditions
CC = Open, VI = 0V or VCC
Typical
Units
pF
CIN
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
V
V
7
8
COUT
CPD
CC = 3.3V, VI = 0V or VCC
pF
CC = 3.3V, VI = 0V or VCC, f = 10 MHz
20
pF
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4
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
VI
6V for VCC = 3.3V, 2.7V
CC * 2 for VCC = 2.5V
CL
50 pF
30 pF
V
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tR = tF = 3ns)
VCC
Symbol
3.3V ± 0.3V
1.5V
1.5V
2.7V
Vmi
Vmo
Vx
1.5V
1.5V
V
V
OL + 0.3V
OH − 0.3V
V
V
OL + 0.3V
OH − 0.3V
Vy
5
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Schematic Diagram Generic for LCX Family
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6
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS48A
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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