74LCXZ16240MTDX [ETC]

BUFFER/DRIVER|QUAD|4-BIT|LCX-CMOS|TSSOP|48PIN|PLASTIC ;
74LCXZ16240MTDX
型号: 74LCXZ16240MTDX
厂家: ETC    ETC
描述:

BUFFER/DRIVER|QUAD|4-BIT|LCX-CMOS|TSSOP|48PIN|PLASTIC

逻辑集成电路 光电二极管 输出元件 输入元件 驱动
文件: 总8页 (文件大小:94K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
March 2002  
Revised March 2002  
74LCXZ16240  
Low Voltage 16-Bit Inverting Buffer/Line Driver  
with 5V Tolerant Inputs/Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCXZ16240 contains sixteen inverting buffers with 3-  
STATE outputs designed to be employed as a memory and  
address driver, clock driver, or bus-oriented transmitter/  
receiver. The device is nibble controlled. Each nibble has  
separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
Guaranteed power up/down high impedance  
Supports live insertion/withdrawal  
2.7V–3.6V VCC specifications provided  
4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max  
±24 mA output drive (VCC = 3.0V)  
When VCC is between 0 and 1.5V, the LCXZ16240 is in the  
high impedance state during power up or power down. This  
places the outputs in the high impedance (Z) state prevent-  
ing intermittent low impedance loading or glitching in bus  
oriented applications.  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
Human body model > 2000V  
The LCXZ16240 is designed for low voltage (2.7V or 3.3V)  
VCC applications with capacity of interfacing to a 5V signal  
Machine model > 200V  
environment.  
The LCXZ16240 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing CMOS low power dissipation.  
Ordering Code:  
Order Number  
74LCXZ16240MEA  
74LCXZ16240MTD  
Package Number  
MS48A  
Package Description  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD48  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagram  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Inputs (Active LOW)  
I0I15  
O0O15  
Inputs  
Outputs  
© 2002 Fairchild Semiconductor Corporation  
DS500257  
www.fairchildsemi.com  
Truth Tables  
Inputs  
Outputs  
O0–O3  
Inputs  
Outputs  
O8–O11  
OE1  
I0–I3  
OE3  
I8–I11  
L
L
L
H
X
H
L
L
L
L
H
X
H
L
H
Z
H
Z
Inputs  
Outputs  
O4–O7  
Inputs  
Outputs  
O12–O15  
OE2  
I4–I7  
OE4  
I12–I15  
L
L
L
H
X
H
L
L
L
L
H
X
H
L
H
Z
H
Z
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
Functional Description  
The LCXZ16240 contains sixteen inverting buffers with 3-  
STATE standard outputs. The device is nibble (4 bits) con-  
trolled with each nibble functioning identically, but indepen-  
dent of the other. The control pins may be shorted together  
to obtain full 16-bit operation. The 3-STATE outputs are  
controlled by an Output Enable (OEn) input for each nibble.  
When OEn is LOW, the outputs are in 2-state mode. When  
OEn is HIGH, the outputs are in the high impedance mode,  
but this does not interfere with entering new data into the  
inputs.  
Logic Diagram  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 1)  
Symbol  
VCC  
VI  
Parameter  
Supply Voltage  
Value  
0.5 to +7.0  
0.5 to +7.0  
0.5 to +7.0  
0.5 to VCC + 0.5  
50  
Conditions  
Units  
V
V
DC Input Voltage  
VO  
DC Output Voltage  
Output in 3-STATE or VCC = 01.5V  
Output in HIGH or LOW State (Note 2)  
VI < GND  
V
IIK  
DC Input Diode Current  
DC Output Diode Current  
mA  
mA  
IOK  
50  
V
O < GND  
+50  
VO > VCC  
IO  
DC Output Source/Sink Current  
DC Supply Current per Supply Pin  
DC Ground Current per Ground Pin  
Storage Temperature  
±50  
mA  
mA  
mA  
°C  
ICC  
±100  
IGND  
TSTG  
±100  
65 to +150  
Recommended Operating Conditions  
(Note 3)  
Symbol  
Parameter  
Min  
2.7  
0
Max  
3.6  
5.5  
VCC  
5.5  
±24  
±12  
85  
Units  
VCC  
Supply Voltage  
Input Voltage  
Output Voltage  
Operating  
V
V
VI  
VO  
HIGH or LOW State  
0
V
3-STATE or VCC = OFF  
0
I
OH/IOL  
Output Current  
V
V
CC = 3.0V 3.6V  
CC = 2.7V 3.0V  
mA  
TA  
Free-Air Operating Temperature  
40  
°C  
t/V  
Input Edge Rate, VIN = 0.8V2.0V, VCC = 3.0V  
0
10  
ns/V  
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated  
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recom-  
mended Operating Conditionstable will define the conditions for actual device operation.  
Note 2: IO Absolute Maximum Rating must be observed.  
Note 3: Unused inputs must be held HIGH or LOW. They may not float.  
DC Electrical Characteristics  
VCC  
TA = −40°C to +85°C  
Symbol  
Parameter  
Conditions  
Units  
(V)  
2.7 3.6  
2.7 3.6  
2.7 3.6  
2.7  
Min  
Max  
VIH  
HIGH Level Input Voltage  
LOW Level Input Voltage  
HIGH Level Output Voltage  
2.0  
V
V
VIL  
0.8  
VOH  
I
I
I
I
I
I
I
I
OH = −100 µA  
OH = −12 mA  
OH = −18 mA  
OH = −24 mA  
OL = 100 µA  
OL = 12 mA  
OL = 16 mA  
OL = 24 mA  
V
CC 0.2  
2.2  
V
V
3.0  
2.4  
3.0  
2.2  
VOL  
LOW Level Output Voltage  
2.7 3.6  
2.7  
0.2  
0.4  
3.0  
0.4  
3.0  
0.55  
±5.0  
II  
Input Leakage Current  
0 VI 5.5V  
0 VO 5.5V  
VI = VIH or VIL  
2.7 3.6  
µA  
µA  
µA  
µA  
IOZ  
3-STATE Output Leakage  
2.7 3.6  
0
±5.0  
10  
IOFF  
Power-Off Leakage Current  
Power Up/Down  
VI or VO = 5.5V  
VO = 0.5V to VCC  
IPU/PD  
0 1.5  
±5.0  
3-STATE Output Current  
Quiescent Supply Current  
VI = GND or VCC  
ICC  
VI = VCC or GND  
2.7 3.6  
2.7 3.6  
2.7 3.6  
225  
±225  
500  
µA  
µA  
3.6V VI, VO 5.5V (Note 4)  
ICC  
Increase in ICC per Input  
VIH = VCC 0.6V  
Note 4: Outputs disabled or 3-STATE only.  
3
www.fairchildsemi.com  
AC Electrical Characteristics  
T
A = −40°C to +85°C, RL = 500 Ω  
CC = 3.3V ± 0.3V CC = 2.7V  
L = 50 pF L = 50 pF  
Max Max  
V
V
Symbol  
Parameter  
Units  
C
C
Min  
Min  
tPHL  
tPLH  
tPZL  
tPZH  
tPLZ  
Propagation Delay  
Data to Output  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
4.5  
4.5  
5.4  
5.4  
5.3  
5.3  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
5.3  
5.3  
6.0  
6.0  
5.4  
5.4  
ns  
ns  
ns  
ns  
Output Enable Time  
Output Disable Time  
tPHZ  
tOSHL  
tOSLH  
Output to Output Skew (Note 5)  
Note 5: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The  
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).  
Dynamic Switching Characteristics  
VCC  
TA = 25°C  
Symbol  
Parameter  
Conditions  
Unit  
(V)  
3.3  
3.3  
Typical  
0.8  
VOLP  
VOLV  
Quiet Output Dynamic Peak VOL  
Quiet Output Dynamic Valley VOL  
C
L = 50 pF, VIH = 3.3V, VIL = 0V  
L = 50 pF, VIH = 3.3V, VIL = 0V  
V
V
C
0.8  
Capacitance  
Symbol  
Parameter  
Conditions  
CC = Open, VI = 0V or VCC  
Typical  
Units  
pF  
CIN  
Input Capacitance  
Output Capacitance  
Power Dissipation Capacitance  
V
V
V
7
8
COUT  
CPD  
CC = 3.3V, VI = 0V or VCC  
pF  
CC = 3.3V, VI = 0V or VCC, f = 10 MHz  
20  
pF  
www.fairchildsemi.com  
4
AC LOADING and WAVEFORMS Generic for LCX Family  
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)  
VI  
CL  
6V for VCC = 3.3V, 2.7V  
50 pF  
30 pF  
V
CC * 2 for VCC = 2.5V  
3-STATE Output High Enable and  
Disable Times for Logic  
Waveform for Inverting and Non-Inverting Functions  
Setup Time, Hold Time and Recovery Time for Logic  
Propagation Delay. Pulse Width and trec Waveforms  
trise and tfall  
3-STATE Output Low Enable and  
Disable Times for Logic  
FIGURE 2. Waveforms  
(Input Characteristics; f =1MHz, tR = tF = 3ns)  
VCC  
Symbol  
3.3V ± 0.3V  
1.5V  
2.7V  
1.5V  
Vmi  
Vmo  
Vx  
1.5V  
1.5V  
V
OL + 0.3V  
V
OL + 0.3V  
Vy  
V
OH 0.3V  
VOH 0.3V  
5
www.fairchildsemi.com  
Schematic Diagram Generic for LCX Family  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
Package Number MS48A  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Package Number MTD48  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
8

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