XRK697H73CR [EXAR]
1:12 LVCMOS PLL CLOCK GENERATOR; 1:12 LVCMOS PLL时钟发生器
| 型号： | XRK697H73CR |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 1:12 LVCMOS PLL CLOCK GENERATOR |
| 文件： | 总12页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
APRIL 2006
REV.P1.0.0
faster clock prior to coincident rising edges of Bank A and
Bank C clocks. QSYNC then goes high again when the
coincident rising edges of Bank A and Bank C occur. This
feature is used primarily in applications where Bank A and
Bank C are running at different frequencies, and is
particularly useful when they are running at non-integer
multiples of one another.
GENERAL DESCRIPTION
The XRK697H73 is a PLL based LVCMOS Clock Generator
targeted for high performance and low skew clock distribu-
tion applications. The XRK697H73 can select between
one of three reference inputs and provides 14 LVCMOS
outputs -12 outputs (3 banks of 4) for clock distribution, 1
for feedback and 1 for synchronization.
The XRK697H73 has an output frequency range of
8.33MHz to 240MHz and an input frequency range of 5MHz
to 120MHz.
The XRK697H73 is a highly flexible device. It has 3 select-
able inputs, (one differential and two single-ended inputs) to
support system clock redundancy. Up to three different
clock frequencys can be generated and outputted on the
three output banks. Switching the internal reference clock
is controlled by the control input, CLK_SEL.
FEATURES
• Fully Integrated PLL
• Selectable Differential PECL or LVCMOS inputs for
reference clock source
The XRK697H73 uses PLL technology to frequency lock its
outputs to the input reference clock. The divider in the feed-
back path will determine the frequency of the VCO. Each of
the separate output banks can individually divide down the
VCO output frequency. This allows the XRK697H73 to
generate a multitude of different bank frequency ratios and
output-to-input frequency ratios.
• 14 LVCMOS outputs
■ 3 banks with 4 outputs each. Frequencies can
be individually controlled by bank
■ 1 dedicated feedback with frequency control
■ 1 Sync
• VCO Range 200MHz to 480MHz
• Output freq. range: 8.33MHz to 240MHz
• Max Output Skew of 250ps
The outputs of the XRK697H73 can individually be immobi-
lized, in the low state, by use of the clock stop feature. All
outputs except QC0 and QFB can be immobilized through a
2 pin serial interface. Global output disabling and reset can
be achieved the control input MR/OE.
• Cycle-to-cycle jitter: 150ps (typ)
APPLICATIONS
The XRK697H73 also has a QSYNC output which can be
used for system synchronization purposes. It monitors
Bank A and Bank C outputs and goes low one period of the
• System Clock generator
• Zero Delay Buffer
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
XRK697H73CR
XRK697H73IR
PACKAGE TYPE
52-LEAD LQFP
52-LEAD LQFP
OPERATING TEMPERATURE RANGE
0°C to +70°C
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRK697H73
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
REV.P1.0.0
FIGURE 1. BLOCK DIAGRAM OF THE XRK697H73
STOP
STOP
STOP
STOP
QA0
QA1
QA2
QA3
PECL
XTAL
0
1
PECL
CLK0
DIVIDER SELECT
÷4, ÷6,
0
1
VDD
0
Ref
VCO
BANK A
÷8, ÷12
÷2
0
1
÷4, ÷6,
BANK B
÷8, ÷10
÷2, ÷4,
BANK C
PLL
CLK1
1
÷6, ÷8
÷4, ÷6, ÷8,
200-480MHz
CLK_SEL
STOP
STOP
STOP
STOP
÷10, ÷12,
FB
QB0
QB1
QB2
QB3
÷16, ÷20
VDD
Sync Pulse
REF_SEL
FB_IN
FB
VCO_SEL
PLL_EN
VDD
QC0
QC1
QC2
QC3
2
2
2
3
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
FSEL_FB[2:0]
STOP
STOP
STOP
0
1
POWER-ON RESET
VDD
QFB
INV_CLK
STOP
QSYNC
STOP_DATA
STOP_CLK
12
SERIAL
INTERFACE
MR/OE
FIGURE 2. PIN OUT OF THE XRK697H73
52 51 50 49 48 47 46 45 44 43 42 41 40
GND
___
1
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
QB0
VDD
QB1
GND
QB2
VDD
QB3
FB_IN
GND
QFB
VDD
MR/OE
STOP_CLK
STOP_DATA
FSEL_FB2
PLL_EN
2
3
4
5
6
REF_SEL
CLK_SEL
CLK0
7
XRK697H73
8
9
CLK1
10
11
12
13
PECL
PECL
VDD_PLL
FSEL_FB0
14 15 16 17 18 19 20 21 22 23 24 25 26
2
PRELIMINARY
XRK697H73
REV. P1.0.0
1:12 LVCMOS PLL CLOCK GENERATOR
PIN DESCRIPTIONS
PIN #
NAME
TYPE
DESCRIPTION
1,15, 24, 30,
35, 39, 47, 51
GND
POWER
Power supply ground
2
MR/OE
INPUT*
Master reset and output enable. High = output enabled, Low = device
reset & outputs tri-stated
3
STOP_CLK
STOP_DATA
FSEL_FB[2:0]
PLL_EN
INPUT*
INPUT*
INPUT*
INPUT*
INPUT*
Clock input for serial control.
4
Data input for serial control
5, 26, 27
Select inputs for control of feedback divide value.
PLL bypass. High = PLL, Low = PLL bypass
6
7
REF_SEL
Xtal or CLK select. High = Xtal input selected, Low = CLK0 or CLK1
selected
8
CLK_SEL
INPUT*
CLK0 or CLK1 Select. High = CLK1 selected, Low= CLK0 selected
PLL Reference Clock Inputs
9
CLK0
CLK1
INPUT*
INPUT*
10
11
12
PECL
PECL
INPUT
Diffferential LVPECL Clock Input
13
14
VDD_PLL
INV_CLK
VDD
POWER
INPUT*
POWER
Analog supply for PLL
Invert clock select for QC3 & QC2. High = invert, Low = normal operation
Power supply for outputs.
17, 22, 28,
33, 37, 45, 49
19,20
FSEL_C[1:0]
QSYNC
INPUT*
Bank C divide select pins.
25
29
OUTPUT Synchronization output for Bank A and Bank C.
OUTPUT Feedback clock output
QFB
31
FB_IN
INPUT*
Feedback input
32, 34, 36, 38
40, 41
QB[3:0]
OUTPUT Clock outputs (Bank B)
FSEL_B[1:0]
FSEL_A[1:0]
QA[3:0]
INPUT*
INPUT*
Bank B divide select pins.
Bank A divide select pins.
42, 43
44, 46, 48, 50
52
OUTPUT Clock outputs (Bank A)
INPUT* VCO select. High = VCO/1, Low = VCO/2.
VCO_SEL
* 25KΩ pull-up resistor
3
XRK697H73
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
1.0 ELECTRICAL SPECIFICATIONS
REV.P1.0.0
TABLE 1: GENERAL SPECIFICATIONS
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
VTT
Output Termination Voltage
VDD÷2
V
ESDMM
ESD Protection (Machine model)
200
V
V
ESDHBM
ESD Protection (Human body
model)
2000
LU
Latch-up Immunity
Input capacitance
200
mA
pf
CIN
per input
4
TABLE 2: ABSOLUTE MAXIMUM RATINGS
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
VDD
Supply Voltage
-0.3
3.9
V
VIN
VOUT
IIN
DC Input Voltage
DC Output Voltage
DC Input Current
-0.3
-0.3
VDD + 0.3
VDD + 0.3
+/-20
V
V
mA
mA
°C
IOUT
TS
DC Output Current
Storage Temperature
+/-50
-65
125
TABLE 3: DC CHARACTERISTICS (V
= 3.3V +/- 5%)
DD
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
VDD_PLL
PLL Supply Voltage
3.0
VDD
V
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
VDD+ 0.3
0.8
V
V
VPP
VCMR
VOH
VOL
Peak to Peak Input Voltage PECL and PECL
Common Mode Range PECL and PECL
Output High Voltage
LVPECL
LVPECL
250
1.0
2.4
mV
V
VDD - 0.6
IOH = -24mA
V
Output Low Voltage
IOL = 24mA
IOL = 12mA
0.55
0.30
V
ZOUT
IPU
IDD_PLL
IDDQ
Output Impedance
Input Current
8-11
8
Ω
VIN = GND or VDD
@ VDD_PLL Pin
-100
200
13.5
35
µA
mA
mA
PLL Supply Current
Quiescent Supply Current
4
PRELIMINARY
XRK697H73
REV. P1.0.0
1:12 LVCMOS PLL CLOCK GENERATOR
TABLE 4: AC CHARACTERISTICS (V
= 3.3V +/- 5%)
DD
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
Input reference frequencya
fREF
÷4 feedback
÷6 feedback
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
120
80.0
60.0
48.0
40.0
30.0
24.0
20.0
15.0
12.0
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
PLL bypass mode
fVCO
fMAX
VCO frequency range
Output frequencya
200
480
MHz
÷2 output
÷4 output
÷6 output
÷8 output
÷10 output
÷12 output
÷16 output
÷20 output
÷24 output
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
240.0
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fSTOP_CLK
VPP
Serial interface frequency
20.0
MHz
mV
Peak to Peak Input Voltage
PECL and PECL
LVPECL
LVPECL
400
1.2
2.0
1000
VCMR
Common Mode Range PECL
and PECL
VDD - 0.9
V
tPW
ItR, ItF
t(∅)
CLKx pulse width
ns
ns
Input CLKx Rise/Fall time
0.8V to 2.0V
1
Propagation Delay (static
phase offset) CLKx to FB_INb
6.25MHz < fREF < 65.0MHz
65.0MHz < fREF < 125MHz
fREF = 50MHz & FB = ÷8
-3
-4
+3
+4
°
°
-166
+166
ps
tSK(O)
Output to output skew
Bank A (QAx to QAy)
Bank B (QBx to QBy)
Bank C (QCx to QCy)
100
100
100
250
ps
ps
ps
ps
all outputs (QXy to QWz)c
Output duty cycled
DC
(T÷2)-200
0.1
T÷2
(T÷2)+200
1.0
ps
ns
OtR, OtF
Output Rise/Fall time
0.55 to 2.4V
5
XRK697H73
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
REV.P1.0.0
TABLE 5: AC CHARACTERISTICS (CON’T) (V
= 3.3V +/- 5%)
DD
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
tPLZ, tPHZ
Output Disable Time
8
ns
tPZL, tPZH
tJIT(CC)
Output Enable Time
Cycle-to-Cycle Jitter
8
ns
ps
All outputs in same divider
config.
150
200
tJIT(PER)
Period Jitter
All outputs in same divider
config.
150
ps
tJIT(Ø)
I/O Phase Jitter RMS (1 σ)
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
11
86
13
88
16
19
21
22
27
30
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
VCO = 400MHz
BW
PLL closed loop bandwidth
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
1.20-3.5
0.70-2.50
0.50-1.80
0.45-1.20
0.30-1.00
0.25-0.70
0.20-0.55
0.17-0.40
0.12-0.30
0.11-0.28
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
tLOCK
PLL Lock Time
10
ms
NOTES:
a. PLL locked, except when configured in bypass mode.
b. t(Ø)[s] = t(Ø)[°] ÷ (fref x 360°)
c. Not including Qsync output
d. T is the output period.
FIGURE 3. TEST LOAD
Transmission Line
Z = 50Ω
50Ω
VTT
6
PRELIMINARY
XRK697H73
REV. P1.0.0
1:12 LVCMOS PLL CLOCK GENERATOR
2.0 CONFIGURATION TABLES
TABLE 6: FUNCTION CONTROLS
CONTROL PIN
LOGIC 0
LOGIC 1
MR/OE
Resets the output divide circuitry and serial
interface, tri-states all outputs
Enables all outputs - normal operation
PLL_EN
PLL bypass mode enabled. This is a test
mode in which the reference clock is provided
to the output dividers in place of the VCO.
PLL enabled - normal operation
REF_SEL
CLKx selected as ref source to PLL
PECL & PECL inputs selected as ref source to
PLL
CLK_SEL
INV_CLK
CLK0 selected
CLK1 selected
QC2 & QC3 are in phase with QC1 & QC4
QC2 & QC3 are 180°out of phase with QC1 &
QC4
VCO_SEL
VCO ÷ 2
no divide of VCO
TABLE 7: BANK OUTPUT DIVIDER CONTROLS
INPUT
OUTPUT
QA
INPUT
OUTPUT
QB
INPUT
OUTPUT
FSEL_A1 FSEL_A0
FSEL_B1
FSEL_B0
FSEL_C1
FSEL_C0
QC
÷2
÷4
÷6
÷8
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷6
÷6
÷8
÷8
÷12
÷10
TABLE 8: FEEDBACK DIVIDER CONTROL
FSEL_FB2
FSEL_FB1
FSEL_FB0
QFB
÷4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷6
÷8
÷10
÷8
÷12
÷16
÷20
7
XRK697H73
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
3.0 QSYNC TIMING
REV.P1.0.0
FIGURE 4. QSYNC TIMING DIAGRAM
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
1
2
3
4
5
6
7
8
9
fVCO
1:1 Mode
2:1 Mode
3:1 Mode
3:2 Mode
4:1 Mode
4:3 Mode
6:1 Mode
QA
QC
QSYNC
QA
QC
QSYNC
QC(/2)
QA(/6)
QSYNC
QA(/4)
QC(/6)
QSYNC
QC(/2)
QA(/8)
QSYNC
QA(/6)
QC(/8)
QSYNC
QA(/12)
QC(/2)
QSYNC
XRK697H73 INDIVIDUAL OUTPUT DISABLE (STOP CLOCK) CIRCUITRY
The user can write to the serial input register through the STOP_DATA input by supplying a logic ’0’ start bit
followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the
free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the XRK697H73 can
sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. A logic "0" to any stop
bit location will disable the corresponding device output while a logic "1" will enable. All outputs are by default,
enabled.
FIGURE 5. STOP CLOCK CIRCUIT PROGRAMMING
STOP_CLK
START
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
STOP_DATA
8
PRELIMINARY
XRK697H73
REV. P1.0.0
1:12 LVCMOS PLL CLOCK GENERATOR
FIGURE 6. OUTPUT-TO-OUTPUT SKEW t
SK(O)
VCC
VCC÷2
GND
VCC
VCC÷2
GND
tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device.
FIGURE 7. PROPOGATION DELAY (t , STATIC PHASE OFFSET) TEST REFERENCE
(Ø)
VCC
CCLKx
VCC÷2
GND
VCC
VCC÷2
GND
FB_IN
t(Ø)
FIGURE 8. OUTPUT DUTY CYCLE (DC)
VCC
VCC÷2
GND
tp
T0
DC=tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
FIGURE 9. I/O JITTER
CCLKx
FB_IN
TJIT(I/O) = |T0-T1mean |
The deviation in t0 for a controlled edge with respect to a t0 mean in a random
sample of cycles
9
XRK697H73
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
REV.P1.0.0
FIGURE 10. CYCLE-TO-CYCLE JITTER
TJIT(CC)= |TN-TN+1
|
TN+1
TN
The variation in cycle time of a signal between adjacent cycles, over a random
sample of adjacent cycle pairs
FIGURE 11. PERIOD JITTER
T0
TJIT(Per)= |TN-1/f0 |
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
FIGURE 12. OUTPUT TRANSITION TIME TEST REFERENCE
VCC=3.3V
2.4
0.55
OtF
OtR
10
PRELIMINARY
XRK697H73
REV. P1.0.0
1:12 LVCMOS PLL CLOCK GENERATOR
PACKAGE DIMENSIONS
E
52 LEAD LOW-PROFILE QUAD FLAT PACK
(10 mm x 10 mm X 1.4 mm LQFP, 1.0 mm Form)
Rev. 1.00
Note: The control dimension is in millimeters.
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.063
0.006
0.057
0.014
0.009
0.480
0.398
MIN
1.40
0.05
1.35
0.25
0.11
11.80
9.90
MAX
1.60
0.15
1.45
0.35
0.23
12.20
10.10
A
A1
A2
B
C
D
0.055
0.002
0.053
0.010
0.004
0.465
0.390
D1
e
0.0256 BSC
0.65 BSC
L
α
0.029
0°
0.041
7°
0.73
0°
1.03
7°
α
11
XRK697H73
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
REV.P1.0.0
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
P1.0.0
April 7, 2006 Initial release.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet April 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
12
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