XRK799J93IQ [EXAR]

INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER; 智能动态时钟切换PLL时钟驱动器
XRK799J93IQ
型号: XRK799J93IQ
厂家: EXAR CORPORATION    EXAR CORPORATION
描述:

INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
智能动态时钟切换PLL时钟驱动器

时钟驱动器 逻辑集成电路
文件: 总10页 (文件大小:226K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
xr  
XRK799J93  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
DECEMBER 2006  
REV.1.0.1  
be latched (H). If that CLK is the primary clock, the  
device will switch to the good secondary clock and  
GENERAL DESCRIPTION  
The XRK799J93 is a PLL clock driver designed  
specifically for redundant clock tree designs. The  
device receives two differential LVPECL clock signals  
from which it generates 5 new differential LVPECL  
clock outputs. Two of the output pairs regenerate the  
input signals frequency and phase while the other  
three pairs generate 2x, phase aligned clock outputs.  
External PLL feedback is used to also provide zero  
delay buffer performance.  
phase/frequency alignment will occur with minimal  
output phase disturbance. The typical phase bump  
caused by a failed clock is eliminated.  
FEATURES  
Fully Integrated PLL  
Intelligent Dynamic Clock Switch  
LVPECL Clock Outputs  
LVCMOS Control I/O  
3.3V Operation  
The XRK799J93 Intelligent Dynamic Clock Switch  
circuit continuously monitors both input CLK signals.  
Upon detection of a failure (CLK stuck HIGH or LOW  
for at least 1 period), the INP_BAD for that CLK will  
32-Lead TQFP Packaging  
FIGURE 1. BLOCK DIAGRAM OF THE XRK799J93  
_
CLK Selected  
INP1Bad  
INP0Bad  
Dynamic  
Switch  
Logic  
Qb0  
Qb0  
_
Man Override  
_
Alarm  
Reset  
_
Sel CLK  
Qb1  
Qb1  
CLK0  
CLK0  
CLK1  
CLK1  
Qb2  
Qb2  
÷2  
÷4  
PLL  
Qa0  
Qa0  
Ext_FB  
Ext_FB  
-
160 380MHz  
Qa1  
Qa1  
PLL_En  
MR  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  
XRK799J93  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
REV.1.0.1  
PRODUCT ORDERING INFORMATION  
PRODUCT NUMBER  
PACKAGE TYPE  
OPERATING TEMPERATURE RANGE  
XRK799J93IQ  
32-Lead TQFP  
-40°C to +85°C  
FIGURE 2. PIN OUT OF THE XRK799J93  
Qa1  
25  
VCC  
16  
Qa1  
26  
Inp0bad  
15  
Qa0  
27  
Inp1bad  
14  
Qa0  
28  
CLK_Selected  
13  
XRK799J93  
VCC  
29  
GND  
12  
VCCA  
30  
Ext_FB  
11  
Man_Override  
31  
Ext_FB  
10  
PLL_En  
32  
GND  
9
2
XRK799J93  
REV. 1.0.1  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
PIN DESCRIPTIONS  
PIN NAME  
TYPE  
DESCRIPTION  
CLK0, CLK0  
CLK1, CLK1  
LVPECL Input  
LVPECL Input  
Clock 0 - Differential PLL clock reference (CLK0 pulldown, CLK0 pulldown)  
Clock 1 - Differential PLL clock reference (CLK1 pulldown, CLK1 pulldown)  
Ext_FB, Ext_FB  
Qa[1:0], Qa[1:0]  
Qb[2:0], Qb[2:0]  
LVPECL Input  
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pulldown)  
LVPECL Output Differential 1x output pairs, connect one QaX pair to Ext_FB  
LVPECL Output Differential 2x output pairs  
Indicates detection of a bad input reference Clock 0 with respect to the feed-  
back signal. The output is active HIGH and will remain HIGH until the alarm  
reset is asserted.  
Inp0bad  
LVCMOS Output  
LVCMOS Output  
Indicates detection of a bad input reference Clock 1 with respect to the feed-  
back signal. The output is active HIGH and will remain HIGH until the alarm  
reset is asserted.  
Inp1bad  
CLK_Selected  
LVCMOS Output 0 - if CLK0 is selected  
1 - if CLK1 is selected  
0 - will reset the input bad flags and align CLK_Selected with Sel_CLK. The  
input is one-shotted  
Alarm_Reset  
Sel_CLK  
LVCMOS Input  
1 - normal operation (50KΩ pullup).  
LVCMOS Input 0 - selects CLK0  
1 - selects CLK1 (50kΩ pulldown)  
Man_Override  
PLL_En  
MR  
LVCMOS Input 0 - normal operation  
1 - disables internal clock switch circuitry (50KΩ pulldown).  
LVCMOS Input 0 - bypasses the phase-locked loop, input CLKx directly drives divider block  
1 - selected input reference applied to PLL (50KΩ pullup).  
LVCMOS Input 0 - resets the internal dividers forcing outputs LOW. Asynchronous to the clock  
1 - normal operation (50KΩ pullup).  
VCCA  
VCC  
Power Supply  
Power Supply  
Power Supply  
Power Supply  
PLL power supply  
Digital power supply  
PLL Ground  
GNDA  
GND  
Digital Ground  
3
XRK799J93  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
REV.1.0.1  
a
ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
CHARACTERISTICS  
MIN  
MAX  
UNIT  
CONDITION  
V
Supply Voltage  
-0.3  
3.9  
V
CC  
V
DC Input Voltage  
-0.3  
-0.3  
V
+0.3  
CC  
V
V
IN  
V
DC Output Voltage  
OUT  
I
+20  
mA  
mA  
°C  
DC Input Current  
IN  
I
DC Output Current  
Storage Temperature  
+50  
125  
OUT  
T
-65  
S
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur.  
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional  
operation at absolute-maximum-rated conditions is not implied.  
GENERAL SPECIFICATIONS  
SYMBOL  
CHARACTERISTICS  
MIN  
TYP  
MAX  
UNIT  
CONDITION  
V
Output termination voltage  
V
-2  
V
TT  
CC  
MM  
HBM  
LU  
ESD Protection (Machine model)  
ESD Protection (Human body model)  
Latch-up immunity  
200  
2000  
200  
V
V
mA  
pF  
C
Input Capacitance  
4.0  
Inputs  
IN  
θ
Thermal resistance junction to ambient  
JESD 51-3, single layer test board  
Natural convection  
JA  
62.0  
°C/W  
JESD 51-6, multilayer test board  
Thermal resistance junction to case  
47  
14  
°C/W  
°C/W  
θ
JC  
Operating junction temperature  
115  
°C  
4
XRK799J93  
REV. 1.0.1  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
DC CHARACTERISTICS (V = 3.3 + 5%, T = -40°C TO +85°C)  
CC  
A
SYMBOL  
CHARACTERISTICS  
MIN  
TYP  
MAX  
UNIT  
CONDITION  
LVCMOS control inputs (MR, PLL_En, Sel_CLK, Man_Override, Alarm_Reset)  
V
Input voltage high  
Input voltage low  
2.0  
VCC+0.3  
0.8  
V
V
IH  
V
I
IL  
Man_Override, Sel_CLK  
(pull down)  
100  
μA  
V =V  
IN  
CC  
Input Current  
IN  
PLL_En, MR, Alarm_Reset  
(pull up)  
-100  
2.0  
μA  
V =GND  
IN  
LVCMOS Control Outputs  
Output High Voltage  
Output Low Voltage  
LVPECL clock inputs (CLK, CLK)  
Input current  
LVPECL clock outputs (Qa[1:0], Qa[1:0], Qb[2:0], Qb[2:0])  
V
V
V
I
I
=-10mA  
OH  
OH  
V
0.55  
=10mA  
OL  
OL  
b
I
+100  
μΑ  
V
=V or V =GND  
IN  
IN  
CC  
IN  
V
Output high voltage  
Output low voltage  
V
V
-1.2  
V
-0.7  
V
V
Termination 50Ω to V  
Termination 50Ω to V  
OH  
CC  
CC  
TT  
TT  
V
-1.9  
V
-1.45  
CC  
OL  
CC  
Supply Current  
I
Maximum ground supply current - gnd pins  
Maximum PLL power supply - VCC_PLL pin  
180  
15  
mA GND pins  
mA pin  
GND  
I
V
CCPLL  
CCPLL  
a. Inputs have internal pullup/pulldown resistors which affect the input current.  
b. Clock inputs driven by LVPECL compatible signals.  
5
XRK799J93  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
REV.1.0.1  
AC CHARACTERISTICS (V = 3.3 + 5%, T = -40°C TO +85°C) f  
CC  
A
SYMBOL  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
CONDITION  
f
Input Reference Frequency  
PLL VCO Lock Range  
÷4 feedback  
40  
95  
MHz  
Locked  
ref  
f
f
160  
380  
MHz  
MHz  
Qa output used  
for feedback  
VCO  
Output Frequency  
Qa[1:0]  
Qb[2:0]  
40  
80  
95  
MAX  
190  
f
Reference Input Duty Cycle  
Propagation Delay  
25  
75  
%
refDC  
t
pd  
c
-150  
0.25  
150  
5
ps  
ns  
PLL_En=1  
PLL_En=0  
CLKn to Ext_FB (SPO)  
CLKn to Q (Bypass)  
g
V
1.3  
V
V
PP  
CMR  
skew  
Differential peak-to-peak input voltage  
h
V
V
-1.7  
V
-0.3  
CC  
CC  
Differential input crosspoint voltage  
t
Output-to-Output Skew  
Within Qa[1:0] or Qb[2:0]  
All outputs  
50  
ps  
80  
Δ
Rate of change of periods  
per/cycle  
d
d
e
e
ps/  
cycle  
Qa[1:0]  
Qb[2:0]  
Qa[1:0]  
Qb[2:0]  
50  
25  
400  
200  
DC  
Output duty cycle  
45  
55  
40  
%
ps  
ms  
ps  
t
@ f =75MHZ  
ref  
jitter  
Cycle-to-cyle jitter, Standard deviation (RMS)  
Maximum PLL lock time  
t
10  
lock  
t /t  
50  
700  
r f  
Output Rise/Fall time  
c. Static phase offset between the selected reference clock and the feedback signal.  
d. Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change  
per cycle is averaged over the clock switch excursion. (See Applications Information section for more detail)  
e. Specification holds for a clock switch between two signals no greater than ±± out of phase. Delta period change per  
cycle is averaged over the clock switch excursion.  
f. PECL output termination is 50 ohms to VCC – 2.0V.  
g. V is the minimum differential input voltage swing required to maintain AC characteristic including SPO, device and  
PP  
part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB.  
h. V  
is the crosspoint of the differential input signal. Normal operation is obtained when the crosspoint is within the  
CMR  
CMR  
V
range and the input swing lies within the V specification. Violation of V  
or V impacts the SPO, device  
CMR PP  
PP  
and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB.  
6
XRK799J93  
REV. 1.0.1  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
APPLICATIONS INFORMATION  
The XRK799J93 is a dual clock PLL with on–chip Intelligent Dynamic Clock Switch circuitry.  
DEFINITIONS  
primary clock: The input CLK selected by Sel_Clk.  
secondary clock: The input CLK NOT selected by Sel_Clk.  
PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or the Intelligent Dynamic  
Clock Switch. The Intelligent Dynamic Clock Switch can override Sel_Clk.  
STATUS FUNCTIONS  
Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H)  
indicates CLK1 is selected as the PLL reference signal.  
Inp0bad, Inp1bad: Inp0bad is latched (H) when CLK0 is stuck (H) or (L) for at least one Ext_FB period, or if one  
of the inputs CLK0 or CLK0 is floating. Inp1bad is latched (H) when CLK1 is stuck (H) or (L) for at least one  
Ext_FB period, or if one of the inputs CLK1 or CLK1 is floating. Both Inp0bad and Inp1bad are latched (H)  
when Ext_FB is stuck (H) or (L) for at least one Qa period, or if one of the inputs Ext_FB or Ext _FB is floating.  
Both Inp0bad and Inp1bad are cleared (L) on assertion of Alarm_Reset. The status functions Inp0bad and  
Inp1bad are active for Man_Override (H) or (L).  
CONTROL FUNCTIONS  
Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock.  
Alarm_Reset: Asserted by a negative edge. Generates a one–shot reset pulse that clears INPUT_BAD latches  
and Clk_Selected latch.  
PLL_En: While (L), the PLL reference signal is substituted for the VCO output.  
MR: While (L), internal dividers are held in reset which holds all Q outputs LOW.  
MAN OVERRIDE (H)  
(IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be  
the CLK selected by Sel_Clk. If Ext_FB misses at least one pulse, Qa and Qb outputs will drop to a minimum  
frequency (~20MHz) for 1-uS, or until Ext_FB shows any activity, whichever is longer. This prevents the Qa  
and Qb frequencies from rising due the PLL incorrectly interpreting an intermittent Ext_FB as a VCO running  
too slow.  
MAN OVERRIDE (L)  
Intelligent Dynamic Clock Switch is enabled. The first CLK to fail will latch it’s INP_BAD (H) status flag and  
select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and  
INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and  
Clk_Selected = Sel_Clk).  
If both Inp0bad and Inp1bad are (H), either due to both CLK0 and CLK1 having missed at least 1 pulse each or  
Ext_FB having missed at least 1 pulse, then Qa and Qb outputs will drop to a minimum frequency (~20MHz)  
until such time as Alarm_Reset_b is asserted.  
NOTE: If both CLKs are bad when Alarm_Reset is asserted, both INP_BADs will be latched (H) after one Ext_FB period  
and Clk_Selected will be latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched  
(H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by the  
Intelligent Dynamic Clock Switch), following the next negative edge of the newly selected PLL reference signal, the  
next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment.  
To calculate the overall uncertainty between the input CLKs and the outputs from multiple XRK799J93’s, the  
following procedure should be used. Assuming that the input CLKs to all XRK799J93’s are exactly in phase,  
the total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew.  
During a dynamic switch, the output phase between two devices may be increased for a short period of time. If  
the two input CLKs are 400ps out of phase, a dynamic switch of an XRK799J93 will result in an instantaneous  
phase change of 400ps to the PLL reference signal without a corresponding change in the output phase (due  
to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially  
7
XRK799J93  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
REV.1.0.1  
be 400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be  
considered when analyzing the overall skew budget of a system.  
HOT INSERTION AND WITHDRAWAL  
In PECL applications, a powered up driver will experience a low impedance path through an XRK799J93 input  
to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input  
pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input  
signals.  
ACQUIRING FREQUENCY LOCK  
1. While the XRK799J93 is receiving a valid CLK signal, assert Man_Override HIGH.  
2. The PLL will phase and frequency lock within the specified lock time.  
3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags.  
4. De–assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode.  
8
XRK799J93  
REV. 1.0.1  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
PACKAGE DIMENSIONS  
32 LEAD THIN QUAD FLAT PACK  
(7 x 7 x 1.4 mm TQFP)  
rev. 2.00  
D
D1  
24  
17  
16  
25  
32  
D1  
D
9
1
8
B
e
A2  
C
A
α
Seating Plane  
A1  
L
Note: The control dimension is the millimeter column  
INCHES MILLIMETERS  
MAX  
SYMBOL  
MIN  
0.055  
0.002  
MIN  
1.40  
0.05  
MAX  
1.60  
A
0.063  
0.006  
A
0.15  
1
A
0.053  
0.012  
0.004  
0.346  
0.272  
0.057  
0.018  
0.008  
0.362  
0.280  
1.35  
0.30  
0.09  
8.80  
6.90  
1.45  
0.45  
0.20  
9.20  
7.10  
2
B
C
D
D
1
e
L
α
0.0315 BSC  
0.80 BSC  
0.018  
0.030  
0.45  
0.75  
0°  
7°  
0°  
7°  
9
XRK799J93  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
REV.1.0.1  
REVISION HISTORY  
REVISION #  
1.0.0  
DATE  
DESCRIPTION  
June 14, 2005  
Initial release.  
1.0.1  
December 15, 2006 Edit block diagram and update pull-up resistors.  
NOTICE  
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to  
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any  
circuits described herein, conveys no license under any patent or other right, and makes no representation that  
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration  
purposes and may vary depending upon a user’s specific application. While the information in this publication  
has been carefully checked; no responsibility, however, is assumed for inaccuracies.  
EXAR Corporation does not recommend the use of any of its products in life support applications where the  
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or  
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless  
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has  
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately  
protected under the circumstances.  
Copyright 2006 EXAR Corporation  
Datasheet December 2006.  
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.  
10  

相关型号:

XRL567MD

Analog Phase-Locked Loop
ETC

XRLP-10T03X

ISOLATED DC/DC CONVERTERS
BEL

XRM-24

2 and 4 Zone Conventional Fire Alarm Control Panels
HONEYWELL

XRM-24

Four-Zone Fire Alarm Control Panel
GAMEWELL-FCI

XRM42L432PZT

RM42L432 16/32-Bit RISC Flash Microcontroller
TI

XRM46L852PGET

16/32-Bit RISC Flash Microcontroller
TI

XRM46L852ZWTT

16/32-Bit RISC Flash Microcontroller
TI

XRM48L950PGET

RM48Lx50 16/32-Bit RISC Flash Microcontroller
TI

XRM48L950ZWTT

RM48Lx50 16/32-Bit RISC Flash Microcontroller
TI

XRM48L952PGET

RM48L952 16/32-Bit RISC Flash Microcontroller
TI

XRM48L952ZWTT

RM48L952 16/32-Bit RISC Flash Microcontroller
TI

XRN740

Stable Extended Capability Chip Series
CALMIRCO