XRK79993IQ [EXAR]

PLL Based Clock Driver, 79993 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32;
XRK79993IQ
型号: XRK79993IQ
厂家: EXAR CORPORATION    EXAR CORPORATION
描述:

PLL Based Clock Driver, 79993 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32

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xr  
PRELIMINARY  
XRK79993  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
SEPTEMBER 2004  
REV. P1.0.0  
device will switch to the good secondary clock and  
phase/frequency alignment will occur with minimal  
output phase disturbance. The typical phase bump  
caused by a failed clock is eliminated.  
GENERAL DESCRIPTION  
The XRK79993 is a PLL clock driver designed  
specifically for redundant clock tree designs. The  
device receives two differential LVPECL clock signals  
from which it generates 5 new differential LVPECL  
clock outputs. Two of the output pairs regenerate the  
input signals frequency and phase while the other  
three pairs generate 2x, phase aligned clock outputs.  
External PLL feedback is used to also provide zero  
delay buffer performance.  
FEATURES  
Fully Integrated PLL  
Intelligent Dynamic Clock Switch  
LVPECL Clock Outputs  
LVCMOS Control I/O  
3.3V Operation  
The XRK79993 Intelligent Dynamic Clock Switch  
circuit continuously monitors both input CLK signals.  
Upon detection of a failure (CLK stuck HIGH or LOW  
for at least 1 period), the INP_BAD for that CLK will  
be latched (H). If that CLK is the primary clock, the  
32-Lead LQFP Packaging  
FIGURE 1. BLOCK DIAGRAM OF THE XRK79993  
CLK_Selected  
Dynamic  
Switch  
Logic  
INP1Bad  
INP0Bad  
Man_Override  
Alarm_Reset  
Sel_CLK  
PLL_En  
Qb0  
Qb0  
Qb1  
Qb1  
OR  
CLK0  
CLK0  
CLK1  
CLK1  
Qb2  
Qb2  
÷4  
÷8  
PLL  
400-800MHz  
Qa0  
Qa0  
Ext_FB  
Ext_FB  
Qa1  
Qa1  
MR  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  
XRK79993  
REV. P1.0.0  
PRELIMINARY  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
PRODUCT ORDERING INFORMATION  
PRODUCT NUMBER  
PACKAGE TYPE  
OPERATING TEMPERATURE RANGE  
XRK79993IQ  
32-Lead LQFP  
-40°C to +85°C  
FIGURE 2. PIN OUT OF THE XRK79993  
Qa1  
25  
VCC  
16  
Qa1  
26  
Inp0bad  
15  
Qa0  
27  
Inp1bad  
14  
Qa0  
28  
CK_Selected  
13  
XRK79993  
VCC  
29  
GND  
12  
VCC_PLL  
30  
Ext_FB  
11  
Man_Override  
31  
Ext_FB  
10  
PLL_En  
32  
GND  
9
2
PRELIMINARY  
XRK79993  
REV. P1.0.0  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
PIN DESCRIPTIONS  
PIN NAME  
TYPE  
DESCRIPTION  
CLK0, CLK0  
CLK1, CLK1  
LVPECL Input  
LVPECL Input  
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)  
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)  
Ext_FB, Ext_FB  
Qa0:1, Qa0:1  
Qb0:2, Qb0:2  
Inp0bad  
LVPECL Input  
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)  
LVPECL Output Differential 1x output pairs  
LVPECL Output Differential 2x output pairs  
LVCMOS Output Indicates detection of a bad input reference clock 0 with respect to the feed-  
back signal. The output is active HIGH and will remain HIGH until the alarm  
reset is asserted.  
Inp1bad  
LVCMOS Output Indicates detection of a bad input reference clock 1 with respect to the feed-  
back signal. The output is active HIGH and will remain HIGH until the alarm  
reset is asserted.  
Clk_Selected  
LVCMOS Output 0 - if clock 0 is selected  
1 - if clock 1 is selected  
Alarm_Reset  
Sel_Clk  
LVCMOS Input  
0 - will reset the input bad flags and align Clk_Selected with Sel_Clk. The input  
is one-shotted (50Kpullup).  
LVCMOS Input  
0 - selects CLK0  
1 - selects CLK1 (50kpulldown)  
Manual_Override  
PLL_En  
LVCMOS Input  
LVCMOS Input  
1 - disables internal clock switch circuitry (50Kpulldown).  
0 - bypasses selected input reference around the phase-locked loop (50KΩ  
pullup).  
MR  
LVCMOS Input  
0 - resets the internal dividers forcing Q outputs LOW. Asynchronous to the  
clock (50Kpullup).  
VCCA  
VCC  
Power Supply  
Power Supply  
Power Supply  
Power Supply  
PLL power supply  
Digital power supply  
PLL Ground  
GNDA  
GND  
Digital Ground  
3
XRK79993  
REV. P1.0.0  
PRELIMINARY  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
a
ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
CHARACTERISTICS  
MIN  
MAX  
UNIT  
CONDITION  
V
Supply Voltage  
-0.3  
3.6  
V
CC  
V
DC Input Voltage  
DC Output Voltage  
DC Input Current  
DC Output Current  
-0.3  
-0.3  
V
V
+0.3  
V
V
IN  
CC  
CC  
V
+0.3  
OUT  
I
+20  
mA  
mA  
°C  
IN  
I
+50  
125  
OUT  
T
Storage Temperature  
-65  
S
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur.  
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional  
operation at absolute-maximum-rated conditions is not implied.  
GENERAL SPECIFICATIONS  
SYMBOL  
CHARACTERISTICS  
MIN  
TYP  
MAX  
UNIT  
CONDITION  
V
Output termination voltage  
V
-2  
V
TT  
CC  
MM  
HBM  
CDM  
LU  
ESD Protection (Machine model)  
ESD Protection (Human body model)  
ESD Protection (Charged device model)  
Latch-up immunity  
TBD  
TBD  
TBD  
200  
V
V
V
mA  
pF  
C
Input Capacitance  
4.0  
Inputs  
IN  
θ
Thermal resistance junction to ambient  
JESD 51-3, single layer test board  
JA  
83.1  
73.3  
68.9  
63.8  
57.4  
86.0  
75.4  
70.9  
65.3  
59.6  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Natural convection  
100 ft/min  
200 ft/min  
400 ft/min  
800 ft/min  
JESD 51-6, 2S2P multilayer test board  
Thermal resistance junction to case  
59.0  
54.4  
52.5  
50.4  
47.8  
60.6  
55.7  
53.8  
51.5  
48.8  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Natural convection  
100 ft/min  
200 ft/min  
400 ft/min  
800 ft/min  
θ
23.0  
26.3  
°C/W  
MIL-SPEC 883E  
Method 1012.1  
JC  
a
Operating junction temperature  
110  
°C  
(continuous operation) MTBF=9.1 years  
a. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should  
be selected according to the application life time requirements.  
4
PRELIMINARY  
XRK79993  
REV. P1.0.0  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
a
DC CHARACTERISTICS (V = 3.3 + 5%, T = -40°C TO +85°C)  
CC  
A
SYMBOL  
CHARACTERISTICS  
MIN  
TYP  
MAX  
UNIT  
CONDITION  
LVCMOS control inputs (OE, FSEL0, FSEL1, MR)  
V
Input voltage low  
Input voltage high  
0.8  
V
V
IL  
IH  
IN  
V
2.0  
b
I
+TBD  
µΑ  
V
=V or V =GND  
IN CC IN  
Input current  
c
LVPECL clock inputs (CLK, CLK)  
d
V
0.1  
1.0  
1.3  
V
V
Differential operation  
Differential operation  
PP  
AC differential input voltage  
e
V
V
-0.3  
CC  
CMR  
Differential cross point voltage  
Input high voltage  
V
TBD  
TBD  
TBD  
IH  
V
Input low voltage  
Input current  
TBD  
IL  
I
+TBD  
µΑ  
V
=TBD or V =TBD  
IN IN  
IN  
LVPECL clock outputs (QA0-4, QA0-4, QB0-4, QB0-4)  
V
Output high voltage  
Output low voltage  
TBD  
TBD  
V
V
-1.005  
-1.705  
TBD  
TBD  
V
V
Termination 50to V  
Termination 50to V  
OH  
CC  
CC  
TT  
TT  
V
OL  
I
Maximum power supply - VCC pins  
TBD  
TBD  
mA  
mA  
CC  
I
Maximum PLL power supply - VCC_PLL pin  
CCA  
a. AC characterisitics are design targets and pending characterization.  
b. Input have internal pullup/pulldown resistors which affect the input current.  
c. Clock inputs driven by LVPECL compatible signals.  
d. V is the minimum differential input voltage swing required to maintain AC characteristic.  
PP  
e. V  
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is  
CMR  
within the V  
(DC) range and the input swing lies within the V (DC) specification.  
CMR  
PP  
5
XRK79993  
REV. P1.0.0  
PRELIMINARY  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
AC CHARACTERISTICS (V = 3.3 + 5%, T = -40°C TO +85°C) (NOTE 5)  
CC  
A
SYMBOL  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
f
PLL VCO Lock Range  
400  
800  
MHz  
VCO  
t
25  
75  
%
pwi  
t
Propagation Delay (Note 1)  
CLKn to Q (Bypass)  
pd  
TBD  
TBD  
ns  
ps  
CLKn to Ext_FB (Locked (Note 2))  
V
Differential input voltage (peak-to-peak)  
Differential input crosspoint voltage  
Output Rise/Fall time  
0.3  
1.3  
V
V
PP  
V
V
-0.3  
CC  
CMR  
t /t  
TBD  
ps  
r
f
t
Output Skew  
Within bank  
All outputs  
skew  
35  
50  
ps  
ps  
Maximum phase error deviation  
TBD (Note 3)  
TBD (Note 4)  
pe  
Rate of change of periods  
75MHz output (Note 1, 3)  
150MHz output (Note 1, 3)  
75MHz output (Note 1, 4)  
150MHz output (Note 1, 4)  
per/cycle  
20  
10  
50  
25  
ps/cycle  
200  
100  
400  
200  
t
Output duty cycle  
45  
55  
20  
10  
%
ps  
ms  
pw  
t
Cycle-to-cyle jitter, Standard deviation (RMS) (Note 1)  
Maximum PLL lock time  
jitter  
t
lock  
1. Guaranteed, not production tested.  
2. Static phase offset between the selected reference clock and the feedback signal.  
3. Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change  
per cycle is averaged over the clock switch excursion. (See Applications Information section for more detail)  
4. Specification holds for a clock switch between two signals no greater than ±π out of phase. Delta period change per  
cycle is averaged over the clock switch excursion.  
5. PECL output termination is 50 ohms to VCC – 2.0V.  
6
PRELIMINARY  
XRK79993  
REV. P1.0.0  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
APPLICATIONS INFORMATION  
The XRK79993 is a dual clock PLL with on–chip Intelligent Dynamic Clock Switch circuitry.  
DEFINITIONS  
primary clock: The input CLK selected by Sel_Clk.  
secondary clock: The input CLK NOT selected by Sel_Clk.  
PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or the Intelligent Dynamic  
Clock Switch. The Intelligent Dynamic Clock Switch can override Sel_Clk.  
STATUS FUNCTIONS  
Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H)  
indicates CLK1 is selected as the PLL reference signal.  
Inp0bad, Inp1bad: Inp0bad is latched (H) when CLK0 is stuck (H) or (L) for at least one Ext_FB period, or if one  
of the inputs CLK0 or CLK0_b is floating. Inp1bad is latched (H) when CLK1 is stuck (H) or (L) for at least one  
Ext_FB period, or if one of the inputs CLK1 or CLK1_b is floating. Both Inp0bad and Inp1bad are latched (H)  
when Ext_FB is stuck (H) or (L) for at least one Qa period, or if one of the inputs Ext_FB or Ext _FB _b is  
floating. Cleared (L) on assertion of Alarm_Reset_b. The status functions Inp0bad and Inp1bad are active for  
Man_Override (H) or (L).  
CONTROL FUNCTIONS  
Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock.  
Alarm_Reset: Asserted by a negative edge. Generates a one–shot reset pulse that clears INPUT_BAD latches  
and Clk_Selected latch.  
PLL_En: While (L), the PLL reference signal is substituted for the VCO output.  
MR: While (L), internal dividers are held in reset which holds all Q outputs LOW.  
MAN OVERRIDE (H)  
(IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be  
the CLK selected by Sel_Clk. If Ext_FB misses at least one pulse, Qa and Qb outputs will drop to a minimum  
TBD frequency for 1-uS, or until Ext_FB shows any activity, whichever is longer. This prevents the Qa and Qb  
frequencies from rising due the PLL incorrectly interpreting an intermittent Ext_FB as a VCO running too slow.  
MAN OVERRIDE (L)  
Intelligent Dynamic Clock Switch is enabled, PLL functions enhanced. The first CLK to fail will latch it’s  
INP_BAD (H) status flag and select the other input as the Clk_Selected for the PLL reference clock. Once  
latched, the Clk_Selected and INP_BAD remain latched until assertion of Alarm_Reset which clears all latches  
(INP_BADs are cleared and Clk_Selected = Sel_Clk).  
If both Inp0bad and Inp1bad are (H), either due to both CLK0 and CLK1 having missed at least 1 pulse each or  
due the Ext_FB having missed at least 1 pulse, then Qa and Qb outputs will drop to a minimum TBD frequency  
until such time as Alarm_Reset_b is asserted.  
NOTE: If both CLKs are bad when Alarm_Reset is asserted, both INP_BADs will be latched (H) after one Ext_FB period  
and Clk_Selected will be latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched  
(H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by the  
Intelligent Dynamic Clock Switch), following the next negative edge of the newly selected PLL reference signal, the  
next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment.  
To calculate the overall uncertainty between the input CLKs and the outputs from multiple XRK79993’s, the  
following procedure should be used. Assuming that the input CLKs to all XRK79993’s are exactly in phase, the  
total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew.  
During a dynamic switch, the output phase between two devices may be increased for a short period of time. If  
the two input CLKs are 400ps out of phase, a dynamic switch of an XRK79993 will result in an instantaneous  
phase change of 400ps to the PLL reference signal without a corresponding change in the output phase (due  
to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially be  
7
XRK79993  
REV. P1.0.0  
PRELIMINARY  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be  
considered when analyzing the overall skew budget of a system.  
HOT INSERTION AND WITHDRAWAL  
In PECL applications, a powered up driver will experience a low impedance path through an XRK79993 input  
to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input  
pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input  
signals.  
ACQUIRING FREQUENCY LOCK  
1. While the XRK79993 is receiving a valid CLK signal, assert Man_Override HIGH.  
2. The PLL will phase and frequency lock within the specified lock time.  
3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags.  
4. De–assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode.  
8
PRELIMINARY  
XRK79993  
REV. P1.0.0  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
PACKAGE DIMENSIONS  
32 LEAD THIN QUAD FLAT PACK  
(7 x 7 x 1.4 mm TQFP)  
rev. 2.00  
D
D1  
24  
17  
16  
25  
32  
D1  
D
9
1
8
B
e
A2  
C
A
α
Seating Plane  
A1  
L
Note: The control dimension is the millimeter column  
INCHES MILLIMETERS  
MAX  
SYMBOL  
MIN  
MIN  
MAX  
1.60  
0.15  
A
0.055  
0.002  
0.063  
0.006  
1.40  
0.05  
A
1
A
0.053  
0.012  
0.004  
0.346  
0.272  
0.057  
0.018  
0.008  
0.362  
0.280  
1.35  
0.30  
0.09  
8.80  
6.90  
1.45  
0.45  
0.20  
9.20  
7.10  
2
B
C
D
D
1
e
L
α
0.0315 BSC  
0.80 BSC  
0.018  
0.030  
0.45  
0.75  
0°  
7°  
0°  
7°  
9
XRK79993  
REV. P1.0.0  
PRELIMINARY  
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER  
REVISION HISTORY  
REVISION #  
DATE  
DESCRIPTION  
P1.0.0  
September 2004 Initial Preliminary release.  
NOTICE  
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to  
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any  
circuits described herein, conveys no license under any patent or other right, and makes no representation that  
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration  
purposes and may vary depending upon a user’s specific application. While the information in this publication  
has been carefully checked; no responsibility, however, is assumed for inaccuracies.  
EXAR Corporation does not recommend the use of any of its products in life support applications where the  
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to  
significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless  
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has  
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately  
protected under the circumstances.  
Copyright 2004 EXAR Corporation  
Datasheet September 2004.  
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.  
10  

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