EM564161BC-55E [ETRON]
256K x 16 Low Power SRAM; 256K ×16低功耗SRAM型号: | EM564161BC-55E |
厂家: | ETRON TECHNOLOGY, INC. |
描述: | 256K x 16 Low Power SRAM |
文件: | 总14页 (文件大小:254K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Et r on Tech
EM564161
256K x 16 Low Power SRAM
Rev 3.1
04/2004
Features
Pin Configuration
48-Ball BGA (CSP), Top View
Single power supply voltage of 2.3V to 3.6V
Power down features using CE1# and CE2
Low power dissipation
•
•
•
•
•
•
•
1
2
3
4
5
6
A
B
C
D
E
F
LB#
OE#
A0
A1
A2
CE2
DQ0
DQ2
VDD
GND
DQ6
DQ7
NC
Data retention supply voltage: 1.0V to 3.6V
Direct TTL compatibility for all input and output
Wide operating temperature range: -40°C to 85°C
Standby current @ VDD = 3.6 V
DQ8
DQ9
GND
VDD
DQ14
DQ15
NC
UB#
DQ10
DQ11
DQ12
DQ13
NC
A3
A5
A4
A6
CE1#
DQ1
DQ3
DQ4
DQ5
WE#
A11
IDDS2
A17
NC
A14
A12
A9
A7
Typical
1 µA
Maximum
10 µA
EM564161BC -55
A16
A15
A13
A10
EM564161BC/BA -70/85
1 µA
10 µA
EM564161BC –55E
5 µA
5 µA
80 µA
80 µA
EM564161BC/BA -70E/85E
G
H
A8
Ordering Information
Part Number
Speed IDDS2
Package
6x8 BGA
6x8 BGA
6x8 BGA
6x8 BGA
8x10 BGA
8x10 BGA
6x8 BGA
8x10 BGA
8x10 BGA
EM564161BC-55
55 ns
10 µA
80 µA
10 µA
80 µA
10 µA
80 µA
10 µA
10 µA
80 µA
Pin Description
EM564161BC-55E 55 ns
EM564161BC-70 70 ns
EM564161BC-70E 70 ns
Symbol
A0 - A17
DQ0 - DQ15
CE1#, CE2
OE#
Function
Address Inputs
Data Inputs / Outputs
Chip Enable Inputs
Output Enable
EM564161BA-70
EM564161BA-70E
EM564161BC-85
EM564161BA-85
EM564161BA-85E
70 ns
70 ns
85 ns
85 ns
85 ns
WE#
LB#, UB#
GND
Read / Write Control Input
Data Byte Control Inputs
Ground
V
DD
Power Supply
NC
No Connection
Overview
The EM564161 is a 4,194,304-bit SRAM organized as 262,144 words by 16 bits. It is designed with advanced
CMOS technology. This Device operates from a single 2.3V to 3.6V power supply. Advanced circuit
technology provides both high speed and low power. It is automatically placed in low-power mode when chip
enable (CE1#) is asserted high or (CE2) is asserted low. There are three control inputs. CE1# and CE2 are
used to select the device and for data retention control, and output enable (OE#) provides fast memory access.
Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various
microprocessor system applications where high speed, low power and battery backup are required. And, with a
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
Et r on Tech
EM564161
guaranteed operating range from -40°C to 85°C, the EM564161 can be used in environments exhibiting
extreme temperature conditions.
Apr. 2004
2
Rev 3.1
Et r on Tech
EM564161
Block Diagram
A0
VDD
GND
MEMORY
CELL ARRAY
2,048X128X16
(4,194,304)
A17
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SENSE AMP
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
COLUMN ADDRESS
DECODER
WE#
UB#
LB#
OE#
CE1#
CE2
POWER DOWN
CIRCUIT
Apr. 2004
3
Rev 3.1
Et r on Tech
EM564161
Operating Mode
Mode
CE1# CE2 OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15
L
H
L
L
L
D
D
OUT
OUT
OUT
Read
L
L
H
H
L
H
L
High-Z
D
H
L
D
High-Z
OUT
L
D
D
IN
IN
Write
X
H
L
L
High-Z
D
IN
H
X
H
X
X
D
High-Z
IN
L
L
H
H
X
L
H
X
X
X
H
X
X
X
X
H
X
X
Output Deselect
Standby
High-Z
High-Z
High-Z
H
X
High-Z
Note: X = don't care. H=logic high. L=logic low.
Absolute Maximum Ratings
Supply voltage, V
Input voltages, V
-0.3 to +4.6V
-0.3 to +4.6V
DD
IN
-0.5 to V
DD
Input and output voltages, V
Operating temperature, T
I/O
+0.5V
-40 to +85°C
-55 to +150°C
240°C
OPR
Storage temperature, T
STRG
Soldering Temperature (10s), T
SOLDER
Power dissipation, P
D
0.6 W
DC Recommended Operating Conditions (Ta=-40 C to 85 C)
°
°
Symbol
Parameter
Power Supply Voltage
Input High Voltage
Min
2.3
Typ
Max
Unit
V
V
3.6
−
−
−
−
DD
V
2.2
-0.3(2)
V
DD
+ 0.3(1)
V
IH
V
Input Low Voltage
0.6
V
IL
V
Data Retention Supply Voltage
1.0
3.6
V
DR
Note:
(1) Overshoot : VDD +2.0V in case of pulse width ≤ 20ns
(2) Undershoot : -2.0V in case of pulse width ≤ 20ns
Apr. 2004
4
Rev 3.1
Et r on Tech
EM564161
DC Characteristics (Ta = -40 C to 85 C, V
= 2.3V to 3.6V)
°
°
DD
Parameter
Symbol
Test Conditions
Min
Typ* Max Unit
Input low current
I
I
I
I
= 0V to V
- 1
-
1
0.4
−
−
−
µA
V
IL
IN
DD
Output low
voltage
V
= 2.1 mA
= -1.0 mA
OL
OL
OH
Output high
voltage
V
-
DD
V
V
−
OH
0.15
20
−
−
V
V
= 3.6 V
= 2.7 V
35
25
DD
Cycle time
= min
13
10
DD
CE1# = V and
IL
55
−
−
−
−
V
V
V
V
= 2.3 V
= 3.6 V
= 2.7 V
= 2.3 V
20
25
15
12
I
DD
DD
DD
DD
DD1
CE2 = V and
IH
Operating current
mA
15
10
7
I
= 0mA
OUT
70/85
Other Input = V / V
IH IL
−
−
−
I
5
Cycle time = 1µs
DD2
I
CE1# = V or CE2 = V
IH
0.5 mA
10
−
DDS1
IL
1
V
V
V
= 3.6 V
−
−
−
DD
DD
DD
CE1# = V
– 0.2V or
I
DD
CE2 = 0.2V
**
DDS2
0.8
0.5
Standby current
55/70/85
µA
= 2.7 V
= 2.3 V
5
3
(Note)
55E/70E/85
E
V
= 3.6 V
5
80
−
DD
Notes:
* Typical value are measured at Ta = 25°C.
** In standby mode with CE1# ≥ V
CE2 ≥ VDD - 0.2V or CE2 ≤ 0.2V.
- 0.2V, these limits are assured for the condition
DD
Capacitance (Ta = 25 C; f = 1 MHz)
°
Parameter
Symbol
Min
−
Typ
−
Max
10
Unit
pF
Test Conditions
Input capacitance
Output capacitance
C
V
= GND
= GND
IN
IN
C
10
pF
V
−
−
OUT
OUT
Notes:
This parameter is periodically sampled and is not 100% tested.
Apr. 2004
5
Rev 3.1
Et r on Tech
EM564161
AC Characteristics and Operating Conditions (Ta = -40 C to 85 C, V
= 2.3V to 3.6V)
°
°
DD
Read Cycle
EM564161
-70
-55
-85
Symbol
Parameter
Unit
Min Max Min Max Min Max
t
Read cycle time
55
−
70
−
85
−
−
55
55
55
25
55
−
−
70
70
70
35
70
−
−
RC
t
Address access time
85
85
85
45
85
−
AA
t
Chip Enable (CE1#) Access Time
Chip Enable (CE2) Access Time
Output enable access time
−
−
−
CO1
t
−
−
−
CO2
t
−
−
−
OE
t
Data Byte Control Access Time
Chip Enable Low to Output in Low-Z
Output enable Low to Output in Low-Z
Data Byte Control Low to Output in Low-Z
Chip Enable High to Output in High-Z
Output Enable High to Output in High-Z
Data Byte Control High to Output in High-Z
Output Data Hold Time
−
−
−
BA
t
10
3
10
3
10
3
ns
LZ
t
−
−
−
OLZ
t
5
5
5
−
−
−
BLZ
t
20
20
20
−
25
25
25
−
35
35
35
−
−
−
−
HZ
t
−
−
−
OHZ
t
−
−
−
BHZ
t
10
10
10
OH
Write Cycle
EM564161
-70
Unit
Symbol
Parameter
-55
-85
Min Max Min Max Min Max
t
Write cycle time
55
45
45
45
0
70
55
60
60
0
85
55
70
70
0
−
−
−
−
−
−
WC
t
Write pulse width
WP
t
Chip Enable to end of write
Data Byte Control to end of Write
Address setup time
−
−
−
CW
t
−
−
−
BW
t
−
−
−
AS
ns
t
Write Recovery time
WE# Low to Output in High-Z
WE# High to Output in Low-Z
Data Setup Time
0
0
0
−
−
−
WR
t
25
−
30
−
35
−
−
5
−
5
−
5
WHZ
t
OW
t
25
0
30
0
35
0
−
−
−
DS
t
Data Hold Time
−
−
−
DH
AC Test Condition
Output load : 50pF + one TTL gate
Input pulse level : 0.4V, 2.4V
Timing measurements : 0.5 x VDD
tR, tF : 5ns
•
•
•
•
Apr. 2004
6
Rev 3.1
Et r on Tech
EM564161
Read Cycle
(See Note 1)
t
RC
Address
CE1#
CE2
t
t
OH
AA
t
CO1
t
CO2
t
HZ
t
OE
OE#
t
OHZ
t
BA
UB# LB#
,
t
BLZ
t
BHZ
t
OLZ
t
LZ
D
OUT
VALID DATA OUT
Apr. 2004
7
Rev 3.1
Et r on Tech
EM564161
Write Cycle1
(WE# Controlled)(See Note 4)
t
WC
Address
t
t
t
AS
WP
WR
WE#
CE1#
CE2
t
CW
t
t
CW
BW
UB# LB#
,
t
t
WHZ
OW
D
(See Note2)
(See Note3)
OUT
t
t
DS
DH
D
(See Note 5)
VALID DATA IN
(See Note 5)
IN
Apr. 2004
8
Rev 3.1
Et r on Tech
EM564161
Write Cycle 2
(CE1# Controlled)(See Note 4)
t
WC
Address
t
t
t
AS
WP
WR
WE#
CE1#
CE2
t
CW
t
t
CW
BW
UB# LB#
,
t
t
WHZ
BLZ
D
OUT
t
LZ
t
t
DS
DH
D
(See Note 5)
VALID DATA IN
IN
Apr. 2004
9
Rev 3.1
Et r on Tech
EM564161
Write Cycle 3
(CE2 Controlled)(See Note 4)
t
WC
Address
t
t
t
AS
WP
WR
WE#
CE1#
CE2
t
CW
t
CW
t
WHZ
D
OUT
t
LZ
t
t
DS
DH
D
(See Note 5)
VALID DATA IN
IN
Apr. 2004
10
Rev 3.1
Et r on Tech
EM564161
Write Cycle4
(UB#, LB# Controlled)(See Note 4)
t
WC
Address
t
t
t
AS
WP
WR
WE#
CE1#
CE2
t
CW
t
t
CW
BW
UB# LB#
,
t
t
WHZ
BLZ
D
OUT
t
LZ
t
t
DS
DH
D
(See Note 5)
VALID DATA IN
IN
Note:
1. WE# remains HIGH for the read cycle.
2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high
impedance.
3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain
at high impedance.
4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
Apr. 2004
11
Rev 3.1
Et r on Tech
EM564161
Data Retention Characteristics (Ta = -40°C to 85°C)
Symbol
Parameter
Min
Typ Max Unit
CE1# ≥ VDD - 0.2V, CE2 ≤ 0.2V,
VIN ≥ VDD - 0.2V or VIN ≤ 0.2V
Data Retention Supply
Voltage
V
1.0
0
3.6
V
−
DR
t
Chip Deselect to Data Retention Mode Time
Recovery Time
ns
ns
−
−
−
−
SDR
t
t
RDR
RC
CE1# Controlled Data Retention Mode
t
RDR
t
Data Retention Mode
SDR
V
DD
2.7V
2.2V
V
DR
Note 1
CE1#
GND
CE2 Controlled Data Retention Mode
Data Retention Mode
V
DD
2.7V
t
t
RDR
SDR
CE2
V
DR
Note 2
0.4V
GND
Note:
1. CE1# ≥ VDD – 0.2V or UB# = LB# ≥ VDD – 0.2V
2. CE2 ≤ 0.2V
Apr. 2004
12
Rev 3.1
Et r on Tech
EM564161
Package Diagrams
48-Ball (6mm x 8mm) BGA
Units in mm
TOP VIEW
BOTTOM VIEW
PIN 1 CORNER
0.10 S
C
C
0.25 S
0.30
A
B
0.05(48X)
PIN 1 CORNER
6
5
4
3
2
1
1
2
3
4
5
6
- B -
0.75
3.75
- A -
0.20(4X)
0.10
- C -
SEATING PLANE
Apr. 2004
13
Rev 3.1
Et r on Tech
EM564161
Package Diagrams
48-Ball (8mm x 10mm) BGA
Units in mm
TOP VIEW
BOTTOM VIEW
PIN 1 CORNER
0.10 S
C
C
0.25 S
0.30
A
B
PIN 1 CORNER
0.05(48X)
1
2
3
4
5
6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
- B -
0.75
3.75
0.10
- A -
8.0
0.20(4X)
0.10
- C -
SEATING PLANE
Apr. 2004
14
Rev 3.1
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