EM565161BA-55 [ETRON]
512K x 16 Low Power SRAM; 512K ×16的低功耗SRAM
| 型号： | EM565161BA-55 |
| 厂家： | 
ETRON TECHNOLOGY, INC. |
| 描述： | 512K x 16 Low Power SRAM |
| 文件： | 总13页 (文件大小：792K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Et r on Tech
EM565161
512K x 16 Low Power SRAM
Preliminary, Rev 0.9 01/2002
Features
Pin Assignment
48-Ball BGA (CSP), Top View
Single Power Supply Voltage, 2.3 ~ 3.6 V
•
•
Power Down Features Using CE1#, CE2, LB# and
UB#
1
2
3
4
5
6
A
B
C
D
E
F
L B #
O E #
A 0
A 1
A 2
C E 2
Low Power Dissipation
•
•
•
•
•
Data retention Supply Voltage: 1.0V to 3.6V
Direct TTL Compatibility for All Input and Output
Wide Operating Temperature Range: -40°C to 85°C
Standby current (maximum) @ VDD = 3.6 V
D Q 8
D Q 9
G N D
V D D
D Q 14
D Q 15
A 1 8
U B #
D Q 10
D Q 11
D Q 12
D Q 13
N C
A 3
A 5
A 4
A 6
C E 1 #
D Q 1
D Q 3
D Q 4
D Q 5
W E #
A 1 1
D Q 0
D Q 2
V D D
G N D
D Q 6
D Q 7
N C
I
DDS2
A 1 7
A 7
Part Number
Typical
2 µA
Maximum
EM565161BA/BJ-55
35 µA
25 µA
80 µA
A 1 6
A 1 5
A 1 3
A 1 0
G N D
A 1 4
A 1 2
A 9
EM565161BA/BJ-70
2 µA
EM565161BA/BJ-55E/70E
14 µA
Ordering Information
G
H
Part Number
Speed IDDS2
Package
6x9 BGA
8x10 BGA
8x10 BGA
6x9 BGA
8x10 BGA
8x10 BGA
EM565161BJ-70
EM565161BA-70
EM565161BA-70E
EM565161BJ-55
EM565161BA-55
EM565161BA-55E
70 ns
70 ns
70 ns
55 ns
55 ns
55 ns
25 µA
25 µA
80 µA
35 µA
35 µA
80 µA
A 8
Pin Names
Symbol
A0 – A18
DQ0-DQ15
CE1#,CE2
OE#
Function
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable
WE#
LB#,UB#
GND
Read/Write Control Input
Data Byte Control Inputs
Ground
V
DD
Power Supply
NC
No Connection
Overview
The EM565161 is an 8M-bit SRAM organized as 512K words by 16 bits. It is designed with advanced CMOS
technology. This Device operates from a single power supply. Advanced circuit technology provides both high
speed and low power. It is automatically placed in low-power mode when CE1# or both UB# and LB# are
asserted high or CE2 is asserted low. There are three control inputs. CE1# and CE2 are used to select the
device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control
pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor
system applications where high speed, low power and battery backup are required. And, with a guaranteed
operating range from –40°C to 85°C, the EM565161 can be used in environments exhibiting extreme
temperature conditions.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
Et r on Tech
EM565161
Block Diagram
A 0
V D D
G N D
M EM O R Y
CELL A RR AY
512kx16
A 18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SEN SE AMP
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
COLUMN ADDRESS
DECODER
W E #
U B #
LB #
O E #
CE 1#
C E 2
POW ER DOW N
CIRCUIT
Preliminary
2
Rev 0.9
Jan 2002
Et r on Tech
EM565161
Operating Mode
Mode
CE1# CE2 OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15
Power
L
H
L
L
L
D
D
D
I
OUT
OUT
OUT
DDO
DDO
DDO
DDO
DDO
DDO
DDO
DDO
Read
L
L
H
H
L
H
L
High-Z
I
I
I
I
I
I
I
H
L
D
High-Z
OUT
L
D
D
IN
IN
Write
Output Disabled
Standby
X
H
L
L
High-Z
D
IN
H
X
H
X
X
H
D
High-Z
High-Z
High-Z
IN
L
L
H
H
X
L
H
X
X
X
X
H
X
X
X
X
X
H
X
X
H
High-Z
High-Z
H
X
X
High-Z
High-Z
I
DDS
X
Note:X=don’t care. H=logic high. L=logic low.
Absolute Maximum Ratings
Supply voltage, V
DD
-0.3 to +4.6V
-0.3 to +4.6V
Input voltages, V
IN
Input and output voltages, V
I/O
-0.5 to V +0.5V
DD
Operating temperature, T
OPR
-40 to +85°C
-55 to +150°C
240°C
Storage temperature, T
STRG
Soldering Temperature (10s), T
SOLDER
Power dissipation, P
D
1 W
Preliminary
3
Rev 0.9
Jan 2002
Et r on Tech
EM565161
DC Recommended Operating Conditions (Ta=-40°C to 85°C)
Symbol
Parameter
Power Supply Voltage
Input High Voltage
Min
2.3
2.2
Typ
3.0
−
Max
Unit
V
3.6
V
DD
(1)
V
V
+ 0.3
IH
DD
(2)
V
Input Low Voltage
-0.3
0.6
3.6
−
IL
V
Data Retention Supply Voltage
1.0
−
DR
Note:
(1) Overshoot : VDD +2.0V in case of pulse width ≤ 20ns
(2) Undershoot : -2.0V in case of pulse width ≤ 20ns
DC Characteristics (Ta = -40°C to 85°C, V
= 2.3V to 3.6V)
DD
Parameter
Symbol
Test Conditions
Min Typ* Max Unit
Input low current
I
I
I
I
= 0V to V
DD
- 1
1
0.4
−
−
−
−
µA
V
IL
IN
Output low
voltage
V
= 2.1 mA
= -1.0 mA
−
OL
OL
OH
Output high
voltage
V
DD
0.15
–
V
V
OH
CE1# = V and
IL
−
Operating current
Standby current
I
Cycle time = min
12
35
5
DD1
CE2 = V and
IH
mA
I
= 0mA
OUT
−
−
−
−
−
2
I
Cycle time = 1µs
DD2
Other Input = V / V
IH IL
I
CE1# = V or CE2 = V
IH
0.3 mA
DDS1
IL
-55
-70
35
µA
25
CE1# = V
DD
– 0.2V or
I
UB# and LB# = V -0.2V or
DD
DDS2
CE2 = 0.2V
2
−
−
-55E/70E
14
80
Notes:
* Typical value are measured at Ta = 25°C.
Capacitance (Ta = 25°C; f = 1 MHz)
Parameter
Symbol
Min
−
Max
8
Unit
pF
Test Conditions
Input capacitance
Input/Output capacitance
C
V
= GND
= GND
IN
IN
IO
C
10
pF
V
−
IO
Notes: This parameter is periodically sampled and is not 100% tested.
Preliminary
4
Rev 0.9
Jan 2002
Et r on Tech
EM565161
AC Characteristics and Operating Conditions (Ta = -40°C to 85°C, V
= 2.3V to 3.6V)
DD
Read Cycle
EM565161
-55 -70
Min Max Min Max
Symbol
Parameter
Unit
t
Read cycle time
55
−
70
−
−
−
RC
t
Address access time
55
55
55
25
55
−
70
70
70
35
70
−
AA
t
Chip Enable (CE1#) Access Time
Chip Enable (CE2) Access Time
Output enable access time
−
−
CO1
t
−
−
CO2
t
−
−
OE
t
Data Byte Control Access Time
−
−
BA
t
Chip Enable Low to Output in Low-Z
Output enable Low to Output in Low-Z
Data Byte Control Low to Output in Low-Z
Chip Enable High to Output in High-Z
Output Enable High to Output in High-Z
Data Byte Control High to Output in High-Z
Output Data Hold Time
10
5
10
5
ns
LZ
t
−
−
OLZ
t
10
−
10
−
−
−
BLZ
t
20
20
20
−
25
25
25
−
HZ
t
−
−
OHZ
t
−
−
BHZ
t
10
10
OH
Write Cycle
EM565161
-55 -70
Min Max Min Max
Symbol
Parameter
Unit
t
Write cycle time
55
45
45
45
0
70
55
60
60
0
−
−
−
−
WC
t
Write pulse width
WP
t
Chip Enable to end of write
Data Byte Control to end of Write
Address setup time
−
−
CW
t
−
−
BW
t
−
−
AS
ns
t
Write Recovery time
0
0
−
−
WR
t
WE# Low to Output in High-Z
WE# High to Output in Low-Z
Data Setup Time
20
−
20
−
−
−
WHZ
t
5
5
OW
t
25
0
30
0
−
−
DS
t
Data Hold Time
−
−
DH
AC Test Condition
Output load : 60pF + one TTL gate
Input pulse level : 0.4V, 2.4V
•
•
•
•
Timing measurements : 0.5 x V
DD
tR, tF : 5ns
Preliminary
5
Rev 0.9
Jan 2002
Et r on Tech
EM565161
Read Cycle
(See Note 1)
t
R C
A d d r e s s
C E 1 #
C E 2
t
t
O H
A A
t
C O 1
t
C O 2
t
H Z
t
O E
O E #
t
O H Z
t
B A
U B #
L B #
,
t
B L Z
t
B H Z
t
O L Z
t
L Z
D
O U T
V A L ID D A T A O U T
Preliminary
6
Rev 0.9
Jan 2002
Et r on Tech
EM565161
Write Cycle1
(WE# Controlled)(See Note 4)
t
W C
A d d r e s s
t
t
t
A S
W P
W R
W E #
C E 1 #
C E 2
t
C W
t
t
C W
B W
U B #
L B #
,
t
t
W H Z
O W
D
(S e e N o te 2 )
(S e e N o te 3 )
O U T
t
t
D S
D H
D
(S e e N o t e 5 )
V A L ID D A T A IN
(S e e N o t e 5 )
IN
Preliminary
7
Rev 0.9
Jan 2002
Et r on Tech
EM565161
Write Cycle 2
(CE1# Controlled)(See Note 4)
t
W C
A d d r e s s
t
t
t
A S
W P
W R
W E #
C E 1 #
C E 2
t
C W
t
t
C W
B W
U B #
L B #
,
t
t
W H Z
B L Z
D
O U T
t
L Z
t
t
D S
D H
D
(S e e N o te 5 )
V A L I D D A T A IN
I N
Preliminary
8
Rev 0.9
Jan 2002
Et r on Tech
EM565161
Write Cycle 3
(CE2 Controlled)(See Note 4)
t
W C
A d d r e s s
t
t
t
A S
W P
W R
W E #
C E 1 #
C E 2
t
C W
t
C W
t
W H Z
D
O U T
t
L Z
t
t
D S
D H
D
(S e e N o te 5 )
V A L I D D A T A IN
I N
Preliminary
9
Rev 0.9
Jan 2002
Et r on Tech
EM565161
Write Cycle4
(UB#, LB# Controlled)(See Note 4)
t
W C
A d d r e s s
t
t
t
A S
W P
W R
W E #
C E 1 #
C E 2
t
C W
t
t
C W
B W
U B #
L B #
,
t
t
W H Z
B L Z
D
O U T
t
L Z
t
t
D S
D H
D
(S e e N o te 5 )
V A L I D D A T A IN
I N
Note:
1. WE# remains HIGH for the read cycle.
2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high
impedance.
3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at
high impedance.
4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
Preliminary
10
Rev 0.9
Jan 2002
Et r on Tech
EM565161
Data Retention Characteristics (Ta = -40°C to 85°C)
Symbol
Parameter
Min
Typ Max Unit
CE1# ≥ V – 0.2V
DD
or UB# = LB# ≥ V – 0.2V
DD
Data Retention Supply
Voltage
V
1.0
0
3.6
V
−
DR
or CE2 ≤ 0.2V,
VIN ≥ V – 0.2V or VIN ≤ 0.2V
DD
t
Chip Deselect to Data Retention Mode Time
Recovery Time
ns
ns
−
−
−
−
SDR
t
t
RDR
RC
CE1# or UB#/LB# Controlled Data Retention Mode
t
t
D a ta R e te n tio n M o d e
R D R
S D R
V
D D
2 .7 V
2 .2 V
V
D R
N o te
1
C E 1 # ,
U B # /L B #
G N D
CE2 Controlled Data Retention Mode
Data Retention Mode
V
DD
2.7V
t
t
RDR
SDR
CE 2
V
DR
Note 2
0.4V
G ND
Note:
1. CE1# ≥ V – 0.2V or UB# = LB# ≥ V – 0.2V
DD
DD
2. CE2 ≤ 0.2V
Preliminary
11
Rev 0.9
Jan 2002
Et r on Tech
EM565161
Package Diagrams
48-Ball (8mm x 10mm) BGA
Units in mm
TOP VIEW
BOTTOM VIEW
0.10 S
PIN 1 CORNER
C
0.25 S
0.30
C
A
B
PIN 1 CORNER
0.05(48X)
1
2
3
4
5
6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
10 .0 0.1
G
H
G
H
- B -
0.75
0.52
0.02
3.75
0.1
- A -
8.0
0.23
0.03
0.20(4X)
0.15
- C -
SEATING PLANE
0.02
0.36
0.05
1.20 MAX
Preliminary
12
Rev 0.9
Jan 2002
Et r on Tech
EM565161
Package Diagrams
48-Ball (6mm x 9mm) BGA
Units in mm
T O P V IE W
B O T T O M V IE W
PIN 1 CO RN ER
0.1 0
0.2 5
S
S
C
C
A
B
0.30 (4 8X)
PIN 1 CO RN ER
6
5
4
3
2
1
1
2
3
4
5
6
7 8 9 1 0 1 1 1 2
L
- B -
0.7 5
3.7 5
- A -
0.20 (4X )
0.1 0
- C -
S E A TIN G P LA N E
Preliminary
13
Rev 0.9
Jan 2002
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