EM564166BC-85E [ETRON]
256K x 16 Low Power SRAM; 256K ×16低功耗SRAM
| 型号： | EM564166BC-85E |
| 厂家： | 
ETRON TECHNOLOGY, INC. |
| 描述： | 256K x 16 Low Power SRAM |
| 文件： | 总11页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EtronTech
EM564166
256K x 16 Low Power SRAM
Preliminary, Rev 1.0 05/2001
Features
Pin Configuration
48-Ball BGA (CSP), Top View
Single power supply voltage of 2.3V to 3.6V
Power down features using CE#
Low power dissipation
·
·
·
·
·
·
·
1
2
3
4
5
6
A
B
C
D
E
F
LB#
OE#
A0
A1
A2
NC
Data retention supply voltage: 1.0V to 3.6V
Direct TTL compatibility for all input and output
Wide operating temperature range: -40°C to 85°C
Standby current @ VDD = 3.6 V
IDDS2
DQ8
DQ9
UB#
A3
A5
A4
A6
CE#
DQ1
DQ3
DQ4
DQ5
WE#
A11
DQ0
DQ2
VDD
GND
DQ6
DQ7
NC
DQ10
GND DQ11
A17
NC
A14
A12
A9
A7
Typical
1 mA
Maximum
10 mA
EM564166BC-70/85
VDD
DQ12
A16
A15
A13
A10
EM564166BC-70E/85E
5 mA
80 mA
DQ14 DQ13
G
H
DQ15
NC
NC
A8
Ordering Information
Part Number
Speed IDDS2
Package
6x8 BGA
6x8 BGA
6x8 BGA
6x8 BGA
EM564166BC-70
EM564166BC-85
70 ns
85 ns
10 mA
10 mA
80 mA
80 mA
Pin Description
Symbol
A0 - A17
DQ0 - DQ15
CE#
Function
Address Inputs
Data Inputs / Outputs
Chip Enable Inputs
Output Enable
EM564166BC-70E 70 ns
EM564166BC-85E 85 ns
OE#
WE#
LB#, UB#
GND
Read / Write Control Input
Data Byte Control Inputs
Ground
V
DD
Power Supply
NC
No Connection
Overview
The EM564166 is a 4,194,304-bit SRAM organized as 262,144 words by 16 bits. It is designed with advanced
CMOS technology. This Device operates from a single 2.3V to 3.6V power supply. Advanced circuit
technology provides both high speed and low power. It is automatically placed in low-power mode when chip
enable (CE#) is asserted high. There are two control inputs. CE# are used to select the device and for data
retention control, and output enable (OE#) provides fast memory access. Data byte control pin (LB#,UB#)
provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating range from -
40°C to 85°C, the EM564166 can be used in environments exhibiting extreme temperature conditions.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
EM564166
Block Diagram
A0
VDD
GND
MEMORY
CELL ARRAY
2,048X128X16
(4,194,304)
A17
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SENSE AMP
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
COLUMN ADDRESS
DECODER
WE#
UB#
LB#
OE#
CE#
POWER DOWN
CIRCUIT
Preliminary
May 2001
2
Rev 1.0
EtronTech
EM564166
Operating Mode
Mode
CE# OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15
L
H
L
L
L
D
D
OUT
OUT
OUT
Read
L
L
L
H
L
High-Z
D
H
L
D
High-Z
OUT
L
D
D
IN
IN
Write
X
H
L
L
High-Z
D
IN
H
X
H
X
X
D
High-Z
IN
L
L
H
X
X
X
H
X
X
X
X
H
X
X
Output Deselect
Standby
High-Z
High-Z
High-Z
H
X
High-Z
Note: X = don't care. H=logic high. L=logic low.
Absolute Maximum Ratings
Supply voltage, V
Input voltages, V
-0.3 to +4.6V
-0.3 to +4.6V
DD
IN
-0.5 to V
DD
Input and output voltages, V
I/O
+0.5V
-40 to +85°C
-55 to +150°C
240°C
Operating temperature, T
OPR
Storage temperature, T
STRG
Soldering Temperature (10s), T
SOLDER
Power dissipation, P
D
0.6 W
DC Recommended Operating Conditions (Ta=-40 C to 85 C)
°
°
Symbol
Parameter
Power Supply Voltage
Input High Voltage
Min
Typ
Max
Unit
V
V
2.3
2.2
-0.3(2)
3.6
-
-
-
-
DD
V
V
+ 0.3(1)
V
IH
DD
V
Input Low Voltage
0.6
V
IL
V
Data Retention Supply Voltage
1.0
3.6
V
DR
Note:
(1) Overshoot : VDD +2.0V in case of pulse width £ 20ns
(2) Undershoot : -2.0V in case of pulse width £ 20ns
Preliminary
May 2001
3
Rev 1.0
EtronTech
EM564166
DC Characteristics (Ta = -40 C to 85 C, V
= 2.3V to 3.6V)
°
°
DD
Parameter
Symbol
Test Conditions
Min
Typ* Max Unit
Input low current
I
I
I
I
= 0V to V
- 1
-
1
0.4
-
-
-
-
mA
V
IL
IN
DD
Output low
voltage
V
= 2.1 mA
= -1.0 mA
OL
OL
OH
Output high
voltage
V
-
DD
V
V
OH
0.15
-
-
-
V
V
V
= 3.6 V
= 2.7 V
= 2.3 V
15
10
25
15
12
5
DD
DD
DD
Cycle time
= min
CE# = V and
IL
I
DD1
Operating current
I
= 0mA
mA
OUT
7
-
Other Input = V / V
IH
IL
-
-
I
Cycle time = 1ms
DD2
I
CE# = V
IH
0.5 mA
10
-
DDS1
1
V
V
V
V
= 3.6 V
-
-
-
DD
DD
DD
DD
CE# ³ V
DD
- 0.2V
0.8
0.5
Standby current
I
-70/85
mA
= 2.7 V
= 2.3 V
= 3.6 V
5
3
DDS2
-70E/85E
5
80
-
Notes:
* Typical value are measured at Ta = 25°C.
Capacitance (Ta = 25 C; f = 1 MHz)
°
Parameter
Symbol
Min
Typ
Max
10
Unit
pF
Test Conditions
Input capacitance
Output capacitance
C
V
= GND
= GND
-
-
-
-
IN
IN
C
10
pF
V
OUT
OUT
Notes:
This parameter is periodically sampled and is not 100% tested.
Preliminary
May 2001
4
Rev 1.0
EtronTech
EM564166
AC Characteristics and Operating Conditions (Ta = -40 C to 85 C, V
= 2.3V to 3.6V)
°
°
DD
Read Cycle
EM564166
-85 -70
Min Max Min Max
Symbol
Parameter
Unit
t
Read cycle time
85
-
70
-
-
-
RC
t
Address access time
85
85
45
45
-
70
70
35
35
-
AA
t
Chip Enable (CE#) Access Time
Output enable access time
-
-
CO1
t
-
-
OE
t
Data Byte Control Access Time
-
-
BA
t
Chip Enable Low to Output in Low-Z
Output enable Low to Output in Low-Z
Data Byte Control Low to Output in Low-Z
Chip Enable High to Output in High-Z
Output Enable High to Output in High-Z
Data Byte Control High to Output in High-Z
Output Data Hold Time
10
3
5
-
10
3
5
-
LZ
ns
t
-
-
OLZ
t
-
-
BLZ
t
35
35
35
-
25
25
25
-
HZ
t
-
-
OHZ
t
-
-
BHZ
t
10
10
OH
Write Cycle
EM564166
-85 -70
Min Max Min Max
Symbol
Parameter
Unit
t
Write cycle time
85
55
70
70
0
70
55
60
60
0
-
-
-
-
WC
t
Write pulse width
WP
t
Chip Enable to end of write
Data Byte Control to end of Write
Address setup time
-
-
CW
t
-
-
BW
t
-
-
AS
ns
t
Write Recovery time
WE# Low to Output in High-Z
WE# High to Output in Low-Z
Data Setup Time
0
0
-
-
WR
t
35
-
30
-
-
-
WHZ
t
5
5
OW
t
35
0
30
0
-
-
DS
t
Data Hold Time
-
-
DH
AC Test Condition
Output load : 50pF + one TTL gate
Input pulse level : 0.4V, 2.4V
Timing measurements : 0.5 x VDD
tR, tF : 5ns
·
·
·
·
Preliminary
May 2001
5
Rev 1.0
EtronTech
EM564166
Read Cycle
(See Note 1)
t
RC
Address
t
t
OH
AA
t
CO1
CE#
t
HZ
t
OE
OE#
t
OHZ
t
BA
UB# LB#
,
t
t
BLZ
BHZ
t
OLZ
t
LZ
D
O UT
VALID DATA OUT
Preliminary
May 2001
6
Rev 1.0
EtronTech
EM564166
Write Cycle1
(WE# Controlled)(See Note 4)
t
WC
Address
t
t
t
AS
WP
WR
WE#
t
CW
CE#
t
BW
UB# LB#
,
t
t
WHZ
OW
D
(See Note2)
(See Note3)
OUT
t
t
DS
DH
D
(See Note 5)
VALID DATA IN
(See Note 5)
IN
Preliminary
May 2001
7
Rev 1.0
EtronTech
EM564166
Write Cycle 2
(CE# Controlled)(See Note 4)
t
WC
Address
t
t
t
AS
W P
WR
WE#
t
CW
CE#
t
BW
UB# LB#
,
t
t
WHZ
BLZ
D
OUT
t
LZ
t
t
DS
DH
D
(See Note 5)
VALID DATA IN
IN
Preliminary
May 2001
8
Rev 1.0
EtronTech
EM564166
Write Cycle3
(UB#, LB# Controlled)(See Note 4)
t
WC
Address
t
t
t
AS
W P
WR
WE#
t
t
CW
CE#
BW
UB# LB#
,
t
t
WHZ
BLZ
D
OUT
t
LZ
t
t
DS
DH
D
(See Note 5)
VALID DATA IN
IN
Note:
1. WE# remains HIGH for the read cycle.
2. If CE# goes LOW with or after WE# goes LOW, the outputs will remain at high impedance.
3. If CE# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.
4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
Preliminary
May 2001
9
Rev 1.0
EtronTech
EM564166
Data Retention Characteristics (Ta = -40°C to 85°C)
Symbol
Parameter
Min
Typ Max Unit
CE# ³ VDD - 0.2V,
Data Retention Supply
Voltage
V
1.0
3.6
3.5
V
-
DR
VIN ³ VDD - 0.2V or VIN £ 0.2V
VDD = 1.0V, CE# ³ VDD - 0.2V,
VIN ³ VDD - 0.2V or VIN £ 0.2V
I
Data Retention Current
0.5
mA
-
DR
t
Chip Deselect to Data Retention Mode Time
Recovery Time
ns
ns
0
-
-
-
-
SDR
t
t
RDR
RC
CE# Controlled Data Retention Mode
t
RDR
t
Data Retention Mode
SDR
V
DD
2.7V
2.2V
V
DR
Note 1
CE#
GND
Note:
1. CE# ³ VDD – 0.2V or UB# = LB# ³ VDD – 0.2V
Preliminary
May 2001
10
Rev 1.0
EtronTech
EM564166
Package Diagrams
48-Ball (6mm x 8mm) BGA
Units in mm
TOP VIEW
BOTTOM VIEW
PIN 1 CORNER
0.10 S
C
C
0.25 S
0.30
A
B
0.05(48X)
PIN 1 CORNER
6
5
4
3
2
1
1
2
3
4
5
6
- B -
0.75
3.75
- A -
0.20(4X)
0.10
- C -
SEATING PLANE
Preliminary
May 2001
11
Rev 1.0
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