W127 [ETC]
Clocks and Buffers ; 时钟和缓冲器\n型号: | W127 |
厂家: | ETC |
描述: | Clocks and Buffers
|
文件: | 总20页 (文件大小:202K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
W127/W127-A
SpreadSpectrum3DIMMSystemFrequencySynthesizerw/AGP
CPU Cycle to Cycle Jitter:...........................................250 ps
Features
CPU to AGP Skew: .................................................0±500 ps
• Maximized EMI suppression using Cypress’s Spread
AGP to PCI Skew:..................................1.5 ns (AGP Leads)
CPU Output Edge Rate:............................................ >1 V/ns
SDRAM Output Edge Rate:.................................... >1.5 V/ns
Spectrum technology
• I2C interface
• Four copies of CPU Output
• Six copies of PCI Output
• Two copies of AGP Output
• One copy of 48-MHz USB Output
• One copy of 24-MHz SIO Output
• Twelve copies of SDRAM Output
• One buffered copy of 14.318-MHz reference input
• Mode input pin selects optional power management in-
put control pins (reconfigures pins 29, 30, 31, and 32)
• Smooth frequency transition upon frequency
reselection
Note: All skews are optimized @VDDQ2 = VDDQ3 = 3.3V±5%.
Skews are not guaranteed for VDDQ2 = 2.5V.
Table 1. Pin Selectable Frequency[1]
Input Address
CPU
AGP
PCI
FS2
0
FS1
0
FS0
0
(MHz)
(MHz)
(MHz)
68.5
112
68.5
74.6
63.5
66.6
55.53
75
34.25
37.3
0
0
1
0
1
0
95.25
100
31.75
33.3
• Available in 48-pin SSOP (300 mils)
0
1
1
• Standard W127 device supports up to 112-MHz opera-
tions. High-performance option W127-A supports up to
124-MHz.
1
0
0
83.3
75.0
124
27.77
37.5
1
0
1
1
1
0
82.6
66.6
41.3
Key Specifications
1
1
1
66.6
33.3
Supply Voltages:.......... VDDQ3 = 3.3V, VDDQ2 = 3.3V or 2.5V
.
Pin Configuration[2]
Block Diagram
SDATA
SCLOCK
Device
Control
Serial Port
XTAL OSC
PLL1
VDDQ3
VDDQ3
REF/SD_SEL*
GND
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48MHz/FS1*
24MHz/FS0*
GND
2
PLL Ref
Freq
3
4
GND
X1
X2
X1
5
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4(AGP_STOP#)*
SDRAM5(PWR_DWN#)*
SDRAM6(CPU_STOP#)*
SDRAM7(PCI_STOP#)*
GND
VDDQ3
X2
6
7
8
9
VDDQ3
PCI_F/FS2*
PCI0
REF/SD_SEL
I/O
4
VDDQ2
CPU0:3
GND
PCI1
PCI2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CPU
STOP
(CPU_STOP#)
PCI3
VDDQ3
PCI4
SDRAM
STOP
÷1
÷1.5
SDRAM0:11
GND
12
GND
AGP_F/MODE*
AGP0
VDDQ3
SDRAM11
SDRAM10
VDDQ3
SDATA
VDDQ3
AGP_F/MODE
AGP0
I/O
I/O
AGP
STOP
SDRAM8
SDRAM9
SCLOCK
÷2
(AGP_STOP#)
PCI_F/FS2
PCI0:4
PCI
STOP
/
5
(PCI_STOP#)
(PWR_DWN#)
Power Down
Control
VDDQ3
÷1
48MHZ/FS1
24MHZ/FS0
I/O
I/O
PLL2
÷2
Notes:
1. Configuration “110” is supported by W127-A only (see shaded row of Table 1).
2. Signal names with “*” denote pins have internal 250K pull-up resistor, though not relied upon for pulling to VDDQ3. Signal names with parenthesis denote function
is selectable by MODE pin strapping.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07225 Rev. *A
Revised December 14, 2002
PRELIMINARY
W127/W127-A
Pin Definitions
Pin
No.
Pin
Type
Pin Name
Pin Description
CPU0:3
44, 43,
41, 40
O
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled
by the CPU_STOP# control pin. Output voltage swing is controlled by voltage
applied to VDDQ2.
PCI_F/FS2
8
I/O
Free-running PCI Clock Output and Frequency Selection Bit 2: As an output,
this pin works in conjunction with PCI0:4. Output voltage swing is controlled by
voltage applied to VDDQ3.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:2 determines the power-up default frequency of device output clocks
as per Table 1, “Pin Selectable Frequency” on page 1.
PCI0:4
9, 11, 12, 13,
14
O
O
PCI Clock Outputs 0 through 4: Output voltage swing is controlled by voltage
applied to VDDQ3. Outputs are held LOW if PCI_STOP# is set LOW.
SDRAM0:3
SDRAM8:11
38, 37, 35, 34,
27, 26, 21, 20
SDRAM Clock Outputs: These eight SDRAM clock outputs run synchronous to
the CPU clock outputs or AGP clock output as selected using SD_SEL per Table 2.
SDRAM4:7
32, 31, 30, 29
I/O
SDRAM Clock Outputs: These four SDRAM clock outputs run synchronous to
the CPU clock outputs or AGP clock output as selected using SD_SEL per Table
2. If programmed as inputs, (refer to MODE pin description), these pins are used
for STOP_ CPU, AGP, PCI, and power-down control.
48MHZ/FS1
48
I/O
I/O
I/O
48-MHz Output and Frequency Selection Bit 1: Fixed clock output that defaults
to 48 MHz following device power-up.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:2 determines the power-up default frequency of device output clocks
as per Table 1, “Pin Selectable Frequency” on page 1.
24MHZ/FS0
47
17
24-MHz Output and Frequency Selection Bit 0: Fixed clock output that defaults
to 24 MHz following device power-up.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:2 determines the power-up default frequency of device output clocks
as per Table 1, “Pin Selectable Frequency” on page 1.
AGP_F/MODE
Free-runningAGPOutputandModeControlInput: As an output, thispinworks
in conjunction with AGP0 and is a free running clock. When an input, it determines
the functions for pin 29, 30, 31, and 32. See Table 3.
AGP0
18
3
O
AGP Output: This output is controlled by the AGP_STOP# pin.
REF/SD_SEL
I/O
Fixed 14.318-MHz and SDRAM Output Selection: As an output, this pin is used
for various system applications. Output voltage swing is controlled by voltage
applied to VDDQ3.
When an input, this pin selects the SDRAM to run synchronous to either CPU or
AGP. See Table 2.
X1
5
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
6
I
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
SDATA
SCLOCK
VDDQ3
23
25
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Inter-
face section that follows.
I
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
1, 2, 7, 19, 22,
24, 36
P
Power Connection: Connected to 3.3V supply.
VDDQ2
GND
42
P
Power Connection: Power Supply for CPU0:3 clock outputs. (3.3V Supply)
4, 10, 15, 16,
28, 33, 39, 45,
46
G
Ground Connection: Connect all ground pins to the common system ground
plane.
Document #: 38-07225 Rev. *A
Page 2 of 20
PRELIMINARY
W127/W127-A
W127/W127-A Pin Selection Tables
Table 2. SD_SEL Function
SD_SEL
SDRAM0:11
1
0
Running @ CPU Frequency
Running @ AGP Frequency
Table 3. Mode Function
Pin Function
Mode
Pin 29
Pin 30
SDRAM6
Pin 31
SDRAM5
Pin 32
SDRAM4
1
0
SDRAM7
PCI_STOP#
CPU_STOP#
PWR_DWN#
AGP_STOP#
Table 4. Power Management Pin Function
SIGNAL
=0
=1
CPU_STOP#
PCI_STOP#
AGP_STOP#
PWR_DWN#
CPU0:3 & SDRAM0:11 = LOW
PCI0:4 = LOW
Active
Active
Active
Active
AGP0 = LOW
All Clock Outputs LOW
Upon W127/W127-A power-up, the first 2 ms of operation is
used for input logic selection. During this period, the 24-MHz,
48-MHz, REF, PCI_F and AGP_F clock output buffers are
three-stated, allowing the output strapping resistor on each l/O
pin to pull the pin and its associated capacitive clock load to
either a logic HIGH or logic LOW state. At the end of the 2-ms
period, the established logic 0 or 1 condition of each l/O pin is
latched. Next the output buffers are enabled, converting all l/O
pins into operating clock outputs. The 2-ms timer starts when
VDDQ3 reaches 2.0V. The input bits can only be reset by turn-
ing VDDQ3 off and then back on again.
Overview
The W127/W127-A was designed specifically to provide all
clock signals required for a motherboard designed with the Via
MVP3 chipset using either a Pentium® or K6 microprocessor.
Although it can be used with split voltages (3.3/2.5), the skew
specifications are guaranteed only for single 3.3V supply. The
primary distinguishing feature of the W127/W127-A is the
95.25-MHz CPU frequency option, which supports the K6 333-
MHz CPU.
Twelve SDRAM outputs are provided for support of up to 3
SDRAM DIMM modules. Unused clock outputs can be dis-
abled through the I2C interface to reduce system power con-
sumption and more importantly reduce EMI emissions.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock output is 40Ω (nominal), which is minimally
affected by the 10-kΩ strap to ground or VDDQ3. As with the
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDDQ3 should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
Functional Description
I/O Pin Operation
Pins 3, 8, 17, 47, and 48 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after power-
up, the logic state of each pin is latched and the pins then
become clock outputs. This feature reduces device pin count
by combining clock outputs with input select pins.
When the clock outputs are enabled following the 2-ms input
period, target (normal) output frequency is delivered, assum-
ing that VDDQ3 has stabilized. If VDDQ3 has not yet reached full
value, output frequency initially may be below target but will
increase to target once VDDQ3 voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
An external 10-kΩ “strapping” resistor is connected between
each l/O pin and ground or VDDQ3. Connection to ground sets
a latch to “0,” connection to VDDQ3 sets a latch to “1.” Figure 1
and Figure 2 show two suggested methods for strapping resis-
tor connection.
Document #: 38-07225 Rev. *A
Page 3 of 20
PRELIMINARY
W127/W127-A
V
DDQ3
Output Strapping Resistor
Series Termination Resistor
10 kΩ
(Load Option 1)
Clock Load
W127/W127-A
R
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
10 kΩ
(Load Option 0)
Q
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
Output Strapping Resistor
Series Termination Resistor
V
DD
10 kΩ
Clock Load
W127/W127-A
R
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
CPU/PCI Frequency Selection
ther an externally generated clock signal or the clock generat-
ed by the internal crystal oscillator. When using an external
clock signal, pin X1 is used as the clock input and pin X2 is left
open. The input threshold voltage of pin X1 is (VDDQ3)/2.
CPU output frequency is selected with I/O pins 8, 47, and 48.
Refer to Table 1 for CPU/PCI frequency programming informa-
tion. Alternatively, frequency selections are available through
the serial data interface. Refer to Table 8, “Additional Frequen-
cy Selections through Serial Data Interface Data Bytes,” on
page 9.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The W127/W127-A
incorporates the necessary feedback resistor and crystal load
capacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 20 pF. For opti-
mum frequency accuracy without the addition of external ca-
pacitors, a parallel-resonant mode crystal specifying a load of
20 pF should be used. This will typically yield reference fre-
quency accuracies within ±100 ppm. To achieve similar accu-
racies with a crystal calling for a greater load, external capac-
itors must be added such that the total load (internal, external,
and parasitic capacitors) equals that called for by the crystal.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serially terminated clock
lines. The W127/W127-A outputs are CMOS-type, which pro-
vide rail-to-rail output swing.
Crystal Oscillator
The W127/W127-A requires one input reference clock to syn-
thesize all output frequencies. The reference clock can be ei-
Document #: 38-07225 Rev. *A
Page 4 of 20
PRELIMINARY
W127/W127-A
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is ±0.5% of the center frequen-
cy. Figure 4 details the Cypress spreading pattern. Cypress
does offer options with more spread and greater EMI reduc-
tion. Contact your local Sales representative for details on
these devices.
Spread Spectrum Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate values for bits 1–0 in data byte 0 of the
I2C data stream. Refer to Table 7 for more details.
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+.0.5%)
MIN. (–0.5%)
Figure 4. Typical Modulation Profile
Document #: 38-07225 Rev. *A
Page 5 of 20
PRELIMINARY
W127/W127-A
logic outputs of the chipset. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions. Table 5 summarizes the control
functions of the serial data interface.
Serial Data Interface
The W127/W127-A features a two-pin, serial data interface
that can be used to configure internal register settings that
control particular device functions. Upon power-up, the
W127/W127-A initializes with default register settings, there-
fore the use of this serial data interface is optional. The serial
interface is write-only (to the clock chip) and is the dedicated
function of device pins SDATA and SCLOCK. In motherboard
applications, SDATA and SCLOCK are typically driven by two
Operation
Data is written to the W127/W127-A in ten bytes of eight bits
each. Bytes are written in the order shown in Table 6.
Table 5. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held LOW.
and system power. Examples are clock out-
puts to unused SDRAM DIMM socket or PCI
slot.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections. Frequen- For alternate CPU devices and power man-
cy is changed in a smooth and controlled fashion. agement options. Smooth frequency transi-
tion allows CPU frequency change under nor-
mal system operation.
Output Three-state
(Reserved)
Puts all clock outputs into a high-impedance state. Production PCB testing.
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
Table 6. Byte Writing Sequence
Byte Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the W127/W127-A to accept the bits in Data Bytes 0–6 for
internal register configuration. Since other devices may exist on the
same common serial data bus, it is necessary to have a specific slave
address for each potential receiver. The slave receiver address for the
W127/W127-A is 11010010. Register setting will not be made if the
Slave Address is not correct (or is for an alternate slave receiver).
2
3
Command
Code
Don’t Care
Don’t Care
Unused by the W127/W127-A, therefore bit values are ignored (“don’t
care”). This byte must be included in the data write sequenceto maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Byte Count
Unused by the W127/W127-A, therefore bit values are ignored (“don’t
care”). This byte must be included in the data write sequenceto maintain
proper byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
4
5
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Refer to Table 7 The data bits in these bytes set internal W127/W127-A registers that
control device operation. The data bits are only accepted when the Ad-
dress Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to Table 7, Data Byte Serial Configuration
Map.
6
7
8
9
10
Document #: 38-07225 Rev. *A
Page 6 of 20
PRELIMINARY
W127/W127-A
Writing Data Bytes
Table 8 details additional frequency selections that are avail-
able through the serial data interface.
Each bit in the data bytes controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 7 gives the bit formats for registers located in Data
Bytes 0–6.
Table 9 details the select functions for Byte 0, bits 1 and 0.
Table 7. Data Bytes 0–6 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 0
7
6
5
4
--
--
--
--
--
--
(Reserved)
--
--
0
0
0
0
0
SEL_2
Refer to Table 8
Refer to Table 8
Refer to Table 8
--
SEL_1
--
SEL_0
3
8, 47, 48
FS0:2
BYT0 /FS#
Frequency Controlled Frequency Controlled
by external pins FS0:2 by SEL_0:2, above
2
(Reserved)
Bit 1 Bit 0
--
--
0
1–0
--
--
Function (See Table 9 for function details)
Normal Operation
00
0
0
1
1
0
1
0
1
(Reserved)
Spread Spectrum On
All Outputs Three-stated
Data Byte 1
7
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
--
--
--
--
0
0
0
0
1
1
1
1
6
5
--
--
--
--
4
--
--
--
--
3
40
41
43
44
CPU3
CPU2
CPU1
CPU0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Active
Active
Active
Active
2
1
0
Data Byte 2
7
6
5
4
3
2
1
0
--
8
--
(Reserved)
--
--
0
1
0
1
1
1
1
1
PCI_F
--
Clock Output Disable
(Reserved)
Low
--
Active
--
--
14
13
12
11
9
PCI4
PCI3
PCI2
PCI1
PCI0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Document #: 38-07225 Rev. *A
Page 7 of 20
PRELIMINARY
W127/W127-A
Table 7. Data Bytes 0–6 Serial Configuration Map (continued)
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 3
7
29
30
31
32
34
35
37
38
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
Active
1
1
1
1
1
1
1
1
6
5
4
3
2
1
0
Data Byte 4
7
--
--
--
(Reserved)
--
--
0
0
1
1
1
1
1
1
6
--
(Reserved)
--
--
5
17
18
20
21
26
27
AGP_F
AGP0
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
4
3
SDRAM11 Clock Output Disable
SDRAM10 Clock Output Disable
2
1
SDRAM9
SDRAM8
Clock Output Disable
Clock Output Disable
0
Data Byte 5
7
--
--
--
--
--
--
--
3
--
--
(Reserved)
--
--
--
0
0
0
0
0
0
0
1
5
(Reserved)
--
5
--
(Reserved)
--
--
4
--
(Reserved)
--
--
--
3
--
(Reserved)
--
2
--
(Reserved)
--
--
1
--
(Reserved)
--
--
0
REF
Clock Output Disable
Low
Active
Data Byte 6
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
Document #: 38-07225 Rev. *A
Page 8 of 20
PRELIMINARY
W127/W127-A
Table 8. Additional Frequency Selections through Serial Data Interface Data Bytes[3]
Input Conditions
Output Frequency
Data Byte 0, Bit 3 = 1
Bit 6
Bit 5
Bit 4
CPU Clocks
(MHz)
PCI Clocks
(MHz)
SEL_2
SEL_1
SEL_0
AGP
68.5
74.6
63.5
66.6
55.53
75
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
68.5
112
34.25
37.3
95.25
100
31.75
33.3
83.3
75.0
124
27.77
37.5
82.6
66.6
41.3
66.6
33.3
Table 9. Select Function for Data Byte 0, Bits 0:1
Input Conditions
Output Conditions
Data Byte 0
CPU0:3,
PCI_F,
Function
Normal Operation
Spread Spectrum
Three-state
Bit 1
Bit 0
SRAM0:11
Note 4
±0.5%
PCI0:4
Note 4
±0.5%
Hi-Z
REF
48/24MHZ
0
1
1
0
0
1
14.318 MHz
14.318 MHz
Hi-Z
48/24 MHz
48/24 MHz
Hi-Z
Hi-Z
Notes:
3. Configuration “110” is supported by W127-A only (see shaded row of Table 8).
4. CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 8.
Document #: 38-07225 Rev. *A
Page 9 of 20
PRELIMINARY
W127/W127-A
Although the W127/W127-A is a receive-only device (no data
write-back capability), it does transmit an “acknowledge” data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.
How To Use the Serial Data Interface
Electrical Requirements
Figure 5 illustrates electrical characteristics for the serial inter-
face bus used with the W127/W127-A. Devices send data over
the bus with an open drain logic output that can (a) pull the bus
line LOW, or (b) let the bus default to logic 1. The pull-up re-
sistors on the bus (both clock and data lines) establish a de-
fault logic 1. All bus devices generally have logic inputs to re-
ceive data.
The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration
total bus line capacitance.
VDD
VDD
~ 2k
Ω
~ 2kΩ
SERIAL BUS DATA LINE
SERIAL BUS CLOCK LINE
SDCLK
SDATA
SCLOCK
SDATA
CLOCK IN
DATA IN
CLOCK IN
DATA IN
DATA OUT
N
N
N
CLOCK OUT
DATA OUT
CHIP SET
(SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE
(SERIAL BUS SLAVE RECEIVER)
Figure 5. Serial Interface Bus Electrical Characteristics
Document #: 38-07225 Rev. *A
Page 10 of 20
PRELIMINARY
W127/W127-A
Signaling Requirements
A write sequence is initiated by a “start bit” as shown in Figure
7. A “stop bit” signifies that a transmission has ended.
As shown in Figure 6, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
As stated previously, the W127/W127-A sends an “acknowl-
edge” pulse after receiving eight data bits in each byte as
shown in Figure 8.
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 6. Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Start
Bit
Stop
Bit
Figure 7. Serial Data Bus Start and Stop Bit
Document #: 38-07225 Rev. *A
Page 11 of 20
PRELIMINARY
W127/W127-A
Signaling from System Core Logic
Start Condition
Stop Condition
Slave Address
(First Byte)
Command Code
(Second Byte)
Byte Count
(Third Byte)
Last Data Byte
(Last Byte)
MSB
1
LSB
1
SDATA
SCLOCK
SDATA
1
2
0
1
0
0
6
0
8
MSB
1
LSB
8
MSB
MSB
1
LSB
8
1
3
4
5
7
A
2
3
4
5
6
7
A
1
2
3
4
2
3
4
5
6
7
A
Acknowledgment Bit
from Clock Device
Signaling by Clock Device
Figure 8. Serial Data Bus Write Sequence
SDATA
tSPF
tLOW
tDSU
tDHD
tSP
tSTHD
tHIGH
tSPSU
tSTHD
SCLOCK
tSPSU
tR
tF
Figure 9. Serial Data Bus Timing Diagram
Document #: 38-07225 Rev. *A
Page 12 of 20
PRELIMINARY
W127/W127-A
Absolute Maximum Ratings [5.]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
VDDQ3, VIN
Description
Voltage on any Pin with Respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
Unit
V
TSTG
TB
°C
°C
°C
kV
Ambient Temperature under Bias
Operating Temperature
TA
ESDPROT
Input ESD Protection
2 (min.)
3.3V DC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = VDDQ2 = 3.3V±5% (3.135–3.465V)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD
Combined 3.3V Supply Current
CPU0:3 = 66.6 MHz
Outputs Loaded[5]
290
mA
Logic Inputs
VIL
VIH
IIL
Input Low Voltage
Input High Voltage
Input Low Current[7]
Input High Current
0.8
V
V
2.0
20
5
µA
µA
IIH
Clock Outputs
VOL
VOH
IOL
Output Low Voltage
IOL = 1 mA
IOH = –1 mA
VOL = 1.5V
50
mV
V
Output High Voltage
Output Low Current
3.1
55
80
CPU0:3
75
105
155
mA
SDRAM0:11,
AGP_F, AGP0
110
PCI_F, PCI0:4
REF
55
60
55
55
80
75
75
105
90
48/24MHz
CPU0:3
75
105
125
175
IOH
Output High Current
VOH = 1.5V
85
mA
SDRAM0:11,
AGP_F, AGP0
120
PCI_F, PCI0:4
REF
55
60
55
85
85
85
125
110
125
48/24MHz
Crystal Oscillator
VTH
X1 Input Threshold Voltage[8]
1.65
20
V
CLOAD
Load Capacitance, Imposed on
pF
External Crystal[9]
CIN,X1
X1 Input Capacitance[10]
Pin X2 unconnected
30
pF
Notes:
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
7. W127/127-A logic inputs have internal pull-up devices (not full CMOS level).
8. X1 input threshold voltage (typical) is VDD/2.
9. The W127/W127-A contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on
crystal is 20 pF; this includes typical stray capacitance of short PCB traces to crystal.
10. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Document #: 38-07225 Rev. *A
Page 13 of 20
PRELIMINARY
W127/W127-A
3.3V DC Electrical Characteristics (continued) TA = 0°C to +70°C, VDDQ3 = VDDQ2 = 3.3V±5% (3.135–3.465V)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Except X1 and X2
5
6
7
pF
pF
nH
COUT
LIN
Output Pin Capacitance
Input Pin Inductance
Serial Input Port
VIL
VIH
IIL
Input Low Voltage
VDDQ3 = 3.3V
VDDQ3 = 3.3V
0.3VDDQ3
V
V
Input High Voltage
Input Low Current
Input High Current
0.7VDDQ3
10
10
µA
µA
mA
IIH
IOL
Sink Current into SDATA or SCLOCK, IOL = 0.3(VDDQ3
)
6
Open Drain N-Channel Device On
CIN
Input Capacitance of SDATA and
SCLOCK
10
pF
CSDATA
Total Capacitance of SDATA Bus
Total Capacitance of SCLOCK Bus
400
400
pF
pF
CSCLOCK
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.35–3.465V), fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU AGP Clock Outputs, CPU0:3, AGP_F, AGP0 (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Min. Typ. Max. Unit
tP
f
Period
15
ns
MHz
ns
Frequency, Actual
High Time
66.6
tH
tL
tR
tF
tD
5.2
5
Low Time
ns
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
1
4
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
1
Measured on rising and falling edge at 1.5V
45
55
250
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
ps
tSK
fST
Output Skew
Measured on rising edge at 1.5V
250
3
ps
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
Power-up (cold start)
ms
from power-up. Short cycles exist prior to frequen-
cy stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
10
15
20
Ω
Document #: 38-07225 Rev. *A
Page 14 of 20
PRELIMINARY
W127/W127-A
AC Electrical Characteristics (continued)
SDRAM Clock Outputs, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6 MHz
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Measured from 0.4V to 2.4V
Min. Typ. Max. Unit
tP
f
Period
15
ns
MHz
V/ns
V/ns
%
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
66.6
tR
tF
1
1
4
4
Measured from 2.4V to 0.4V
tD
tJC
Measured on rising and falling edge at 1.5V
45
55
250
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
ps
tSK
tSK
Output Skew
Measured on rising edge at 1.5V
100
ps
ps
CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on
rising edge at 1.5V.
500
3
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within 1 ms
ms
Power-up (cold start)
from power-up. Short cycles exist prior to frequen-
cy stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
10
15
20
Ω
PCI Clock Outputs, PCI_F and PCI0:4 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6 MHz
Min. Typ. Max. Unit
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
tP
f
Period
30
ns
MHz
ns
Frequency, Actual
High Time
33.3
tH
tL
12
12
1
Low Time
ns
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
1
tD
tJC
Measured on rising and falling edge at 1.5V
45
55
250
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
ps
tSK
tO
Output Skew
Measured on rising edge at 1.5V
250
3
ps
ns
AGP to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within 1 ms
3
ms
Power-up (cold start)
from power-up. Short cycles exist prior to frequen-
cy stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
20
Ω
Document #: 38-07225 Rev. *A
Page 15 of 20
PRELIMINARY
W127/W127-A
AC Electrical Characteristics (continued)
REF Clock Output (Lump Capacitance Test Load = 45 pF)
CPU = 66.6 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
14.31818
tR
0.5
0.5
40
2
2
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
60
1.5
fST
Frequency Stabilization
Assumes full supply voltage reached within
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
30
Ω
48-/24-MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio
(see m/n below)
48.008/24.004
MHz
fD
Deviation from 48 MHz
PLL Ratio
(48.008 – 48)/48
+167
ppm
m/n
tR
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
57/17, 54/34
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization
Assumes full supply voltage reached within
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
30
0
Ω
Serial Input Port
Parameter
Description
Test Condition
Min.
0
Typ.
Max.
Unit
kHz
µs
fSCLOCK
tSTHD
tLOW
SCLOCK Frequency
Start Hold Time
Normal Mode
100
4.0
4.7
4.0
250
0
µs
SCLOCK Low Time
SCLOCK High Time
Data Set-up Time
Data Hold Time
µs
tHIGH
tDSU
ns
tDHD
(Transmitter should provide a 300-ns hold
time to ensure proper timing at the receiver.)
ns
tR
Rise Time, SDATA and SCLOCK From 0.3VDD to 0.7VDD
Fall Time, SDATA and SCLOCK From 0.7VDD to 0.3VDD
Stop Set-up Time
1000
300
ns
ns
µs
µs
tF
tSTSU
tSPF
4.0
4.7
Bus Free Time between Stop
and Start Condition
ns
tSP
Allowable Noise Spike Pulse
Width
50
Document #: 38-07225 Rev. *A
Page 16 of 20
PRELIMINARY
W127/W127-A
Ordering Information
Package
Name
Ordering Code
W127
Package Type
H
48-pin SSOP (300 mils)
W127-A
Pentium is a registered trademark of Intel Corporation.
Document #: 38-07225 Rev. *A
Page 17 of 20
PRELIMINARY
W127/W127-A
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
Document #: 38-07225 Rev. *A
Page 18 of 20
PRELIMINARY
W127/W127-A
Addendum: W127/W127-A Replaces W48S87-27A
The W127/W127-A is a pin-compatible replacement for the W48S87-27A with the following output frequency modifications (Refer
to Table 1):
1. The 90-MHz CPU operation is changed to 95.25-MHz to support the K6 333-MHz chipset.
2. The 60-MHz CPU operation is changed to 124-MHz to support new motherboard designs.
Document #: 38-07225 Rev. *A
Page 19 of 20
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
W127/W127-A
Document Title: W127/W127-A Spread Spectrum 3 DIMM System Frequency Synthesizer w/AGP
Document Number: 38-07225
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
110490
Description of Change
02/13/02
12/14/02
SZV
RBI
Change from Spec number: 38-00893 to 38-07225
*A
122842
Power up requirements added to Operating Conditions Information
Document #: 38-07225 Rev. *A
Page 20 of 20
相关型号:
W12NK90Z
N-CHANNEL 900V - 0.72 ohm - 11A TO-247 Zener-Protected SuperMESH Power MOSFET
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明