NT3882H [ETC]
Dot Matrix LCD 40-Channel Driver; 点阵LCD 40通道驱动器
| 型号： | NT3882H |
| 厂家： | 
ETC |
| 描述： | Dot Matrix LCD 40-Channel Driver |
| 文件： | 总9页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NT3882
Dot Matrix LCD 40-Channel Driver
Features
Provides a 40 channel LCD driver
DD
EE
LCD driving voltage range (V - V ): 3.5V to 11V
Internal serial to parallel conversion circuits:
20-bit shift register X 2
40-bit latch X 1
40-bit 4 level driver X 1
Logic circuit supply voltage range: 4.5V - 5.5V
Applicable LCD duty cycle: 1/2 to 1/16
Interfaces with a NT3881C/D LCD controller
LCD bias voltage can be supplied externally
Available in 64-pin QFP and in CHIP FORM
General Description
The NT3882 is a dot matrix LCD 40 channel driver
fabricated by low power CMOS technology. This IC
consists of two 20-bit shift registers, a 40-bit latch, and a
40-bit 4 level LCD driver. The NT3882 converts serial
data which is received from the LCD controller
(NT3881C/D) to parallel data and then outputs LCD
driving waveforms to drive LCD. Expansion of character-
type liquid crystal display can be easily obtained
according to the number and structure of characters.
Pin Configuration
Pad Configuration
S
2
9
S
3
4
S
3
3
S
3
2
S
3
1
S
3
0
S
3
5
S
3
6
S
3
7
S
3
8
S
3
9
S
4
0
S
3
3
S
3
2
S
3
1
S
3
0
S
3
5
S
3
6
S
3
7
S
3
8
S
3
9
S
4
0
S
3
4
N
C
N
C
2
6 3
6 2
6 1
6 0
5 9
5 7
5 6
5 5
5 4
5 3
5 2
S 2 8
S 2 7
S 2 6
S 2 5
S 2 4
S 2 3
S 2 2
S 2 1
S 2 0
S 1 9
S 1 8
S 1 7
S 1 6
S 1 5
S 1 4
S 1 3
3
64 63 62 61 60 59 58 57 56 55 54 53 52
4
NC
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
1
2
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
2
5 1
4 8
V
V
2
3
5
NC
NC
3
6
4
V
3
4 6
4 2
VEE
M
7
5
NC
8
6
VEE
NC
4 0
3 9
D R 2
D L 2
9
7
8
NC
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
9
NC
NT3882H
3 8
3 7
D R 1
D L 1
10
11
12
13
14
15
16
17
18
19
M
NT3882F
NC
DR2
DL2
DR1
DL1
GND
CL2
CL1
NC
3 6
3 5
3 4
3 2
G N D
C L 2
C L 1
S 1
2 5
1 9
2 0
2 1
2 2
2 3
2 4
2 7
2 8
2 9
3 0
3 1
20 21 22 23 24 25 26 27 28 29 30 31 32
S
1
2
S
9
S
1
0
S
1
1
S
8
S
7
V
S
6
S
5
S
4
S
3
S
2
D
D
S
9
S
1
0
S
1
1
S
8
S
7
V
N
C
S
6
S
5
S
4
S
3
S
2
S
1
D
D
1
V2.0 November, 1999
NT3882
Block Diagram
S1
S2
S19
S20
S21
S22
S39
S40
V
DD
V
V
2
3
40-Bit 4-Level LDC Drivers
V
EE
M
40-Bit Latch
CL1
DL2
CL2
20-Bit Shift
Register
20-Bit Shift
Register
DR2
DR1 DL2
GND
2
NT3882
Pin and Pad Descriptions
Pin No.
Pad No.
Designation
I/O
External Connection
Description
2- 24,
27 - 32,
52 - 57,
59 - 63
27 - 32,
2 - 24,
52 - 57,
59 - 63
S29 - S7,
S6 - S1,
S40 - S35,
S30 - S34
O
LCD panel
Segment signal output pins
25
25
P
I
Power supply
Controller
Power for logic circuits
Clock to latch serial data
Clock to shift serial data
0V
DD
V
34
34
CL1
CL2
GND
DL1
DR1
DL2
DR2
M
35
35
I
Controller
36
36
P
I
Power Supply
Controlleror NT3882
NT3882
37
37
Data input of 1 - 20 bits from controller
Data output of 20 bit shift register
Data input of 21 - 40 bits from controller
Data output of 40 bit shift register
Alternate signal for LCD drivers
Power for LCD drivers
38
38
O
I
39
40
39
40
Controlleror NT3882
NT3882
O
I
42
42
Controller
46, 48, 51
46, 48, 51
P
Power Supply
EE
3
2
V , V , V
1, 26, 33, 41,
43 - 45, 47,
49, 50, 58,
64
-
NC
-
-
No connection
Functional Description
NT3882 is a dot matrix LCD segment driver LSI. It
operates with the controller, such as NT3881C/D, and/or
another segment driver LSI NT3882. NT3882 receives
serial data from the controller or another NT3882,
converts it to parallel data and then supplies the LCD
driving waveforms to the LCD panel.
4. DR1
The 20th bit data of first 20-bit shift register output from
DR1. The data shifted out from DR1 after 20 bit delay
are synchronized with the clock pulse (CL2). By
connecting DR1 to DL2, two 20-bit shift registers can be
cascaded to one 40-bit shift register.
1. CL1
This signal is used for latching the shift register contents.
When CL1 is set at high, the shift register contents are
transferred to the 40-bit 4level LCD driver. When CL1 is
set at low, the last display output data (S1 to S40) is
held.
5. DL2
The 21 - 40 bit data from the LCD controller is fed into
the second 20-bit shift register through DL2.
6. DR2
2. CL2
The 40th bit data of the second 20-bit shift register
output is from DR2. The data shifted out from DR2 after
a 20-bit delay is synchronized with the clock pulse (CL2).
By connecting DR2 to the next NT3882 DL1, the cascade
construction is obtained to drive a wider LCD panel.
Clock pulse inputs for the two 20-bit shift registers. The
data is shifted to a 40-bit latch at the falling edge of CL2.
The clock singal CL2 must be active when operating to
refresh shift registers' contents.
7. S1 to S40
3. DL1
These 40 bits represent the 40 data bits in the 40-bit
The 1 - 20 bit data from LCD controller is fed into the
first 20-bit shift register through DL1.
DD
2
3
EE
latch. One of V , V , V and V is selected as a LCD
driving voltage source according to the combination of
latched data level and the alternate signal (M).
3
NT3882
The truth table is listed as follows:
Latched Data
1(High)
M
Output level of S1 to S40
1(High)
0(Low)
1(High)
0(Low)
EE
V
(Selected)
0(Low)
DD
V
3
V
(Nonselected)
2
V
*Comments
Absolute Maximum Ratings*
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposed to the absolute
maximum rating conditions for extended periods may
affect device reliability.
Power Supply Voltage (VDD-GND) . . . . . . . -0.3V to 7.0V
Power Supply Voltage (VDD-VEE) . . . . . . . . . . . . . . . . . .
DD
DD
. . . . . . . . . . . . . . . . . . . . . . . V - 13.5V to V + 0.3V
DD
Input Voltage . . . . . . . . . . . . . . . . . .-0.3V to V + 0.3V
Operating Temperature . . . . . . . . . . . . . -20 C to + 75 C
Storage Temperature . . . . . . . . . . . . . .-55 C to + 125 C
DC Electrical Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25 C)
Symbol
Parameter
Terminal
CL1, CL2
DL1, DL2
DR1, DR2
Min.
0.7 X V
0
Typ.
Max.
Unit
V
Conditions
Input Voltage
-
-
-
-
-
IH
V
DD
DD
V
V
IL
V
DD
0.3 X V
Output Voltage
-
V
OH
V
DD
V
OH
OL
ON
ON
- 0.4
I
I
I
I
= -0.4mA
-
0.4
1.1
105
5
V
OL
V
= 0.4mA
Vi-Sj Voltage
Descending
Note 1
-
V
D1
V
= 0.1mA for one of Sj
= 0.05mA for each of Sj
V
D2
V
Input Leakage
Current
CL1, CL2
DL1, DL2
-5
-10
-
-
-
-
IL
A
A
A
VIN = 0 or VDD
S1 to S40 open
I
Vi Leakage
Current
10
VL
2
3
EE
I
V , V , V
Power Supply
Current
Note 2
200
DD
CL1
CL2
I
f
f
= 1KH
= 400KHz
i
j
i
DD
2
3
EE
Note 1: V - S (V = V , V , V , V ; j = 1 to 40) equivalent circuit.
1Kmax.
Vi
1Kmax.
Power
Switch
Data
Sj
Swtich
Note 2: Input/output current is excluded. When the input is at the intermediate level with CMOS, some excessive current
will flow through the input circuit to the power supply. To avoid this, the input level must be fixed at a high or low
state.
4
NT3882
AC Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25 C)
Symbol
Parameter
Data Shift Frequency
Terminal
CL2
Min.
-
Typ.
Max.
Unit
KHz
ns
-
-
-
-
-
-
-
-
-
400
CL2
f
Clock Width
High
Low
CL1, CL2
CL2
800
800
300
300
500
500
-
-
CWH
t
-
ns
CWL
t
Data Hold Time
DL1, DL2
DL1, DL2
CL1, CL2
CL1, CL2
CL1, CL2
-
-
ns
DH
t
Data Set-up Time
-
-
ns
SUD
t
ns
SUC1
SUC2
Clock Set-up Time (CL2
Clock Set-up Time (CL1
Clock Rise/Fall Time
Data Delay Time
CL1)
CL2)
t
t
-
ns
200
500
ns
CL
t
75
ns
PD
t
Timing Waveforms
V
IH
t
CWL
CL2
V
IL
t
t
t
CL
CL
CWH
t
DH
t
t
SUC1
SUD
DL1,DL2
DR1,DR2
t
PD
V
OH
OL
V
t
SUC2
t
SUC2
CL1
t
t
CL
CWH
t
CL
5
NT3882
Application Circuit (for reference only)
LCD PANEL
C1
-
C16
S1
-
S40
S1
-
S40
S1
-
S40
D
DL1
CL2
DR2
DL2
DL1
CL2
CL1
M
DR2
DL2
DR1
NT3882
NT3882
CL1
M
DR1
V
DD
V
DD
2
3
EE
V
GND
V
V
GND
V
2
V
3
VEE
CL2
CL1
M
NT3881D
V
DD
GND
V
1
V
V
2
3
V
V
4
5
VR
R
R
R
R
R
C
C
C
C
C
GND or other
negative voltage
6
NT3882
Bonding Diagram
S
2
9
S
3
4
S
3
3
S
3
2
S
3
1
S
3
0
S
3
5
S
3
6
S
3
7
S
3
8
S
3
9
S
4
0
2
63
62
61
60
59
57
56
55
54
53
52
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
3
4
51
48
V
V
2
3
5
NT3882H
6
46
42
VEE
M
7
8
Y
40
39
DR2
DL2
9
2514
m
10
11
12
13
14
15
16
17
18
X
(0,0)
38
37
DR1
DL1
36
35
34
32
GND
CL2
CL1
S1
25
19
20
21
22
23
24
27
28
29
30
31
S
1
2
S
9
S
1
0
S
1
1
S
8
S
7
V
S
6
S
5
S
4
S
3
S
2
D
D
m
2235
* Connecting IC substrate to VDD or keeping floating is
recommended.
* Pad window area120 m X 100 m.
7
NT3882
Bonding Dimensions
unit:
Y
m
Pad No.
Designation
X
Y
Pad No.
29
Designation
S4
X
2
3
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
-729
-985
-985
-985
-985
-985
-985
-985
-985
-985
-985
-985
-985
1148
1125
975
825
675
525
375
225
75
621
771
921
985
985
985
985
985
985
985
985
985
985
-1148
-1148
-1148
-859
-705
-555
-373
-204
-54
30
S3
4
31
S2
5
32
S1
6
34
CL1
CL2
GND
DL1
DR1
DL2
DR2
M
7
35
8
36
9
37
10
11
12
13
14
38
-75
39
96
-225
-375
-525
40
246
42
396
46
562
VEE
V3
15
16
S16
S15
-985
-985
-675
-825
48
51
985
985
722
882
V2
17
18
19
20
21
22
23
24
25
S14
S13
S12
S9
-985
-985
-729
-579
-429
-279
-129
21
-975
52
53
54
55
56
57
59
60
61
S40
S39
S38
S37
S36
S35
S30
S31
S32
921
771
621
471
321
171
21
1148
1148
1148
1148
1148
1148
1148
1148
1148
-1125
-1148
-1148
-1148
-1148
-1148
-1148
-1090
S10
S11
S8
S7
-129
-279
171
VDD
S6
27
28
321
471
-1148
-1148
62
63
S33
S34
-429
-579
1148
1148
S5
Ordering Information
Part No.
NT3882H
NT3882F
Package
CHIP FORM
64L QFP
8
NT3882
Package Information
QFP 64L Outline Dimensions
unit: inches/mm
y
Symbol
Dimensions in inches
0.130 Max.
Dimensions in mm
3.30 Max.
A
A1
A2
0.004 Min.
0.10 Min.
0.112 ± 0.005
2.85 ± 0.13
b
0.016 +0.004
-0.002
0.40 +0.10
-0.05
c
0.006 +0.004
-0.002
0.15 +0.10
-0.05
D
E
0.551 ± 0.005
0.787 ± 0.005
0.039 ± 0.006
0.693 NOM.
0.929 NOM.
0.740 ± 0.012
0.976 ± 0.012
0.047 ± 0.008
0.095 ± 0.008
0.006 Max.
14.00 ± 0.13
20.00 ± 0.13
1.00 ± 0.15
17.60 NOM.
23.60 NOM.
18.80 ± 0.31
24.79 ± 0.31
1.19 ± 0.20
2.41 ± 0.20
0.15 Max.
e
GD
GE
HD
HE
L
L1
y
0 ~ 12
0 ~ 12
Notes:
1. Dimensions D & E do not include resin fins.
D
E
2. Dimensions G & G are for PC Board surface mount pad pitch
design reference only.
9
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