NT3883H [ETC]
Dot Matrix LCD 80-Channel Driver; 点阵LCD 80通道驱动器
| 型号： | NT3883H |
| 厂家： | 
ETC |
| 描述： | Dot Matrix LCD 80-Channel Driver |
| 文件： | 总12页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NT3883
Dot Matrix LCD 80-Channel Driver
Features
Provides 80-channel LCD driver
DD
EE
LCD driving voltage range (V - V ): 3.5V to 11V
Internal serial to parallel conversion circuits:
40-bit bi-direction shift register
80-bit latch
80-bit 4-level driver
Applicable LCD duty cycle: 1/2 to 1/16
2
Interfaces with a NT3881B/C/D LCD controller
LCD bias voltage can be supplied externally
Available in 100-pin QFP and in CHIP FORM
1
1
Logic circuit supply voltage range: 4.5V - 5.5V
General Description
as NT3881B/C/D, to parallel data and outputs LCD driving
waveforms to drive LCD. Expansion of character-type
liquid crystal display can be easily obtained according to
the number and structure of characters.
The NT3883 is a dot matrix LCD 80-channel driver
fabricated by low power CMOS technology. This IC
consists of two 40-bit bi-directional shift registers, 80-bit
latch and 80-bit 4-level LCD driver. The NT3883 converts
serial data that are received from the LCD controller, such
Pin Configuration
S
3
1
S
3
2
S
3
3
S
3
4
S
3
5
S
3
6
S
3
7
S
3
8
S
3
9
S
4
0
S
8
0
S
7
9
S
7
8
S
7
7
S
7
6
S
7
5
S
7
4
S
7
3
S
7
2
S
7
1
100 99 98 97
95 94 93 92 91 90 89 88
86 85 84 83 82 81
87
96
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NT3883F
S8
S7
S6
S5
S4
S3
S2
S1
31 32 33 34
36 37 38 39 40 41 42 43
45 46 47 48 49 50
44
35
N
C
V
V
V
V
G
N
D
C
L
1
S
L
1
S
L
2
N
C
N
C
N
C
C
L
2
D
L
1
D
R
1
D
L
2
D
R
2
M
N
C
N
C
E
E
D
D
3
2
1
V2.1 November, 1999
NT3883
Pad Configuration
S
7
8
S
7
6
S
3
9
S
4
0
S
7
9
S
7
7
S
7
5
S
7
4
S
3
8
S
8
0
S
7
3
S
7
2
S
3
5
S
3
7
S
3
2
S
3
4
S
3
6
S
3
3
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
100
1
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82
81
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
80
79
78
77
76
75
74
73
2
3
4
5
6
7
8
9
72
71
70
69
68
10
11
12
13
14
15
16
17
18
19
20
21
67
66
65
64
NT3883H
63
62
61
60
59
58
57
56
55
54
22
23
24
S8
S7
S6
25
26
27
28
29
30
S5
S4
53
52
51
S3
S2
31
V
36
47
S1
33
V
34
35
37 38
39
43 44
45
46
48
M
D
R
2
G
N
D
V
3
V
2
G
L
S
L
1
S
L
2
C
L
2
D
L
1
D
R
1
D
L
2
E
E
D
D
1
2
NT3883
Block Diagram
S1
S2
S39
S40
S41
S42
S79
S80
V
DD
V
V
2
3
80-Bit 4-Level LCD Drivers
V
EE
M
80-Bit Latch
CL1
DL2
CL2
First
40-Bit Shift Register
Second
40-Bit Shift Register
DR2
SL1
SL2
DR1 DL2
GND
3
NT3883
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
Power Supply Voltage (VDD-GND) . . . . . . -0.3V to 7.0V
Power Supply Voltage (VDD-VEE) . . . . . . . . . . . . . . . . . .
DD
DD
. . . . . . . . . . . . . . . . . . . . . .V - 13.5V to V + 0.3V
DD
Input Voltage . . . . . . . . . . . . . . -0.3V to V + 0.3V
Operating Temperature . . . . . . . . . . -20 C to + 75 C
Storage Temperature . . . . . . . . . . . . . -55 C to + 125 C
DC Electrical Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25 C)
Parameter
Symbol
Terminal
Min.
Typ.
Max.
Unit
V
Conditions
Input Voltage
CL1, CL2,
DL1, DL2
*1
-
-
IH
V
DD
0.7 V
DD
V
0
V
IL
V
DD
0.3 V
Output Voltage
DR1, DR2
*1
-
-
V
OH
V
DD
V
OH
- 0.4
I
= -0.4mA
-
-
-
-
-
-
0.4
1.1
1.5
5
V
V
V
A
OL
OL
ON
ON
V
I
I
I
= +0.4mA
Vi - Sj Voltage
Descending
*2
D1
V
= 0.1mA for one of Sj
= 0.05mA for each of Sj
-
D2
V
Input Leakage
Current
CL1, CL2
DL1,
-5
IL
VIN = 0 or VDD
I
DL2*1
Vi Leakage
Current
-10
-
-
-
10
S1 to S80 open
VL
2
3
EE
A
A
I
V , V , V
Power Supply
Current
*3
500
DD
CL1
CL2
I
f
f
= 1KHz
= 1MHz
Note *1: SL1 and SL2 determine The Input or Output of DL1, DL2, DR1 and DR2 and the configuration is as follows.
Terminal
DL1
SL1 = High
SL1 = Low
SL2 = High
SL2 = Low
Output
Input
-
-
-
-
DR1
Input
Output
DL2
-
-
-
-
Output
Input
Input
Output
DR2
*2: Vi – Sj (Vi = VDD, V2, V3, VEE; j = 1 to 80) equivalent circuit (for reference)
*3: Input/output current is excluded. When the input is at the intermediate level with CMOS, some excessive
1Kmax.
10Kmax.
Vi
Power
Switch
Data
Sj
Swtich
Current will flow through the input circuit to power supply. To avoid this, the input level must be fixed at high or
low state.
4
NT3883
AC Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25 C)
Symbol
Terminal
Min.
Typ.
Max.
Unit
Parameter
Data Shift Frequency
Clock Width
fCL2
tCWH
tCWL
tDH
CL2
CL1, CL2
CL2
-
-
-
-
-
-
-
400
KHz
ns
High
Low
800
800
300
300
500
-
-
-
-
-
ns
Data Hold Time
DL1~2, DR1~2
DL1~2, DR1~2
CL1, CL2
ns
Data Set-up Time
tSUD
tSUC1
ns
ns
Clock Set-up Time(CL2 CL1)
Clock Set-up Time(CL1 CL2)
Clock Rise/Fall Time
tSUC2
CL1, CL2
500
-
-
ns
tCL
tPD
CL1, CL2
-
-
-
-
-
200
500
ns
ns
Data Delay Time
Timing Waveforms
V
IH
t
CWL
CL2
V
IL
t
t
t
CL
CWH
CL
t
DH
t
SUD
t
SUC1
DL1, DL2
t
PD
V
V
OH
OL
DR1, DR2
t
SUC2
t
SUC2
CL1
t
t
CL
CWH
t
CL
5
NT3883
Pin and Pad Descriptions
Pin No.
Pad No.
Designation
I/O
External
Description
Connection
1~30,
51~100
1~30,
51~100
S1~S30,
S80~S31
O
LCD panel
Segment signal output pins
33
36
37
38
33
36
37
38
VDD
GND
CL1
SL1
P
P
I
Power supply
Power supply
Controller
MPU
Power for logic circuits
0V
Clock to latch serial data
I
Shift left control for 1st 40-bit shift register
(see NOTE*4)
39
39
SL2
I
MPU
Shift left control for 1st 40-bit shift register
(see NOTE*4)
43
44
43
44
CL2
DL1
I
Controller
Clock to shift serial data
I/O
Controller or
NT3882A/NT3
883
Data input/output of 1st 40-bit shift register
(see NOTE*4)
45
46
47
48
45
46
47
48
DR1
DL2
DR2
I/O
I/O
I/O
Controller or
NT3882A/NT3
883
Data input/output of 1st 40-bit shift register
(see NOTE*4)
Controller or
NT3882A/NT3
883
Data input/output of 2nd 40-bit shift register
(see NOTE*4)
Controller or
NT3882A/NT3
883
Data input/output of 2nd 40-bit shift register
(see NOTE*4)
M
VEE, V3, V2
NC
I
P
-
Controller
Alternate signal for LCD drivers
Power for LCD drivers
No connection
31, 34, 35 31, 34, 35
Power supply
-
32, 40,
41, 42,
49,50
-
NOTE *4: Relation of SL1, SL2, DL1, DR1, DL2 and DR2
SL1
SL2
Shift Direction
Left(S40 to S1)
Right(S1 to S40)
Left(S80 to S41)
Right(S41 to S80)
DR1
DL2
DR2
DL1
1(High)
-
Output
Input
-
-
-
-
0(Low)
-
Input
Output
-
-
1(High)
0(Low)
-
-
-
-
Output
Input
Input
Output
6
NT3883
Functional Description
NT3883 is a dot matrix LCD segment driver LSI. It
operates with the controller, such as NT3881B/C/D,
and/or another segment driver LSI NT3882A/3883.
NT3883 receives serial data from the controller or
another NT3883, converts it to parallel data and then
supplies the LCD driving waveforms to the LCD panel.
5. DL2
Data input/output of the 41st - 80th register. When SL2 is
connected to GND, the data from LCD controller is fed
into the 41st - 80th register through DL2 serially. If SL2 is
connected to VDD, the DL2 becomes the output of the
41st - 80th register.
1. CL1
6. DR2
This signal is used for latching the shift register contents.
When CL1 is set at high, the shift register contents are
transferred to the 80-bit 4level LCD driver. When CL1 is
set at low, the last display output data (S1 to S80) is
held.
Data input/output of the 41st - 80th register. When SL2 is
connected to GND, the 80th bit of the 41st - 80th register
output from DR2. By connecting DR2 to DL1 of next
NT3882A/3883, the cascade structure is obtained to
drive a wider LCD panel. If SL2 is connected to VDD, the
DR2 becomes the input of the 41st - 80th register, in this
case, the data may come from the next NT3882A/3883.
2. CL2
Clock pulse inputs for the two 40-bit shift registers. The
data is shifted to an 80-bit latch at the falling edge of
CL2. The clock signal CL2 must be active when
operating to refresh shift registers' contents.
7. SL1
The shift direction of S1 to S40, i.e. 1st to 40th shift
register, is selected by SL1. The detail function
description is listed in Note*4 of Page5.
3. DL1
Data input/output of the 1st - 40th register. When SL1 is
connected to GND or open, the data from LCD controller
is fed into the 1st - 40th register through DL1 serially. If
SL1 is connected to VDD, the DL1 becomes the output of
the 1st - 40th register.
8. SL2
The shift direction of S41 to S80, i.e. 41st to 80th shift
register, is selected by SL2. The detail function
description is listed in Note*4 of Page5.
9. S1 to S80
4. DR1
LCD driver output pins. These 80 bits represent the 80
Data input/output of the 1st - 40th register. When SL1 is
connected to GND, the 20th bit of the 1st - 40th register
output from DR1. By connecting DR1 to DL2, two 40-bit
shift registers cascaded to one 80-bit shift register. If
SL1 is connected to VDD, the DR1 becomes the input of
the 1st - 40th register, in this case, the data may come
from DL2.
DD
2
3
data bits in the 80-bit latch and one of V , V , V and
EE
V
is selected as a LCD driving voltage source
according to the combination of latched data level and
the alternate signal (M). The truth table is listed as
follows:
Latched Data
1(High)
M
Output Level of S1 to S80
1(High)
0(Low)
1(High)
0(Low)
VEE
VDD
V3
(Selected)
0(Low)
(Non-selected)
V2
7
NT3883
Application Circuit (for reference only)
20 Chars x 4 Lines LCD PANEL
C1
-
C16
S1
-
S40
S1
-
S80
S1
-
S80
D
D L 1
C L 2
D R 2
D L 2
D L 1
C L 2
C L 1
M
D R 2
D L 2
NT3883
NT3883
C L 1
M
D R 1
D R 1
V
DD
V
DD
G N D
V
2
V
3
VEE
2
3
EE
V
G N D
V
V
C L 2
C L 1
M
NT3881D
V
DD
G N D
V
1
V
V
2
3
V
V
4
5
V R
R
R
R
R
R
C
C
C
C
C
GND or other
negative voltage
8
NT3883
Bonding Diagram
S
3
2
S
3
3
S
3
4
S
3
5
S
3
6
S
3
7
S
3
8
S
3
9
S
4
0
S
8
0
S
7
9
S
7
8
S
7
7
S
7
6
S
7
5
S
7
4
S
7
3
S
7
2
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82
81
80
79
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
1
2
78
77
76
75
3
4
5
6
74
73
72
71
70
69
68
7
8
9
10
11
NT3883H
3940
m
12
13
14
15
16
17
18
19
20
21
22
67
66
65
64
Y
63
62
61
60
X
(0,0)
59
58
57
56
55
54
S8
23
24
25
26
27
28
29
30
S7
S6
S5
S4
53
52
51
S3
S2
31
36
47
S1
33
34
35
37
38
39
43
44
45
46
48
M
D
R
2
G
N
D
V
E
E
V
D
D
V
3
V
2
G
L
1
S
L
1
S
L
2
C
L
2
D
L
1
D
R
1
D
L
2
2590
m
DD
* Connecting IC substrate to V or keeping floating is recommended.
* Pad window area 100 m
100 m.
9
NT3883
Bonding Dimensions
unit:
Y
m
Pad No.
1
Designation
X
Y
Pad No.
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Designation
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
X
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1194
-1184
-945
1677
1557
1437
1317
1197
1077
957
837
717
597
477
357
237
117
-2
-122
-242
-362
-482
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1195
1185
995
-1442
-1311
-1202
-1082
-962
-842
-722
-602
-482
-362
-242
-122
-2
117
237
357
477
597
717
837
957
1077
1197
1317
1437
1557
1677
1811
1821
1821
1821
1821
1821
1821
1821
1821
1821
1821
1821
1821
1821
1821
1821
1821
1821
1821
1811
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
39
43
44
45
46
47
48
51
52
53
-602
-722
-842
-962
S8
S7
S6
S5
S4
S3
S2
S1
-1082
-1202
-1322
-1442
-1562
-1682
-1812
-1822
-1822
-1822
-1822
-1822
-1822
-1822
-1822
-1822
-1822
-1822
-1822
-1822
-1822
-1812
-1682
-1562
875
755
635
515
395
275
155
35
VEE
VDD
V3
-807
-670
-520
-353
-204
-54
95
245
395
545
695
845
V2
GND
CL1
SL1
SL2
CL2
DL1
DR1
DL2
DR2
M
-84
-204
-324
-444
-564
-684
-805
-925
-1045
-1184
995
S41
S42
S43
1185
1195
1195
10
NT3883
Ordering Information
Part No.
NT3883H
NT3883F
Package
CHIP FORM
100L QFP
11
NT3883
Package Information
QFP 100L Outline Dimensions
unit: inches/mm
HD
D
80
65
1
64
24
41
25
b
40
e
GD
GD
See Detail F
Seating Plane
L
y
L
1
Detail F
Symbol
Dimensions in inches
0.130 Max.
Dimensions in mm
3.30 Max.
A
A1
A2
0.004 Min.
0.10 Min.
0.112±0.005
2.85±0.13
b
0.014 +0.004
-0.002
0.35 +0.10
-0.05
c
0.006 +0.004
-0.002
0.15 +0.10
-0.05
D
E
0.551±0.005
0.787±0.005
0.031±0.006
0.693 NOM.
0.929 NOM.
0.740±0.012
0.976±0.012
0.047±0.008
0.095±0.008
0.006 Max.
0 ~ 12
14.00±0.13
20.00±0.13
0.80±0.15
17.60 NOM.
23.60 NOM.
18.80±0.31
24.79±0.31
1.19±0.20
2.41±0.20
0.15 Max.
0 ~ 12
e
GD
GE
HD
HE
L
L1
y
Notes:
1. Dimensions D & E do not include resin fins.
D
E
2. Dimensions G & G are for PC Board surface mount pad pitch
design reference only
12
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