NT3967_技术文档

NT3967

TFT LCD Source Driver

Features

nOutput: 402 output channels

nPower for interface circuit: 2.5~3.6V

n6-bitresolution /64 gray scales

nDot inversion with polarity control

nOperating frequency: 65MHz

nOutput deviation: 10 ~ 20mV

nV1 ~ V10 for adjusting Gamma correction

nPower for analog circuit: 6.5 ~ 10 V

nOutput dynamic range: 0.1 ~ AVDD-0.1V

nPower consumption of analog circuit: 3 mA

nData inversion for reducing EMI

nCascade function with bi-direction shift control

nCMOS silicon gate ( p-type substrate )

nTCP package

General Description

The NT3967 is a data driver IC for a color TFT LCD panel, SVGA(800*600) and UXGA(1600*1200) applications. For better

performance, dot inversion and a wide range voltage output are designed in this chip and for reducing EMI, data inversion

control is used. This chip supplies 10 sections of voltage-reference for Gamma correction.

Block diagram

OUT1

OUT3

OUT402

OUT2

OUT401

Out Driver Buffer ( 402 channels )

Digit to Analog Converter

10

POL

V1 ~ V10

REV1

6

Level Shift

6

D00 ~ D05

D10 ~ D15

D20 ~ D25

Decoder

18

Line Latch ( 402 X 6 bits X 2 )

LD

D30 ~ D35

D40 ~ D45

D50 ~ D55

1

67

REV2

DIO1

67-bit Shift Register

CLK

DIO2

Vcc GND

AVDD AVSS

SHL

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NT3967

TFT LCD Source Driver

NT3967 Padconfiguration (Face up): This figure does not specify the TCP package.

OUT402

OUT401

OUT400

OUT399

OUT398

DIO2

D55

D54

D53

D52

D51

D50

D45

D44

D43

D42

D41

D40

D35

D34

D33

D32

D31

D30

Vcc

SHL

V10

V9

V8

V7

V6

OUT206

Dummy

AVDD

AVSS

V5

V4

V3

18 pads

V2

V1

GND

CLK

Dummy

OUT205

LD

POL

REV1

REV2

D25

D24

D23

D22

D21

D20

D15

D14

D13

D12

D11

D10

D05

D04

D03

D02

D01

D00

DIO1

OUT5

OUT4

OUT3

OUT2

OUT1

Version 1.0

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NT3967

TFT LCD Source Driver

Pin Description

Description

Designation I/O

D05 ~ D00

D15 ~ D10

D25 ~ D20

Data input. For six 6-bit data,2 pixels, of color data (R, G, B)

DX5 : MSB; DX0 : LSB

I

D35 ~ D30

D45 ~ D40

D55 ~ D50

REV1

I

Controls whether the data of D00~D25 are inverted or not.

When “REV1”=1 these data will be inverted. EX. “00” à“ 3F”, “07” à“ 38”, “15” à“2A”, and so on.

Controls whether the data of D30~D55 are inverted or not, same as REV1.

Clock input; latching data onto the line latches at the rising edge.

Gamma correction reference voltage. The voltage of these pins must be AVSS< V10< V9<

V8<V7<V6; V5<V4<V3<V2<V1< AVDD

REV2

CLK

V1 ~ V10

I

OUT1 ~

OUT402

SHL

O

I

Output drive signals;

Selects left or right shift;

SHL=“1” : DIO1→OUT1,2,3,4,5,6→OUT7,8,9,10,11,12--→OUT397,398,399,400,401,402= DIO2

SHL=“0” : DIO1=OUT1,2,3,4,5,6←OUT7,8,9,10,11,12←-- OUT397,398,399,400,401,402←DIO2

SHL

DIO1

DIO2

SHIFT

1

0

Input

Output

Input

Right

Left

DIO1

DIO2

I/O Start pulse signal input/output

When SHL is applied high (SHL="1"), a start high-pulse on DIO1 is latched at the rising edge of the

CLK. Then the data are latched serially onto internal latches at the rising edge of the CLK. After all

line latches are filled with data, 67 clocks, a pulse is shifted out through the DIO2 pin at the rising

edge of the CLK. This function can cascade two or more devices for dot-size expansion. In normal

applications, the DIO2 signal of the first device is connected to the DIO1 of the second stage, the

DIO2 of the second one is connected to the DIO1 of the third, and so on, like a daisy chain.

In contrast, when SHL is applied low, a start pulse inputs on DIO2, and a pulse outputs through

DIO1.

*Remark: The input pulse-width of DIO1/2 may exceed 1 clock-cycle.

Latches the polarity of outputs and switches the new data to outputs.

1. At the rising edge, latches the “POL” signal to control the polarity of the outputs.

2. The pin also controls the switch of the line registersthat switches the new incoming data

to outputs.

*Remark: The LD may switch the new data to outputs at anytime even if the line data are not

completely full.

Polarity selector for the dot-inversion control. Available at the rising edge of LD

LD

I

POL

“POL” value is latched at the rising edge of “LD” to control the polarity of the even or odd outputs.

“POL=1” indicates that even outputs are of positive polarity with a voltage range from V1~V5, and

odd outputs are of negative polarity with a voltage range from V6 to V10. On the other hand, if LD

receives low level “POL”, even outputs are of negative polarity and odd outputs are of positive

polarity.

POL=1: Even outputs range from V1 ~ V5

Odd outputs range from V6 ~ V10

POL=0: Even outputs range from V6 ~ V10

Odd outputs range from V1 ~ V5

Power supply for analog circuit

Ground pin for analog circuit

Power supply for digital circuit

Ground pin for digital circuit

AVDD

AVSS

Vcc

GND

Dummy

I

-

Dummy pads

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DEC 7,2001

NT3967

TFT LCD Source Driver

Power on/off sequence:

This IC is a high-voltage LCD driver, soit may be damaged by a large current flow when an incorrect power sequence is used.

The recommend ed power on/off sequence is to first connect the logical power, Vcc & GND and then the drive power,

AVDD&AVSS with V1~V10 . When shutting off the power, first shut off the drive power and then the logic system, or turn off all

power simultaneously.

Relationship between the order of input data and output channels

(1) SHL=”1”, Start pulse from DIO1, shift right

Output

Order

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

- - -

--à

- - -

OUT402

Last data

D55~D50

First data

Data D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50

(2) SHL=”0”, Start pulse from DIO2, shift left

Output OUT397 OUT398 OUT399 OUT400 OUT401 OUT402

- - -

--à

- - -

OUT6

Last data

D55~D50

Order

First data

Data D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50

Relationship between input data and output voltage

The figure below shows the relationship between the input data and the output voltage with the polarity. The range of

V1~V5 is for positive polarity, and V6 ~ V10 for negative polarity. Please refer to the following page to get the relative re sistor

value and voltage calculation method.

Gamma correction diagram

Vout

AVDD

V1

V2

Positive polarity

V3

V4

V5

Vcom

V6

V7

V8

Negative polarity

V9

V10

AVSS

08H

00H

10H

18H

20H

28H

30H

38H

3FH

Remark:AVDD-0.1 > V1 > V2 > V3 > V4 > V5; V6> V7 > V8 > V9 > V10 >AVSS+0.1V

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NT3967

TFT LCD Source Driver

Gamma correction resistor

Name Resistor

V1, V10

V3, V8

R0

800

750

700

650

600

550

500

400

350

300

250

200

150

100

R32

R33

R34

R35

R36

R37

R38

R39

R40

R41

R42

R43

R44

R45

R46

R47

R48

R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

R59

R60

R61

R62

100

150

200

250

300

500

800

R1

R2

R3

R4

R5

R6

1.6K

R7

8.05K

R8

R9

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

R31

V2, V9

V4, V7

3.45K

2.75K

V5, V6

V3, V8

Total impedance, Rn=R0 ~ R62, equals 15.85K

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DEC 7,2001

NT3967

TFT LCD Source Driver

Output Voltage VS Input Data

Data

Output Voltage

( Positive polarity )

V1

V2 + ( V1 – V2) X 7250/8050

( Negative polarity )

V10

V10 + ( V9 – V10) X 800/8050

00H

01H

02H

V2 + ( V1 – V2) X 6500/8050

V10 + ( V9 – V10) X 1550/8050

V2 + ( V1 – V2) X 5800/8050

V2 + ( V1 – V2) X 5150/8050

V2 + ( V1 – V2) X 4550/8050

V2 + ( V1 – V2) X 4000/8050

V10 + ( V9 – V10) X 2250/8050

V10 + ( V9 – V10) X 2900/8050

V10 + ( V9 – V10) X 3500/8050

V10 + ( V9 – V10) X 4050/8050

03H

04H

05H

06H

V2 + ( V1 – V2) X 3450/8050

V2 + ( V1 – V2) X 2950/8050

V10 + ( V9 – V10) X 4600/8050

V10 + ( V9 – V10) X 5100/8050

07H

08H

V2 + ( V1 – V2) X 2450/8050

V2 + ( V1 – V2) X 2050/8050

V2 + ( V1 – V2) X 1650/8050

V2 + ( V1 – V2) X 1300/8050

V2 + ( V1 – V2) X 950/8050

V2 + ( V1 – V2) X 600/8050

V2 + ( V1 – V2) X 300/8050

V10 + ( V9 – V10) X 5600/8050

V10 + ( V9 – V10) X 6000/8050

V10 + ( V9 – V10) X 6400/8050

V10 + ( V9 – V10) X 6750/8050

V10 + ( V9 – V10) X 7100/8050

V10 + ( V9 – V10) X 7450/8050

V10 + ( V9 – V10) X 7750/8050

09H

0AH

0BH

0CH

0DH

0EH

0FH

V2

V9

10H

11H

V3 + (V2 – V3) X2450/2750

V9+ ( V8 – V9) X 300/2750

V3 + (V2 – V3) X 2200/2750

V3 + (V2 – V3) X 1950/2750

V3 + (V2 – V3) X 1700/2750

V3 + (V2 – V3) X 1500/2750

V9 + ( V8 – V9) X 550/2750

V9 + ( V8 – V9) X 800/2750

V9 + ( V8 – V9) X 1050/2750

V9 + ( V8 – V9) X 1250/2750

12H

13H

14H

15H

V3 + (V2 – V3) X 1300/2750

V3 + (V2 – V3) X 1100/2750

V9 + ( V8 – V9) X 1450/2750

V9 + ( V8 – V9) X 1650/2750

16H

17H

V3 + (V2 – V3) X 950/2750

V3 + (V2 – V3) X 800/2750

V3 + (V2 – V3) X 650/2750

V3 + (V2 – V3) X 500/2750

V9 + ( V8 – V9) X 1800/2750

V9 + ( V8 – V9) X 1950/2750

V9 + ( V8 – V9) X 2100/2750

V9 + ( V8 – V9) X 2250/2750

18H

19H

1AH

1BH

V3 + (V2 – V3) X 400/2750

V3 + (V2 – V3) X 300/2750

V9 + ( V8 – V9) X 2350/2750

V9 + ( V8 – V9) X 2450/2750

1CH

1DH

V3 + (V2 – V3) X 200/2750

V3 + (V2 – V3) X 100/2750

V3

V9 + ( V8 – V9) X 2550/2750

V9 + ( V8 – V9) X 2650/2750

V8

1EH

1FH

20H

21H

V4 + (V3 – V4) X 1500/1600

V8 + ( V7 – V8) X 100/1600

V4 + (V3 – V4) X 1400/1600

V4 + (V3 – V4) X 1300/1600

V4 + (V3 – V4) X 1200/1600

V4 + (V3 – V4) X 1100/1600

V4 + (V3 – V4) X 1000/1600

V4 + (V3 – V4) X 900/1600

V4 + (V3 – V4) X 800/1600

V8 + ( V7 – V8) X 200/1600

V8 + ( V7 – V8) X 300/1600

V8 + ( V7 – V8) X 400/1600

V8 + ( V7 – V8) X 500/1600

V8 + ( V7 – V8) X 600/1600

V8 + ( V7 – V8) X 700/1600

V8 + ( V7 – V8) X 800/1600

22H

23H

24H

25H

26H

27H

28H

V4 + (V3 – V4) X 700/1600

V4 + (V3 – V4) X 600/1600

V8 + ( V7 – V8) X 900/1600

V8 + ( V7 – V8) X 1000/1600

29H

2AH

V4 + (V3 – V4) X 500/1600

V4 + (V3 – V4) X 400/1600

V4 + (V3 – V4) X 300/1600

V4 + (V3 – V4) X 200/1600

V4 + (V3 – V4) X 100/1600

V8 + ( V7 – V8) X 1100/1600

V8 + ( V7 – V8) X 1200/1600

V8 + ( V7 – V8) X 1300/1600

V8 + ( V7 – V8) X 1400/1600

V8 + ( V7 – V8) X 1500/1600

2BH

2CH

2DH

2EH

2FH

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NT3967

TFT LCD Source Driver

Output Voltage VS Input Data (continued)

Data

Output Voltage

( Positive polarity )

( Negative polarity )

V4

V7

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

V5 + (V4 – V5) X 3350/3450

V5 + (V4 – V5) X 3250/3450

V5 + (V4 – V5) X 3150/3450

V5 + (V4 – V5) X 3050/3450

V5 + (V4 – V5) X 2950/3450

V5 + (V4 – V5) X 2800/3450

V5 + (V4 – V5) X 2650/3450

V5 + (V4 – V5) X 2500/3450

V5 + (V4 – V5) X 2300/3450

V5 + (V4 – V5) X 2100/3450

V5 + (V4 – V5) X 1850/3450

V5 + (V4 – V5) X 1600/3450

V5 + (V4 – V5) X 1300/3450

V5 + (V4 – V5) X 800/3450

V5

V7 + ( V6 – V7) X 100/3450

V7 + ( V6 – V7) X 200/3450

V7 + ( V6 – V7) X300/3450

V7 + ( V6 – V7) X 400/3450

V7 + ( V6 – V7) X 500/3450

V7 + ( V6 – V7) X 650/3450

V7 + ( V6 – V7) X 800/3450

V7 + ( V6 – V7) X 950/3450

V7 + ( V6 – V7) X 1150/3450

V7 + ( V6 – V7) X 1350/3450

V7 + ( V6 – V7) X 1600/3450

V7 + ( V6 – V7) X 1850/3450

V7 + ( V6 – V7) X 2150/3450

V7 + ( V6 – V7) X 2650/3450

V6

Version 1.0

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NT3967

TFT LCD Source Driver

Absolute Maximum Ratings*

*Comments

Digital supply voltage, Vcc

Analog supply voltage, AVDD

Supply voltage, V1~ V10

Digital input voltage

Output voltage, DIO1 & DIO2

Output voltage,OUT1~OUT420 -0.5V to AVDD+0.5V

Storage temperature

-0.5V to 5V

-0.5V to +11V

-0.3 ~AVDD+0.3

-0.5V to Vcc+0.5V

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

These are stress ratings only. Functional operation of this

device at these or under any other conditions above those

indicated in the operational sections of this specificationare

not implied and exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

℃

-55 to 100

Operating temperature

-10℃ to 75℃

DC Electrical Characteristics (Vcc =2.5~3.6V , AVDD=6.5~10V, AVSS=GND=0V, TA=-10℃~75℃)

(For the digital circuit)

Parameter

Supply Voltage

Symbol

Vcc

Min.

2.5

Typ.

-

Max.

3.6

Unit

V

Conditions

Digital power

Low Level Input Voltage

High Level Input Voltage

High Level Output Voltage

Vil

Vih

Voh

0

-

0.3xVcc

Vcc

-

V

For the digital circuit

DIO1/2, Ioh=500uA

0.7xVcc

Vcc-0.3V

Low Level Output Voltage

Input Leakage Current

Vol

Ii

-

GND+0.3V

+1

V

mA

DIO1/2, Iol=-500uA

For the digital circuit

Digital Stand-by current

Digital Operating Current

Ist

Icc

-

3

50

5

CLK is stopped, DIO1/2 No load

mA Fclk=40 MHz, FLD=50KHz

mA

(For the analog circuit)

Parameter

Supply Voltage

Input level of V1 ~ V5

Input level of V6 ~ V10

Voltage Output Deviation

Symbol

AVDD

Vref

Vvd

Min.

6.5

0.4AVDD

Typ.

8.4

-

Max.

10

AVDD-0.1

0.6AVDD

+25

Unit

V

mV

Conditions

For the analog circuit power

Gamma correction voltage

Vo=0.1V ~ 1.5V & AVDD-1.5 ~ AVDD-

0.1V

0.1

-

+20

+10

-

+20

mV

V

Vo=1.5V ~ AVDD-1.5V

Voltage Output Offset

Dynamic Range of Output

Sinking Current of outputs

Voc

Vdr

IOL

0.1

-150

AVDD-0.1

-

OUT1 ~ OUT402

OUT1 ~ OUT402; Vo=0.1V V.S 1.1V

-180

mA

Driving Current of outputs

Impedance of Gamma

Correction

IOH

Ri

150

0.8*Rn

200

Rn

-

OUT1 ~ OUT402; Vo=9.9V V.S 8.9V

Rn=15850 ohm, from V1 ~ V5 & V6~V10

mA

ohm

1.3*Rn

Analog Operating Current

IDD

-

3

6

mA

No load, Fclk=33MHz, FLD=50KHz

Version 1.0

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DEC 7,2001

NT3967

TFT LCD Source Driver

AC Electrical Characteristics 1 (Vcc =3.0~3.6V , AVDD=6.5~10V, AVSS=GND=0V, TA= -10~75℃)

Parameter

CLK frequency

CLK period cycle

CLK pulse width

Data set-up time

Data hold time

Symbol

Fclk

Tcph

Tcw

Tsu

Thd

Min.

-

15

6

4

2

Typ.

Max.

65

-

Unit

Mhz

ns

Conditions

-

D00 ~ D55, REVx and DIO1/2 to CLK

CL=25pF ( Output )

-

11

ns

Propagation delay of DIO2/1

Tphl

6

Time that the last data to LD

Pulse width of LD

Tld

Twld

1

2

-

Tcph

Time that LD to DIO1/2

POL set-up time

POL hold time

Tlds

Tpsu

Tphd

Tst

2

6

-

Tcph

ns

POL to LD

96% final value or below with 30mV

precision , CL=75pF, R=5K ohm

Output stable time

4.5

9

us

Output loading

CL

-

pF

For OUT1 ~ OUT402

75

AC Electrical Characteristics 2 (Vcc =2.5~3.0V , AVDD=6.5~10V, AVSS=GND=0V, TA= -10~75℃)

Parameter

CLK frequency

Symbol

Fclk

Min.

-

Typ.

-

Max.

45

Unit

Mhz

Conditions

CLK period cycle

CLK pulse width

Data set-up time

Tcph

Tcw

Tsu

22

8

6

-

ns

D00 ~ D55, REVx and DIO1/2 to CLK

Data hold time

Propagation delay of DIO2/1

Thd

Tphl

2

-

15

ns

D00 ~ D55, REVx and DIO1/2 to CLK

CL=25pF ( Output )

Time that the last data to LD

Pulse width of LD

Time that LD to DIO1/2

POL set-up time

POL hold time

Output stable time

Tld

Twld

Tlds

Tpsu

Tphd

Tst

1

2

6

-

Tcph

ns

us

POL to LD

-

4.5

9

96% final value or below with 30mV

precision , CL=75pF, R=5K ohm

For OUT1 ~ OUT402

Output loading

CL

-

pF

75

Version 1.0

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DEC 7,2001

NT3967

TFT LCD Source Driver

Timing Diagram

Tcph

66

67

CLK

Tcw Tcw

Tsu Thd

DIO1/2

( Input )

Tsu Thd

First data

Data,

REVx

Second data

Last data

Tphl

DIO1/2

( Output )

CLK

LD

Last

Tld

Twld

Tlds

DIO1/2

( Input )

LD

TpsuTpdh

POL

Positive

96%

Odd outputs

96%

High-Z

Even outputs

Negative

High-Z

Tst

Output load condition :

1K

Output

15P

Vcom

Version 1.0

10

DEC 7,2001

NT3967

TFT LCD Source Driver

Function operation

CLK

2CLK ( min.)

DIO1/2

( Input )

1CLK ( min.)

LD

1CLK

Data,

N-2

N-1

N

1

2

3

REVx

Last Data

First Data

LD

POL

V1 ~V5

Vcom

Odd Outputs

Even Outputs

V6 ~V10

V1 ~V5

V6 ~V10

Version 1.0

11

DEC 7,2001


型号：	NT3967
厂家：	ETC
描述：	TFT LCD Source Driver TFT LCD源极驱动器驱动器 CD
文件：	总11页 (文件大小：98K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NT3967 [ETC]

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