ISPLSI3320-70LM [ETC]
;
ETC 
®
ispLSI 3320
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 160 I/O Pins
— 14000 PLD Gates
Output Routing Pool (ORP)
G3 G2 G1 G0
Output Routing Pool (ORP)
Boundary
Scan
F3
F2
F1
F0
— 480 Registers
H0
H1
H2
E3
E2
E1
D
Q
Q
Q
Q
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
D
D
D
OR
Array
Twin
GLB
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 100 MHz Maximum Operating Frequency
— tpd = 10 ns Propagation Delay
H3
E0
D
D
D
D
Q
Q
Q
Q
OR
D3
D2
D1
I0
I1
I2
Array
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
D0
I3
• ispLSI FEATURES:
J0
J1
J2
C3
C2
C1
— 5V In-System Programmable (ISP™) Using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
Global Routing Pool
(GRP)
— Reprogram Soldered Devices for Faster Debugging
J3
C0
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
A0
A1
A2
A3
B0
B1
B2
B3
Output Routing Pool (ORP)
Output Routing Pool (ORP)
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
0139/3320
Description
The ispLSI 3320 is a High-Density Programmable Logic
Device containing 480 Registers, 160 Universal I/O pins,
five Dedicated Clock Input Pins, ten Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3320 features 5V in-system pro-
grammability and in-system diagnostic capabilities. The
ispLSI 3320 offers non-volatile reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems.
— Enhanced Pin Locking Capability
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Pin Compatible with ispLSI 3160
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
The basic unit of logic on the ispLSI 3320 device is the
TwinGenericLogicBlock(TwinGLB)labelledA0,A1...J3.
There are a total of 40 of these Twin GLBs in the ispLSI
3320 device. Each Twin GLB has 24 inputs, a program-
mable AND array and two OR/Exclusive-OR Arrays, and
eight outputs which can be configured to be either com-
binatorial or registered. All Twin GLB inputs come from
the GRP.
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright©1999LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 1999
3320_06
1
Specifications ispLSI 3320
Functional Block Diagram
Figure 1. ispLSI 3320 Functional Block Diagram
Input Bus
Input Bus
Input Bus
TDI/SDI
TOE
Boundary
Scan
Output Routing Pool (ORP)
J3
J2 J1 J0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
H3
H2 H1 H0
TRST
TDO/SDO
I3
I2
I1
I0
I/O 111
I/O 110
I/O 109
I/O 108
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
A2
A3
G3
G2
G1
G0
I/O 4
I/O 5
I/O 6
I/O 7
I/O 107
I/O 106
I/O 105
I/O 104
I/O 8
I/O 9
I/O 10
I/O 11
I/O 103
I/O 102
I/O 101
I/O 100
I/O 12
I/O 13
I/O 14
I/O 15
I/O 99
I/O 98
I/O 97
I/O 96
Global Routing Pool
(GRP)
I/O 16
I/O 17
I/O 18
I/O 19
I/O 95
I/O 94
I/O 93
I/O 92
B0
B1
B2
B3
F3
F2
F1
F0
I/O 20
I/O 21
I/O 22
I/O 23
I/O 91
I/O 90
I/O 89
I/O 88
I/O 24
I/O 25
I/O 26
I/O 27
I/O 87
I/O 86
I/O 85
I/O 84
I/O 28
I/O 29
I/O 30
I/O 31
I/O 83
I/O 82
I/O 81
I/O 80
C0
C1
C2
C3
D0
D1
D2
D3
E0
E1
E2
E3
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Input Bus
RESET
0139/3320
2
Specifications ispLSI 3320
Description (continued)
Clocks in the ispLSI 3320 device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.
All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 160 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorialinput,aregisteredinput,alatchedinput,an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
The table below lists key attributes of the device along
with the number of resources available.
An additional feature of the ispLSI 3320 is the Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device’s input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.
The 160 I/O cells are grouped into ten sets of 16 bits.
Each of these I/O groups is associated with a logic
MegablockthroughtheuseoftheORP. EachMegablock
is able to provide one Product Term Output Enable
(PTOE) signal which is globally distributed to all I/O cells.
ThatPTOEsignalcanbegeneratedwithinanyGLBinthe
Megablock. Each I/O cell can select one of 12 available
OEs (two Global OEs and ten PTOEs).
The ispLSI 3320 supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.
Key Attributes of the ispLSI 3320
Attribute
Quantity
Twin GLBs
Registers
I/O Pins
40
480
160
5
Four Twin GLBs, 16 I/O cells and one ORP are con-
nected together to make a logic Megablock. The
Megablockisdefinedbythe resourcesthatitshares. The
outputs of the four Twin GLBs are connected to a set of
16 I/O cells by the ORP. The ispLSI 3320 Device
contains ten of these Megablocks.
Global Clocks
Global OE
Test OE
2
1
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equal-
ized to minimize timing skew and logic glitching.
Table 1-0003/3320
3
Specifications ispLSI 3320
1
Absolute Maximum Ratings
Supply Voltage V ................................................................................ -0.5 to +7.0V
cc
Input Voltage Applied..................................................................... -2.5 to V +1.0V
CC
Off-State Output Voltage Applied .................................................. -2.5 to V +1.0V
CC
Storage Temperature............................................................................. -65 to 150°C
Case Temp. with Power Applied ........................................................... -55 to 125°C
Max. Junction Temp. (T ) with Power Applied (208-Pin PQFP and MQFP) ....150°C
J
Max. Junction Temp. (T ) with Power Applied (320-Ball BGA) ........................140°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
MIN.
0
MAX.
70
UNITS
Ambient Temperature
Supply Voltage
°C
V
T
A
4.75
0
5.25
0.8
V
V
V
CC
Input Low Voltage
Input High Voltage
V
IL
2.0
VCC +1
V
IH
Table 2-0005/3320
Capacitance (TA=25°C,f=1.0 MHz)
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
CC= 5.0V, VI/O = 2.0V
VCC= 5.0V, VY = 2.0V
10
pf
V
I/O Capacitance
C1
C2
11
pf
Clock Capacitance
Table 2-0006/3320
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
MAXIMUM
UNITS
Years
Cycles
20
–
–
ispLSI Erase/Reprogram Cycles
10000
Table 2-0008/3320
4
Specifications ispLSI 3320
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
≤ 3 ns 10% to 90%
1.5V
+ 5V
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
R
1
1.5V
Device
Output
Test
Point
See Figure 2
Table 2-0003/3320
3-state levels are measured 0.5V from
steady-state active level.
R
2
C *
L
Output Load conditions (See Figure 2)
*
C includes Test Fixture and Probe Capacitance.
L
0213A
TEST CONDITION
R1
470Ω
∞
R2
CL
A
B
390Ω
390Ω
390Ω
35pF
35pF
35pF
Active High
Active Low
470Ω
Active High to Z
∞
390Ω
390Ω
5pF
at VOH-0.5V
C
Active Low to Z
at VOL+0.5V
470Ω
5pF
Table 2 - 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
CONDITION
IOL= 8 mA
MIN.
–
TYP. MAX. UNITS
–
–
0.4
–
V
VOL
IOH = -4 mA
2.4
–
V
VOH
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
0V ≤ V ≤ V (Max.)
–
-10
10
µA
µA
µA
µA
mA
mA
I
I
I
I
I
I
IL
IH
IN
IL
3.5V ≤ V ≤ V
–
–
IN
CC
0V ≤ V ≤ V
–
–
-150
-150
-200
–
IL-isp
IL-PU
OS1
IN
IL
0V ≤ V ≤ V
–
–
IN
IL
Output Short Circuit Current
VCC= 5V, VOUT = 0.5V
–
–
CC2, 4
V = 0.0V, V = 3.0V, fCLOCK = 1 MHz
Operating Power Supply Current
–
370
IL
IH
Table 2-0007/3320
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using twenty 16-bit counters.
3. Typical values are at VCC= 5V and T = 25°C.
A
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC
.
5
Specifications ispLSI 3320
External Switching Characteristics1, 2, 3
Over Recommended Operating Conditions
TEST5
COND.
-100
-70
DESCRIPTION1
UNITS
2
PARAMETER
#
MIN. MAX. MIN. MAX.
A
A
A
–
1 Data Propagation Delay, 4PT Bypass, ORP Bypass
2 Data Propagation Delay
3 Clock Frequency with Internal Feedback 3
–
–
10.0
13.0
–
–
–
15.0
18.0
–
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
pd2
100
77.0
100
6.0
–
70.0
50.0
83.0
9.0
–
MHz
MHz
MHz
ns
max
1
4 Clock Frequency with External Feedback
5 Clock Frequency, Maximum Toggle 4
(
)
–
–
max (Ext.)
max (Tog.)
su1
tsu2 + tco1
–
–
–
–
6 GLB Reg. Setup Time before Clock, 4 PT Bypass
7 GLB Reg. Clock to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clock, 4 PT Bypass
9 GLB Reg. Setup Time before Clock
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
–
–
A
–
6.0
–
9.0
–
ns
co1
0.0
7.0
–
0.0
11.0
–
ns
h1
–
–
–
ns
su2
–
7.0
–
10.0
–
ns
co2
–
0.0
–
0.0
–
ns
h2
A
–
13.5
–
15.0
–
ns
r1
6.5
–
12.0
–
ns
rw1
B
C
B
C
B
C
–
14 Input to Output Enable
18.0
18.0
9.0
9.0
12.0
12.0
–
21.0
21.0
12.0
12.0
15.0
15.0
–
ns
ptoeen
ptoedis
goeen
goedis
toeen
toedis
wh
15 Input to Output Disable
–
–
ns
16 Global OE Output Enable
–
–
ns
17 Global OE Output Disable
–
–
ns
18 Test OE Output Enable
–
–
ns
19 Test OE Output Disable
–
–
ns
20 Ext. Synchronous Clock Pulse Duration, High
21 Ext. Synchronous Clock Pulse Duration, Low
5.0
5.0
4.5
0.0
6.0
6.0
5.0
0.0
ns
–
–
–
ns
wl
–
22 I/O Reg Setup Time before Ext. Synchronous Clock (Y3, Y4)
23 I/O Reg Hold Time after Ext. Sync Clock (Y3, Y4)
–
–
ns
su3
–
–
–
ns
h3
Table 2-0030/3320
1. Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
6
Specifications ispLSI 3320
Internal Timing Parameters1
Over Recommended Operating Conditions
-100
-70
2
PARAMETER
Inputs
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
24 I/O Register Bypass
25 I/O Latch Delay
–
–
1.5
13.0
–
–
–
3.2
18.2
–
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
iobp
iolat
iosu
ioh
26 I/O Register Setup Time before Clock
27 I/O Register Hold Time after Clock
28 I/O Register Clock to Out Delay
29 I/O Register Reset to Out Delay
7.5
-3.0
–
9.0
-4.0
–
–
–
2.5
2.5
4.2
4.2
ioco
ior
–
–
GRP
30 GRP Delay
–
–
3.0
1.1
–
–
3.5
1.6
ns
ns
t
grp
31 Feedback Delay
tfeedback
GLB
32 4 Product Term Bypass Path Delay (Comb.)
33 4 Product Term Bypass Path Delay (Reg.)
34 1 Product Term/XOR Path Delay
–
–
3.5
3.5
4.5
4.5
5.5
0.5
–
–
–
5.3
3.8
5.8
5.8
7.3
0.5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbp
4ptbr
1ptxor
20ptxor
xoradj
gbp
–
–
35 20 Product Term/XOR Path Delay
36 XOR Adjacent Path Delay3
–
–
–
–
37 GLB Register Bypass Delay
–
–
38 GLB Register Setup Time before Clock
39 GLB Register Hold Time after Clock
40 GLB Register Clock to Output Delay
41 GLB Register Reset to Output Delay
42 GLB Product Term Reset to Register Delay
43 GLB Product Term Output Enable to I/O Cell Delay
44 GLB Product Term Clock Delay
1.0
4.9
–
2.5
6.3
–
gsu
–
–
gh
0.5
1.0
7.9
9.5
1.0
1.0
11.5
9.3
gco
–
–
gro
–
–
ptre
–
–
ptoe
ptck
3.2 3.2
4.5 4.5
ORP
45 ORP Delay
–
–
1.5
0.0
–
–
2.0
0.0
ns
ns
t
orp
46 ORP Bypass Delay
torpbp
Table 2-0036/3320
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Specifications ispLSI 3320
Internal Timing Parameters1
Over Recommended Operating Conditions
-100
-70
2
PARAMETER
Outputs
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
47 Output Buffer Delay
–
–
–
–
2.0
12.0
4.0
–
–
–
–
3.0
13.0
5.0
ns
ns
ns
ns
t
t
t
t
ob
48 Output Buffer Delay, Slew Limited Adder
49 I/O Cell OE to Output Enabled
obs
oen
odis
50 I/O Cell OE to Output Disabled
4.0
5.0
Clocks
t
t
gy0/1/2
ioy3/4
51 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line
52 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line
3.0 3.0 4.0 4.0
3.0 3.0 4.0 4.0
ns
ns
Global Reset
53 Global Reset to GLB and I/O Registers
54 Global OE Pad Buffer
9.0
5.0
8.0
–
–
–
9.0
7.0
ns
ns
ns
t
t
t
gr
–
–
–
goe
toe
55 Test OE Pad Buffer
10.0
Table 2-0037/3320
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
8
Specifications ispLSI 3320
ispLSI 3320 Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
#31
#32
I/O Reg Bypass
GRP
#30
4 PT Bypass
#33
GLB Reg Bypass
#37
ORP Bypass
#46
#47, 48
I/O Pin
I/O Pin
#24
(Output)
(Input)
Input
Register
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
Q
D
RST
D
Q
#45
#34 - 36
#53
#53
#25 - 29
#49, 50
RST
#38 - 41
Reset
Y3,4
#52
Control
PTs
RE
OE
CK
#42 - 44
#51
Y0,1,2
#54
#55
GOE0,1
TOE
0902/3320
Derivations of
t
su,
= Logic + Reg su - Clock (min)
= ( iobp + grp + 20ptxor) + ( gsu) - (tiobp + tgrp + tptck(min))
th and t
co from the Product Term Clock1
tsu
t
t
t
t
= (#24+ #30+ #35) + (#38) - (#24+ #30+ #44)
= (1.5 + 3.0 + 4.5) + (1.0) - (1.5 + 3.0 + 3.2)
2.3 ns
3.6 ns
th
= Clock (max) + Reg h - Logic
= (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)
= (#24+ #30+ #44) + (#39) - (#24+ #30+ #35)
= (1.5 + 3.0 + 3.2) + (4.9) - (1.5 + 3.0 + 4.5)
tco
= Clock (max) + Reg co + Output
= (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#24 + #30 + #44) + (#40) + (#45 + #47)
= (1.5 + 3.0 + 3.2) + (0.5) + (1.5 + 2.0)
11.7 ns
Table 2-0042/3320
Note: Calculations are based on timing specs for the ispLSI 3320-100L.
9
Specifications ispLSI 3320
Power Consumption
Figure 3 shows the relationship between power and
operating speed.
Power consumption in the ispLSI 3320 device depends
on two primary factors: the speed at which the device is
operating and the number of product terms used.
Figure 3. Typical Device Power Consumption vs fmax
800
700
ispLSI 3320
600
500
400
300
200
0
25
50
75
100
fmax (MHz)
Notes: Configuration of 20 16-bit Counters
Typical Current at 5V, 25° C
I
I
can be estimated for the ispLSI 3320 using the following equation:
CC
= 60 + (# of PTs 0.5) + (# of nets Max. freq 0.0095) where:
*
*
*
CC
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The I
estimate is based on typical conditions (V
= 5.0V, room temperature) and an assumption of 2 GLB loads
CC
CC
on average exists. These values are for estimates only. Since the value of I
and the program in the device, the actual I
is sensitive to operating conditions
CC
should be verified.
CC
0127A/3320
10
Specifications ispLSI 3320
Signal Descriptions
Signal Name
Description
GOE0, GOE1
I/O
Global Output Enable input pins.
Input/Output Pins – These are the general purpose I/O pins used by the logic array.
Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
TOE
RESET
Y0, Y1, Y2
Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on
the device.
Y3, Y4
Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells on
the device.
BSCAN/ispEN
Input – Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP
controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State
Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put
the device in the programming mode and put all I/O pins in the high-Z state.
TDI/SDI
Input – This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When
ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used
as one of the two control pins for the ISP State Machine.
TCK/SCLK
Input – This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When
ispEN is logic low, it functions as a clock pin for the Serial Shift Register.
TMS/MODE
Input – This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high.
When ispEN is logic low, it functions as a pin to control the operation of the ISP State Machine.
TRST
Input – Test Reset, active low to reset the Boundary Scan State Machine.
TDO/SDO
Output – This pin performs two functions. When ispEN is logic low, it functions as the pin to read the ISP
data. When ispEN is high, it functions as Test Data Out.
GND
VCC
NC1
Ground (GND)
Vcc
No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 3320
Signal Locations
Signal
208-Pin PQFP/MQFP
320-Ball BGA
GOE0, GOE1
TOE
133, 134
AD12, AC11
30
28
B14
RESET
D13
Y0, Y1, Y2, Y3, Y4 132, 130, 129, 128, 127
AA12, AC13, AB13, AA13, AD13
BSCAN/ispEN
TDI/SDI
27
25
24
23
29
185
B12
C12
D12
A12
A13
M4
TCK/SCLK
TMS/MODE
TRST
TDO/SDO
GND
11, 26, 42, 53, 65, 78, 92, 104, 115,
131, 146, 157, 169, 183, 196, 208
A16, B13, C8, D6, D19, F4, F21, H22, J1, M2, N23, T24, U3,
W4, W21, AA6, AA19, AB17, AC12, AD9
VCC
NC1
14, 39, 58, 80, 99, 118, 143, 162, 181, B10, B18, C3, D4, D21, G2, K23, R2, V23, AA4, AA21,AC7,
203
AC15
76, 77, 79, 81, 180, 182, 184
A1, A2, A3, A6, A9, A11, A14, A20, A23, A24, B1, B2, B5, B8,
B9, B16, B17, B20, B23, B24, C5, C13, C17, C20, C24, D7,
D11, D14, D17, D20, E1, E2, E3, E4, E22, E23, F24, G21,
G23, H2, H3, H4, H23, J2, J23, J24, K3, L1, L4, L21, L24, M3,
M21, M22, M23, N2, N3, N4, N21, N22, N24, P1, P4, P21,
P24, R22, T1, T2, T23, U2, U21, U22, U23, V2, V4, W1, Y2,
Y3, Y21, Y22, Y23, Y24, AA5, AA8, AA11, AA14, AA18, AB1,
AB5, AB8, AB12, AB20, AC1, AC2, AC5, AC8, AC9, AC16,
AC17, AC20, AC23, AC24, AD1, AD2, AD5, AD11, AD14,
AD16, AD19, AD22, AD23, AD24
1. NC pins are not to be connected to any active signals, VCC or GND.
12
Specifications ispLSI 3320
I/O Locations
PQFP/
MQFP
PQFP/
MQFP
PQFP/
MQFP BGA
PQFP/
MQFP BGA
Signal
BGA
Signal
Signal
BGA
Signal
I/O 80
I/O 81
I/O 82
I/O 83
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
I/O 96
I/O 97
I/O 98
I/O 99
I/O 100 158
I/O 101 159
I/O 102 160
I/O 103 161
I/O 104 163
I/O 105 164
I/O 106 165
I/O 107 166
I/O 108 167
I/O 109 168
I/O 110 170
I/O 111 171
I/O 112 172
I/O 113 173
I/O 114 174
I/O 115 175
I/O 116 176
I/O 117 177
I/O 118 178
I/O 119 179
135
136
137
138
139
140
141
142
144
145
147
148
149
150
151
152
153
154
155
156
AB11
AD10
AC10
AB10
AA10
AD8
AB9
AA9
AD7
AD6
AB7
AC6
AA7
AB6
AD4
AC4
AD3
AB4
AC3
AB3
AB2
AA3
Y4
AA2
AA1
W3
Y1
W2
V3
U4
V1
T4
T3
U1
R4
R3
R1
P3
P2
N1
I/O 120 186
I/O 121 187
I/O 122 188
I/O 123 189
I/O 124 190
I/O 125 191
I/O 126 192
I/O 127 193
I/O 128 194
I/O 129 195
I/O 130 197
I/O 131 198
I/O 132 199
I/O 133 200
I/O 134 201
I/O 135 202
I/O 136 204
I/O 137 205
I/O 138 206
I/O 139 207
M1
L2
L3
K1
K2
K4
H1
J3
J4
G1
F1
G3
F2
G4
F3
D1
D2
C1
D3
C2
B3
C4
D5
B4
A4
C6
A5
B6
C7
D8
B7
A7
D9
C9
A8
D10
C10
A10
C11
B11
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
31
32
33
34
35
36
37
38
40
41
43
44
45
46
47
48
49
50
51
52
54
55
56
57
59
60
61
62
63
64
66
67
68
69
70
71
72
73
74
75
C14
A15
B15
C15
D15
A17
C16
D16
A18
A19
C18
B19
D18
C19
A21
B21
A22
C21
B22
C22
C23
D22
E21
D23
D24
F22
E24
F23
G22
H21
G24
J21
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
I/O 64
I/O 65
I/O 66
I/O 67
I/O 68
I/O 69
I/O 70
I/O 71
I/O 72
I/O 73
I/O 74
I/O 75
I/O 76
I/O 77
I/O 78
I/O 79
82
83
84
85
86
87
88
89
90
91
93
94
95
96
97
98
100
101
102
103
105
106
107
108
109
110
111
112
113
114
116
117
119
120
121
122
123
124
125
126
P23
P22
R24
R23
R21
U24
T22
T21
V24
W24
V22
W23
V21
W22
AA24
AA23
AB24
AA22
AB23
AB22
AC22
AB21
AA20
AC21
AD21
AB19
AD20
AC19
AB18
AA17
AC18
AD18
AA16
AB16
AD17
AA15
AB15
AD15
AB14
AC14
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 140
I/O 141
I/O 142
I/O 143
I/O 144
I/O 145
I/O 146
I/O 147
I/O 148
1
2
3
4
5
6
7
8
9
I/O 149 10
I/O 150 12
I/O 151 13
I/O 152 15
I/O 153 16
I/O 154 17
I/O 155 18
I/O 156 19
I/O 157 20
I/O 158 21
I/O 159 22
J22
H24
K21
K22
K24
L22
L23
M24
13
Specifications ispLSI 3320
Pin Configuration
ispLSI 3320 208-Pin PQFP (with Heat Spreader) and 208-Pin MQFP Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
I/O 99
I/O 98
I/O 97
I/O 96
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
GND
I/O 140
I/O 141
I/O 142
I/O 143
I/O 144
I/O 145
I/O 146
I/O 147
I/O 148
I/O 149
GND
I/O 150
I/O 151
VCC
I/O 152
I/O 153
I/O 89
I/O 88
VCC
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
GOE1
GOE0
Y0
I/O 154
I/O 155
I/O 156
I/O 157
I/O 158
I/O 159
TMS/MODE
TCK/SCLK
TDI/SDI
GND
BSCAN/ispEN
ispLSI 3320
GND
Y1
Y2
Y3
RESET
1TRST/NC
Top View
Y4
TOE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
VCC
I/O 8
I/O 9
GND
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
VCC
I/O 71
I/O 70
GND
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
49
50
51
52
1. NC pins are not to be connected to any active signal, VCC or GND.
208MQUAD/3320
14
Specifications ispLSI 3320
Signal Configuration
ispLSI 3320 320-Ball BGA Signal Diagram
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
I/O I/O
16 14
I/O I/O I/O
I/O
1
I/O
157
I/O I/O
154 151
I/O I/O
146 144
TMS/
MODE
NC1 NC1
NC1 NC1
NC1
NC1
NC1
GND
NC1 TRST
NC1
NC1
NC1
NC1 NC1 NC1
NC1 NC1
A
B
A
B
9
8
5
I/O I/O
18 15
I/O
11
I/O
2
I/O
159
I/O I/O
150 147
I/O I/O
143 140
ispEN/
VCC NC1 NC1
TOE GND BSCAN
VCC NC1 NC1
NC1
NC1
I/O I/O I/O
20 19 17
I/O I/O
I/O I/O I/O
TDI/ I/O I/O I/O
SDI 158 156 153
I/O I/O
148 145
I/O
141
I/O I/O
139 137
NC1
NC1
NC1
NC1
GND
VCC
C
C
13
10
6
3
0
I/O I/O I/O
I/O
12
I/O I/O
I/O I/O I/O
155 152 149
I/O
142
I/O I/O I/O
138 136 135
TCK/
SCLK
VCC NC1 GND
NC1
NC1
NC1 GND
VCC
RESET
D
D
24
23
21
7
4
I/O
26
I/O
22
NC1 NC1
NC1 NC1 NC1 NC1
E
E
I/O I/O
I/O I/O I/O
GND
NC1
GND
NC1
F
F
27
25
134 132 130
I/O
30
I/O
28
I/O I/O
133 131
I/O
129
NC1
VCC
G
H
G
H
I/O
33
I/O
29
I/O
126
NC1 GND
NC1 NC1 NC1
I/O I/O
128 127
I/O I/O
32 31
NC1 NC1
NC1 GND
J
J
I/O
I/O I/O
I/O
I/O I/O
124 123
VCC
36
NC1
125
K
K
35
34
I/O I/O
38 37
I/O I/O
122 121
NC1
NC1
NC1
NC1
L
L
I/O
39
SDO/
TDO
I/O
120
NC1 NC1 NC1
NC1 GND
ispLSI 3320
M
N
M
N
I/O
119
NC1 NC1 NC1
NC1 GND NC1 NC1
Bottom View
I/O I/O
I/O I/O
NC1
NC1
NC1
NC1
P
P
40
41
117 118
I/O I/O
VCC
I/O
116
I/O I/O
42 43
I/O
44
NC1
R
R
114 115
I/O I/O
111 112
I/O I/O
46 47
GND NC1
NC1 NC1
T
T
I/O
109
I/O
113
I/O
45
GND NC1
NC1 NC1 NC1
U
U
I/O
48
I/O I/O
VCC
I/O
NC1
I/O
110
NC1
V
V
50
52
108
I/O I/O
105 107
I/O I/O I/O
GND
NC1
GND
W
Y
W
Y
49
51
53
I/O
102
I/O
106
NC1 NC1 NC1 NC1
NC1 NC1
I/O I/O I/O
VCC
I/O
62
I/O I/O I/O
69 72 75
I/O I/O
I/O
92
I/O I/O I/O
101 103 104
GND NC1
I/O I/O
NC1 Y3 Y0 NC1
NC1
NC1
GND NC1 VCC
AA
AB
AC
AD
AA
AB
AC
AD
54
55
57
84
87
I/O I/O I/O I/O
56 58 59 61
I/O I/O I/O
I/O I/O I/O
I/O I/O
90
I/O I/O I/O
NC1
NC1
GND
Y2 NC1
NC1
NC1
NC1
NC1
NC1 NC1
NC1 NC1
65
68
73
76
78
80 83
86
93
97
I/O I/O
95 98
I/O I/O
99 100
I/O I/O
NC1 NC1
60 63
I/O I/O
67
I/O
79
GOE I/O
I/O
91
NC1 NC1 VCC
Y1 GND
GOE
NC1 NC1 VCC
70
I/O I/O
1
82
I/O I/O
64
I/O
77
I/O
81
I/O I/O I/O
85 88
NC1 NC1 NC1
NC1
NC1
NC1 Y4
NC1
GND
66
71 74
0
89
94
96
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
320BGA/3320
1. NCs are not to be connected to any active signals, Vcc or GND.
Note: Ball A1 indicator dot on top side of package.
15
Specifications ispLSI 3320
Part Number Description
–
ispLSI
XXX X XXXX X
3320
Device Family
Grade
Blank = Commercial
Device Number
Speed
Package
Q = PQFP (with Heat Spreader)
B320 = BGA
M = MQFP*
100 = 100 MHz
fmax
70 = 70 MHz max
f
Power
L = Low
0212A/3320
Ordering Information
COMMERCIAL
ORDERING NUMBER
FAMILY
fmax (MHz)
100
tpd (ns)
PACKAGE
208-Pin PQFP
320-Ball BGA
10
10
ispLSI 3320-100LQ
100
ispLSI 3320-100LB320
100
70
10
15
15
15
ispLSI 3320-100LM*
ispLSI 3320-70LQ
208-Pin MQFP
208-Pin PQFP
320-Ball BGA
ispLSI
70
ispLSI 3320-70LB320
ispLSI 3320-70LM*
70
208-Pin MQFP
Table 2-0041A/3320
*Use the 208-pin PQFP for new designs.
16
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