ISPLSI3448-90LB432_技术文档

®

ispLSI 3448

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 224 I/O

— 20000 PLD Gates

Output Routing Pool (ORP)

Boundary

Scan

...

J3

J2

J1

J0

H3

H2

H1

H0

— 672 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

K0

K1

K2

G3

G2

G1

D

Q

OR

Array

• HIGH-PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 90 MHz Maximum Operating Frequency

— tpd = 12 ns Propagation Delay

Twin

GLB

K3

G0

D

OR

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

Array

N0

N1

N2

D3

D2

D1

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Global Routing Pool

(GRP)

• ispLSI FEATURES:

— 5V In-System Programmable (ISP™) Using Lattice

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

N3

D0

A0

A1

A2

A3

C0

C1

C2

C3

— Reprogram Soldered Devices for Faster Debugging

...

Output Routing Pool (ORP)

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

0139/3448

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Five Dedicated Clock Inputs

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

Description

The ispLSI 3448 is a High-Density Programmable Logic

Devicecontaining672Registers, 224UniversalI/Os, five

Dedicated Clock Inputs, 14 Output Routing Pools (ORP)

and a Global Routing Pool (GRP) which allows complete

inter-connectivity between all of these elements. The

ispLSI 3448 features 5V in-system programmability and

in-systemdiagnosticcapabilities. TheispLSI3448offers

non-volatile reprogrammabilityofthelogic, aswellasthe

interconnect to provide truly reconfigurable systems.

— Flexible I/O Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on the ispLSI 3448 device is the

TwinGenericLogicBlock(TwinGLB)labelledA0,A1...N3.

There are a total of 56 of these Twin GLBs in the ispLSI

3448 device. Each Twin GLB has 24 inputs, a program-

mable AND array and two OR/Exclusive-OR Arrays, and

eight outputs which can be configured to be either com-

binatorial or registered. All Twin GLB inputs come from

the GRP.

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

February 2000

3448_06

1

Specifications ispLSI 3448

Functional Block Diagram

Figure 1. ispLSI 3448 Functional Block Diagram

Input Bus

Output Routing Pool

L2 L1

Input Bus

TOE

TDI/SDI

TRST

Boundary

Scan

Output Routing Pool

TDO/SDO

N3

N2

N1

N0

M3

M2

M1

M0

L3

L0

K3

K2

K1

K0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 159

I/O 158

I/O 157

I/O 156

A0

A1

A2

A3

J3

J2

J1

J0

I/O 4

I/O 5

I/O 6

I/O 7

I/O 155

I/O 154

I/O 153

I/O 152

I/O 8

I/O 9

I/O 151

I/O 150

I/O 149

I/O 148

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 147

I/O 146

I/O 145

I/O 144

I/O 16

I/O 17

I/O 18

I/O 19

I/O 143

I/O 142

I/O 141

I/O 140

B0

B1

B2

B3

I3

I2

I1

I0

I/O 20

I/O 21

I/O 22

I/O 23

I/O 139

I/O 138

I/O 137

I/O 136

I/O 24

I/O 25

I/O 26

I/O 27

Global Routing Pool

(GRP)

I/O 135

I/O 134

I/O 133

I/O 132

I/O 28

I/O 29

I/O 30

I/O 31

I/O 131

I/O 130

I/O 129

I/O 128

I/O 32

I/O 33

I/O 34

I/O 35

I/O 127

I/O 126

I/O 125

I/O 124

C0

C1

C2

C3

H3

H2

H1

H0

I/O 36

I/O 37

I/O 38

I/O 39

I/O 123

I/O 122

I/O 121

I/O 120

I/O 40

I/O 41

I/O 42

I/O 43

I/O 119

I/O 118

I/O 117

I/O 116

I/O 44

I/O 45

I/O 46

I/O 47

I/O 115

I/O 114

I/O 113

I/O 112

D0

D1

D2

D3

E0

E1

E2

E3

F0

F1

F2

F3

G0

G1

G2

G3

Output Routing Pool

Input Bus

Output Routing Pool

Input Bus

Output Routing Pool

Input Bus

Output Routing Pool

Input Bus

RESET

0130/3448

2

Specifications ispLSI 3448

Description (continued)

Clocks in the ispLSI 3448 device are provided through

five dedicated signals. Three clocks are provided for the

Twin GLBs and the remaining two clocks are provided for

the I/O cells.

All local logic block outputs are brought back into the

GRP so they can be connected to the inputs of any other

logic block on the device. The device also has 224 I/O

cells, each of which is directly connected to an I/O ball.

Each I/O cell can be individually programmed to be a

combinatorialinput,aregisteredinput,alatchedinput,an

output or a bidirectional I/O with 3-state control. The

signal levels are TTL compatible voltages and the output

drivers can source 4 mA or sink 8 mA. Each output can

be programmed independently for fast or slow output

slew rate to minimize overall output switching noise.

The table below lists key attributes of the device along

with the number of resources available.

An additional feature of the ispLSI 3448 is the Boundary

Scan capability, which is composed of cells connected

between the on-chip system logic and the device’s inputs

and outputs. All I/O have associated boundary scan

registers, with 3-state I/O using three boundary scan

registers and inputs using one.

The224I/Ocellsaregroupedinto14setsof16bits. Each

of these I/O groups is associated with a logic Megablock

through the use of the ORP. Each Megablock is able to

provide one Product Term Output Enable (PTOE) signal

which is globally distributed to all I/O cells. That PTOE

signalcanbegeneratedwithinanyGLBintheMegablock.

Each I/O cell can select one of 16 available OEs (two

Global OEs and 14 PTOEs).

The ispLSI 3448 supports all IEEE 1149.1 mandatory

instructions, which include BYPASS, EXTEST and

SAMPLE.

Key Attributes of the ispLSI 3448

Attribute

Quantity

Four Twin GLBs, 16 I/O cells and one ORP are con-

nected together to make a logic Megablock. The

Megablockisdefinedbythe resourcesthatitshares. The

outputs of the four Twin GLBs are connected to a set of

16 I/O cells by the ORP. The ispLSI 3448 device

contains 14 of these Megablocks.

Twin GLBs

Registers

I/O

56

672

224

5

Global Clocks

Global OE

Test OE

2

The GRP has as its inputs the outputs from all of the Twin

GLBs and all of the inputs from the bidirectional I/O cells.

All of these signals are made available to the inputs of the

Twin GLBs. Delays through the GRP have been equal-

ized to minimize timing skew and logic glitching.

1

Table 1-0003/3448

3

Specifications ispLSI 3448

1

Absolute Maximum Ratings

Supply Voltage V .................................. -0.5 to +7.0V

cc

Input Voltage Applied........................ -2.5 to V +1.0V

CC

Off-State Output Voltage Applied ..... -2.5 to V +1.0V

CC

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (T ) with Power Applied ... 140°C

J

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

SYMBOL

PARAMETER

MIN.

0

MAX.

70

UNITS

Ambient Temperature

Supply Voltage

°C

V

TA

4.75

0

5.25

0.8

V

CC

Input Low Voltage

Input High Voltage

V

IL

2.0

V_CC+1

V

IH

Table 2-0005/3448

Capacitance (T_A=25°C,f=1.0 MHz)

SYMBOL

PARAMETER

TYPICAL

UNITS

TEST CONDITIONS

_CC= 5.0V, V_I/O= 2.0V

V_CC= 5.0V, V_Y= 2.0V

10

pf

V

I/O Capacitance

C₁

C₂

11

pf

Clock Capacitance

Table 2-0006/3320

Data Retention Specifications

PARAMETER

Data Retention

MINIMUM

MAXIMUM

UNITS

Years

Cycles

20

–

ispLSI Erase/Reprogram Cycles

10000

Table 2-0008/3320

4

Specifications ispLSI 3448

Switching Test Conditions

Figure 2. Test Load

Input Pulse Levels

GND to 3.0V

≤ 3 ns 10% to 90%

1.5V

+ 5V

Input Rise and Fall Time

Input Timing Reference Levels

Ouput Timing Reference Levels

Output Load

R

1

1.5V

Device

Output

Test

Point

See Figure 2

Table 2-0003/3448

3-state levels are measured 0.5V from

steady-state active level.

R

2

C *

L

Output Load conditions (See Figure 2)

*

C includes Test Fixture and Probe Capacitance.

L

0213A

TEST CONDITION

R1

470Ω

∞

R2

CL

A

B

390Ω

35pF

Active High

Active Low

470Ω

Active High to Z

∞

390Ω

5pF

at V_OH-0.5V

C

Active Low to Z

at V_OL+0.5V

470Ω

5pF

Table 2 - 0004A

DC Electrical Characteristics

Over Recommended Operating Conditions

3

SYMBOL

PARAMETER

Output Low Voltage

Output High Voltage

CONDITION

I_OL= 8 mA

MIN.

–

TYP. MAX. UNITS

–

0.4

–

V

VOL

I_OH= -4 mA

2.4

–

V

VOH

Input or I/O Low Leakage Current

Input or I/O High Leakage Current

ispEN Input Low Leakage Current

I/O Active Pull-Up Current

0V ≤ V ≤ V (Max.)

–

-10

10

µA

mA

I

IL

IH

IN

IL

3.5V ≤ V ≤ V

–

IN

CC

0V ≤ V ≤ V

–

-150

-200

–

IL-isp

IL-PU

OS¹

IN

IL

0V ≤ V ≤ V

–

IN

IL

Output Short Circuit Current

V_CC= 5V, V_OUT= 0.5V

–

CC^{2, 4}

V = 0.0V, V = 3.0V, f_CLOCK= 1 MHz

Operating Power Supply Current

–

470

IL

IH

Table 2-0007/3448

1. One output at a time for a maximum duration of one second. V_OUT= 0.5V was selected to avoid test problems

by tester ground degradation. Guaranteed but not 100% tested.

2. Measured using 28 16-bit counters.

3. Typical values are at V_CC= 5V and T = 25°C.

A

4. Maximum I_CCvaries widely with specific device configuration and operating frequency. Refer to the Power Consumption

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate

maximum I_CC

.

5

Specifications ispLSI 3448

External Switching Characteristics^{1, 2, 3}

Over Recommended Operating Conditions

TEST⁵

COND.

-90

-70

DESCRIPTION¹

UNITS

2

PARAMETER

#

MIN. MAX. MIN. MAX.

A

–

1 Data Propagation Delay, 4PT Bypass, ORP Bypass

2 Data Propagation Delay

3 Clock Frequency with Internal Feedback ³

–

12.0

15.0

–

15.0

18.0

–

ns

t

f

t

pd1

pd2

90.0

62.5

100

7.0

–

70.0

50.0

83.0

9.0

–

MHz

ns

max

1

4 Clock Frequency with External Feedback

5 Clock Frequency, Maximum Toggle ⁴

(

)

–

max (Ext.)

max (Tog.)

su1

tsu2 + tco1

–

6 GLB Reg. Setup Time before Clock, 4 PT Bypass

7 GLB Reg. Clock to Output Delay, ORP Bypass

8 GLB Reg. Hold Time after Clock, 4 PT Bypass

9 GLB Reg. Setup Time before Clock

10 GLB Reg. Clock to Output Delay

11 GLB Reg. Hold Time after Clock

12 Ext. Reset Pin to Output Delay

13 Ext. Reset Pulse Duration

–

A

–

7.5

–

9.0

–

ns

co1

0.0

8.5

–

0.0

11.0

–

ns

h1

–

ns

su2

–

8.0

–

10.0

–

ns

co2

–

0.0

–

0.0

–

ns

h2

A

–

14.0

–

15.0

–

ns

r1

9.0

–

12.0

–

ns

rw1

B

C

B

C

B

C

–

14 Input to Output Enable

25.0

10.0

13.0

–

30.0

12.0

15.0

–

ns

ptoeen

ptoedis

goeen

goedis

toeen

toedis

wh

15 Input to Output Disable

–

ns

16 Global OE Output Enable

–

ns

17 Global OE Output Disable

–

ns

18 Test OE Output Enable

–

ns

19 Test OE Output Disable

–

ns

20 Ext. Synchronous Clock Pulse Duration, High

21 Ext. Synchronous Clock Pulse Duration, Low

5.0

4.5

0.0

6.0

5.0

0.0

ns

–

ns

wl

–

22 I/O Reg Setup Time before Ext. Synchronous Clock (Y3, Y4)

23 I/O Reg Hold Time after Ext. Sync Clock (Y3, Y4)

–

ns

su3

–

ns

h3

Table 2-0030/3320

1. Unless noted otherwise, all parameters use 20 PTXOR path and ORP.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.

5. Reference Switching Test Conditions section.

6

Specifications ispLSI 3448

Internal Timing Parameters¹

Over Recommended Operating Conditions

-90

-70

2

PARAMETER

Inputs

#

DESCRIPTION

UNITS

MIN. MAX. MIN. MAX.

24 I/O Register Bypass

25 I/O Latch Delay

–

2.3

14.0

–

3.2

18.2

–

ns

t

iobp

iolat

iosu

ioh

26 I/O Register Setup Time before Clock

27 I/O Register Hold Time after Clock

28 I/O Register Clock to Out Delay

29 I/O Register Reset to Out Delay

7.5

-3.0

–

9.0

-4.0

–

8.3

10.2

ioco

ior

–

GRP

30 GRP Delay

–

3.2

1.0

–

3.5

1.6

ns

t

grp

31 Feedback Delay

tfeedback

GLB

32 4 Product Term Bypass Path Delay (Comb.)

33 4 Product Term Bypass Path Delay (Reg.)

34 1 Product Term/XOR Path Delay

–

4.0

3.5

5.0

6.2

0.5

–

5.3

3.8

5.8

7.3

0.5

–

ns

t

4ptbp

4ptbr

1ptxor

20ptxor

xoradj

gbp

–

35 20 Product Term/XOR Path Delay

36 XOR Adjacent Path Delay³

–

37 GLB Register Bypass Delay

–

38 GLB Register Setup Time before Clock

39 GLB Register Hold Time after Clock

40 GLB Register Clock to Output Delay

41 GLB Register Reset to Output Delay

42 GLB Product Term Reset to Register Delay

43 GLB Product Term Output Enable to I/O Cell Delay

44 GLB Product Term Clock Delay

1.5

5.4

–

2.5

6.3

–

gsu

–

gh

0.5

1.0

8.9

15.0

1.0

10.5

18.3

gco

–

gro

–

ptre

–

ptoe

ptck

3.7 3.7

4.5 4.5

ORP

45 ORP Delay

–

1.5

0.0

–

2.0

0.0

ns

t

orp

46 ORP Bypass Delay

torpbp

Table 2-0036/3448

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

7

Specifications ispLSI 3448

Internal Timing Parameters¹

Over Recommended Operating Conditions

-90

-70

2

PARAMETER

Outputs

#

DESCRIPTION

UNITS

MIN. MAX. MIN. MAX.

47 Output Buffer Delay

–

2.5

13.0

4.5

–

3.0

13.0

5.0

ns

t

ob

48 Output Buffer Delay, Slew Limited Adder

49 I/O Cell OE to Output Enabled

obs

oen

odis

50 I/O Cell OE to Output Disabled

4.5

5.0

Clocks

t

gy0/1/2

ioy3/4

51 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line

52 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line

3.5 3.5 4.0 4.0

3.0 3.0 4.0 4.0

ns

Global Reset

53 Global Reset to GLB and I/O Registers

54 Global OE Pad Buffer

9.0

5.5

8.5

–

9.0

7.0

ns

t

gr

–

goe

toe

55 Test OE Pad Buffer

10.0

Table 2-0037/3448

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

8

Specifications ispLSI 3448

ispLSI 3448 Timing Model

I/O Cell

GRP

GLB

ORP

I/O Cell

Feedback

#31

#32

I/O Reg Bypass

GRP

#30

4 PT Bypass

#33

GLB Reg Bypass

#37

ORP Bypass

#46

#47, 48

I/O

#24

(Output)

(Input)

Input

Register

20 PT

XOR Delays

GLB Reg

Delay

ORP

Delay

Q

D

RST

D

Q

#45

#34 - 36

#53

#25 - 29

#49, 50

RST

#38 - 41

Reset

Y3,4

#52

Control

PTs

RE

OE

CK

#42 - 44

#51

Y0,1,2

#54

#55

GOE0,1

TOE

0902/3448

Derivations of

t

su,

= Logic + Reg su - Clock (min)

= ( iobp + grp + 20ptxor) + ( gsu) - (tiobp + tgrp + tptck(min))

th and t

co from the Product Term Clock¹

tsu

t

= (#24+ #30+ #35) + (#38) - (#24+ #30+ #44)

= (2.3 + 3.2 + 5.0) + (1.5) - (2.3 + 3.2 + 3.7)

2.8 ns

4.1 ns

th

= Clock (max) + Reg h - Logic

= (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)

= (#24+ #30+ #44) + (#39) - (#24+ #30+ #35)

= (2.3 + 3.2 + 3.7) + (5.4) - (2.3 + 3.2 + 5.0)

tco

= Clock (max) + Reg co + Output

= (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)

= (#24 + #30 + #44) + (#40) + (#45 + #47)

= (2.3 + 3.2 + 3.7) + (0.5) + (1.5 + 2.5)

13.7 ns

Table 2-0042/3448

Note: Calculations are based on timing specs for the ispLSI 3448-90L.

9

Specifications ispLSI 3448

Power Consumption

Power consumption in the ispLSI 3448 device depends Figure 3 shows the relationship between power and

on two primary factors: the speed at which the device is operating speed.

operating and the number of product terms used.

Figure 3. Typical Device Power Consumption vs fmax

1000

ispLSI 3448

800

600

400

200

0

30

60

90

fmax (MHz)

Notes: Configuration of 28 16-bit Counters

Typical Current at 5V, 25° C

I

can be estimated for the ispLSI 3448 using the following equation:

CC

= 60 + (# of PTs 0.46) + (# of nets Max. freq 0.01) where:

*

CC

# of PTs = Number of Product Terms used in design

# of nets = Number of Signals used in device

Max. freq = Highest Clock Frequency to the device

The I

estimate is based on typical conditions (V

= 5.0V, room temperature) and an assumption of two

CC

GLB loads on average exists. These values are for estimates only. Since the value of I

operating conditions and the program in the device, the actual I

is sensitive to

CC

should be verified.

CC

0127A/3448

10

Specifications ispLSI 3448

Signal Description

Signal Name

Description

I/O

Input/Output – These are the general purpose I/O used by the logic array.

Global Output Enable inputs.

GOE0, GOE1

TOE

Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven.

Active Low (0) Reset which resets all of the GLB and I/O registers in the device.

Dedicated Clock inputs connect to one of the clock inputs of all the GLBs on the device.

Dedicated Clock inputs connect to one of the clock inputs of all the I/O cells on the device.

RESET

Y0, Y1, Y2

Y3, Y4

BSCAN/ispEN

Input – Dedicated in-system programming enable input. When this is high, the BSCAN TAP

controller signals TMS, TDI, TDO and TCK are enabled. When this is brought low, the ISP State

Machine control signals MODE, SDI, SDO and SLCK are enabled. High-to-low transition will put the

device in the programming mode and put all I/O in the high-Z state.

TDI/SDI

Input – This signal performs two functions. It is the Test Data input signal when ispEN is logic high.

When ispEN is logic low, it functions as an input to load programming data into the device. SDI is also

used as one of the two control signals for the ISP State Machine.

TCK/SCLK

Input – This signal performs two functions. It is the Test Clock input signal when ispEN is logic high.

When ispEN is logic low, it functions as a clock signal for the Serial Shift Register.

TMS/MODE

Input – This signal performs two functions. It is the Test Mode Select input signal when ispEN is logic

high. When ispEN is logic low, it controls the operation of the ISP State Machine.

TRST

Input – Test Reset, active low to reset the Boundary Scan State Machine.

TDO/SDO

Output – This signal performs two functions. When ispEN is logic low, it reads the ISP data. When

ispEN is high, it functions as Test Data Out.

GND

VCC

NC¹

Ground (GND)

Vcc

No Connect.

Signal Locations

Signal

432-Ball BGA

GOE0, GOE1

TOE

R2, W1

H3

RESET

AA31

Y0, Y1, Y2, Y3, Y4 U30, N31, L1, AB3, AF1

BSCAN/ispEN

TDI/SDI

AD29

K29

AG29

F31

TCK/SCLK

TMS/MODE

TRST

E3

TDO/SDO

GND

AH3

A1, A2, A16, A30, A31, B1, B5, B9, B13, B19, B23, B27, B31, E2, E30, J2, J30, N2, N30, T1, T31, W2,

W30, AC2, AC30, AG2, AG30, AK1, AK5, AK9, AK13, AK19, AK23, AK27, AK31, AL1, AL2, AL16,

AL30, AL31

VCC

NC¹

A3, A10, A22, A29, B14, B18, C1, C31, K1, K31, P2, P30, V2, V30, AB1, AB31, AJ1, AJ31, AK14,

AK18, AL3, AL10, AL22, AL29

B2, B3, B30, C3, C7, C11, C14, C18, C21, C25, C29, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13,

D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, E4, E28, F4, F28,

G3, G4, G28, G29, H4, H28, J4, J28, K4, K28, L3, L4, L28, L29, M4, M28, N4, N28, P3, P4, P28, P29,

R4, R28, T4, T28, U4, U28, V3, V4, V28, V29, W4, W28, Y4, Y28, AA3, AA4, AA28, AA29, AB4, AB28,

AC4, AC28, AD4, AD28, AE3, AE4, AE28, AE29, AF4, AF28, AG4, AG28, AH4, AH5, AH6, AH7, AH8,

AH9, AH10, AH11, AH12, AH13, AH14, AH15, AH16, AH17, AH18, AH19, AH20, AH21, AH22, AH23,

AH24, AH25, AH26, AH27, AH28, AJ3, AJ7, AJ11, AJ14, AJ18, AJ21, AJ25, AJ29, AK2, AK30

1. NCs are not to be connected to any active signals, VCC or GND.

11

Specifications ispLSI 3448

I/O Locations

Signal

BGA

Signal

BGA

Signal

BGA

Signal

BGA

Signal

BGA

Signal

BGA

I/O 114 R1

I/O 115 P1

I/O 116 N1

I/O 117 N3

I/O 118 M1

I/O 119 M2

I/O 120 M3

I/O 121 L2

I/O 122 K2

I/O 123 K3

I/O 124 J1

I/O 125 J3

I/O 126 H1

I/O 127 H2

I/O 128 G1

I/O 129 G2

I/O 130 F1

I/O 131 F2

I/O 132 F3

I/O 133 E1

I/O 134 D1

I/O 135 D2

I/O 136 C2

I/O 137 D3

I/O 138 C4

I/O 139 B4

I/O 140 C5

I/O 141 A4

I/O 142 A5

I/O 143 C6

I/O 144 B6

I/O 145 A6

I/O 146 B7

I/O 147 A7

I/O 148 C8

I/O 149 B8

I/O 150 A8

I/O 151 C9

I/O 152 A9

I/O 153 C10

I/O 154 B10

I/O 155 B11

I/O 156 A11

I/O 157 C12

I/O 158 B12

I/O 159 A12

I/O 160 C13

I/O 161 A13

I/O 162 A14

I/O 163 C15

I/O 164 B15

I/O 165 A15

I/O 166 C16

I/O 167 B16

I/O 168 C17

I/O 169 B17

I/O 170 A17

I/O 171 A18

I/O 172 A19

I/O 173 C19

I/O 174 A20

I/O 175 B20

I/O 176 C20

I/O 177 A21

I/O 178 B21

I/O 179 B22

I/O 180 C22

I/O 181 A23

I/O 182 C23

I/O 183 A24

I/O 184 B24

I/O 185 C24

I/O 186 A25

I/O 187 B25

I/O 188 A26

I/O 189 B26

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

T30

U29

U31

V31

W31

W29

Y31

Y30

I/O 190 C26

I/O 191 A27

I/O 192 A28

I/O 193 C27

I/O 194 B28

I/O 195 B29

I/O 196 C28

I/O 197 D29

I/O 198 C30

I/O 199 D30

I/O 200 E29

I/O 201 D31

I/O 202 E31

I/O 203 F29

I/O 204 F30

I/O 205 G30

I/O 206 G31

I/O 207 H29

I/O 208 H30

I/O 209 H31

I/O 210 J29

I/O 211 J31

I/O 212 K30

I/O 213 L30

I/O 214 L31

I/O 215 M29

I/O 216 M30

I/O 217 M31

I/O 218 N29

I/O 219 P31

I/O 220 R29

I/O 221 R30

I/O 222 R31

I/O 223 T29

I/O 38

I/O 39

I/O 40

I/O 41

I/O 42

I/O 43

I/O 44

I/O 45

I/O 46

I/O 47

I/O 48

I/O 49

I/O 50

I/O 51

I/O 52

I/O 53

I/O 54

I/O 55

I/O 56

I/O 57

I/O 58

I/O 59

I/O 60

I/O 61

I/O 62

I/O 63

I/O 64

I/O 65

I/O 66

I/O 67

I/O 68

I/O 69

I/O 70

I/O 71

I/O 72

I/O 73

I/O 74

I/O 75

AK24

AL24

AJ23

AL23

AJ22

AK22

AK21

AL21

AJ20

AK20

AL20

AJ19

AL19

AL18

AJ17

AK17

AL17

AJ16

AK16

AJ15

AK15

AL15

AL14

AL13

AJ13

AL12

AK12

AJ12

AL11

AK11

AK10

AJ10

AL9

I/O 76

I/O 77

I/O 78

I/O 79

I/O 80

I/O 81

I/O 82

I/O 83

I/O 84

I/O 85

I/O 86

I/O 87

I/O 88

I/O 89

I/O 90

I/O 91

I/O 92

I/O 93

I/O 94

I/O 95

I/O 96

I/O 97

I/O 98

I/O 99

I/O 100 AB2

I/O 101 AA2

I/O 102 AA1

I/O 103 Y3

I/O 104 Y2

I/O 105 Y1

I/O 106 W3

I/O 107 V1

I/O 108 U3

I/O 109 U2

I/O 110 U1

I/O 111 T3

I/O 112 T2

I/O 113 R3

AK7

AL6

AK6

AJ6

AL5

AL4

AJ5

AK4

AK3

AJ4

AJ2

AH2

AG3

AH1

AG1

AF3

AF2

AE2

AE1

AD3

AD2

AD1

AC3

AC1

I/O 8

I/O 9

Y29

AA30

AB30

AB29

AC31

AC29

AD31

AD30

AE31

AE30

AF31

AF30

AF29

AG31

AH31

AH30

AJ30

AH29

AJ28

AK29

AK28

AJ27

AL28

AL27

AJ26

AK26

AL26

AK25

AL25

AJ24

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 32

I/O 33

I/O 34

I/O 35

I/O 36

I/O 37

AJ9

AL8

AK8

AJ8

AL7

12

Specifications ispLSI 3448

Signal Configuration

ispLSI 3448 432-Ball BGA Signal Diagram

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

I/O

192

I/O

191

I/O

188

I/O

186

I/O

183

I/O

181

I/O

177

I/O

174

I/O

172

I/O

171

I/O

170

I/O

165

I/O

162

I/O

161 159

I/O

156

I/O

152

I/O

150

I/O

147

I/O

145

I/O

142

I/O

141

A

B

A

B

GND GND VCC

VCC

GND

VCC

VCC GND GND

I/O

GND NC¹

195

I/O

194

I/O

189

I/O

187

I/O

184

I/O

179

I/O

178 175

I/O

169

I/O

167

I/O

164

I/O

158

I/O

155

I/O

154

I/O

149

I/O

146

I/O

144

I/O

139

GND

GND VCC

VCC GND

GND

I/O

NC¹NC¹GND

I/O

198

I/O

196

I/O

193

I/O

190

I/O

185

I/O

182

I/O

180

I/O

NC¹

I/O

173

I/O

168

I/O

166

I/O

163

I/O

NC¹

I/O

157

I/O

153

I/O

151

I/O

148

I/O

143 140

I/O

138

C

VCC

NC¹

VCC

176

160

136

I/O

201

I/O

199

I/O

197

I/O

137

I/O

135

I/O

134

NC¹

NC¹NC¹

NC¹NC¹NC¹NC¹

NC¹NC¹NC¹NC¹NC¹NC¹NC¹NC¹NC¹NC¹

NC¹NC¹NC¹NC¹NC¹NC¹NC¹NC¹

D

I/O

202

I/O

200

I/O

133

NC¹TRST GND

E

GND

MODE/ I/O

TMS

I/O

203

I/O

132

I/O

131

I/O

130

NC¹

F

204

I/O

206

I/O

205

I/O

129

I/O

128

NC¹NC¹

NC¹TOE

G

I/O

209

I/O

208

I/O

127

I/O

126

NC¹

H

207

I/O

211

I/O

210

I/O

NC¹

I/O

124

NC¹

GND

J

GND

125

I/O

212

TDI/

SDI

I/O

NC¹

I/O

122

NC¹

VCC

Y2

K

VCC

123

I/O

214

I/O

213

I/O

121

NC¹NC¹

L

I/O

217

I/O

216

I/O

215

I/O

NC¹

I/O

119

I/O

118

NC¹

M

120

I/O

117

I/O

116

I/O

218

NC¹

GND

N

Y1

GND

I/O

219

I/O

115

VCC NC¹NC¹

NC¹NC¹VCC

P

I/O

222

I/O

221

I/O

220

I/O GOE I/O

NC¹

R

NC¹

R

113

0

114

ispLSI 3448

I/O

111

I/O

112

I/O

0

I/O

223

T

GND

I/O

108

I/O

109

I/O

110

I/O

2

I/O

1

U

Y0

U

Bottom View

I/O

3

VCC NC¹NC¹

NC¹NC¹VCC

I/O

107

V

I/O

106

GOE

1

W

Y

NC¹

GND

W

Y

I/O

4

I/O

5

NC¹

GND

I/O

103

I/O

104

I/O

105

I/O

6

I/O

7

I/O

8

NC¹

I/O

9

I/O

101

I/O

102

NC¹NC¹

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

RESET

NC¹NC¹

I/O

10

I/O

100

NC¹

Y3

VCC

NC¹

I/O

11

I/O

12

I/O

NC¹

13

I/O

98

I/O

99

NC¹

GND

I/O

14

I/O ispEN/

15 BSCAN

I/O

95

I/O

96

I/O

97

NC¹

I/O

16

I/O

17

I/O

93

I/O

94

NC¹NC¹

I/O

18

I/O

19

I/O

NC¹

20

I/O

NC¹

I/O

92

Y4

91

I/O

21

TCK/

NC¹

I/O

NC¹

I/O

90

GND

SCLK

88

NC¹

I/O

22

I/O

23

I/O

25

TDO/ I/O

I/O

89

NC¹NC¹NC¹NC¹NC¹

NC¹NC¹

NC¹NC¹NC¹

NC¹NC¹NC¹NC¹NC¹NC¹NC¹NC¹

NC¹NC¹NC¹NC¹NC¹NC¹

SDO

87

I/O

69

I/O

24

I/O

26

I/O

29

I/O

32

I/O

37

I/O

40

I/O

42

I/O

46

I/O

49

I/O

52

I/O

55

I/O

57

I/O

62

I/O

65

I/O

71

I/O

74

I/O

79

I/O

82

I/O

85

I/O

86

VCC

NC¹

VCC

I/O

68

I/O

27

I/O

28

I/O

33

I/O

35

I/O

38

I/O

43

I/O

44

I/O

47

I/O

53

I/O

56

I/O

58

I/O

64

I/O

67

I/O

73

I/O

76

I/O

78

I/O

83

I/O

84

GND NC¹

GND

GND VCC

VCC GND

GND

NC¹GND

I/O

30

I/O

31

I/O

34

I/O

36

I/O

39

I/O

41

I/O

45

I/O

48

I/O

50

I/O

51

I/O

54

I/O

59

I/O

60

I/O

61

I/O

63

I/O

66

I/O

70

I/O

72

I/O

75

I/O

77

I/O

80

I/O

81

VCC

GND GND VCC

VCC

GND

VCC GND GND

9

8

7

6

5

4

3

2

1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

1. NCs are not to be connected to any active signals, VCC or GND.

Note: Ball A1 indicator dot on top side of package.

13

Specifications ispLSI 3448

Part Number Description

–

ispLSI

XX X XXXX X

3448

Device Family

Grade

Blank = Commercial

Device Number

Speed

Package

B432 = BGA

90 = 90 MHz

70 = 70 MHz

f

max

Power

L = Low

0212/3448

Ordering Information

COMMERCIAL

FAMILY

ispLSI

fmax (MHz)

tpd (ns)

12

ORDERING NUMBER

PACKAGE

432-Ball BGA

90

70

ispLSI 3448-90LB432

ispLSI 3448-70LB432

15

Table 2-0041/3448

14


型号：	ISPLSI3448-90LB432
厂家：	LATTICE SEMICONDUCTOR
描述：	In-System Programmable High Density PLD 在系统可编程高密度PLD 可编程逻辑器件输入元件时钟
文件：	总14页 (文件大小：173K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISPLSI3448-90LB432 [LATTICE]

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