ISPLSI5128VE-125LT128I [LATTICE]
In-System Programmable 3.3V SuperWIDE High Density PLD; 在系统可编程3.3V超宽高密度PLD
| 型号： | ISPLSI5128VE-125LT128I |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | In-System Programmable 3.3V SuperWIDE High Density PLD |
| 文件： | 总21页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispLSI 5128VE
In-System Programmable
3.3V SuperWIDE™ High Density PLD
Features
Functional Block Diagram
• Second Generation SuperWIDE HIGH DENSITY
IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
— 3.3V Power Supply
Input Bus
Boundary
Scan
Interface
Generic
Logic Block
— User Selectable 3.3V/2.5V I/O
— 6000 PLD Gates / 128 Macrocells
— 96 I/O Pins Available
— 128 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
Global Routing Pool
(GRP)
—
Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
Generic
Logic Block
Input Bus
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
ispLSI 5000VE Description
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
The ispLSI 5000VE Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
— Programmable I/O Supports Programmable Bus
Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two
Global OE Pins and One Product Term OE per
Macrocell
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and three extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
in both true and complement form for every product term.
The 160 product terms are grouped in 32 sets of five and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of five product terms or less. The
three extra product terms are used for shared controls:
reset, clock, clock enable and output enable.
Copyright©2002LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
5128ve_05
1
Specifications ispLSI 5128VE
Functional Block Diagram
Figure 1. ispLSI 5128VE Functional Block Diagram (96-I/O)
Input Bus
Generic
TDI
Boundary
Scan
Interface
TDO
VCCIO
Logic Block
I/O 71
I/O 70
I/O 69
I/O 68
1
TOE
I/O 1
I/O 2
I/O 3
Global Routing Pool
(GRP)
I/O 51
I/O 50
I/O 49
I/O 48
I/O 20
I/O 21
I/O 22
I/O 23
Generic
Logic Block
Input Bus
RESET
1. CLK2, CLK3 and TOE signals are shared with I/O signals. Use the table below to determine which I/O is shared.
Package Type
Multplexed Signals
128 TQFP
I/O 59 / CLK2
I/O 65 / CLK3
I/O 0 / TOE
2
Specifications ispLSI 5128VE
The ispLSI 5000VE Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface. Boundary Scan test is also
supported through the same interface.
ispLSI 5000VE Description (Continued)
The32registeredmacrocellsintheGLBaredrivenbythe
32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch and the necessary clocks and
control logic to allow combinatorial or registered opera-
tion.Themacrocellseachhavetwooutputs,combinatorial
and registered. This dual output capability from the
macrocell allows efficient use of the hardware resources.
One output can be a registered function for example,
while the other output can be an unrelated combinatorial
function. A direct register input from the I/O pad facili-
tates efficient use of this feature to construct high-speed
input registers.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 5000VE Family Members
Macrocell registers can be clocked from one of several
global or product term clocks available on the device. A
global and product term clock enable is also available to
eachregister, eliminatingtheneedtogatetheclocktothe
macrocell registers. Reset for the macrocell register is
provided from the global signal, its polarity is user-
selectable.Themacrocellregistercanbeprogrammedto
operate as a D-type register or a D-type latch.
The ispLSI 5000VE Family ranges from 128 macrocells
to 512 macrocells and operates from a 3.3V power
supply. All family members will be available with multiple
package options. The ispLSI 5000VE Family device
matrix showing the various bondout options is shown in
the table below.
Theinterconnectstructure(GRP)isverysimilartoLattice's
existing ispLSI 1000, 2000 and 3000 families, but with an
enhanced interconnect structure for optimal pin locking
and logic routing. This eliminates the need for registered
I/O cells or an Output Routing Pool.
The 32 outputs from the GLB can drive both the Global
RoutingPoolandthedeviceI/Ocells.TheGlobalRouting
Pool contains one input from each macrocell output and
one input from each I/O pin.
The ispLSI 5000VE encompasses the innovative fea-
tures of the ispLSI 5000VA family with several
enhancements. The macrocell is optimized and the T-
type flip flop option is removed. To improve the efficiency
of design fits, the Product Term Reset Logic is simplified
and the polarity option as well as the Global Preset
function are removed. The programmable output-delay
feature (skew option) is also removed. As a result, the
ispLSI 5000VE is not JEDEC compatible with the ispLSI
5000VA. ispLSI 5000VA and 5000VE pinouts may differ
in the same package, however all programming and
power/ground pins are located in the same locations.
The input buffer threshold has programmable TTL/3.3V/
2.5V compatible levels. The output driver can source
4mA and sink 8mA in 3.3V mode. The output drivers
have a separate VCCIO reference input which is inde-
pendent of the main VCC supply for the device. This
feature allows individual output drivers to drive either
3.3V (from the device VCC) or 2.5V (from the VCCIO pin)
outputlevelswhilethedevicelogicandtheoutputcurrent
drive are powered from device supply (VCC). The output
drivers also provide individually programmable edge
rates and open drain capability. A programmable pullup
resistor is provided to tie off unused inputs. Additionally,
aprogrammablebus-holdlatchisavailabletoholdtristate
outputs in their last valid state until the bus is driven again
by some device.
Table 1. ispLSI 5000VE Family
Package Type
Device
GLBs
4
Macrocells 100 TQFP 128 TQFP 256 fpBGA 272 BGA 388 fpBGA 388 BGA
ispLSI 5128VE
128
256
384
512
—
72 I/O
—
96 I/O
96 I/O
—
—
—
—
—
—
—
ispLSI 5256VE
ispLSI 5384VE
ispLSI 5512VE
8
144 I/O
192 I/O
192 I/O
144 I/O
192 I/O
192 I/O
12
16
—
—
—
—
256 I/O
256 I/O
3
Specifications ispLSI 5128VE
Figure 2. ispLSI 5128VE Block Diagram (96 I/O)
24
24
CLK2
24
I/O
24
I/O
32
32
CLK3
GLB2
32
GLB1
32
Q
D
D
Q
24
32
32
24
160
160
3
PT
160
PT
160
PT
3
PT
3
160
160
3
68
68
24
32
24
32
24
I/O
24
IO0/TOE
I/O
GLB3
GLB0
32
32
Q
D
D
Q
24
32
32
24
224
160
160
3
PT
160
PT
160
PT
3
PT
CLK0
CLK1
3
160
160
3
GOE0
GOE1
RESET
68
68
4
Specifications ispLSI 5128VE
Figure 3. ispLSI 5000VE Generic Logic Block (GLB)
From GRP
0
1
2
66 67
Global PTOE Bus
PTSA
PT 0
PT 1
PT 2
PT 3
PT 4
Macrocell 0
From PTSA
To I/O Pad
PTSA bypass
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock
Shared PT Reset
Global PTOE 0 ... 3
To GRP
4
PT 9
PT 8
PT 7
PT 6
PT 5
Macrocell 1
From PTSA
To I/O Pad
PTSA bypass
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock
Shared PT Reset
Global PTOE 0 ... 3
To GRP
4
PT 79
PT 78
PT 77
PT 76
PT 75
Macrocell 15
From PTSA
To I/O Pad
PTSA bypass
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock
Shared PT Reset
Global PTOE 0 ... 3
To GRP
4
PT 159
PT 158
PT 157
PT 156
PT 155
Macrocell 31
From PTSA
To I/O Pad
PTSA bypass
PTOE
PT Clock
PT Reset
PT Preset
PT 160
PT 161
Shared PT Clock
Shared PT Reset
Global PTOE 0 ... 3
To GRP
4
PT 162
5
Specifications ispLSI 5128VE
Figure 4. ispLSI 5000VE Macrocell
VCCIO
VCC
VCCIO
Global PTOE 0
Global PTOE 1
Global PTOE 2
Global PTOE 3
PTOE
GOE0
GOE1
TOE
PTSA bypass
I/O Pad
D
Q
PTSA
Slew
rate
Open
drain
Clk En
To GRP
To GRP
PT Clock
2.5V/3.3V
Output
R/L
Input threshold
2.5V/3.3V
Shared PT Clock
CLK0
Clk
R
CLK1
CLK2
CLK3
P
PT Reset
Shared PT Reset
Global Reset
PT Preset
speed/
power
Note: Not all macrocells have I/O pads.
6
Specifications ispLSI 5128VE
speed. The clock inversion is available on the remaining
CLK1 - CLK3 signals. By sharing the pins with the I/O
pins, CLK2 and CLK3 can not only be inverted but are
also available for logic implementation through GRP
signal routing. Figure 5 shows these different clock
distribution options.
Global Clock Distribution
TheispLSI5000VEFamilyhasfourdedicatedclockinput
pins: CLK0 - CLK3. CLK0 input is used as the dedicated
master clock that has the lowest internal clock skew with
no clock inversion to maintain the fastest internal clock
Figure 5. ispLSI 5000VE Global Clock Structure
CLK 0
(dedicated pin)
CLK0
CLK1
CLK 1
(dedicated pin)
IO/CLK 2
(shared pin)
to/from GRP
CLK2
CLK3
IO/CLK 3
to/from GRP
(shared pin)
RESET
(dedicated pin)
Global Reset
IO0/TOE
(shared pin)
to/from GRP
TOE
7
Specifications ispLSI 5128VE
Figure 6. Boundary Scan Register Circuit for I/O Pins
HIGHZ
EXTEST
SCANIN
(from previous
cell)
TOE
BSCAN
Registers
BSCAN
Latches
Normal
Function
0
1
0
OE
D
D
D
Q
Q
Q
D
Q
1
EXTEST
PROG_MODE
Normal
0
Function
I/O Pin
1
0
D
Q
1
1
0
SCANOUT
(to next cell)
Shift DR
Clock DR
Update DR
Reset
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Input Pin
0
SCANOUT
(to next cell)
SCANIN
(from previous
cell)
D
Q
1
Shift DR
Clock DR
8
Specifications ispLSI 5128VE
Figure 8. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
T
T
bth
btsu
T
T
T
btcp
btch
btcl
TCK
TDO
T
T
T
btoz
btvo
btco
Valid Data
Valid Data
T
T
btcpsu
btcph
Data to be
captured
Data Captured
T
T
T
btuoz
btuov
btuco
Data to be
driven out
Valid Data
Valid Data
SYMBOL PARAMETER
MIN
MAX UNITS
t
125
62.5
62.5
25
25
50
–
–
ns
ns
btcp
btch
TCK [BSCAN test] clock pulse width
TCK [BSCAN test] pulse width high
TCK [BSCAN test] pulse width low
TCK [BSCAN test] setup time
t
t
–
–
ns
btcl
t
t
t
t
t
t
t
t
t
t
t
–
ns
btsu
bth
–
ns
TCK [BSCAN test] hold time
–
mV/ns
ns
rf
TCK [BSCAN test] rise and fall time
TAP controller falling edge of clock to valid output
25
25
25
–
btco
btoz
btvo
btcpsu
btcph
btuco
btuoz
btuov
–
ns
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
–
ns
25
25
–
ns
–
ns
BSCAN test Capture register hold time
50
50
50
ns
BSCAN test Update reg, falling edge of clock to valid output
–
ns
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
–
ns
9
Specifications ispLSI 5128VE
1, 2
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +5.4V
cc
Input Voltage Applied............................... -0.5 to +5.6V
Tri-Stated Output Voltage Applied........... -0.5 to +5.6V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Condition
SYMBOL
PARAMETER
Supply Voltage
I/O Reference Voltage
MIN.
3.00
3.00
2.3
MAX.
3.60
3.60
3.60
UNITS
T = 0°C to +70°C
Commercial
Industrial
V
V
A
V
CC
CCIO
T = -40°C to +85°C
A
V
V
Table 2-0005/5KVE
Capacitance (TA=25°C,f=1.0 MHz)
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
CC= 3.3V, VI/O = 0.0V
CC= 3.3V, VCK = 0.0V
CC= 3.3V, VG = 0.0V
10
pf
V
I/O Capacitance
C1
C2
C3
10
10
pf
pf
V
Clock Capacitance
V
Global Input Capacitance
Table 2-0006/5KVE
Erase Reprogram Specification
PARAMETER
MINIMUM
10000
MAXIMUM
UNITS
ispLSI Erase/Reprogram Cycles
–
Cycles
Table 2-0008/5KVE
10
Specifications ispLSI 5128VE
Switching Test Conditions
Figure 9. Test Load
Input Pulse Levels
GND to VCCIO
min
Input Rise and Fall Time
Input Timing Reference Levels
Ouput Timing Reference Levels
Output Load
≤ 1.5ns 10% to 90%
V
CCIO
1.5V
1.5V
R
1
2
See Figure 9
Device
Output
Test
Point
Table 2-0003/5KVE
3-state levels are measured 0.5V from
steady-state active level.
R
C
*
L
Output Load Conditions (See Figure 9)
*
C includes Test Fixture and Probe Capacitance.
L
3.3V
R2
316Ω 348Ω 511Ω 475Ω 35pF
2.5V
0213D
TEST CONDITION
R1
R1
R2
CL
A
Active High
Active Low
∞
348Ω
∞
475Ω 35pF
35pF
475Ω 5pF
B
316Ω
∞
511Ω
∞
Active High to Z
at VOH-0.5V
∞
348Ω
∞
C
D
Active Low to Z
at VOL+0.5V
316Ω
∞
∞
511Ω
∞
∞
5pF
Slow Slew
∞
∞
35pF
Table 2-0004A/5KVE
DC Electrical Characteristics for 3.3V Range1
Over Recommended Operating Conditions
SYMBOL
PARAMETER
I/O Reference Voltage
CONDITION
MIN.
3.0
-0.3
2.0
–
TYP. MAX. UNITS
–
–
–
–
–
3.6
0.8
5.25
0.4
–
V
V
V
V
V
VCCIO
VIL
VIH
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VCCIO = min, IOL = 8 mA
VCCIO = min, IOH = -4 mA
2.4
Table 2-0007/5KVE
1. I/O voltage configuration must be set to VCC.
11
Specifications ispLSI 5128VE
DC Electrical Characteristics for 2.5V Range1
Over Recommended Operating Conditions
SYMBOL
PARAMETER
I/O Reference Voltage
CONDITION
MIN.
2.3
TYP. MAX. UNITS
–
–
–
2.7
0.7
V
V
V
V
V
V
CCIO
Input Low Voltage
Input High Voltage
-0.3
1.7
IL
5.25
IH
VCCIO=min, IOL= 100µA
–
–
–
–
–
–
0.2
0.6
–
V
V
V
Output Low Voltage
Output High Voltage
V
OL
VCCIO=min, IOL= 2mA
VCCIO=min, IOH= -100µA
VCCIO=min, IOH= -2mA
2.1
1.8
VOH
–
V
2.5V/5128VE
1. I/O voltage configuration must be set to VCCIO.
DC Electrical Characteristics
Over Recommended Operating Conditions
PARAMETER CONDITION
0V ≤ VIN≤ VIL(Max.)
SYMBOL
MIN.
–
TYP. MAX. UNITS
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
–
–
–
–
–
–
–
–
–
–
-10
10
µA
µA
µA
µA
µA
µA
µA
µA
V
I
I
IL
(VCCIO-0.2)V ≤ VIN ≤ VCCIO
–
IH
VCCIO ≤ VIN ≤ 5.25V
0V ≤ VIN ≤ VIL
–
50
I
I
I
I
I
I
PU1
I/O Active Pullup Current
–
-200
–
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
40
-40
–
VIN = VIL(max)
BHL
–
VIN = VIH(min)
BHH
BHLO
BHLH
BHT
0V ≤ VIN ≤ VCCIO
550
-550
VIH
30
–
0V ≤ VIN ≤ VCCIO
VIL
–
Current Needed for VCCIO Pin
All I/Os Pulled-up, (Total I/Os * IPUmax
)
mA
I
VCCIO
DC Char_5KVE
1. Pullup is capable of pulling to a minimum voltage of VOH under no-load conditions.
12
Specifications ispLSI 5128VE
External Switching Characteristics
Over Recommended Operating Conditions
TEST3
COND.
-180
-125
DESCRIPTION 4,5
UNITS
PARAM.
MIN. MAX. MIN. MAX.
6
A
A
Data Prop. Delay, 5PT Bypass
—
—
5.0
7.0
—
—
—
7.5
9.5
—
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
6
Data Propagation Delay
pd2
A
Clock Frequency with Internal Feedback1
Clock Freq. with Ext. Feedback,1/(tsu2 + tco1)
Clock Frequency, Max Toggle2
180
133
227
3.5
—
125
87
MHz
MHz
MHz
ns
max
—
—
—
A
—
—
max (Ext.)
max (Tog.)
su1
—
167
5.0
—
—
GLB Reg. Setup Time before Clk, 5PT bypass
GLB Reg. Clock to Output Delay
—
—
6
3.0
—
4.5
—
ns
co1
—
—
—
—
—
A
GLB Reg. Hold Time after Clock, 5PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Hold Time after Clock
0.0
4.5
0.0
2.5
0.5
—
0.0
7.0
0.0
3.5
0.5
—
ns
h1
—
—
ns
su2
h2
—
—
ns
GLB Reg. Setup Time before Clock, Input Reg. Path
GLB Reg. Hold Time after Clock, Input Reg. Path
Ext. Reset Pin to Output Delay
—
—
ns
su3
h3
—
—
ns
6.0
—
10.0
—
ns
r1
7
—
Ext. Reset Pulse Duration
3.5
—
5.0
—
ns
rw1
6
B/C Local Product Term Output Enable/Disable
B/C Global Product Term Output Enable/Disable
B/C Global OE Input to Output Enable/Disable
B/C Test OE Input to Output Enable/Disable
6.0
7.0
3.5
5.5
8.5
14.0
5.5
10.5
ns
pten/dis
6
—
—
ns
gpten/dis
6
—
—
ns
gen/dis
6
—
—
ns
ten/dis
—
—
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
2.2
2.2
—
—
3.0
3.0
—
—
ns
ns
t
wh
wl
t
1. Standard 16-bit counter using GRP feedback.
2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
3. Reference Switching Test Conditions section.
Timing Ext.5128ve1.eps
Timing v.2.0
4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, CLK0, and high-
speed AND array.
5. Timing parameters measured using normal active output driver.
6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
7. Pulse widths less than minimum may cause unknown output behavior.
13
Specifications ispLSI 5128VE
External Switching Characteristics
Over Recommended Operating Conditions
TEST3
COND.
-100
-80
DESCRIPTION 4,5
UNITS
PARAM.
MIN. MAX. MIN. MAX.
6
A
A
Data Prop. Delay, 5PT Bypass
—
—
10.0
12.0
—
—
—
12.0
15.0
—
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
6
Data Propagation Delay
pd2
A
Clock Frequency with Internal Feedback1
Clock Freq. with Ext. Feedback,1/(tsu2 + tco1)
Clock Frequency, Max Toggle2
100
67
80
MHz
MHz
MHz
ns
max
—
—
—
A
—
56
—
max (Ext.)
max (Tog.)
su1
125
7.0
—
—
100
8.0
—
—
GLB Reg. Setup Time before Clk, 5PT bypass
GLB Reg. Clock to Output Delay
—
—
6
6.0
—
7.0
—
ns
co1
—
—
—
—
—
A
GLB Reg. Hold Time after Clock, 5PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Hold Time after Clock
0.0
9.0
0.0
4.5
1.0
—
0.0
11.0
0.0
5.5
1.0
—
ns
h1
—
—
ns
su2
h2
—
—
ns
GLB Reg. Setup Time before Clock, Input Reg. Path
GLB Reg. Hold Time after Clock, Input Reg. Path
Ext. Reset Pin to Output Delay
—
—
ns
su3
h3
—
—
ns
11.5
—
13.0
—
ns
r1
7
—
Ext. Reset Pulse Duration
6.5
—
8.0
—
ns
rw1
6
B/C Local Product Term Output Enable/Disable
B/C Global Product Term Output Enable/Disable
B/C Global OE Input to Output Enable/Disable
B/C Test OE Input to Output Enable/Disable
10.0
15.5
7.5
11.5
12.0
17.0
9.0
12.5
ns
pten/dis
6
—
—
ns
gpten/dis
6
—
—
ns
gen/dis
6
—
—
ns
ten/dis
—
—
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
4.0
4.0
—
—
5.0
5.0
—
—
ns
ns
t
wh
wl
t
1. Standard 16-bit counter using GRP feedback.
2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
3. Reference Switching Test Conditions section.
Timing Ext.5128ve2.eps
Timing v.2.0
4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, CLK0, and high-
speed AND array.
5. Timing parameters measured using normal active output driver.
6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O reference.
7. Pulse widths less than minimum may cause unknown output behavior.
used as I/O voltage reference.
14
Specifications ispLSI 5128VE
Internal Timing Parameters
Over Recommended Operating Conditions
-180
-125
-100
-80
PARAMETER
In/Out Delays
DESCRIPTION
MIN MAX MIN MAX MIN MAX MIN MAX UNIT
tin
Input Buffer Delay
–
–
–
–
–
–
–
0.9
1.0
4.4
2.5
1.1
1.0
1.0
–
–
–
–
–
–
–
1.3
1.3
6.6
3.9
2.2
1.6
1.6
–
–
–
–
–
–
–
2.3
1.8
7.1
5.9
2.7
1.6
1.6
–
–
–
–
–
–
–
2.3
1.8
7.1
7.4
3.7
1.6
1.6
ns
ns
ns
ns
ns
ns
ns
tgclk_in
trst
Global Clock Buffer Input Delay (clk0)
Global Reset Pin Delay
Global OE Pin Delay
tgoe
tbuf
ten
Output Buffer Delay
Output Enable Delay
tdis
Output Disable Delay
Routing/GLB Delays
troute
tpdb
tpdi
GRP and Logic Delay
–
–
–
–
–
–
2.7
0.3
1.0
1.3
0.0
2.0
–
–
–
–
–
–
3.6
0.4
0.0
2.4
0.0
2.5
–
–
–
–
–
–
4.0
1.0
0.0
3.0
0.0
2.5
–
–
–
–
–
–
4.5
1.5
0.0
4.5
0.5
3.5
ns
ns
ns
ns
ns
ns
5-pt Bypass Propagation Delay
Combinatorial Propagation Delay
Product Term Sharing Array
tptsa
tfbk
Internal Feedback Delay
tinreg
Input Buffer to Macrocell Register Delay
Register/Latch Delays
ts
Register Setup Time
0.6
0.6
2.4
–
–
–
1.0
1.0
3.0
–
–
–
1.5
1.5
4.0
–
–
–
1.5
1.5
5.0
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ts_pt
th
Register Setup Time (Product Term Clock)
Register Hold Time
–
–
–
–
tcoi
Register Clock to GLB Output Delay
Latch Setup Time
0.9
–
1.0
–
1.5
–
1.5
–
tsl
0.6
2.4
–
1.0
3.0
–
1.5
4.0
–
1.5
5.0
–
thl
Latch Hold Time
–
–
–
–
tgoi
Latch Gate to GLB Output Delay
GLB Latch propagation Delay
Clock Enable Setup Time
0.9
1.0
–
1.0
1.5
–
1.5
2.0
–
1.5
2.5
–
tpdli
tces
tceh
tsri
–
–
–
–
4.1
0.3
–
4.3
1.7
–
5.3
2.7
–
6.3
3.7
–
Clock Enable Hold Time
–
–
–
–
Asynchronous Set/Reset to GLB Output Delay
Asynchronous Set/Reset Recovery Time
0.5
–
1.2
–
1.7
–
2.2
–
tsrr
1.1
1.2
1.2
2.2
Control Delays
tptclk
tbclk
tptsr
tbsr
Macrocell PT Clock Delay
Block PT Clock Delay
–
–
–
–
–
–
0.4
1.4
1.8
2.8
1.4
2.4
–
–
–
–
–
–
0.4
1.9
3.7
5.7
2.0
7.5
–
–
–
–
–
–
0.5
2.5
4.8
6.8
2.1
7.6
–
–
–
–
–
–
0.5
2.5
4.8
6.8
3.6
8.6
ns
ns
ns
ns
ns
ns
Macrocell PT Set/Reset Delay
Block PT Set/Reset Delay
Macrocell PT OE Delay
Global PT OE Delay
tptoe
tgptoe
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet Timing v.2.0
for further details.
15
Specifications ispLSI 5128VE
ispLSI 5128VE Timing Parameters (continued)
ADDER
BASE PARAMETER
-180
-125
-100
-80
ADDER TYPE
UNITS
Routing Adders
tlp
1.0
1.5
1.5
1.5
ns
troute
Tioi Input Adders
clk1
0.9
1.4
1.4
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
ns
ns
ns
tgclk_in
tgclk_in
t
gclk_in
clk2
clk3
Tioo Output Adders1
Slow Slew I/O
LVTTL_out
LVCMOS25_out
LVCMOS33_out
4.0
0.0
0.5
0.0
4.0
0.0
0.5
0.0
4.0
0.0
0.5
0.0
4.0
0.0
0.5
0.0
ns
ns
ns
ns
t
buf, en
t
t
t
t
buf,
buf,
buf,
ten,
ten,
ten,
tdis
tdis
tdis
Tbla Additional Block Loading Adders
1
0.1
0.2
0.3
0.1
0.2
0.3
0.1
0.2
0.3
0.1
0.2
0.3
ns
ns
ns
t
t
t
route
route
route
2
3
1
Timing for open drain configurations is the same as non-open drain configurations.
Timing Table/5128VE
Timing v.2.0
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for
details.
16
Specifications ispLSI 5128VE
ispLSI 5128VE Timing Model
Routing/
GLB Delays
From Feedback
tPDb
Feedback
tPDi
tFBK
tROUTE
tBLA
tLP
tBUF
tEN
tDIS
tIOO
tPTSA
DATA
OUT
tIN
IN
Q
tINREG
In/Out
Delays
tGCLK_IN
tIOI
CLK
tPTCLK
tBCLK
CE
tPTSR
tBSR
S/R
MC Reg
tRST
Register/
Latch Delays
RST
OE
tGPTOE
tPTOE
tGOE
Control
Delays
5000VE Timing Model
In/Out
Delays
Note: Italicized parameters are delay adders above and beyond default conditions (i.e. GRP load of one GLB, CLK0, high-speed AND Array
and VCC I/O option).
17
Specifications ispLSI 5128VE
Power Consumption
Power consumption in the ispLSI 5128VE device de- setting operates product terms at their normal full power
pends on two primary factors: the speed at which the consumption. For portions of the logic that can tolerate
device is operating and the number of product terms longer propagation delays, selecting the slower “low-
used. The product terms have a fuse-selectable speed/ power” setting will reduce the power dissipation for these
power tradeoff setting. Each group of five product terms product terms. Figure 10 shows the relationship between
has a single speed/power tradeoff control fuse that acts power and operating frequency.
on the complete group of five. The fast “high-speed”
Figure 10. Typical Device Power Consumption vs fmax
180
165
150
135
120
105
90
ispLSI 5128VE
High Speed Mode
ispLSI 5128VE
Low Power Mode
0
25
50
75
100
125
150
175
200
f
max (MHz)
Notes: Configuration of 8 16-bit Counters
Typical Current at 3.3V, 25° C
I
can be estimated for the ispLSI 5128VE using the following equation:
CC
High Speed Mode: ICC = 12.4 + (# of PTs * 0.408) + (# of nets * Fmax * 0.00169)
Low Power Mode: ICC = 12.4 + (# of PTs * 0.349) + (# of nets * Fmax * 0.00169)
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Fmax = Highest Clock Frequency to the device
The I
estimate is based on typical conditions (V
= 3.3V, room temperature) and an assumption of one GLB load
CC
CC
on average exists. These values are for estimates only. Since the value of I
and the program in the device, the actual I
is sensitive to operating conditions
CC
should be verified.
CC
0127/5128VE
18
Specifications ispLSI 5128VE
Signal Descriptions
Signal Name
Description
TMS
Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine.
Input - This pin is the Test Clock input pin used to clock through the JTAG state machine.
Input - This pin is the JTAG Test Data In pin used to load data.
TCK
TDI
TDO
Output - This pin is the JTAG Test Data Out pin used to shift data out.
TOE / I/O0
Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon
customer's design. TOE tristates all I/O pins when a logic low is driven.
GOE0, GOE1
RESET
Input - These two pins are the Global Output Enable input pins.
Dedicated Reset Input - This pin resets all registers in the device. The global polarity (active
high or low input) for this pin is selectable.
I/O
Input/Output – These are the general purpose I/O used by the logic array.
GND
Ground
Vcc
VCC
CLK0, CLK1
Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock
input to all registers in the device.
CLK2 / I/O,
CLK3 / I/O
Input/Output - These pins share functionality. They can be used as dedicated clock inputs for
all registers, as well as I/O pins.
VCCIO
Input-Thispinisusedforoptional2.5Voutputs.EveryI/Ocanindependentlyselecteither3.3V
or the optional voltage as its output level. If the optional output voltage is not required, this pin
must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches
only draw current from this supply.
19
Specifications ispLSI 5128VE
Pin Configuration
ispLSI 5128VE 128-Pin TQFP (0.4mm Lead Pitch / 14.0mm x 14.0mm Body Size)
1
2
3
4
5
96
95
94
93
92
91
90
89
88
87
86
85
84
I/O 82
I/O 83
I/O 84
I/O 85
I/O 86
I/O 87
GND
VCC
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
VCC
6
7
I/O 88
VCC
8
9
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
GND
TMS
TCK
TDI
VCC
10
11
12
RESET
VCCIO
TDO
13
14
83
82
GND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
VCC
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
ispLSI 5128VE
Top View
I/O 0/TOE
I/O 1
I/O 41
GND
I/O 2
I/O 3
I/O 4
GND
I/O 5
VCC
I/O 6
I/O 7
I/O 8
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
I/O 35
VCC
128 TQFP/5128VE
20
Specifications ispLSI 5128VE
Part Number Description
ispLSI 5128VE – XXX X XXXX X
Device Family
Grade
Blank = Commercial
I = Industrial
Device Number
Package
T128 = 128-Pin TQFP
Speed
180 = 180 MHz
125 = 125 MHz
100 = 100 MHz
fmax
fmax
fmax
Power
L = Low
0212/5128ve
80 = 80 MHz fmax
Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
180
tpd (ns)
5.0
ORDERING NUMBER
ispLSI 5128VE-180LT128
ispLSI 5128VE-125LT128
ispLSI 5128VE-100LT128
PACKAGE
128-Pin TQFP
128-Pin TQFP
128-Pin TQFP
125
7.5
100
10
Table 2-0041A/5128VE
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
7.5
ORDERING NUMBER
ispLSI 5128VE-125LT128I
ispLSI 5128VE-100LT128I
ispLSI 5128VE-80LT128I
PACKAGE
128-Pin TQFP
128-Pin TQFP
128-Pin TQFP
125
100
80
10
12
Table 2-0041B/5128VE
The ispLSI 5128VE is dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster
(i.e. ispLSI 5128VE-180LT128) than the Industrial speed grade (i.e. ispLSI 5128VE-125LT128I).
21
相关型号：
©2020 ICPDF网 联系我们和版权申明