IS61LV12824-9B [ETC]
x24 SRAM ; X24 SRAM\n型号: | IS61LV12824-9B |
厂家: | ETC |
描述: | x24 SRAM
|
文件: | 总11页 (文件大小:80K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
IS61LV12824
128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
ISSI
DECEMBER 1999
FEATURES
DESCRIPTION
TheISSIIS61LV12824isahigh-speed, staticRAMorganized
as 131,072 words by 24 bits. It is fabricated using ISSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 8 ns with low power consumption.
• High-speed access time: 8, 9, 10, 12 ns
• CMOS low power operation
— 756 mW (max.) operating @ 8 ns
— 36 mW (max.) standby @ 8 ns
• TTL compatible interface levels
• Single 3.3V power supply
When CE1, CE2 are HIGH and CE2 is LOW (deselected), the
device assumes a standby mode at which the power dissipa-
tion can be reduced down with CMOS input levels.
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using Chip Enable
andOutputEnableinputs,CE1, CE2, CE2and OE. Theactive
LOW Write Enable (WE) controls both writing and reading of
the memory.
• Three state outputs
• Available in 119-pin Plastic Ball Grid Array
(PBGA) and 100-pin TQFP packages.
• Industrial temperature available
The IS61LV12824 is packaged in the JEDEC standard
119-pin PBGA and 100-pin TQFP.
FUNCTIONAL BLOCK DIAGRAM
128K x 24
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O23
CIRCUIT
CE2
CE1
CE2
OE
CONTROL
CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. B
04/17/01
®
ISSI
IS61LV12824
PIN CONFIGURATION - 119-pin PBGA
PIN DESCRIPTIONS
1
2
3
4
5
6
7
A0-A16
Address Inputs
A
B
C
D
E
F
NC
A11
A12
NC
A14
A13
CE2
A15
CE1
NC
A16
A5
A4
NC
I/O0-I/O23 Data Inputs/Outputs
NC
A3
NC
CE1, CE2 Chip Enable Input LOW
I/O16
CE2
NC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCCQ
I/O6
I/O7
I/O8
I/O9
CE2
OE
Chip Enable Input HIGH
Output Enable Input
Write Enable Input
No Connection
Power
I/O17 VCCQ GND GND GND
I/O18 GND GND
I/O19 VCCQ GND GND GND
I/O20 GND GND
I/O21 VCCQ GND GND GND
GND GND
I/O22 VCCQ GND GND GND
I/O23 GND GND
I/O12 VCCQ GND GND GND
I/O13 GND GND
VCCQ
GND
VCCQ
GND
VCCQ
GND
VCCQ
GND
VCCQ
GND
VCC
VCC
WE
NC
G
H
J
VCC
VCC
Vcc
VCCQ
GND
I/O Power
VCCQ
VCC
VCC
Ground
K
L
VCC
VCC
M
N
P
R
T
VCC
VCC
I/O14 VCCQ GND GND GND VCCQ I/O10
I/O15
NC
NC
A10
A9
NC
A8
A7
NC
WE
OE
NC
A0
A6
NC
A1
A2
I/O11
NC
U
NC
NC
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/17/01
®
IS61LV12824
ISSI
PIN CONFIGURATION
100-Pin TQFP
1
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
2
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
Vcc
GND
I/O0
I/O1
GND
NC
Vcc
GND
I/O16
I/O17
GND
3
Vcc
Q
VccQ
I/O2
I/O3
GND
I/O18
I/O19
GND
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Vcc
Q
VccQ
I/O4
I/O5
Vcc
NC
I/O20
I/O21
Vcc
NC
NC
GND
I/O22
I/O23
5
NC
GND
I/O6
I/O7
6
Vcc
Q
VccQ
GND
I/O8
I/O9
GND
I/O12
I/O13
7
Vcc
Q
VccQ
GND
I/O10
I/O11
Vcc
GND
NC
GND
I/O14
I/O15
Vcc
8
GND
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. B
04/17/01
®
ISSI
IS61LV12824
TRUTH TABLE
Mode
WE
CE1
CE2
CE2
OE
I/O0-I/O23
Vcc Current
Not Selected
X
X
X
H
X
X
X
L
X
X
X
H
X
X
X
High-Z
ISB1, ISB2
Output Disabled
Read
Write
H
H
L
L
L
L
H
H
H
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC
ICC
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
Parameter
Value
–0.5 to 5.0
–0.5 to Vcc + 0.5
–65 to + 150
Unit
V
V
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
Storage Temperature
VTERM
TSTG
°C
TBIAS
Temperature Under Bias:
Com.
Ind.
–10 to + 85
–45 to + 90
°C
°C
PT
Power Dissipation
DC Output Current
2.0
20
W
mA
IOUT
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC (8, 9 ns)
3.3V + 10%, – 5%
3.3V + 10%, – 5%
VCC (10, 12 ns)
3.3V 10%
–40°C to +85°C
3.3V 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
V
2.2
–0.3
–1
VCC + 0.3
V
0.8
1
V
GND ≤ VIN ≤ VCC
µA
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–1
1
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 2.0 ns).
VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width ≤ 2.0 ns).
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/17/01
®
IS61LV12824
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min. Max.
-9 ns
Min. Max.
-10ns
Min. Max.
-12ns
Min. Max. Unit
Symbol Parameter
Test Conditions
1
ICC
Vcc Dynamic Operating VCC = Max.,
Com.
Ind.
—
—
210
—
—
—
200
220
—
—
180
210
—
—
170
190
mA
mA
Supply Current
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL, f = max.
CE1, CE2, ≥ VIH, CE2 ≤ VIL
Com.
Ind.
—
—
70
—
—
—
60
70
—
—
50
55
—
—
50
55
2
ISB2
CMOSStandby
VCC = Max.,
Com.
Ind.
—
—
10
—
—
—
10
20
—
—
10
20
—
—
10
20
mA
Current(CMOSInputs)
CE1, CE2 ≥ VCC – 0.2V,
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V, f = 0
3
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
5
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
6
AC TEST CONDITIONS
7
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Unit
0V to 3.0V
2 ns
8
1.5V
Output Load
See Figures 1 and 2
9
AC TEST LOADS
319 Ω
10
11
12
3.3V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
353 Ω
5 pF
Including
jig and
scope
1.5V
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
04/17/01
®
ISSI
IS61LV12824
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
-9
-10
-12
Symbol Parameter
Min. Max.
Min. Max.
Min.
10
—
Max.
—
Min. Max.
Unit
ns
tRC
Read Cycle Time
8
—
3
—
8
9
—
3
—
9
12
—
3
—
12
—
12
tAA
Address Access Time
Output Hold Time
10
ns
tOHA
—
—
—
9
3
—
ns
tACE
tACE2
CE1, CE2 Access Time
CE2 Access Time
8
—
—
10
—
ns
tDOE
OE Access Time
—
0
4
3
—
0
4
3
—
0
4
3
—
0
4
3
ns
ns
ns
ns
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE1, CE2 to High-Z Output
(2)
tLZOE
0
—
4
0
—
5
0
—
5
0
—
6
(2)
tHZCE
0
0
0
0
tHZCE2(2) CE2 to High-Z Output
(2)
tLZCE
CE, CE2 to Low-Z Output
3
—
3
—
3
—
3
—
ns
tLZCE2(2) CE2 to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/17/01
®
IS61LV12824
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE1 = CE2 = OE = VIL; CE2 = VIH
)
1
t
RC
ADDRESS
2
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
3
READ1.eps
4
READ CYCLE NO. 2(1,3)
t
RC
5
ADDRESS
t
AA
t
OHA
OE
CS1
CS2
6
t
HZOE
t
DOE
LZOE
t
7
8
t
tAACCSS21
t
tHHZZCCSS21
t
tLLZZCCSS21
HIGH-Z
D
OUT
DATA VALID
9
CS2_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1, CE2 = VIL. CE2 = VIH.
10
11
12
3. Address is valid prior to or coincident with CE1, CE2 LOW and CE2 HIGH transition.
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
04/17/01
®
ISSI
IS61LV12824
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
-9
-10
-12
Symbol Parameter
Min. Max.
Min. Max.
Min.
Max.
Min. Max.
Unit
ns
tWC
Write Cycle Time
8
—
9
—
10
—
12
—
tSCE
tSCE2
CE1, CE2 to Write End
CE2 to Write End
7
7
—
—
8
8
—
—
8
8
—
—
9
9
—
—
ns
tAW
Address Setup Time
to Write End
7
—
8
—
8
—
9
—
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
3.5
—
0
0
—
—
—
—
—
—
3.5
—
0
0
—
—
—
—
—
—
3.5
—
0
0
—
—
—
—
—
—
3.5
—
ns
ns
ns
ns
ns
ns
ns
ns
tSA
tPWE1
tPWE2
tSD
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
6
8
8
9
6
9
9
10
5
4.5
0
5
5
tHD
0
0
0
(2)
tHZWE
—
3
—
3
—
3
—
3
(2)
tLZWE
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/17/01
®
IS61LV12824
ISSI
WRITE CYCLE NO. 1(CE Controlled, OE = HIGH or LOW)
t
WC
1
VALID ADDRESS
ADDRESS
CE1
t
tSSCCEE21
t
SA
t
HA
2
CE2
3
t
AW
t
tPPWWEE21
WE
4
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
5
t
SD
t
HD
DATAIN VALID
D
IN
6
CE2_WR1.eps
WRITE CYCLE NO. 2(1) (WE Controlled: OE = HIGH during Write Cycle)
7
t
WC
ADDRESS
OE
VALID ADDRESS
8
t
HA
9
LOW
HIGH
CE1
CE2
10
11
12
t
AW
t
PWE1
WE
t
HZWE
t
LZWE
t
SA
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
CE2_WR2.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. B
04/17/01
®
ISSI
IS61LV12824
WRITE CYCLE NO. 3(1) (WE Controlled: OE I S LOW DURING
WRITE
CYLE
)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
OE
CE1
LOW
HIGH
CE2
WE
t
t
AW
t
PWE2
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE2_WR3.eps
Note:
1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is
referenced to the rising or falling edge of the signal that terminates the Write.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/17/01
®
IS61LV12824
ISSI
ORDERING INFORMATION
1
Commercial Range: 0°C to +70°C
ORDERING INFORMATION
Speed (ns) Order Part No.
Package
Industrial Range: –40°C to +85°C
2
8
IS61LV12824-8B
IS61LV12824-8TQ
Plastic Ball Grid Array
TQFP
Speed (ns) Order Part No.
Package
9
IS61LV12824-9B
IS61LV12824-9TQ
Plastic Ball Grid Array
TQFP
9
IS61LV12824-9BI
IS61LV12824-9TQI
Plastic Ball Grid Array
TQFP
3
10
12
IS61LV12824-10B
IS61LV12824-10TQ
Plastic Ball Grid Array
TQFP
10
12
IS61LV12824-10BI
IS61LV12824-10TQI TQFP
Plastic Ball Grid Array
IS61LV12824-12B
IS61LV12824-12TQ
Plastic Ball Grid Array
TQFP
IS61LV12824-12BI
IS61LV12824-12TQI TQFP
Plastic Ball Grid Array
4
5
6
7
8
9
®
10
11
12
ISSI
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. B
04/17/01
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