HI5740_技术文档

ISL5740

TM

Data Sheet

June 2000

File Number 4821.2

PRELIMINARY

3V Dual 10-Bit, 20/40/60MSPS A/D

Features

Converter with Internal Voltage Reference

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . .20/40/60MSPS

The ISL5740 is a monolithic, dual 10-bit analog-to-digital

converter fabricated in an advanced CMOS process. It is

designed for high speed applications where integration,

bandwidth and accuracy are essential. The ISL5740

features a 9-stage pipeline architecture. The fully pipelined

architecture and an innovative input stage enable the

ISL5740 to accept a variety of input conﬁgurations, single-

ended or fully differential. Only one external clock is

necessary to drive both converters and an internal band-gap

voltage reference is provided. This allows the system

designer to realize an increased level of system integration

resulting in decreased cost and power dissipation.

• 9.1 Bits at f = 10MHz

IN

• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . .280mW

• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6mW

• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 400MHz

• SFDR at f = 10MHz. . . . . . . . . . . . . . . . . . . . . . . . .70dB

IN

• Excellent Channel-to-Channel Isolation . . . . . . . . . . .75dB

• On-Chip Sample and Hold Ampliﬁers

• Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V

• Single Supply Voltage Operation . . . . . . . . . .+2.7V - 3.6V

• TTL/CMOS(3V) Digital Inputs CMOS Digital Outputs

The ISL5740 has excellent dynamic performance while

consuming less than 280mW power at 60MSPS. The A/D

only requires a single +3.0V power supply. Data output

latches are provided which present valid data to the output

bus with a latency of 5 clock cycles.

• Offset Binary or Two’s Complement Digital Data Output

Format

• Dual 10-Bit A/D Converters on a Monolithic Chip

• Pin Compatible Upgrade to AD9288

The ISL5740 is offered in 20MSPS, 40MSPS and 60MSPS

sampling rates.

Pinout

• Wireless Local Loop

Ordering Information

• PSK and QAM I&Q Demodulators

• Medical Imaging and Instrumentation

• Wireless Communications Systems

• Battery Powered Instruments

TEMP.

SAMPLIN

G RATE

PACKAGE PKG. NO. (MSPS)

PART

NUMBER

RANGE

o

( C)

ISL5740/2IN

ISL5740/3IN

ISL5740/4IN

ISL5740/6IN

ISL5740 EVAL

-40 to 85 48 Ld LQFP

Q48.7x7

20

30

40

60

Pinout

25

Evaluation Platform

48 47 46 45 44 43 42 41 40 39 38 37

ID1

ID0

GND

DV

36

35

34

33

32

31

30

29

28

27

26

25

1

GND

I

+

2

3

IN

I

-

IN

DFS

4

5

CC

GND

AV

IV

RIN

CC

V

ROUT

6

7

AV

QV

CC

RIN

S1

GND

DV

8

CC

S2

9

GND

QD0

QD1

Q

-

10

IN

Q

+

11

12

IN

GND

13 14 15 16 17 18 19 20 21 22 23 24

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

3-1

ISL5740

Functional Block Diagram

I/Q

-

IN

I/QCLK

CLOCK

I/Q

+

IN

S/H

STAGE 1

2-BIT

FLASH

2-BIT

DAC

+

-

∑

X2

I/QD9 (MSB)

I/QD8

I/QD7

I/QD6

DIGITAL DELAY

AND

STAGE 8

I/QD5

DIGITAL ERROR

CORRECTION

I/QD4

I/QD3

2-BIT

FLASH

2-BIT

DAC

I/QD2

I/QD1

+

I/QD0 (LSB)

∑

-

X2

STAGE 9

2-BIT

FLASH

I OR Q CHANNEL

V

ROUT

I/QV

MODE

DATA FORMAT

S1/S2

DFS

REFERENCE

RIN

AV

AGND

DV

CC

DGND

CC

3-2

ISL5740

Typical Application Schematic

ISL5740

(LSB) ID0 (35)

ID0

ID1

ID2

ID3

ID4

ID5

ID6

ID7

ID8

ID9

I

+

(2) I

(3) I

+

-

IN

ID1 (36)

ID2 (37)

I

-

IN

ID3 (38)

ID4 (39)

ID5 (40)

ID6 (41)

ID7 (42)

ID8 (43)

(MSB) ID9 (44)

(LSB) QD0 (26)

QD1 (25)

QD0

QD1

QD2

QD3

QD4

QD5

QD6

QD7

QD8

QD9

Q

+

-

(11) Q

(10) Q

+

-

IN

QD2 (24)

Q

IN

QD3 (23)

QD4 (22)

QD5 (21)

QD6 (20)

QD7 (19)

QD8 (18)

(5) IV

RIN

(MSB) QD9 (17)

(6) QV

RIN

(7) V

ROUT

0.1µF

ICLK (47)

CLOCK

QCLK (14)

S1 (8)

S2 (9)

S1

S2

DFS (4)

DFS

(13,30,31,48) AV

+3V

CC

DV

CC

(15, 28, 33, 46)

3V

+

0.1µF

10µF

0.1µF

(12,29,32) AGND

DGND (16, 27, 34, 45)

DGND

10µF AND 0.1µF CAPS

ARE PLACED AS CLOSE

TO PART AS POSSIBLE

AGND

BNC

3-3

ISL5740

Pin Descriptions (Continued)

Pin Descriptions

PIN NO.

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

NAME

DESCRIPTION

Q-Channel, Data Bit 2 Output

Q-Channel, Data Bit 1 Output

Q-Channel, Data Bit 0 Output (LSB)

Digital Ground

PIN NO.

NAME

DESCRIPTION

Analog Ground

QD2

1

2

3

4

A

GND

QD1

I

I-Channel Positive Analog Input

I-Channel Negative Analog Input

IN+

QD0

I

IN-

D

DFS

Data Format Select (Low for Offset

Binary and High for Twos Complement

Output Format)

GND

DV

Digital Supply

CC

A

Analog Ground

GND

5

6

IV

I-Channel Voltage Reference Input

RIN

AV

Analog Supply

CC

V

+1.25V Reference Voltage Output

(Decouple with 0.1µF Capacitor)

ROUT

AV

Analog Supply

7

QV

Q-Channel Voltage Reference Input

Mode Select Pin 1 (See Table)

Mode Select Pin 2 (See Table)

Q-Channel Negative Analog Input

Q-Channel Positive Analog Input

Analog Ground

A

Analog Ground

RIN

S1

S2

GND

8

DV

Digital Supply

CC

9

D

Digital Ground

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Q

ID0

ID1

ID2

ID3

ID4

ID5

ID6

ID7

ID8

ID9

I-Channel, Data Bit 0 Output (LSB)

I-Channel, Data Bit 1 Output

I-Channel, Data Bit 2 Output

I-Channel, Data Bit 3 Output

I-Channel, Data Bit 4 Output

I-Channel, Data Bit 5 Output

I-Channel, Data Bit 6 Output

I-Channel, Data Bit 7 Output

I-Channel, Data Bit 8 Output

I-Channel, Data Bit 9 Output (MSB)

Digital Ground

IN-

Q

IN+

A

GND

AV

Analog Supply

CC

QCLK

Q-Channel Clock Input

DV

Digital Supply

CC

D

Digital Ground

GND

QD9

QD8

QD7

QD6

QD5

QD4

QD3

Q-Channel, Data Bit 9 Output (MSB)

Q-Channel, Data Bit 8 Output

Q-Channel, Data Bit 7 Output

Q-Channel, Data Bit 6 Output

Q-Channel, Data Bit 5 Output

Q-Channel, Data Bit 4 Output

Q-Channel, Data Bit 3 Output

D

GND

DV

Digital Supply

CC

ICLK

I-Channel Clock Input

Analog Supply

AV

CC

3-4

ISL5740

o

Absolute Maximum Ratings T = 25 C

Thermal Information

A

o

Supply Voltage, AV

CC

or DV

to AGND or DGND . . . . . . . . . . .4V

Thermal Resistance (Typical, Note 1)

θ_JA( C/W)

CC

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

70

o

Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

CC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C

o

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

o

(Lead Tips Only)

Operating Conditions

Temperature Range

o

ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Speciﬁcations AV = DV

= +3.0V; I/QV = 1.25V; f = 60MSPS at 50% Duty Cycle;

RIN S

C = 10pF; T = 25 C; Differential Analog Input, Unless Otherwise Speciﬁed

CC

o

L

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ACCURACY

Resolution

10

-

2

-

1

Bits

LSB

Integral Linearity Error, INL

f

= 10MHz

IN

Differential Linearity Error, DNL

(Guaranteed No Missing Codes)

= 10MHz

-

±0.4

±1.0

Offset Error, V

OS

f

= DC

-36

-3

-

12

1

+36

3

LSB

IN

Full Scale Error, FSE

%f

S

Gain Matching

Full Scale (Peak-to-Peak)

±1.5

6

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate

Maximum Conversion Rate

Effective Number of Bits, ENOB

No Missing Codes

-

1

-

MSPS

Bits

60

f

= 10MHz

9.1

56.8

-

IN

Signal to Noise and Distortion Ratio, SINAD

-

dB

RMS Signal

= -------------------------------------------------------------

RMS Noise + Distortion

Signal to Noise Ratio, SNR

f

= 10MHz

57

-

dB

IN

RMS Signal

= -------------------------------

RMS Noise

Total Harmonic Distortion, THD

2nd Harmonic Distortion

f

= 10MHz

-70

-

dBc

IN

-

3rd Harmonic Distortion

-

dBc

Spurious Free Dynamic Range, SFDR

Intermodulation Distortion, IMD

I/Q Channel Crosstalk

70

-

dBc

= 1MHz, f = 1.02MHz

-

dBc

1

2

-

-75

10

1

dBc

I/Q Channel Offset Match

I/Q Channel Full Scale Error Match

Transient Response

-

LSB

Cycle

-

(Note 2)

-

Over-Voltage Recovery

0.2V Overdrive (Note 2)

-

1

3-5

ISL5740

Electrical Speciﬁcations AV = DV

= +3.0V; I/QV

RIN

= 1.25V; f = 60MSPS at 50% Duty Cycle;

CC

S

o

C = 10pF; T = 25 C; Differential Analog Input, Unless Otherwise Speciﬁed (Continued)

L

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG INPUT

Maximum Peak-to-Peak Differential Analog Input

Range (I/Q + - I/Q -)

IN IN

-

±0.5

-

V

Maximum Peak-to-Peak Single-Ended

Analog Input Range

1.0

Analog Input Resistance, R

or R

V

, V = V

IN+ IN-

, DC

-

1

10

-

MΩ

pF

IN+

IN-

REF

Analog Input Capacitance, C

or C

, V = V

IN+ IN-

IN+

IN-

Analog Input Bias Current, I + or I -

, V = V

IN+ IN-

-10

10

µA

B

(Notes 2, 3)

Differential Analog Input Bias Current

= (I + - I -)

(Notes 2, 3)

-0.5

-

0.5

-

µA

I

BDIFF

B

Full Power Input Bandwidth, FPBW

(Note 2)

-

400

-

MHz

V

Analog Input Common Mode Voltage Range

Differential Mode (Note 2)

0.25

AV -0.25

CC

(V + + V -) / 2

IN IN

INTERNAL VOLTAGE REFERENCE

Reference Output Voltage, V

(Loaded)

-

1.25

1

-

V

ROUT

Reference Output Current, I

mA

ROUT

o

Reference Temperature Coefficient

200

ppm/ C

REFERENCE VOLTAGE INPUT

Reference Voltage Input, V

RIN

-

1.25

-

V

Total Reference Resistance, R

With V

= 1.25V

-

MΩ

mA

RIN

Reference Current, I

RIN

SAMPLING CLOCK INPUT

Input Logic High Voltage, V

CLK

2.0

-

0.8

1

V

IH

Input Logic Low Voltage, V

V

IL

Input Logic High Current, I

CLK, V = 5V

IH

-1

-

µA

pF

IH

Input Logic Low Current, I

CLK, V = 0V

IL

1

IL

Input Capacitance, C

CLK

-

IN

DIGITAL OUTPUTS

Output Logic High Voltage, V

OH

I

= 100µA

2.45

2.98

0.001

7

-

0.5

-

V

OH

OL

Output Logic Low Voltage, V

OL

-

Output Capacitance, C

pF

OUT

TIMING CHARACTERISTICS

Aperture Delay, t

-

100

5

-

ns

ps

AP

Aperture Delay Match

Aperture Jitter, t

-

ps

RMS

AJ

Data Output Hold, t

-

3

ns

H

Data Output Delay, t

-

4.5

7

OD

Data Latency, t

For a Valid Sample (Note 2)

Data Invalid Time (Note 2)

(Note 2)

Cycles

ns

LAT

Power-Up Initialization

-

Sample Clock Pulse Width (Low)

7.5

8.3

3-6

ISL5740

Electrical Speciﬁcations AV = DV

= +3.0V; I/QV

RIN

= 1.25V; f = 60MSPS at 50% Duty Cycle;

CC

S

o

C = 10pF; T = 25 C; Differential Analog Input, Unless Otherwise Speciﬁed (Continued)

L

A

PARAMETER

Sample Clock Pulse Width (High)

Sample Clock Duty Cycle Variation

TEST CONDITIONS

MIN

7.5

-

TYP

8.3

±5

MAX

UNITS

ns

(Note 2)

-

%

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, AV

(Note 2)

2.7

3.0

3.6

93.3

68.3

25

V

CC

Digital Supply Voltage, DV

and DV

CC2

2.7

3.0

V

CC1

Supply Current Total, I

CCT

-

mA

mW

LSB

Analog Supply Current IA

CC

-

Digital Supply Current ID

CC

Power Dissipation Total P

-

280

-

T

Offset Error Sensitivity, ∆V

OS

AV

or DV

= 3V ±5%

±0.5

CC

Gain Error Sensitivity, ∆FSE

-

CC

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

3-7

ISL5740

Timing Waveforms

ANALOG

INPUT

CLOCK

INPUT

S

H

S

H

S

H

N + 1

S

H

S

H

S

H

S

H

N + 8

N - 1

N

N + 1

N + 2

N + 5

N + 6

N + 7

N + 8

INPUT

S/H

1ST

STAGE

B ,

1 N + 7

1

N - 1

1

N

1

N + 1

1

N + 4

1

N + 5

1

N + 6

2ND

STAGE

B ,

2 N + 6

B ,

2 N

2

N + 4

2

N + 5

2

N - 2

2

N - 1

9TH

STAGE

B ,

9 N + 3

9

N - 5

9

N - 4

9

N

9

N + 1

9

N + 2

DATA

OUTPUT

D

N + 2

N - 6

N - 5

N - 1

N

N + 1

t

LAT

NOTES:

4. S : N-th sampling period.

N

5. H : N-th holding period.

N

6. B

, : M-th stage digital output corresponding to N-th sampled input.

N

M

7. D : Final data output corresponding to N-th sampled input.

N

FIGURE 1. ISL5740 INTERNAL CIRCUIT TIMING

ANALOG

INPUT

t

AP

t

AJ

CLOCK

INPUT

1.5V

t

OD

t

H

2.4V

0.5V

DATA

OUTPUT

DATA N-1

DATA N

FIGURE 2. ISL5740 INPUT TO OUTPUT TIMING

3-8

ISL5740

TABLE 1. A/D CODE TABLE

OFFSET BINARY OUTPUT CODE

DIFFERENTIAL INPUT

VOLTAGE

(I/Q + - I/Q -)

MSB

LSB

CODE CENTER

DESCRIPTION

I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0

IN IN

1

+Full Scale (+f ) - / LSB

0.499756V

0.498779V

732.422µV

-244.141µV

-0.498291V

-0.499268V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

S

4

1

+f - 1 / LSB

S

4

3

+ / LSB

4

1

- / LSB

4

3

-f + 1 / LSB

S

4

3

-Full Scale (-f ) + / LSB

S

4

NOTE:

8. The voltages listed above represent the ideal center of each output code shown with V

= +1.25V.

REFIN

Detailed Description

Theory of Operation

Φ

C

1

H

The ISL5740 is a dual 10-bit fully differential sampling pipeline

Φ

1

C

S

I/Q

IN+

A/D converter with digital error correction logic. Figure 15

depicts the circuit for the front end differential-in-differential-

out sample-and-hold (S/H) amplifiers. The switches are

controlled by an internal sampling clock which is a non-

overlapping two phase signal, Φ and Φ , derived from the

V

OUT+

+

-

Φ

2

V

+

-

OUT-

IN-

S

Φ

1

Φ

C

Φ

1

2

1

H

1

master sampling clock. During the sampling phase, Φ , the

1

input signal is applied to the sampling capacitors, C . At the

S

same time the holding capacitors, C , are discharged to

H

FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD

analog ground. At the falling edge of Φ the input signal is

1

sampled on the bottom plates of the sampling capacitors. In

As illustrated in the Functional Block Diagram and the timing

diagram in Figure 1, eight identical pipeline subconverter

stages, each containing a two-bit ﬂash converter and a two-

bit multiplying digital-to-analog converter, follow the S/H

circuit with the ninth stage being a two bit ﬂash converter.

Each converter stage in the pipeline will be sampling in one

phase and amplifying in the other clock phase. Each

individual subconverter clock signal is offset by 180 degrees

from the previous stage clock signal resulting in alternate

stages in the pipeline performing the same operation.

the next clock phase, Φ , the two bottom plates of the

2

sampling capacitors are connected together and the holding

capacitors are switched to the op amp output nodes. The

charge then redistributes between C and C completing one

S

H

sample-and-hold cycle. The front end sample-and-hold output

is a fully-differential, sampled-data representation of the

analog input. The circuit not only performs the sample-and-

hold function but will also convert a single-ended input to a

fully-differential output for the converter core. During the

sampling phase, the I/Q pins see only the on-resistance of a

switch and C . The relatively small values of these

S

components result in a typical full power input bandwidth of

400MHz for the converter.

IN

The output of each of the eight identical two-bit subconverter

stages is a two-bit digital word containing a supplementary bit

to be used by the digital error correction logic. The output of

each subconverter stage is input to a digital delay line which is

controlled by the internal sampling clock. The function of the

digital delay line is to time align the digital outputs of the eight

identical two-bit subconverter stages with the corresponding

output of the ninth stage flash converter before applying the

eighteen bit result to the digital error correction logic. The

digital error correction logic uses the supplementary bits to

correct any error that may exist before generating the final ten

bit digital data output of the converter.

Because of the pipeline nature of this converter, the digital

data representing an analog input sample is output to the

digital data bus following the 6th cycle of the clock after the

3-9

ISL5740

analog sample is taken (see the timing diagram in Figure 1).

This time delay is speciﬁed as the data latency. After the

data latency time, the digital data representing each

succeeding analog sample is output during the following

clock cycle. The digital output data is provided in offset

binary format (see Table 1, A/D Code Table).

signiﬁcantly with the value of the analog input common

mode voltage.

For the AC coupled differential input (Figure 16) and with V

RIN

connected to V

, full scale is achieved when the V and

ROUT

IN

-V input signals are 0.5V , with -V being 180 degrees

IN P-P IN

out of phase with V . The converter will be at positive full

IN

scale when the I/Q + input is at I/Q

IN VRIN

+ 0.25V and the

Internal Reference Voltage Output, V

ROUT

The ISL5740 is equipped with an internal 1.25V bandgap

reference voltage generator, therefore, no external reference

I/Q - input is at I/Q

- 0.25V (I/Q + - I/Q - = +0.5V).

IN VRIN IN IN

Conversely, the converter will be at negative full scale when

the I/Q + input is equal to I/Q - 0.25V and I/Q - is at

IN VRIN IN

voltage is required. V

should be connected to V

ROUT

RIN

I/Q

VRIN

+ 0.25V (I/Q + - I/Q - = -0.5V).

IN IN

when using the internal reference voltage. An external, user-

supplied, 0.1µF capacitor may be connected from the V

output pin to filter any stray board noise.

ROUT

The analog input can be DC coupled (Figure 17) as long as

the inputs are within the analog input common mode voltage

range (0.25V ≤ VDC ≤ 2.75V).

Reference Voltage Inputs, I/Q V

REFIN

The ISL5740 is designed to accept a 1.25V reference

voltage source at the V input pins for the I and Q

The resistors, R, in Figure 17 are not absolutely necessary

but may be used as load setting resistors. A capacitor, C,

RIN

channels. Typical operation of the converter requires V

to

connected from I/Q + to I/Q - will help ﬁlter any high

RIN

connected

IN IN

be set at 1.25V. The ISL5740 is tested with V

frequency noise on the inputs, also improving performance.

Values around 20pF are sufﬁcient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

RIN

to V

yielding a fully differential analog input voltage

range of ±0.5V.

ROUT

The user does have the option of supplying an external 1.25V

reference voltage. As a result of the high input impedance

presented at the V

input pin, MΩ typically, the external

RIN

V

reference voltage being used is only required to source small

amount of reference input current.

IN

I/Q

+

IN

V

DC

R

In order to minimize overall converter noise it is

recommended that adequate high frequency decoupling be

ISL5740

I/QV

C

RIN

provided at the reference voltage input pin, V

.

RIN

-V

IN

Analog Input, Differential Connection

I/Q

-

IN

DC

The analog input of the ISL5740 is a differential input that

can be conﬁgured in various ways depending on the signal

source and the required level of performance. A fully

differential connection (Figure 16 and Figure 17) will deliver

the best performance from the converter.

FIGURE 5. DC COUPLED DIFFERENTIAL INPUT

Analog Input, Single-Ended Connection

The conﬁguration shown in Figure 18 may be used with a

single ended AC coupled input.

V

I/Q +

IN

R

ISL5740

I/QV

RIN

I/Q

+

V

IN

R

-V

I/Q -

IN

V

ISL5740

DC

-

IN

FIGURE 4. AC COUPLED DIFFERENTIAL INPUT

Since the ISL5740 is powered by a single +3V analog

supply, the analog input is limited to be between ground and

+3V. For the differential input connection this implies the

analog input common mode voltage can range from 0.25V to

2.75V. The performance of the ADC does not change

FIGURE 6. AC COUPLED SINGLE ENDED INPUT

Again, with V

RIN

connected to V

, if V is a 1V

IN P-P

ROUT

sinewave, then I/Q + is a 1.0V

sinewave riding on a

IN

P-P

positive voltage equal to V . The converter will be at

DC

positive full scale when I/Q + is at V

IN

+ 0.5V (I/Q + -

IN

DC

3-10

ISL5740

I/Q - = +0.5V) and will be at negative full scale when I/Q

IN

+

The delay mode can be used to set the Q channel 180

IN

is equal to V

- 0.5V (I/Q + - I/Q - = -0.5V). Sufﬁcient

degrees out phase of the I channel if the same clock is

driving both channels. If separate, inverted clocks are used

for the I and Q channels, this feature can be used to align the

data.

DC

IN IN

headroom must be provided such that the input voltage

never goes above +3V or below AGND. In this case, V

DC

could range between 0.5V and 2.5V without a signiﬁcant

change in ADC performance. The simplest way to produce

OPERATIONAL MODES

VDC is to use the I/Q

the ISL5740.

bias source, I/QV , output of

DC

VRIN

S1

0

S2

0

MODE

Standby I and Q Channels.

The single ended analog input can be DC coupled

(Figure 19) as long as the input is within the analog input

common mode voltage range.

0

1

I channel operates normally with Q Channel in

standby mode.

1

0

1

I and Q Channels operating with I/Q output data in

phase.

V

IN

I/Q

+

IN

V

DC

I and Q Channels operating with Q data 180 degrees

out of phase.

R

ISL5740

C

Sampling Clock Requirements

The ISL5740 sampling clock input provides a standard high-

speed interface to external TTL/CMOS logic families.

V

I/Q

-

IN

DC

In order to ensure rated performance of the ISL5740, the

duty cycle of the clock should be held at 50% ±5%. It must

also have low jitter and operate at standard TTL/CMOS

levels.

FIGURE 7. DC COUPLED SINGLE ENDED INPUT

Performance of the ISL5740 will only be guaranteed at

conversion rates above 1MSPS (Typ). This ensures proper

performance of the internal dynamic circuits. Similarly, when

power is ﬁrst applied to the converter, a maximum of 20

cycles at a sample rate above 1MSPS must be performed

before valid data is available.

The resistor, R, in Figure 19 is not absolutely necessary but

may be used as a load setting resistor. A capacitor, C,

connected from I/Q + to I/Q - will help ﬁlter any high

IN IN

frequency noise on the inputs, also improving performance.

Values around 20pF are sufﬁcient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

Supply and Ground Considerations

The ISL5740 has separate analog and digital supply and

ground pins to keep digital noise out of the analog signal

path. The part should be mounted on a board that provides

separate low impedance connections for the analog and

digital supplies and grounds. For best performance, the

supplies to the ISL5740 should be driven by clean, linear

regulated supplies. The board should also have good high

frequency decoupling capacitors mounted as close as

possible to the converter. If the part is powered off a single

supply then the analog supply can be isolated by a ferrite

bead from the digital supply.

A single ended source may give better overall system

performance if it is ﬁrst converted to differential before

driving the ISL5740.

Operational Mode

The ISL5740 contains several operational modes including a

normal two channel operation, placing one or both channels

in standby and delaying the Q channel data 1/2 clock cycle.

The operational mode is selected via the S1 and S2 pins and

is asynchronous to either clock. When either channel is

placed in standby, the output data is stalled and not high

impedance. When recovering from standby, valid data is

available after 20 clock cycles.

Refer to the application note “Using Intersil High Speed A/D

Converters” (AN9214) for additional considerations when

using high speed converters.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

3-11


型号：	HI5740
厂家：	ETC
描述：	3V， Dual 10-Bit， 20/ 40/60 MSPS A/D Converter with Internal Voltage Reference (2 pages) FN4821 3V ，双通道，10位， 20 / 40/60 MSPS A / D转换器，内置参考电压（ 2页） FN4821 转换器
文件：	总11页 (文件大小：80K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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