HI5746KCA [INTERSIL]
10-Bit, 40 MSPS A/D Converter; 10位， 40 MSPS A / D转换器
| 型号： | HI5746KCA |
| 厂家： | 
Intersil |
| 描述： | 10-Bit, 40 MSPS A/D Converter |
| 文件： | 总17页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5746
Data Sheet
February 1999
File Number 4129.4
10-Bit, 40 MSPS A/D Converter
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MSPS
The HI5746 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a CMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its 40 MSPS speed is
made possible by a fully differential pipelined architecture
with an internal sample and hold.
• 8.8 Bits at f = 10MHz
IN
• Low Power at 40 MSPS . . . . . . . . . . . . . . . . . . . . 225mW
• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz
• On-Chip Sample and Hold
The HI5746 has excellent dynamic performance while
consuming only 225mW power at 40 MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles. It is pin-for-pin
functionally compatible with the HI5702 and the HI5703.
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V
• TTL/CMOS Compatible Digital Inputs
• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V
• Offset Binary or Two’s Complement Output Format
For internal voltage reference, please refer to the HI5767
data sheet.
Applications
Ordering Information
• Professional Video Digitizing
• Medical Imaging
PART
NUMBER
TEMP.
PKG.
NO.
o
RANGE ( C)
0 to 70
0 to 70
25
PACKAGE
28 Ld SOIC (W)
28 Ld SSOP
• Digital Communication Systems
• High Speed Data Acquisition
HI5746KCB
HI5746KCA
HI5746EVAL1
M28.3
M28.15
Evaluation Board
Pinout
HI5746
(SOIC, SSOP)
TOP VIEW
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DV
D0
D1
D2
D3
D4
DV
CC1
DGND1
3
DV
CC1
4
DGND1
5
AV
CC
6
AGND
CC2
7
V
+
-
CLK
DGND2
D5
REF
8
V
REF
9
V
+
IN
10
11
12
13
14
V
-
D6
IN
V
D7
DC
AGND
D8
AV
CC
D9
OE
DFS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
70
HI5746
Functional Block Diagram
CLK
CLOCK
V
BIAS
DC
V
-
IN
V
+
IN
S/H
STAGE 1
DFS
OE
2-BIT
FLASH
2-BIT
DAC
+
∑
-
DV
CC2
X2
D9 (MSB)
D8
D7
D6
DIGITAL DELAY
AND
STAGE 8
D5
DIGITAL ERROR
CORRECTION
D4
D3
2-BIT
FLASH
2-BIT
DAC
D2
D1
+
D0 (LSB)
∑
-
X2
DGND2
STAGE 9
2-BIT
FLASH
AV
AGND DV
CC1
DGND1
V
+
V
- (OPTIONAL)
REF
CC
REF
71
HI5746
Typical Application Schematic
HI5746
+ (7)
2.5V
V
V
REF
REF
- (8)
2.0V
(OPTIONAL)
(LSB) (28) D0
(27) D1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
(26) D2
(25) D3
(24) D4
(20) D5
(19) D6
(18) D7
(17) D8
AGND (12)
AGND (6)
DGND
AGND
BNC
DGND1 (2)
DGND1 (4)
DGND2 (21)
(MSB) (16) D9
10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
V
+
-
(1) DV
CC1
V
V
V
+ (9)
(11)
IN
IN
(3) DV
CC1
DC
IN
V
- (10) (23) DV
IN
CC2
+5V
+
0.1µF
10µF
CLOCK
CLK (22)
DFS (15)
OE (14)
(13) AV
CC
(5) AV
+5V
CC
+
0.1µF
10µF
Pin Descriptions
PIN NO.
NAME
DV
DESCRIPTION
PIN NO.
NAME
DESCRIPTION
1
2
3
4
5
6
7
Digital Supply (+5.0V).
Digital Ground.
15
16
17
18
19
20
21
22
23
DFS
D9
Data Format Select Input.
Data Bit 9 Output (MSB).
Data Bit 8 Output.
Data Bit 7 Output.
Data Bit 6 Output.
Data Bit 5 Output.
Digital Ground.
CC1
DGND1
DV
Digital Supply (+5.0V).
Digital Ground.
D8
CC1
DGND1
D7
AV
CC
Analog Supply (+5.0V).
Analog Ground.
D6
AGND
D5
V
+
+2.5V Positive Reference Voltage
Input.
DGND2
CLK
REF
Sample Clock Input.
8
V
-
+2.0V Negative Reference Voltage
Input (Optional).
REF
DV
Digital Output Supply
(+3.0V or +5.0V).
CC2
9
V
+
Positive Analog Input.
Negative Analog Input.
DC Bias Voltage Output.
Analog Ground.
IN
24
25
26
27
28
D4
Data Bit 4 Output.
Data Bit 3 Output.
Data Bit 2 Output.
Data Bit 1 Output.
Data Bit 0 Output (LSB).
10
11
12
13
14
V
-
IN
D3
D2
D1
D0
V
DC
AGND
AV
CC
Analog Supply (+5.0V).
Digital Output Enable Control Input.
OE
72
HI5746
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
o
Supply Voltage, AV
CC
or DV
to AGND or DGND . . . . . . . . . . .6V
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
CC
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
100
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV
CC
o
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
Operating Conditions
o
Temperature Range
o
(SOIC, SSOP - Lead Tips Only)
o
HI5746KCB (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications AV = DV
= 5.0V; DV
CC2
= 3.0V, V
+ = 2.5V; V
- = 2.0V; f = 40 MSPS at 50% Duty Cycle;
REF S
CC
CC1
REF
o
o
C = 10pF; T = 25 C; Differential Analog Input; Typical Values are Test Results at 25 C,
L
A
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
10
-
-
-
Bits
LSB
LSB
Integral Linearity Error, INL
f
f
= DC
= DC
±1.0
±0.5
±2.0
±1.0
IN
IN
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
-
Offset Error, V
OS
f
f
= DC
= DC
-40
-
12
4
40
-
LSB
LSB
IN
IN
Full Scale Error, FSE
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
No Missing Codes
No Missing Codes
-
0.5
-
1
-
MSPS
MSPS
Bits
Maximum Conversion Rate
40
Effective Number of Bits, ENOB
Signal to Noise and Distortion Ratio, SINAD
f
f
= 10MHz
= 10MHz
8.55
53.2
8.8
54.9
-
IN
IN
-
dB
RMS Signal
= -------------------------------------------------------------
RMS Noise + Distortion
Signal to Noise Ratio, SNR
f
= 10MHz
53.2
55.4
-
dB
IN
RMS Signal
= -------------------------------
RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
f
f
f
f
f
f
f
= 10MHz
= 10MHz
= 10MHz
= 10MHz
-
-
-
-
-
-
-
-
-
-64.6
-67.8
-68.3
67.8
64
-
-
-
-
-
-
-
-
-
dBc
dBc
IN
IN
IN
IN
dBc
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
Differential Gain Error
dBc
= 1MHz, f = 1.02MHz
2
dBc
1
= 17.72 MSPS, 6 Step, Mod Ramp
= 17.72 MSPS, 6 Step, Mod Ramp
0.8
%
S
S
Differential Phase Error
0.1
Degree
Cycle
Cycle
Transient Response
(Note 2)
1
Over-Voltage Recovery
0.2V Overdrive (Note 2)
1
73
HI5746
Electrical Specifications AV = DV
= 5.0V; DV
CC2
= 3.0V, V
+ = 2.5V; V
- = 2.0V; f = 40 MSPS at 50% Duty Cycle;
REF S
CC
CC1
REF
o
o
C = 10pF; T = 25 C; Differential Analog Input; Typical Values are Test Results at 25 C,
L
A
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input
-
-
±0.5
-
-
V
V
Range (V + - V -)
IN IN
Maximum Peak-to-Peak Single-Ended
Analog Input Range
1.0
Analog Input Resistance, R
(Note 3)
-
-
1
10
-
-
MΩ
pF
IN
Analog Input Capacitance, C
IN
-
+10
-
Analog Input Bias Current, I + or I -
(Note 3)
(Note 3)
-10
-
µA
µA
B
B
Differential Analog Input Bias Current
= (I + - I -)
±0.5
I
BDIFF
B
B
Full Power Input Bandwidth, FPBW
-
250
-
-
MHz
V
Analog Input Common Mode Voltage Range
Differential Mode (Note 2)
0.25
4.75
(V + + V -)/2
IN IN
REFERENCE INPUT
Total Reference Resistance, R
V
+ to AGND
REF
-
-
-
-
-
-
2.5K
1.07
21
-
-
-
-
-
-
Ω
mA
µA
V
L
Positive Reference Current, I
+
REF
Negative Reference Current, I
REF
-
Positive Reference Voltage Input, V
+
(Note 2)
(Note 2)
(Note 2)
2.5
REF
Negative Reference Voltage Input, V
-
2.0
V
REF
Reference Common Mode Voltage
2.25
V
(V
+ + V -)/2
REF
REF
DC BIAS VOLTAGE
DC Bias Voltage Output, V
Maximum Output Current
DIGITAL INPUTS
-
-
3.2
-
-
V
DC
0.4
mA
Input Logic High Voltage, V
IH
CLK, DFS, OE
CLK, DFS, OE
2.0
-
-
-
-
V
Input Logic Low Voltage, V
0.8
V
IL
Input Logic High Current, I
CLK, DFS, OE, V = 5V
IH
-10.0
-10.0
-
-
+10.0
+10.0
-
µA
µA
pF
IH
Input Logic Low Current, I
CLK, DFS, OE, V = 0V
IL
-
IL
Input Capacitance, C
7
IN
DIGITAL OUTPUTS
Output Logic High Voltage, V
I
I
= 100µA; DV
= 5V
= 5V
4.0
-
-
-
V
V
OH
OH
OL
CC2
Output Logic Low Voltage, V
= 100µA; DV
= 0/5V; DV
-
-
0.5
±10
-
OL
CC2
Output Three-State Leakage Current, I
V
= 5V
±1
-
µA
V
OZ
O
CC2
Output Logic High Voltage, V
I
I
= 100µA; DV
= 3V
= 3V
2.4
-
OH
OH
OL
CC2
CC2
Output Logic Low Voltage, V
= 100µA; DV
-
0.5
V
OL
74
HI5746
Electrical Specifications AV = DV
= 5.0V; DV
CC2
= 3.0V, V
+ = 2.5V; V
- = 2.0V; f = 40 MSPS at 50% Duty Cycle;
REF S
CC
CC1
REF
o
o
C = 10pF; T = 25 C; Differential Analog Input; Typical Values are Test Results at 25 C,
L
A
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
Output Three-State Leakage Current, I = 0/5V; DV = 3V
MIN
TYP
±1
MAX
±10
-
UNITS
µA
V
-
-
OZ
O
CC2
Output Capacitance, C
10
pF
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
AP
-
-
-
-
-
-
-
-
5
5
7
8
5
5
-
-
-
ns
Aperture Jitter, t
AJ
ps
RMS
Data Output Hold, t
-
ns
ns
H
Data Output Delay, t
-
OD
Data Output Enable Time, t
-
ns
EN
Data Output Enable Time t
-
ns
DIS
Data Latency, t
For a Valid Sample (Note 2)
Data Invalid Time (Note 2)
7
20
Cycles
Cycles
LAT
Power-Up Initialization
POWER SUPPLY CHARACTERISTICS
-
Analog Supply Voltage, AV
4.75
5.0
5.0
3.0
5.0
46
5.25
V
V
CC
Digital Supply Voltage DV
4.75
5.25
CC1
Digital Output Supply Voltage, DV
At 3.0V
At 5.0V
2.7
3.3
V
CC2
4.75
5.25
V
Total Supply Current, I
CC
f
f
f
f
f
= 10MHz and DFS = “0”
= 10MHz and DFS = “0”
= 10MHz and DFS = “0”
= 10MHz and DFS = “0”
= 10MHz and DFS = “0”
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mW
LSB
LSB
IN
IN
IN
IN
IN
Analog Supply Current, AI
30
-
CC
Digital Supply Current, DI
13
-
CC1
Output Supply Current, DI
Power Dissipation
3
-
CC2
225
±0.4
±0.8
275
Offset Error Sensitivity, ∆V
OS
AV
AV
or DV
or DV
= 5V ±5%
= 5V ±5%
-
-
CC
CC
CC
Gain Error Sensitivity, ∆FSE
CC
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
75
HI5746
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
S
H
S
H
S
H
S
S
H
S
H
S
H
S
H
N + 8
N - 1
N - 1
N
N
N + 1
N + 1
N + 2
N + 5
N + 5
N + 6
N + 6
N + 7
N + 7
N + 8
INPUT
S/H
1ST
STAGE
B
B
B
B
B
B
B
1, N + 7
1, N - 1
1, N
1, N + 1
1, N + 4
1, N + 5
1, N + 6
2ND
STAGE
B
B
B
2, N + 6
B
B
B
2, N
2, N + 4
2, N + 5
2, N - 2
2, N - 1
9TH
STAGE
B
B
B
B
B
B
9, N + 3
9, N - 5
9, N - 4
9, N
9, N + 1
9, N + 2
DATA
OUTPUT
D
D
D
D
D
D
N + 1
N - 7
N - 6
N - 2
N - 1
N
t
LAT
NOTES:
4. S : N-th sampling period.
N
5. H : N-th holding period.
N
6. B
: M-th stage digital output corresponding to N-th sampled input.
M, N
7. D : Final data output corresponding to N-th sampled input.
N
FIGURE 1. HI5746 INTERNAL CIRCUIT TIMING
ANALOG
INPUT
t
AP
t
AJ
CLOCK
INPUT
1.5V
1.5V
t
OD
t
H
2.4V
0.5V
DATA
OUTPUT
DATA N
DATA N - 1
FIGURE 2. INPUT-TO OUTPUT TIMING
76
HI5746
Typical Performance Curves
9
57
52
47
42
37
SNR
SINAD
8
7
o
o
= 40 MSPS, T = 25 C
f = 40 MSPS, T = 25 C
S A
f
S
A
6
1
10
INPUT FREQUENCY (MHz)
100
1
10
INPUT FREQUENCY (MHz)
100
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
FIGURE 4. SINAD AND SNR vs INPUT FREQUENCY
85
o
= 40 MSPS, T = 25 C
f
S
A
9
8
7
6
5
4
80
75
70
65
60
55
50
45
o
f
= 40 MSPS, f = 10MHz, T = 25 C
S
IN
A
-2HD
SFDR
-3HD
-THD
1
10
INPUT FREQUENCY (MHz)
100
0
-5
-10
-15
-20
-25
-30
-35
INPUT LEVEL (dBFS)
NOTE: SFDR depicted here does not include any harmonic distortion.
FIGURE 5. -2HD, -3HD, -THD AND SFDR vs INPUT
FREQUENCY
FIGURE 6. EFFECTIVE NUMBER OF BITS (ENOB) vs
ANALOG INPUT LEVEL
9
10
o
o
f
= 40 MSPS, f = 10MHz, T = 25 C
S
IN
A
f
= 40 MSPS, f = 10MHz, T = 25 C
S
IN
V
A
9.5
9
+ - V
- = 0.5V
REF
REF
8.8
8.6
8.5
8
7.5
7
8.4
8.2
6.5
6
2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75
30
35
40
45
50
55
60
65
70
V
+ (V)
REF
DUTY CYCLE (%, T /T
)
CLK
H
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs
SAMPLE CLOCK DUTY CYCLE
FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs V +
REF
77
HI5746
Typical Performance Curves (Continued)
80
75
70
55
-2HD
SNR
54
SFDR
SINAD
53
-3HD
-THD
65
52
60
55
f
= 40 MSPS, f = 10MHz
IN
f
= 40 MSPS, f = 10MHz
S
S IN
o
o
V
+ - V
- = 0.5V, T = 25 C
V
+ - V
- = 0.5V, T = 25 C
REF A
REF
REF
A
REF
51
2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75
+ (V)
2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75
+ (V)
V
REF
V
REF
NOTE: SFDR depicted here does not include any harmonic distortion.
FIGURE 10. -2HD, -3HD, -THD AND SFDR vs V
+
FIGURE 9. SINAD AND SNR vs V
+
REF
REF
8.8
8.6
8.4
53
52
51
f
T
= 40 MSPS, f = 10MHz
IN
= 25 C
f
T
= 40 MSPS, f = 10MHz
IN
= 25 C
S
S
o
o
A
A
SNR
SINAD
8.2
8
50
49
2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75
+ (V)
2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75
+ (V)
V
V
REF
REF
FIGURE 11. EFFECTIVE NUMBER OF BITS (ENOB) vs V
+
FIGURE 12. SINAD AND SNR vs V
+ (V - NOT DRIVEN)
REF
REF
REF
(V
- NOT DRIVEN)
-2HD
REF
80
75
70
9.0
f
= 40 MSPS, f = 10MHz
IN
f
= 1MHz
S
IN
o
T
= 25 C
A
8.8
8.6
8.4
f
= 10MHz
IN
-3HD
-THD
65
8.2
8.0
60
55
SFDR
o
f
= 40 MSPS, T = 25 C
A
S
DIFFERENTIAL ANALOG INPUT
2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75
+ (V)
0.25 0.75 1.25
1.75 2.25 2.75 3.25 3.75 4.25 4.75
(V)
V
V
CM
REF
FIGURE 13. -2HD, -3HD, -THD AND SFDR vs V
REF
+
FIGURE 14. EFFECTIVE NUMBER OF BITS (ENOB) vs
ANALOG INPUT COMMON MODE VOLTAGE
(V
- NOT DRIVEN)
REF
78
HI5746
Typical Performance Curves (Continued)
45.0
50
40
o
1MHz ≤ f ≤ 15MHz, T = 25 C
IN
A
f
= 40 MSPS, V + = V -
IN IN
S
44.5
44.0
43.5
43.0
42.5
42.0
41.5
I
(TOTAL)
CC
CC
AI
30
20
DI
CC1
10
0
41.0
40.5
DI
CC2
10
20
30
40
-40
-20
0
20
40
o
60
80
f
(MSPS)
TEMPERATURE ( C)
S
FIGURE 15. TOTAL SUPPLY CURRENT vs TEMPERATURE
FIGURE 16. SUPPLY CURRENT vs SAMPLE CLOCK
FREQUENCY
1200
9.5
9.0
8.5
1000
800
600
400
I
+
REF
t
OD
8.0
7.5
7.0
200
0
6.5
6.0
I
-
REF
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 17. REFERENCE CURRENT vs TEMPERATURE
FIGURE 18. DATA OUTPUT DELAY vs TEMPERATURE
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.25
0.70
0.3
f
= 17.72 MSPS
S
DP
DG
0.65
0.60
0.55
0.50
0.45
0.40
0.25
0.2
0.15
0.1
0.05
0
DG
0.2
0.15
0.1
0.05
0
DP
DG
DP
f
= 17.72 MSPS
S
o
AV /DV
CC CC1
= 5V ±5%, T = 25 C
A
2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
DV 2 (V)
-40
-20
0
20
40
o
60
80
TEMPERATURE ( C)
CC
FIGURE 19. DIFFERENTIAL GAIN/PHASE vs TEMPERATURE
FIGURE 20. DIFFERENTIAL GAIN/PHASE vs SUPPLY VOLTAGE
79
HI5746
Typical Performance Curves (Continued)
3.30
9.0
8.8
8.6
8.4
8.2
3.20
3.10
3.00
-40
-20
0
20
40
60
80
o
TEMPERATURE ( C)
-40
-20
0
20
40
60
80
o
TEMPERATURE ( C)
FIGURE 21. DC BIAS VOLTAGE (V ) vs TEMPERATURE
DC
FIGURE 22. EFFECTIVE NUMBER OF BITS F(ENOB) vs
TEMPERATURE
0
0
f
f
= 1MHz
= 40 MSPS
f
f
= 10MHz
= 40 MSPS
IN
S
IN
S
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
512
1023
0
512
1023
FREQUENCY BIN
FREQUENCY BIN
FIGURE 23. 2048 POINT FFT PLOT
FIGURE 24. 2048 POINT FFT SPECTRAL PLOT
Detailed Description
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fully-
differential output for the converter core. During the sampling
Theory of Operation
The HI5746 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 25 depicts
the circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
phase, the V pins see only the on-resistance of a switch and
IN
sampling clock which is a non-overlapping two phase signal, φ
1
C . The relatively small values of these components result in a
S
typical full power input bandwidth of 250MHz for the converter.
and φ , derived from the master sampling clock. During the
2
sampling phase, φ , the input signal is applied to the sampling
1
capacitors, C . At the same time the holding capacitors, C ,
S
H
are discharged to analog ground. At the falling edge of φ the
1
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase, φ , the two bottom plates of
2
the sampling capacitors are connected together and the
holding capacitors are switched to the op amp output nodes.
The charge then redistributes between C and C completing
S
H
80
HI5746
structure of the V
+ and V - input pins consists of a
REF
REF
resistive voltage divider with one resistor of the divider
(nominally 500Ω) connected between V + and V
- and
φ
φ
REF REF
C
1
1
H
the other resistor of the divider (nominally 2000Ω) connected
between V - and analog ground. This allows the user the
φ
REF
option of supplying only the +2.5V V
1
C
C
S
V
V
IN+
+ voltage reference
V
REF
- being generated internally by the
OUT+
+
-
φ
with the +2.0V V
2
REF
V
+
-
OUT-
voltage division action of the input structure.
IN-
S
φ
1
The HI5746 is tested with V - equal to +2.0V and V
+
REF REF
equal to +2.5V yielding a fully differential analog input voltage
range of ±0.5V. V + and V - can differ from the above
φ
C
φ
1
H
1
REF REF
voltages (see the Typical Performance Curves, Figure 8
through Figure 13).
FIGURE 25. ANALOG INPUT SAMPLE-AND-HOLD
In order to minimize overall converter noise it is recommended
that adequate high frequency decoupling be provided at both
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a
two-bit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
of the reference voltage input pins, V
+ and V -.
REF
REF
Analog Input, Differential Connection
The analog input to the HI5746 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 26 and Figure 27) will give the
best performance for the converter.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
V
V
+
V
IN
IN
R
R
HI5746
DC
-V
IN
V
-
IN
FIGURE 26. AC COUPLED DIFFERENTIAL INPUT
Since the HI5746 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 7th cycle of the clock after the analog
sample is taken. This time delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital output data is
synchronized to the external sampling clock by a double
buffered latching technique. The output of the digital error
correction circuit is available in two’s complement or offset
binary format depending on the state of the Data Format
Select (DFS) control input (see Table 1, A/D Code Table).
A DC voltage source, V , equal to 3.2V (typical), is made
DC
available to the user to help simplify circuit design when using
an AC coupled differential input. This low output impedance
voltage source is not designed to be a reference but makes an
excellent DC bias source and stays well within the analog
input common mode voltage range over temperature (see the
Typical Performance Curves, Figure 21).
Reference Voltage Inputs, V
- and V
+
REF
For the AC coupled differential input (Figure 26) assume
REF
The HI5746 is designed to accept two external reference
the difference between V
+, typically 2.5V, and V
-,
REF
REF
typically 2.0V, is 0.5V. Full scale is achieved when the V
voltage sources at the V
the converter requires V
input pins. Typical operation of
IN
REF
and -V input signals are 0.5V
, with -V being
+ to be set at +2.5V and V
- to
IN
P-P IN
REF REF
180 degrees out of phase with V . The converter will be
IN
be set at 2.0V. However, it should be noted that the input
81
HI5746
at positive full scale when the V + input is at
IN
The single ended analog input can be DC coupled
(Figure 27) as long as the input is within the analog input
common mode voltage range.
V
+ 0.25V and the V - input is at V
- 0.25V (V + -
DC
IN
DC IN
V
- = +0.5V). Conversely, the converter will be at
IN
negative fullscale when the V + input is equal to V
-
IN
DC
0.25V and V - is at V
IN
+ 0.25V (V + - V - = -0.5V).
IN IN
DC
V
IN
The analog input can be DC coupled (Figure 27) as long as
the inputs are within the analog input common mode voltage
range (0.25V ≤ VDC ≤ 4.75V).
V
+
VDC
IN
R
HI5746
C
V
IN
V
+
IN
VDC
VDC
V
-
IN
R
R
HI5746
C
V
V
DC
FIGURE 29. DC COUPLED SINGLE ENDED INPUT
-V
IN
VDC
-
IN
The resistor, R, in Figure 29 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
FIGURE 27. DC COUPLED DIFFERENTIAL INPUT
connected from V + to V - will help filter any high
IN IN
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
The resistors, R, in Figure 27 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from V + to V - will help filter any high
IN IN
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the HI5746.
Digital Output Control and Clock Requirements
The HI5746 provides a standard high-speed interface to
external TTL logic families.
Analog Input, Single-Ended Connection
The configuration shown in Figure 28 may be used with a
single ended AC coupled input.
In order to ensure rated performance of the HI5746, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
V
+
V
IN
IN
R
Performance of the HI5746 will only be guaranteed at
conversion rates above 1 MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.
HI5746
-
VDC
V
IN
FIGURE 28. AC COUPLED SINGLE ENDED INPUT
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 1 for further information.
Again, assume the difference between V
REF
+, typically
2.5V, and V
-, typically 2V, is 0.5V. If V is a 1V
REF
IN
P-P
sinewave, then V + is a 1V
IN P-P
sinewave riding on a positive
voltage equal to VDC. The converter will be at positive full
scale when V + is at VDC + 0.5V (V + - V - = +0.5V)
IN IN IN
and will be at negative full scale when V + is equal to
IN
VDC - 0.5V (V + - V - = -0.5V). Sufficient headroom must
IN IN
be provided such that the input voltage never goes above
+5V or below AGND. In this case, VDC could range between
0.5V and 4.5V without a significant change in ADC
performance. The simplest way to produce VDC is to use the
DC bias source, V , output of the HI5746.
DC
82
HI5746
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
(DFS LOW)
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
M
S
B
L
S
B
M
S
B
L
S
B
DIFFERENTIAL
INPUT VOLTAGE
CODE CENTER
DESCRIPTION
(V + - V -)
IN IN
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
+Full Scale (+FS) -
1
0.499756V
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
/
LSB
4
1
+FS - 1 / LSB
4
0.498779V
732.422µV
-244.141µV
-0.498291V
-0.499268V
1
1
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
1
0
0
0
1
1
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
1
0
3
+ / LSB
4
1
- / LSB
4
3
-FS + 1 / LSB
4
-Full Scale (-FS) +
3
/
LSB
4
NOTES:
8. The voltages listed above represent the ideal center of each output code shown as a function of the reference differential voltage,
(V + - V -) = 0.5V.
REF REF
9. V
+ = 2.5V and V
- = 2V.
REF
REF
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE
input to logic low for normal operation.
Static Performance Definitions
Offset Error (V
)
OS
1
The midscale code transition should occur at a level / LSB
4
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
OE INPUT
DIGITAL DATA OUTPUTS
Active
0
1
Full-Scale Error (FSE)
High Impedance
The last code transition should occur for an analog input that
3
is / LSB below positive Full scale (+FS) with the offset
4
Supply and Ground Considerations
error removed. Fullscale error is defined as the deviation of
the actual code transition from this point.
The HI5746 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The digital data outputs also have a separate supply
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
pin, DV
, which can be powered from a 3V or 5V supply.
CC2
This allows the outputs to interface with 3V logic if so
desired.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5746 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a
single supply then the analog supply should be isolated
with a ferrite bead from the digital supply.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5% and
the shift in the offset and full scale error (in LSBs) is noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5746. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from Fullscale for all these tests.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
83
HI5746
SNR and SINAD are quoted in dB. The distortion numbers are
quoted in dBc (decibels with respect to carrier) and DO NOT
include any correction factors for normalizing to full scale.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD - 1.76 + V
CORR
) / 6.02,
Video Definitions
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
where:
V
= 0.5 dB.
CORR
V
adjusts the SINAD, and hence the ENOB, for the
CORR
amount the analog input signal is below fullscale.
Signal To Noise and Distortion Ratio (SINAD)
Differential Gain (DG)
SINAD is the ratio of the measured RMS signal to RMS sum
of all the other spectral components below the Nyquist
Differential Gain is the peak difference in chrominance
amplitude (in percent) relative to the reference burst.
frequency, f /2, excluding DC.
S
Differential Phase (DP)
Signal To Noise Ratio (SNR)
Differential Phase is the peak difference in chrominance
phase (in degrees) relative to the reference burst.
SNR is the ratio of the measured RMS signal to RMS noise at
a specified input and sampling frequency. The noise is the
Timing Definitions
RMS sum of all of the spectral components below f /2
S
Refer to Figure 1 and Figure 2 for these definitions.
excluding the fundamental, the first five harmonics and DC.
Aperture Delay (t
)
Total Harmonic Distortion (THD)
AP
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Aperture Jitter (t
Aperture jitter is the RMS variation in the aperture delay due
)
AJ
Spurious Free Dynamic Range (SFDR)
to variation of internal clock path delays.
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spectral component in the
spectrum below f /2.
S
Data Hold Time (t )
H
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Intermodulation Distortion (IMD)
Data Output Delay Time (t
Data output delay time is the time to where the new data (N)
is valid.
)
OD
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f and f , are
1
2
present at the inputs. The ratio of the measured signal to
the distortion terms is calculated. The terms included in the
calculation are (f +f ), (f -f ), (2f ), (2f ), (2f +f ), (2f -f ),
Data Latency (t
)
LAT
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus on
the 7th cycle of the clock after the analog sample is taken.
This is due to the pipeline nature of the converter where the
analog sample has to ripple through the internal subconverter
stages. This delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital data lags the analog input sample by 7
sample clock cycles.
1
2
1 2
1
2
1
2
1 2
(f +2f ), (f -2f ). The ADC is tested with each tone 6dB
1
2
1
2
below full scale.
Transient Response
Transient response is measured by providing a full scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
10-bit accuracy.
Over-Voltage Recovery
Power-Up Initialization
Over-Voltage Recovery is measured by providing a full scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
84
HI5746
AMP
A/D
DSP/µP
D/A
AMP
HFA1100
HFA1105
HFA1106
HFA1135
HFA1145
HFA1245
HI5703
HI5746
HI5767
HSP9501
HI5780
HI1171
HI3338
HA5020
HA2842
HFA1115
HFA1212
HFA1412
HSP48410
HSP48908
HSP48212
HSP43891
HSP43168
HSP43216
HFA1100: 850MHz Video Op Amp
HFA1105: 300MHz Video Op Amp
HFA1106: 250MHz Video Op Amp with Bandwidth Limit Control
HFA1135: 350MHz Video Op Amp with Output Limiting
HFA1145: 300MHz Video Op Amp with Output Disable
HFA1245: Dual, 350MHz, Video Op Amp with Output Disable
HSP48212: Digital Video Mixer
HSP43891: Digital Filter, 30MHz, 9-Bit
HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz
HSP43216: Digital Half Band Filter
HI5780:
HI1171:
HI3338:
HA5020:
10-Bit, 80 MSPS, Video D/A Converter
8-Bit, 40 MSPS, Video D/A Converter
8-Bit, 50 MSPS, Video D/A Converter
100MHz Video Op Amp
HI5703:
10-Bit, 40 MSPS, Low Power A/D Converter
HI5746:
10-Bit, 40 MSPS, Very Low Power A/D Converter
HI5767:
10-Bit, 40 MSPS A/D Converter with Voltage Reference HA2842:
High Output Current, Video Op Amp
HSP9501: Programmable Data Buffer
HSP48410: Histogrammer/Accumulating Buffer, 10-Bit Pixel
Resolution
HFA1115: 225MHz Programmable Gain Video Buffer with
Output Limiting
HFA1212: 350MHz Dual Programmable Gain Video Buffer
HFA1412: 350MHz Quad Programmable Gain Video Buffer
HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit
In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.
FIGURE 30. 10-BIT VIDEO IMAGING COMPONENTS
AMP
A/D
DSP/µP
D/A
AMP
HFA1100
HFA1110
HFA3101
HFA3102
HFA3600
HI5703
HI5746
HI5767
HSP43168
HSP43216
HSP43220
HSP43891
HSP50016
HSP50110
HSP50210
HI5721
HI5780
HI20201
HI20203
HFA1112
HFA1113
HFA1100: 850MHz Op Amp
HFA1110: 750MHz Unity Gain Video Buffer
HFA3101: Gilbert Cell Transistor Array
HFA3102: Dual Long-Tailed Pair Transistor Array
HFA3600: Low Noise Amplifier/Mixer
HI5703: 10-Bit, 40 MSPS, Low Power A/D Converter
HI5746: 10-Bit, 40 MSPS, Very Low Power A/D Converter
HI5767: 10-Bit, 40 MSPS A/D Converter with Voltage Reference
HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz
HSP43216: Digital Half Band Filter
HSP43220: Decimating Digital Filter
HSP43891: Digital Filter, 30MHz, 9-Bit
HSP50016: Digital Down Converter
HSP50110: Digital Quadrature Tuner
HSP50210: Digital Costas Loop
HI5721: 10-Bit, 100 MSPS, Communications D/A Converter
HI5780: 10-Bit, 80 MSPS, D/A Converter
HI20201: 10-Bit, 160 MSPS, High Speed D/A Converter
HI20203: 8-Bit, 160 MSPS, High Speed D/A Converter
HFA1112: 850MHz Programmable Gain Video Buffer
HFA1113: 850MHz Programmable Gain Video Buffer with Output Limiting
In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.
FIGURE 31. 10-BIT COMMUNICATIONS COMPONENTS
85
HI5746
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
86
相关型号：
HI5760/6IBZ
10-Bit, 125/60MSPS, High Speed D/A Converter; SOIC28, TSSOP28; Temp Range: -40° to 85°C
RENESAS
HI5760/6IBZ-T
PARALLEL, WORD INPUT LOADING, 0.035us SETTLING TIME, 10-BIT DAC, PDSO28, LEAD FREE, PLASTIC, MS-013-AE, SOIC-28
RENESAS
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