HI5760 [INTERSIL]
10-Bit, 125/60MSPS, High Speed D/A Converter; 10位， 125 / 60MSPS ，高速D / A转换器
| 型号： | HI5760 |
| 厂家： | 
Intersil |
| 描述： | 10-Bit, 125/60MSPS, High Speed D/A Converter |
| 文件： | 总18页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5760
Data Sheet
November 1999
File Number 4320.5
10-Bit, 125/60MSPS, High Speed D/A
Converter
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS
• Low Power . . . . . . . . . . . . . . . 165mW at 5V, 27mW at 3V
• Power Down Mode . . . . . . . . . . 23mW at 5V, 10mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . ±1 LSB
• Adjustable Full Scale Output Current. . . . . 2mA to 20mA
• SFDR to Nyquist at 5MHz Output . . . . . . . . . . . . . .68dBc
The HI5760 is a 10-bit, 125MSPS, high speed, low power,
D/A converter which is implemented in an advanced CMOS
process. Operating from a single +3V to +5V supply, the
converter provides 20mA of full scale output current and
includes edge-triggered CMOS input data latches. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented current source architecture. For
an equivalent performance dual version, see the HI5728.
• Internal 1.2V Temperature Compensated Bandgap
Voltage Reference
This device complements the CommLink™ HI5X60 family of
high speed converters offered by Intersil, which includes 8,
10, 12, and 14-bit devices.
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
Ordering Information
• Excellent Spurious Free Dynamic Range
PART
NUMBER
TEMP.
RANGE ( C) PACKAGE
PKG.
NO.
CLOCK
SPEED
o
Applications
HI5760BIB
HI5760IA
-40 to 85
-40 to 85
-40 to 85
-40 to 85
25
28 Ld SOIC
M28.3
125MHz
• Cable Modems
28 Ld TSSOP M28.173 125MHz
28 Ld SOIC M28.3 60MHz
28 Ld TSSOP M28.173 60MHz
Evaluation Platform 125MHz
• Set Top Boxes
HI5760/6IB†
HI5760/6IA†
HI5760EVAL1
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• Test Instrumentation
† Contact factory for availability.
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout
HI5760 (SOIC, TSSOP)
TOP VIEW
D9 (MSB)
D8
1
2
3
4
5
6
7
8
9
CLK
28
27 DV
DD
26 DCOM
25 NC
D7
D6
D5
24 AV
DD
D4
23 NC
D3
22 IOUTA
21 IOUTB
D2
D1
20
ACOM
D0 (LSB) 10
NC 11
19 COMP1
18 FSADJ
17 REFIO
16 REFLO
15 SLEEP
NC 12
NC 13
NC 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CommLink™ is a trademark of Intersil Corporation.
1
HI5760
Typical Applications Circuit
HI5760
NC
(11-14, 25)
(15) SLEEP
(16) REFLO
DCOM
ACOM
D9 (MSB) (1)
D8 (2)
D9
(17) REFIO
D8
D7
D6
D5
D4
D3
D2
D1
0.1µF
D7 (3)
D6 (4)
(18) FSADJ
(22) IOUTA
D5 (5)
R
SET
2kΩ
D4 (6)
D3 (7)
D/A OUT
50Ω
50Ω
D2 (8)
D1 (9)
D0 (LSB) (10)
D0
(21) IOUTB
D/A OUT
CLK (28)
(23) NC
50Ω
(19) COMP1
DCOM (26)
0.1µF
(20) ACOM
FERRITE
BEAD
FERRITE
BEAD
+5V OR +3V (V
)
DD
(24) AV
DD
DV
DD
(27)
+
+
10µH
10µH
10µF
10µF
0.1µF
0.1µF
Functional Block Diagram
IOUTA IOUTB
(LSB) D0
D1
CASCODE
CURRENT
SOURCE
D2
D3
5 LSBs
+
36
36
D4
SWITCH
MATRIX
LATCH
LATCH
31 MSB
D5
D6
SEGMENTS
UPPER
5-BIT
31
D7
DECODER
D8
(MSB) D9
COMP1
CLK
INT/EXT
VOLTAGE
REFERENCE
BIAS
GENERATION
INT/EXT
REFERENCE
SELECT
FSADJ
SLEEP
AV
ACOM DV
DD
DCOM
REFLO
REFIO
DD
2
HI5760
Absolute Maximum Ratings
Thermal Information
o
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . . +5.5V
to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
Analog Supply Voltage AV
DD
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
70
117
Grounds, ACOM TO DCOM. . . . . . . . . . . . . . . . . . . -0.3V To + 0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . DV + 0.3V
DD
Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . ±50µA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV + 0.3V
o
HI5760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
o
Analog Output Current (I
OUT
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications
AV
DD
= DV
DD
= +5V, V
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values
A
REF
HI5760
= -40 C TO 85 C
o
o
T
A
PARAMETER
SYSTEM PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
-1
-
-
+1
Bits
LSB
Integral Linearity Error, INL
Differential Linearity Error, DNL
“Best Fit” Straight Line (Note 7)
±0.5
±0.25
(Note 7)
(Note 7)
(Note 7)
-0.5
-0.025
-
+0.5
+0.025
-
LSB
Offset Error, I
% FSR
ppm
OS
Offset Drift Coefficient
0.1
o
FSR/ C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
With External Reference (Note 7)
-10
-10
-
±2
±1
+10
+10
-
% FSR
% FSR
ppm
Full Scale Gain Drift
±50
o
FSR/ C
With Internal Reference (Note 7)
(Note 3)
-
±100
-
ppm
FSR/ C
o
Full Scale Output Current, I
2
-
-
20
mA
V
FS
Output Voltage Compliance Range
-0.3
1.25
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
Output Settling Time, (t
(Note 3)
125
-
-
-
-
-
-
-
-
-
-
MHz
ns
CLK
)
0.2% (±1 LSB, equivalent to 9 Bits) (Note 7)
0.1% (±1/2 LSB, equivalent to 10 Bits) (Note 7)
-
-
-
-
-
-
-
-
20
35
5
SETT
ns
Singlet Glitch Area (Peak Glitch)
Output Rise Time
R
= 25Ω (Note 7)
pV•s
ns
L
Full Scale Step
Full Scale Step
1.0
1.5
10
50
30
Output Fall Time
ns
Output Capacitance
Output Noise
pF
IOUTFS = 20mA
IOUTFS = 2mA
pA/√Hz
pA/√Hz
3
HI5760
o
Electrical Specifications
PARAMETER
AV
DD
= DV
DD
= +5V, V
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values (Continued)
REF
A
HI5760
= -40 C TO 85 C
o
o
T
A
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS - HI5760BIB, HI5760IA - 125MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
= 125MSPS, f
= 100MSPS, f
= 32.9MHz, 10MHz Span (Notes 4, 7)
= 5.04MHz, 4MHz Span (Notes 4, 7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
76
75
76
78
71
71
76
54
64
52
60
68
74
63
55
68
73
73
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
CLK
OUT
f
CLK
OUT
f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 10.1MHz, 10MHz Span (Notes 4, 7)
= 5.02MHz, 2MHz Span (Notes 4, 7)
= 1.00MHz, 2MHz Span (Notes 4, 7)
CLK
OUT
OUT
OUT
f
CLK
f
CLK
Total Harmonic Distortion (THD) to
Nyquist
f
f
f
= 100MSPS, f
= 2.00MHz (Notes 4, 7)
OUT
CLK
CLK
CLK
= 50MSPS, f
= 50MSPS, f
= 2.00MHz (Notes 4, 7)
OUT
OUT
= 1.00MHz (Notes 4, 7)
Spurious Free Dynamic Range,
SFDR to Nyquist
f
= 125MSPS, f
= 125MSPS, f
= 100MSPS, f
= 100MSPS, f
= 100MSPS, f
= 100MSPS, f
= 32.9MHz, 62.5MHz Span (Notes 4, 7)
= 10.1MHz, 62.5MHz Span (Notes 4, 7)
= 40.4MHz, 50MHz Span (Notes 4, 7)
= 20.2MHz, 50MHz Span (Notes 4, 7)
= 5.04MHz, 50MHz Span (Notes 4, 7)
= 2.51MHz, 50MHz Span (Notes 4, 7)
CLK
OUT
OUT
OUT
OUT
OUT
OUT
f
CLK
f
CLK
f
CLK
f
CLK
f
CLK
f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 10.1MHz, 30MHz Span (Notes 4, 7)
= 20.2MHz, 25MHz Span (Notes 4, 7)
= 5.02MHz, 25MHz Span (Notes 4, 7)
= 2.51MHz, 25MHz Span (Notes 4, 7)
= 1.00MHz, 25MHz Span (Notes 4, 7)
CLK
OUT
OUT
OUT
OUT
OUT
f
CLK
f
CLK
f
CLK
f
CLK
AC CHARACTERISTICS - HI5760/6IB, HI5760/6IA - 60MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 10.1MHz, 10MHz Span (Notes 4, 7)
= 5.02MHz, 2MHz Span (Notes 4, 7)
= 1.00MHz, 2MHz Span (Notes 4, 7)
-
-
-
-
-
-
-
-
-
-
-
-
75
76
78
71
76
56
63
55
68
73
73
71
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
CLK
OUT
OUT
OUT
f
CLK
f
CLK
Total Harmonic Distortion (THD) to
Nyquist
f
f
= 50MSPS, f
= 50MSPS, f
= 2.00MHz (Notes 4, 7)
= 1.00MHz (Notes 4, 7)
CLK
CLK
OUT
OUT
Spurious Free Dynamic Range,
SFDR to Nyquist
f
= 60MSPS, f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 25MSPS, f
= 20.2MHz, 30MHz Span (Notes 4, 7)
= 10.1MHz, 30MHz Span (Notes 4, 7)
= 20.2MHz, 25MHz Span (Notes 4, 7)
= 5.02MHz, 25MHz Span (Notes 4, 7)
= 2.51MHz, 25MHz Span (Notes 4, 7)
= 1.00MHz, 25MHz Span (Notes 4, 7)
= 5.02MHz, 25MHz Span (Notes 4, 7)
CLK
OUT
OUT
OUT
OUT
OUT
OUT
OUT
f
CLK
f
CLK
f
CLK
f
CLK
f
CLK
f
CLK
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Pin 18 Voltage with Internal Reference
1.04
1.16
±60
0.1
1.28
V
o
Internal Reference Voltage Drift
-
-
-
-
ppm/ C
Internal Reference Output Current
Sink/Source Capability
µA
Reference Input Impedance
-
-
1
-
-
MΩ
Reference Input Multiplying Bandwidth (Note 7)
1.4
MHz
4
HI5760
o
Electrical Specifications
AV
DD
= DV
DD
= +5V, V
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values (Continued)
REF
A
HI5760
= -40 C TO 85 C
o
o
T
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS D9-D0, CLK
Input Logic High Voltage with
(Note 3)
(Note 3)
(Note 3)
(Note 3)
3.5
2.1
-
5
3
0
0
-
V
V
V
V
5V Supply, V
IH
Input Logic High Voltage with
3V Supply, V
-
IH
Input Logic Low Voltage with
5V Supply, V
1.3
0.9
IL
Input Logic Low Voltage with
3V Supply, V
-
IL
Input Logic Current, I
-10
-10
-
-
-
+10
+10
-
µA
µA
pF
IH
IL
Input Logic Current, I
Digital Input Capacitance, C
IN
5
TIMING CHARACTERISTICS
Data Setup Time, t
See Figure 41 (Note 3)
See Figure 41 (Note 3)
See Figure 41
3
3
-
-
-
-
-
-
-
ns
ns
ns
ns
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
1
-
PD
CLK Pulse Width, t
, t
PW1 PW2
See Figure 41 (Note 3)
4
POWER SUPPLY CHARACTERISTICS
AV
DV
Power Supply
Power Supply
(Note 8)
2.7
5.0
5.0
23
4
5.5
V
V
DD
(Note 8)
2.7
5.5
DD
Analog Supply Current (I
)
(5V or 3V, IOUTFS = 20mA)
(5V or 3V, IOUTFS = 2mA)
(5V, IOUTFS = Don’t Care) (Note 5)
(3V, IOUTFS = Don’t Care) (Note 5)
(5V or 3V, IOUTFS = Don’t Care)
(5V, IOUTFS = 20mA) (Note 6)
(5V, IOUTFS = 2mA) (Note 6)
(5V, IOUTFS = 20mA) (Note 9)
(3.3V, IOUTFS = 20mA) (Note 9)
(3V, IOUTFS = 20mA) (Note 6)
(3V, IOUTFS = 20mA) (Note 9)
(3V, IOUTFS = 2mA) (Note 6)
Single Supply (Note 7)
-
30
mA
AVDD
-
-
mA
Digital Supply Current (I
DVDD
)
-
3
5
mA
-
1.5
1.6
165
70
150
75
85
67
27
-
-
mA
Supply Current (I
) Sleep Mode
-
3
mA
AVDD
Power Dissipation
-
-
mW
mW
mW
mW
mW
mW
mW
% FSR/V
-
-
-
-
-
-
-
-
-
-
-
-
Power Supply Rejection
NOTES:
-0.2
+0.2
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
ratio should be 31.969.
(typically 625µA). Ideally the
SET
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential coupled transformer.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.
7. See ‘Definition of Specifications’.
8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DV
and
DD
AV
DD
do not have to be equal.
9. Measured with the clock at 60MSPS and the output frequency at 10MHz.
5
HI5760
Typical Performance Curves, 5V Power Supply
80
75
70
65
60
55
50
76
74
72
70
-6dBFS
-6dBFS
0dBFS
-12dBFS
68
66
64
62
60
-12dBFS
0dBFS
1
2
3
4
5
6
7
8
9
10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 1. SFDR vs f
, CLOCK = 5MSPS
OUT
FIGURE 2. SFDR vs f
, CLOCK = 25MSPS
OUT
80
75
70
65
60
55
0dBFS
-6dBFS
75
70
-12dBFS
-6dBFS
65
60
55
-12dBFS
0dBFS
50
45
0
5
10
15
20
25
30
35
40
45
0
2
4
6
8
10
12
14
16
18
20
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 3. SFDR vs f
, CLOCK = 50MSPS
FIGURE 4. SFDR vs f
, CLOCK =100MSPS
OUT
OUT
75
80
75
70
65
60
55
50
45
25MSPS
70
65
60
55
50
45
50MSPS
100MSPS
6dBFS
-12dBFS
125MSPS
0dBFS
30
0
5
10
15
20
25
35
40
45
50
-25
-20
-15
-10
-5
0
AMPLITUDE (dBFS)
OUTPUT FREQUENCY (MHz)
FIGURE 5. SFDR vs f
, CLOCK = 125MSPS
FIGURE 6. SFDR vs AMPLITUDE, f = 10
/f
OUT
CLK OUT
6
HI5760
Typical Performance Curves, 5V Power Supply (Continued)
75
70
65
60
55
50
45
40
80
75
70
65
60
55
50
45
40
25MSPS
50MSPS
25MSPS
(3.38/3.63MHz)
100MSPS
50MSPS
(6.75/7.25MHz)
125MSPS
100MSPS
(13.5/14.5MHz)
125MSPS
(16.9/18.1MHz)
-25
-20
-15
-10
-5
0
-25
-20
-15
-10
-5
0
AMPLITUDE (dBFS)
AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS)
FIGURE 7. SFDR vs AMPLITUDE, f
/f
CLK OUT
= 5
FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, f /f = 7
CLK OUT
75
75
2.5MHz
10MHz
70
65
60
55
50
45
40
70
-6dBFS DIFF
0dBFS DIFF
65
20MHz
60
40MHz
55
-6dBFS SINGLE
50
0dBFS SINGLE
45
0
5
10
15
20
25
30
35
40
2
4
6
8
10
12
14
16
18
20
I
(mA)
OUTPUT FREQUENCY (MHz)
OUT
FIGURE 9. SFDR vs I
, CLOCK = 100MSPS
FIGURE 10. DIFFERENTIAL vs SINGLE-ENDED,
CLOCK = 100MSPS
OUT
80
75
70
65
60
55
50
45
40
-10
2.5MHz
f
= 100MSPS
-20
CLK
f
= 9.95MHz
OUT
AMPLITUDE = 0dBFS
SFDR = 64dBc
-30
10.1MHz
-40
14dB EXTERNAL ANALYZER ATTENUATION
-50
-60
-70
-80
-90
40.4MHz
-100
-110
-40
-20
0
20
40
60
80
0
50
FREQUENCY (MHz)
5MHz/DIV
o
TEMPERATURE ( C)
FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS
FIGURE 12. SINGLE TONE SFDR
7
HI5760
Typical Performance Curves, 5V Power Supply (Continued)
-10
-20
f
= 100MSPS
CLK
= 100MSPS
f
CLK
-20
-30
-40
-50
-60
-70
-80
-90
-100
-30
f
= 3.8,4.4,5.6,6.2MHz
OUT
f
= 13.5/14.5MHz
OUT
COMBINED PEAK
COMBINED PEAK
-40
AMPLITUDE = 0dBFS
SFDR = 71.4dBc
(IN A WINDOW)
AMPLITUDE = 0dBFS
SFDR = 62.9dBc
-50
14dB EXTERNAL
ANALYZER ATTENUATION
-60
-70
-80
-90
-100
-110
0
5MHz/div
50
5MHz/DIV
0.5
15
FREQUENCY (MHz)
1.45MHz/DIV
FIGURE 13. TWO TONE, CLOCK = 100MSPS
FIGURE 14. FOUR-TONE, CLOCK = 100MSPS
-20
-30
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
= 50MSPS
CLK
f
= 100MSPS
CLK
= 2.6,3.2,3.8,4.4,5.6,6.2,6.8MHz
f
= 1.9,2.2,2.8,3.1MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 73.6dBc
(IN A WINDOW)
OUT
f
OUT
COMBINED PEAK AMPLITUDE = 0dBFS
SFDR = 67dBc (IN A WINDOW)
-40
-50
-60
-70
-80
-90
-100
-110
0.5
950kHz/DIV
10
1.95MHz/DIV
20
0.5
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS
FIGURE 16. FOUR-TONE, CLOCK = 50MSPS
0.4
0.2
0
0.4
0.2
0
-0.2
-0.4
-0.2
-0.4
0
200
400
600
800
1000
0
200
400
600
800
1000
CODE
CODE
FIGURE 17. DIFFERENTIAL NONLINEARITY
FIGURE 18. INTEGRAL NONLINEARITY
8
HI5760
Typical Performance Curves, 5V Power Supply (Continued)
160
155
150
145
140
135
130
125
120
115
110
105
0
20
40
60
80
100
120
CLOCK RATE (MSPS)
FIGURE 19. POWER vs CLOCK RATE, f
/f
= 10, I
= 20mA
OUT
CLK OUT
Typical Performance Curves, 3V Power Supply
80
75
70
65
80
0dBFS
-6dBFS
75
-6dBFS
70
0dBFS
65
-12dBFS
60
-12dBFS
55
60
1
50
2
3
4
5
6
7
8
9
10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 20. SFDR vs f
, CLOCK = 5MSPS
FIGURE 21. SFDR vs f
0dBFS
, CLOCK = 25MSPS
OUT
OUT
80
75
70
65
60
55
50
80
75
70
65
60
55
50
45
-6dBFS
-6dBFS
-12dBFS
-12dBFS
0dBFS
0
5
10
15
20
25
30
35
40
45
0
2
4
6
8
10
12
14
16
18
20
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 22. SFDR vs f
, CLOCK = 50MSPS
FIGURE 23. SFDR vs f
, CLOCK = 100MSPS
OUT
OUT
9
HI5760
Typical Performance Curves, 3V Power Supply (Continued)
80
75
70
65
60
55
50
45
80
75
70
65
60
55
50
45
0dBFS
25MSPS
50MSPS
100MSPS
125MSPS
-6dBFS
-12dBFS
0
5
10
15
20
25
30
35
40
45
50
-25
-20
-15
-10
-5
0
OUTPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
FIGURE 24. SFDR vs f
, CLOCK = 125MSPS
25MSPS
FIGURE 25. SFDR vs AMPLITUDE, f
/f = 10
CLK OUT
OUT
75
70
80
75
70
65
60
55
50
45
40
25MSPS
65
(3.38/3.63MHz)
50MSPS
60
100MSPS
50MSPS
(6.75/7.25MHz)
5MSPS
55
100MSPS
125MSPS
(13.5/14.5MHz)
50
45
40
125MSPS
(16.9/18.1MHz)
-25
-20
-15
-10
-5
0
-25
-20
-15
-10
-5
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
FIGURE 26. SFDR vs AMPLITUDE, f
/f
= 5
FIGURE 27. SFDR vs AMPLITUDE OF TWO TONES, f
/f
CLK OUT
= 7
CLK OUT
80
80
2.5MHz
75
70
65
60
55
50
45
75
70
65
60
55
50
45
0dBFS DIFF
10MHz
20MHz
-6dBFS SINGLE
-6dBFS DIFF
40MHz
0dBFS SINGLE
0
5
10
15
20
25
30
35
40
2
4
6
8
10
12
14
16
18
20
I
(MA)
OUT
OUTPUT FREQUENCY (MHz)
FIGURE 28. SFDR vs I
, CLOCK = 100MSPS
FIGURE 29. DIFFERENTIAL vs SINGLE-ENDED,
CLOCK = 100MSPS
OUT
10
HI5760
Typical Performance Curves, 3V Power Supply (Continued)
80
75
70
65
60
55
50
45
40
-10
-20
f
= 100MSPS
CLK
f
2.5MHz
= 9.95MHz
OUT
AMPLITUDE = 0dBFS
SFDR = 63dBc
14dB EXTERNAL
ANALYZER ATTENUATION
-30
10.1MHz
-40
-50
-60
-70
-80
40.4MHz
60
-90
-100
-110
-40
-20
0
20
40
80
0
5MHz/DIV
50
o
TEMPERATURE ( C)
FREQUENCY (MHz)
FIGURE 30. SFDR vs TEMPERATURE, CLOCK = 100MSPS
-20
FIGURE 31. SINGLE TONE SFDR
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
= 100MSPS
CLK
f
= 100MSPS
CLK
= 13.5/14.5MHz
-30
-40
f
= 3.8,4.4,5.6,6.2MHz
OUT
f
OUT
COMBINED PEAK
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 70.6dBc
(IN A WINDOW)
AMPLITUDE = 0dBFS
SFDR = 61.5dBc
-50
14dB EXTERNAL
ANALYZER ATTENUATION
-60
-70
-80
-90
-100
-110
0.5
1.45MHz/DIV
15
0
5MHz/DIV
50
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 32. TWO-TONE, CLOCK = 100MSPS
FIGURE 33. FOUR-TONE, CLOCK = 100MSPS
-20
-30
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
= 100MSPS
CLK
f
= 50MSPS
CLK
f
= 2.6, 3.2, 3.8, 4.4,
OUT
f
= 1.9, 2.2, 2.8, 3.1MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 74.2dBc
OUT
5.6, 6.2, 6.8MHz
-40
COMBINED PEAK
-50
AMPLITUDE = 0dBFS
SFDR = 67.4dBc
(IN A WINDOW)
(IN A WINDOW)
-60
-70
-80
-90
-100
-110
0.5
1.95MHz/DIV
20
0
950kHz/DIV
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS
FIGURE 35. FOUR-TONE, CLOCK = 50MSPS
11
HI5760
Typical Performance Curves, 3V Power Supply (Continued)
0.4
0.2
0
0.4
0.2
0
-0.2
-0.4
-0.2
-0.4
0
200
400
600
800
1000
0
200
400
600
800
1000
CODE
CODE
FIGURE 36. DIFFERENTIAL NONLINEARITY
FIGURE 37. INTEGRAL NONLINEARITY
76
74
72
70
68
66
64
62
60
0
20
40
60
80
100
120
CLOCK RATE (MSPS)
FIGURE 38. POWER vs CLOCK RATE, f
/f
= 10, I
= 20mA
CLK OUT
OUT
12
HI5760
Timing Diagrams
50%
CLK
D9-D0
1
GLITCH AREA =
/ (H x W)
2
V
1
/
LSB ERROR BAND
2
HEIGHT (H)
I
OUT
t(ps)
WIDTH (W)
t
SETT
t
PD
FIGURE 39. OUTPUT SETTLING TIME DIAGRAM
FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
t
t
PW2
PW1
50%
CLK
t
t
SU
t
SU
SU
t
HLD
t
t
HLD
HLD
D9-D0
t
SETT
t
PD
I
OUT
t
t
SETT
SETT
t
t
PD
PD
FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
13
HI5760
either T
range) per degree C.
or T
. The units are ppm of FSR (full scale
Definition of Specifications
MIN
MAX
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Power Supply Rejection, is measured using a single power
supply. Its nominal +5V is varied ±10% and the change in the
DAC full scale output is noted.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is 0.707
of its original value.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. In the case of the
HI5760, the measurement was done by switching from code
0 to 256, or quarter scale. Termination impedance was 25Ω
due to the parallel resistance of the output 50Ω and the
oscilloscope’s 50Ω input. This also aids the ability to resolve
the specified error band without overdriving the oscilloscope.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either Tmin or Tmax.
The units are ppm per degree C.
Detailed Description
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification.
The HI5760 is a 10-bit, current out, CMOS, digital to analog
converter. Its maximum update rate is 125MSPS and can be
powered by either single or dual power supplies in the
recommended range of +3V to +5V. It consumes less than
165mW of power when using a +5V supply with the data
switching at 100MSPS. The architecture is based on a
segmented current source arrangement that reduces glitch
by reducing the amount of current switching at any one time.
The five MSBs are represented by 31 major current sources
of equivalent current. The five LSBs are comprised of binary
weighted current sources. Consider an input waveform to the
converter which is ramped through all the codes from 0 to
1023. The five LSB current sources would begin to count up.
When they reached the all high state (decimal value of 31)
and needed to count to the next code, they would all turn off
and the first major current source would turn on. To continue
counting upward, the 5 LSBs would count up another 31
codes, and then the next major current source would turn on
and the five LSBs would all turn off. The process of the
single, equivalent, major current source turning on and the
five LSBs turning off each time the converter reaches
another 31 codes greatly reduces the glitch at any one
switching point. In previous architectures that contained all
binary weighted current sources or a binary weighted
resistor ladder, the converter might have a substantially
larger amount of current turning on and off at certain, worst-
case transition points such as mid-scale and quarter scale
transitions. By greatly reducing the amount of current
switching at certain ‘major’ transitions, the overall glitch of
the converter is dramatically reduced, improving settling
times and transient problems.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through R
).
SET
Full Scale Gain Drift, is measured by setting the data inputs
to all ones and measuring the output voltage through a
known resistance as the temperature is varied from T
to
MIN
T
. It is defined as the maximum deviation from the value
MAX
measured at room temperature to the value measured at
either T or T . The units are ppm of FSR (full scale
MIN
MAX
range) per degree C.
Total Harmonic Distortion, THD, is the ratio of the DAC
output fundamental to the RMS sum of the first five
harmonics.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental to the largest harmonically or
non-harmonically related spur within the specified window.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance load should
be chosen such that the voltage developed does not violate
the compliance range.
Offset Error, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance. Offset error is defined as the maximum deviation
of the output current from a value of 0mA.
Offset Drift, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance as the temperature is varied from T
to T
.
MAX
MIN
It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
14
HI5760
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86kΩ R
resistor, then the input coding to output current will resemble
Digital Inputs and Termination
SET
The HI5760 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital
inputs are 50Ω lines, then 50Ω termination resistors should
be placed as close to the converter inputs as possible to the
digital ground plane (if separate grounds are used).
the following:
TABLE 1. INPUT CODING vs OUTPUT CURRENT
INPUT CODE (D9-D0)
11111 11111
IOUTA (mA)
IOUTB (mA)
20
10
0
0
10000 00000
10
20
00000 00000
Outputs
Ground Plane(s)
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
If separate digital and analog ground planes are used, then
all of the digital functions of the device and their
corresponding components should be over the digital ground
plane and terminated to the digital ground plane. The same
is true for the analog components and the analog ground
plane. The converter will function properly with a single
ground plane, as the Evaluation Board is configured in this
matter. Refer to the AppNote on the HI5760 Evaluation
Board for further discussion of the ground plane(s) upon
availability.
compliance range of -0.3V to 1.25V. R
should be
LOAD
chosen so that the desired output voltage is produced in
conjunction with the output full scale current, which is
described above in the ‘Reference’ section. If a known line
impedance is to be driven, then the output load resistor
should be chosen to match this impedance. The output
voltage equation is:
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AV
and DV . Also, should the layout be designed
DD
DD
V
= I
OUT
X R .
LOAD
OUT
using separate digital and analog ground planes, these
capacitors should be terminated to the digital ground for
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 21
and 22 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
DV
and to the analog ground for AV . Additional filtering
DD
DD
of the power supplies on the board is recommended. See
the AppNote on the HI5760 Evaluation Board for more
information upon availability.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ±60 ppm/oC drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO
pin (16) selects the reference. The internal reference can
be selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (to the
analog supply voltage) and the external reference driven
into REFIO, pin 17. The full scale output current of the
converter is a function of the voltage reference used and
is -300mV, imposing a maximum of 600mV
amplitude
P-P
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
V
= (2 x I
x R )V
OUT EQ
OUT
50Ω
100Ω
50Ω
IOUTB
IOUTA
PIN 21
50Ω
PIN 22
HI5760
the value of R
. I should be within the 2mA to 20mA
SET OUT
range, through operation below 2mA is possible, with
performance degradation.
FIGURE 42.
If the internal reference is used, V
FSADJ
will equal
approximately 1.16V (pin 18). If an external reference is used,
will equal the external reference. The calculation for
V
= 2 x I
x R , where R is ~12.5Ω.
EQ EQ
OUT
OUT
V
FSADJ
I
(Full Scale) is:
OUT
I
(Full Scale) = (V
/R
)x 32.
OUT
FSADJ SET
15
HI5760
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
1-10
D9 (MSB) Through Digital Data Bit 9, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
D0 (LSB)
11-14
15
NC
No Connect. Recommend ground.
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20µA active pulldown current.
16
17
18
REFLO
REFIO
FSADJ
Connect to analog ground to enable internal 1.2V reference or connect to AV
reference.
to disable internal
DD
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x V
/R .
FSADJ SET
19
20
21
COMP1
ACOM
IOUTB
For use in reducing bandwidth/noise. Recommended: connect 0.1µF to AV
.
DD
Analog Ground.
The complimentary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
22
23
IOUTA
NC
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
Internally connected to ACOM via a resistor. Recommend leave disconnected. Adding a capacitor to
ACOM for upward compatibility is valid. Grounding to ACOM is valid. (For upward compatibility to 12-bit
and 14-bit devices, pin 23 needs the ability to have a 0.1µF capacitor to ACOM.)
24
25
26
27
28
AV
DD
Analog Supply (+3V to +5V).
NC
DCOM
DV
No Connect. (For upward compatibility to 12 and 14b devices, pin 25 needs to be grounded to ACOM.)
Digital Ground.
Digital Supply (+3V to +5V).
DD
CLK
Input for clock. Positive edge of clock latches data.
16
HI5760
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
-A-
0.7125 17.70
3
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
17
HI5760
Thin Shrink Small Outline Plastic Packages (TSSOP)
M28.173
N
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.386
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
9.80
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.378
0.169
0.05
0.80
0.19
0.09
9.60
4.30
-
L
-
0.25
0.010
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
E1
e
3
-C-
4
α
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
α
28
28
7
o
o
o
o
NOTES:
0
8
0
8
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
Rev. 0 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
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相关型号：
HI5760/6IBZ
10-Bit, 125/60MSPS, High Speed D/A Converter; SOIC28, TSSOP28; Temp Range: -40° to 85°C
RENESAS
HI5760/6IBZ-T
PARALLEL, WORD INPUT LOADING, 0.035us SETTLING TIME, 10-BIT DAC, PDSO28, LEAD FREE, PLASTIC, MS-013-AE, SOIC-28
RENESAS
HI5760BIB
D/A Converter, 1 Func, Parallel, Word Input Loading, 0.035us Settling Time, PDSO28, PLASTIC, MS-013-AE, SOIC-28
ROCHESTER
HI5760BIBZ
D/A Converter, 1 Func, Parallel, Word Input Loading, 0.035us Settling Time, PDSO28, LEAD FREE, PLASTIC, MS-013-AE, SOIC-28
ROCHESTER
HI5760BIBZ-T
10-Bit, 125/60MSPS, High Speed D/A Converter; SOIC28, TSSOP28; Temp Range: -40° to 85°C
RENESAS
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