HI5741-EVS [INTERSIL]
14-Bit, 100MSPS, High Speed D/A Converter; 14位， 100MSPS ，高速D / A转换器
| 型号： | HI5741-EVS |
| 厂家： | 
Intersil |
| 描述： | 14-Bit, 100MSPS, High Speed D/A Converter |
| 文件： | 总13页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5741
®
Data Sheet
September 20, 2006
FN4071.12
14-Bit, 100MSPS, High Speed D/A
Converter
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .100MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . . . 1 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . . 1pV-s
• TTL/CMOS Compatible Inputs
The HI5741 is a 14-bit, 100MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 14-bit linearity is maintained along the
entire transfer curve.
• Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Cellular Base Stations
Ordering Information
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
PART
PART
TEMP.
PKG.
NUMBER
MARKING RANGE (°C) PACKAGE DWG. #
HI5741BIB
HI5741BIB -40 to +85 28 Ld SOIC M28.3
HI5741BIB-T HI5741BIB 28 Ld SOIC Tape and Reel M28.3
• Test Equipment
HI5741BIBZ
(Note)
HI5741BIBZ
-40 to +85 28 Ld SOIC M28.3
(Pb-free)
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
HI5741BIBZ-T HI5741BIBZ 28 Ld SOIC Tape and Reel M28.3
(Note)
(Pb-free)
Pinout
HI5741-EVS
+25
Evaluation Board
(SOIC)
HI5741
(28 LD SOIC)
TOP VIEW
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
D13 (MSB)
D12
D11
D10
D9
1
2
3
4
5
6
7
8
9
28 DGND
27 AGND
26
REF OUT
25 CTRL AMP OUT
24 CTRL AMP IN
D8
23 R
SET
22 AV
D7
EE
OUT
D6
21 I
20
D5
I
OUT
19 ARTN
18 DV
D4 10
D3 11
EE
17 DGND
16 DV
D2 12
D1 13
CC
15 CLOCK
D0 (LSB) 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2001, 2003, 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5741
Typical Application Circuit
+5V
HI5741
0.01µF
DV
(16)
CC
D13 (MSB) (1)
D12 (2)
D13
D12
D11
D10
D9
0.1µF
D11 (3)
(24) CTRL AMP IN
D10 (4)
D9 (5)
D8 (6)
D7 (7)
D6 (8)
D5 (9)
D4 (10)
(25) CTRL AMP OUT
-5.2V (AV
)
EE
D8
(26) REF OUT
D7
D/A OUT
D6
(21) I
OUT
64Ω
D5
D4
D3
64Ω
D3 (11)
(20) I
OUT
D2
D1
D2 (12)
D1 (13)
(23) R
SET
976Ω
D0 (LSB) (14)
CLK (15)
D0
(19) ARTN
(27) AGND
50Ω
DGND (17, 28)
(22) AV
EE
DV (18)
EE
0.01µF
0.1µF
0.1µF
0.01µF
-5.2V (AV
)
-5.2V (DV
)
EE
EE
Functional Block Diagram
(LSB) D0
D1
D2
D3
D4
D5
10 LSBs
CURRENT
CELLS
R2R
NETWORK
DATA
BUFFER/
LEVEL
14-BIT
MASTER
REGISTER
D6
ARTN
SLAVE
REGISTER
D7
SHIFTER
227Ω
227Ω
D8
D9
D10
D11
D12
15
15
15
UPPER
4-BIT
DECODER
SWITCHED
CURRENT
CELLS
I
OUT
I
OUT
(MSB) D13
CLK
REF CELL
CTRL AMP
IN
25Ω
+
OVERDRIVEABLE
VOLTAGE
CTRL AMP
OUT
-
REFERENCE
R
REF OUT
SET
AV
EE
AGND DV
DGND DV
CC
EE
FN4071.12
September 20, 2006
2
HI5741
Absolute Maximum ratings T = +25°C
Thermal Information
A
Digital Supply Voltage V
to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
70
CC
JA
Negative Digital Supply Voltage DV to DGND . . . . . . . . . . -5.5V
EE
Negative Analog Supply Voltage AV to AGND, ARTN . . . . -5.5V
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
HI5741BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
EE
Digital Input Voltages (D13-D0, CLK) to DGND. . . . . DV
to -0.5V
CC
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA
Voltage from CTRL AMP IN to AV . . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . -3.7V to AV
EE
EE
Analog Output Current (I
) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
OUT
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications AV , DV = -4.94V to -5.46V, V = +4.75 to +5.25V, V = Internal,
REF
EE
= +25°C
EE
CC
T
A
HI5741BI
T
= -40°C TO +85°C
A
PARAMETER
SYSTEM PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
14
-1.5
-1.75
-1.0
-
-
±1.0
-
-
1.5
1.75
1.0
75
10
-
Bits
LSB
LSB
LSB
µA
Integral Linearity Error, INL
(Note 5)
“Best Fit Straight Line”, T = +25°C
A
“Best Fit Straight Line”, T = -40°C to +85°C
A
Differential Linearity Error, DNL
(Note 5) T = +25°C
A
±0.5
8
Offset Error, I
(Note 5)
OS
Full Scale Gain Error, FSE
Full Scale Gain Drift
(Notes 3, 5)
-
3.2
±150
%
With Internal Reference
-
ppm
FSR/°C
Offset Drift Coefficient
(Note 4)
(Note 4)
(Note 4)
-
-
-
-20.48
-
0.05
µA/°C
mA
V
Full Scale Output Current, I
-
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Throughput Rate
-1.25
0
100
-
11
-
-
-
-
-
-
-
-
-
-
-
-
-
MSPS
ns
Output Voltage Settling Time
1
R
R
R
= 64Ω (Note 4) - Settling to 0.024%
= 64Ω (Note 4) - Settling to 0.012%
= 64Ω (Note 4)
-
-
-
-
-
-
-
-
-
-
-
-
L
L
L
( / th Scale Step Across Segment)
16
20
ns
Singlet Glitch Area, GE (Peak)
Output Slew Rate
1
pV•s
V/µs
ps
R = 64Ω, DAC Operating in Latched Mode (Note 4)
1,000
675
470
87
L
Output Rise Time
R = 64Ω, DAC Operating in Latched Mode (Note 4)
L
Output Fall Time
R = 64Ω, DAC Operating in Latched Mode (Note 4)
ps
L
Spurious Free Dynamic Range within a Window
(Note 4)
f
f
f
f
f
f
= 10 MSPS, f
= 20 MSPS, f
= 40 MSPS, f
= 50 MSPS, f
= 80 MSPS, f
= 1.23MHz, 2MHz Span
= 5.055MHz, 2MHz Span
= 16MHz, 10MHz Span
= 10.1MHz, 2MHz Span
= 5.1MHz, 2MHz Span
dBc
dBc
dBc
dBc
dBc
dBc
CLK
CLK
CLK
CLK
CLK
CLK
OUT
OUT
OUT
OUT
OUT
77
75
80
78
= 100 MSPS, f
= 10.1MHz, 2MHz Span
79
OUT
FN4071.12
September 20, 2006
3
HI5741
Electrical Specifications AV , DV = -4.94V to -5.46V, V = +4.75 to +5.25V, V = Internal,
REF
EE
EE
CC
T
= +25°C (Continued)
A
HI5741BI
T
= -40°C TO +85°C
A
PARAMETER
TEST CONDITIONS
MIN
TYP
86
85
77
74
73
71
76
MAX
UNITS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Spurious Free Dynamic Range to Nyquist
(Note 4)
f
f
f
f
f
f
= 10 MSPS, f
= 10 MSPS, f
= 25 MSPS, f
= 50 MSPS, f
= 75 MSPS, f
= 1.023MHz, 5MHz Span
= 2.02MHz, 5MHz Span
= 2.02MHz, 12.5MHz Span
= 5.055MHz, 25MHz Span
= 7.52MHz, 37.5MHz Span
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
OUT
OUT
OUT
OUT
OUT
= 100 MSPS, f
= 10.1MHz, 50MHz Span
OUT
Multi-Tone Power Ratio
(MTPR)
8 Tones, no Clipping, 110kHz Spacing, 220kHz spacing
between tones 4 and 5, f
= 20 MSPS (Note 7)
CLK
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, V
(Note 5)
(Note 4)
(Note 4)
-1.27
-
-1.23
50
-1.17
-
V
REF
Internal Reference Voltage Drift
µV/°C
µA
Internal Reference Output Current Sink/Source
Capability
-500
-
+50
Internal Reference Load Regulation
Amplifier Input Impedance
I
= 0 to I
REF
= -500µA
-
-
-
-
-
-
100
3
-
-
-
-
-
-
µV
MΩ
REF
(Note 4)
Amplifier Large Signal Bandwidth
Amplifier Small Signal Bandwidth
Reference Input Impedance (CTL IN)
Reference Input Multiplying Bandwidth (CTL IN)
4.0V
1.0V
Sine Wave Input, to Slew Rate Limited (Note 4)
Sine Wave Input, to -3dB Loss (Note 4)
1
MHz
MHz
kΩ
P-P
P-P
5
(Note 4)
12
75
R
= 50Ω, 100mV Sine Wave, to -3dB Loss at I
MHz
L
OUT
(Note 4)
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, V
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 4)
2.0
-
-
V
IH
Input Logic Low Voltage, V
-
-
-
-
-
-
0.8
400
700
-
V
IL
Input Logic Current, I
Input Logic Current, I
µA
µA
pF
IH
IL
-
Digital Input Capacitance, C
3.0
IN
TIMING CHARACTERISTICS
Data Setup Time, t
See Figure 1 (Note 4)
See Figure 1 (Note 4)
See Figure 1 (Note 4)
See Figure 1 (Note 4)
3
0.5
-
2.0
0.25
4.5
-
-
-
-
ns
ns
ns
ns
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
CLK Pulse Width, t
, t
PW1 PW2
1.0
0.85
POWER SUPPLY CHARACTERISTICS
IV
IV
IV
(Note 5)
(Note 5)
(Note 5)
(Note 5)
-
-
-
-
-
42
75
13
650
5
50
95
20
-
mA
mA
EEA
EED
CCD
mA
Power Dissipation
Power Supply Rejection Ratio
NOTES:
mW
µA/V
V
±5%, V ±5%
EE
-
CC
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Gain Error measured as the error in the ratio between the full scale output current and the current through R
ratio should be 16.
(typically 1.28mA). Ideally the
SET
4. Parameter guaranteed by design or characterization and not production tested.
5. All devices are 100% tested at +25°C.
6. Dynamic Range must be limited to a 1V swing within the compliance range.
7. In testing MTPR, tone frequencies ranged from 1.95MHz to 3.05MHz. The ratio is measured as the range from peak power to peak distortion in
the region of removed tones.
FN4071.12
September 20, 2006
4
HI5741
Timing Diagrams
50%
CLK
D13-D0
1
GLITCH AREA =
/ (H x W)
2
V
ERROR BAND
HEIGHT (H)
I
OUT
t(ps)
WIDTH (W)
t
t
SETT
PD
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
t
t
PW2
PW1
50%
CLK
t
t
t
SU
SU
SU
t
t
t
HLD
HLD
HLD
D13-D0
t
SETT
t
PD
I
OUT
t
t
SETT
SETT
t
t
PD
PD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
FN4071.12
September 20, 2006
5
HI5741
Typical Performance Curves
-1.17
-1.18
-1.19
-1.20
-1.21
-1.22
-1.23
-1.24
-1.25
-1.26
-1.27
670
660
650
640
630
620
NOTE: CLOCK FREQUENCY DOES NOT
610
ALTER POWER DISSIPATION
600
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 4. TYPICAL POWER DISSIPATION OVER
TEMPERATURE
FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER
TEMPERATURE
1.5
1.0
0.5
0
0.8
0.5
0.25
0
-0.5
-1.0
-1.5
-0.25
-0.5
-0.8
0
5000
10,000
15,000
0
5000
10,000
CODE
15,000
CODE
FIGURE 6. TYPICAL INL PERFORMANCE
FIGURE 7. TYPICAL DNL PERFORMANCE
40
35
30
25
20
15
10
5
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
0
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 8. TYPICAL OFFSET CURRENT OVER
TEMPERATURE
FIGURE 9. TYPICAL GAIN ERROR OVER TEMPERATURE
FN4071.12
September 20, 2006
6
HI5741
Typical Performance Curves (Continued)
90
85
80
75
70
65
60
90
85
80
75
70
65
1
= ( / ) f
1
f
f
= ( / ) f
CLK
OUT
10 CLK
OUT
5
60
10
20
30
40
50 60 70 80 90100
10
20
30
40
50 60 70 80 90100
f
(MSPS)
CLK
f
(MSPS)
CLK
FIGURE 10. SFDR vs CLOCK FREQUENCY
FIGURE 11. SFDR vs CLOCK FREQUENCY
82
80
76
74
72
70
68
66
64
62
82
80
78
76
74
72
70
68
66
64
62
f
= 75 MSPS
CLK
f
= 50 MSPS
CLK
1
5
10
15
1
5
10
f
(MSPS)
OUT
f
(MHz)
OUT
FIGURE 12. SFDR vs f
FIGURE 13. SFDR vs f
OUT
OUT
80
78
76
74
72
70
68
66
64
62
-72
-74
-76
-78
-80
-82
-84
-86
f
= 2.03MHz
OUT
3RD HARMONIC
2ND HARMONIC
f
= 100 MSPS
CLK
1
5
10
15
20
10
20
30
40
50 60 70 80 90100
f
(MHz)
f
(MSPS)
OUT
CLK
FIGURE 14. SFDR vs f
FIGURE 15. HARMONIC DISTORTION vs CLOCK FREQUENCY
OUT
FN4071.12
September 20, 2006
7
HI5741
Typical Performance Curves (Continued)
10dB/
10dB/
f
= 20 MSPS
CLK
f
f
= 100 MSPS
= 26.6MHz
MTPR = 75.17dBc
CLK
OUT
SFDR = 77.5dBc
S
S
C
C
CENTER 26.637MHz
START 1.900MHz
SPAN 2.000MHz
STOP 3.100MHz
FIGURE 17. SFDR WITHIN A WINDOW
FIGURE 16. TYPICAL MTPR PERFORMANCE
12-BIT WINDOW
∆: 240µV
@: -30.96mV
∆: 300µV
@: -124.1mV
SETTLING TIME
~10ns
1
1
GLITCH = (0.5) • (300µV) • (3.3ns)
= 0.495pV/s
CH1 1.00mV~
M 5.0ns CH1
-16.9mV
CH1 1.00mV
M 5.0ns CH1
-109mV
FIGURE 18. TYPICAL SETTLING TIME PERFORMANCE
FIGURE 19. TYPICAL GLITCH ENERGY
Pin Descriptions
PIN NO.
1-14
15
PIN NAME
PIN DESCRIPTION
D13 (MSB) thru D0 (LSB) Digital Data Bit 13, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit.
CLK
DV
Data Clock Pin 100kHz to 100 MSPS.
Digital Logic Supply +5V.
Digital Ground.
16
CC
DGND
17, 28
18
DV
-5.2V Logic Supply.
EE
23
R
External Resistor to set the full scale output current. I = 16 x (V
FS
/R ). Typically 976Ω.
REFOUT SET
SET
27
AGND
ARTN
Analog Ground Supply current return pin.
Analog Signal Return for the R/2R ladder.
Current Output Pin.
19
21
I
I
OUT
OUT
20
Complementary Current Output pin.
-5.2V Analog Supply.
22
AV
EE
24
CTRL AMP IN
CTRL AMP OUT
REF OUT
Input to the current source base rail. Typically connected to CTRL AMP OUT and a 0.1µF capacitor to AV
Allows external control of the current sources.
.
EE
25
26
Control amplifier out. Provides precision control of the current sources when connected to CTRL AMP IN
such that I = 16 x (V /R ).
FS REFOUT SET
-1.23V (typical) bandgap reference voltage output. Can sink up to 500µA or be overdriven by an external
reference capable of delivering up to 2mA.
FN4071.12
September 20, 2006
8
HI5741
Detailed Description
HI5741
DAC
Z
= 50Ω
O
The HI5741 is a 14-bit, current out D/A converter. The DAC
can convert at 100 MSPS and runs on +5V and -5.2V
supplies. The architecture is an R/2R and segmented
switching current cell arrangement to reduce glitch. Laser
trimming is employed to tune linearity to true 14-bit levels.
The HI5741 achieves its low power and high speed
performance from an advanced BiCMOS process. The
HI5741 consumes 650mW (typical) and has an improved
hold time of only 0.25ns (typical). The HI5741 is an excellent
converter for use in communications applications and high
performance video systems.
CLK
R
= 50Ω
T
FIGURE 20. HI5741 CLOCK LINE TERMINATION
Rise and Fall times and propagation delay of the line will be
affected by the shunt terminator. The terminator should be
connected to DGND.
Noise Reduction
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1µF and 0.01µF
ceramic capacitors placed as close to the body of the
Digital Inputs
HI5741 as possible on the analog (AV ) and digital (DV
supplies. The analog and digital ground returns should be
connected together back at the device to ensure proper
)
The HI5741 is a TTL/CMOS compatible D/A. Data is latched
by a Master register. Once latched, data inputs D0 (LSB)
through D13 (MSB) are internally translated from TTL to ECL.
The internal latch and switching current source controls are
implemented in ECL technology to maintain high switching
speeds and low noise characteristics.
EE
EE
operation on power up. The V
power pin should also be
CC
decoupled with a 0.1µF capacitor.
Reduction of digital noise (caused by high slew rates on the bit
inputs to the HI5741) can be accomplished through the use of
series termination resistors. The use of serial resistors, which
combine with the input capacitance of the HI5741 to induce a
low pass filter characteristic, keeps the noise generated by high
slew rate digital signals from corrupting the high accuracy
analog data. Refer to Application Note AN9619 “Optimizing
setup conditions for high accuracy measurements of the
HI5741” for further details on selecting the proper value of
series termination to meet application specific needs.
Decoder/Driver
The architecture employs a split R/2R ladder and segmented
current source arrangement. Bits D0 (LSB) through D9 directly
drive a typical R/2R network to create the binary weighted
current sources. Bits D10 through D13 (MSB) pass through a
“thermometer” decoder that converts the incoming data into 15
individual segmented current source enables. This split
architecture helps to improve glitch, thus resulting in a
more constant glitch characteristic across the entire output
transfer function.
Reference
The internal reference of the HI5741 is a -1.23V (typical)
bandgap voltage reference with 50µV/°C of temperature drift
(typical). The internal reference is connected to the Control
Amplifier which in turn drives the segmented current cells.
Reference Out (REF OUT) is internally connected to the
Control Amplifier. The Control Amplifier Output (CTRL OUT)
should be used to drive the Control Amplifier Input (CTRL IN)
Clocks and Termination
The internal 14-bit register is updated on the rising edge of the
clock. Since the HI5741 clock rate can run to 100 MSPS, to
minimize reflections and clock noise into the part, proper
termination should be used. In PCB layout clock runs should
be kept short and have a minimum of loads. To guarantee
consistent results from board to board, controlled impedance
and a 0.1µF capacitor to analog V . This improves settling
EE
PCBs should be used with a characteristic line impedance Z
of 50Ω.
O
time by providing an AC ground at the current source base
node. The Full Scale Output Current is controlled by the REF
To terminate the clock line, a shunt terminator to ground is
the most effective type at a 100 MSPS clock rate. A typical
value for termination can be determined by the equation:
OUT pin and the set resistor (R
). The ratio is:
) x 16.
SET
I
(Full Scale) = (V
/R
OUT
REF OUT SET
R
= Z
O
The internal reference (REF OUT) can be overdriven with a
more precise external reference to provide better
performance over temperature. Figure 21 illustrates a typical
external reference configuration.
T
for the termination resistor. For a controlled impedance board
with a Z of 50Ω, the R = 50Ω. Shunt termination is best
used at the receiving end of the transmission line or as close
O
T
to the HI5741 CLK pin as possible.
HI5741
-1.25V
(26) REF OUT
R
-5.2V
FIGURE 21. EXTERNAL REFERENCE CONFIGURATION
FN4071.12
September 20, 2006
9
HI5741
Multiplying Capability
TABLE 1. CAPACITOR SELECTION
The HI5741 can operate in two different multiplying
configurations. For frequencies from DC to 100kHz, a signal
f
C
C
2
IN
1
100kHz
>1MHz
0.01µF
1µF
of up to 0.6V
can be applied directly to the REF OUT pin
P-P
0.001µF
0.1µF
as shown in Figure 22.
Also, the input signal must be limited to 1V
P-P
distortion in the DAC output current caused by excessive
modulation of the internal current sources.
to avoid
CTRL OUT
CTRL IN
0.01µF
AV
EE
HI5741
Outputs
REF OUT
RSET
C
(OPTIONAL)
IN
V
The outputs I
OUT
and I
OUT
outputs. Current is steered to either I
are complementary current
or I in proportion
IN
OUT
OUT
to the digital input code. The sum of the two currents is always
equal to the full scale current minus one LSB. The current
output can be converted to a voltage by using a load resistor.
Both current outputs should have the same load resistor (64Ω
typically). By using a 64Ω load on the output, a 50Ω effective
FIGURE 22. LOW FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
The signal must have a DC value such that the peak
negative voltage equals -1.25V. Alternately, a capacitor can
be placed in series with REF OUT if a DC multiplying is not
required. The lower input bandwidth can be calculated using
the following formula:
output resistance (R
) is achieved due to the 227Ω (±15%)
OUT
parallel resistance seen looking back into the output. This is the
nominal value of the R2R ladder of the DAC. The 50Ω output is
needed for matching the output with a 50Ω line. The load
resistor should be chosen so that the effective output resistance
1
C
= -------------------------------------------
IN
(R
) matches the line resistance. The output voltage is:
OUT
(2π)(1400)(f
)
IN
V
I
= I
x R .
OUT
OUT
OUT
For multiplying frequencies above 100kHz, the CTRL IN pin
can be driven directly as seen in Figure 23.
is defined in the reference section. I
OUT
is not trimmed to
OUT
14 bits, so it is not recommended that it be used in conjunction
HI5741
with I in a differential-to-single-ended application. The
OUT
compliance range of the output is from -1.25V to 0V, with a
CTRL OUT
C
2
1V
P-P
voltage swing allowed within this range.
200Ω
AV
EE
TABLE 2. INPUT CODING vs CURRENT OUTPUT
V
C
1
IN
INPUT CODE (D13-D0)
I
(mA)
I
(mA)
OUT
CTRL IN
OUT
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0000
-20.48
0
50Ω
-10.24
0
-10.24
-20.48
FIGURE 23. HIGH FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
Settling Time
The nominal input/output relationship is defined as:
The settling time of the HI5741 is measured as the time it
∆V
IN
∆I
= -------------
takes for the output of the DAC to settle to within a ±defined
1
OUT
80Ω
error band of its final value during a / th (code 0000... to
16
In order to prevent the full scale output current from
exceeding 20.48mA, the R resistor must be adjusted
according to the following equation:
0001 0000.... or 1111... to 1110 1111...) scale transition. In
defining settling time specifications for the HI5741, two levels
of accuracy are considered. The accuracy levels defined for
the HI5741 are 12 (or 0.024%) and 13 (0.012%) bits.
SET
16V
REF
R
= -----------------------------------------------------------------------------------------
SET
V
Glitch
IN(PEAK)
⎛
⎝
⎞
⎠
-----------------------------
I
(Full scale) –
OUT
80Ω
The output glitch of the HI5741 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
The circuit in Figure 23 can be tuned to adjust the lower
cutoff frequency by adjusting capacitor values. Table 1
illustrates the relationship.
FN4071.12
September 20, 2006
10
HI5741
to change before another. In order to minimize this, the
Intersil HI5741 employs an internal register, just prior to the
current sources, which is updated on the clock edge. Lastly,
the worst case glitch on traditional D/A converters usually
occurs at the major transition (i.e., code 8191 to 8192).
However, due to the split architecture of the HI5741, the
glitch is moved to the 1023 to 1024 transition (and every
subsequent 1024 code transitions thereafter). This split
R/2R segmented current source architecture, which
decreases the amount of current switching at any one time,
makes the glitch practically constant over the entire output
range. By making the glitch a constant size over the entire
output range this effectively integrates this error out of the
end application.
5kΩ
-
-
REF OUT
(26)
+
+
5kΩ
60Ω
1
1
/
CA2904
/
CA2904
2
2
0.1µF
240Ω
240Ω
HI5741
50Ω
I
OUT
(21)
V
OUT
-
+
HFA1100
FIGURE 26. BIPOLAR OUTPUT CONFIGURATION
Interfacing to the HSP45106 NCO-16
In measuring the output glitch of the HI5741 the output is
terminated into a 64Ω load. The glitch is measured at any
one of the current cell carry (code 1023 to 1024 transition or
any multiple thereof) throughout the DACs output range.
The HSP45106 is a 16-bit Numerically Controlled Oscillator
(NCO). The HSP45106 can be used to generate various
modulation schemes for Direct Digital Synthesis (DDS)
applications. Figure 27 shows how to interface an HI5741 to
the HSP45106.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 25 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt/seconds (pV/s).
Definition of Specifications
Integral Linearity Error (INL) is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
HI5741
100MHz
SCOPE
LOW PASS
FILTER
(21) I
OUT
Differential Linearity Error (DNL) is the measure of the error
in step size between adjacent codes along the converter’s
transfer curve. Ideally, the step size is 1 LSB from one code to
the next, and the deviation from 1 LSB is known as DNL. A
DNL specification of greater than -1 LSB guarantees
monotonicity.
64Ω
50Ω
FIGURE 24. GLITCH TEST CIRCUIT
Feedthru is the measure of the undesirable switching noise
coupled to the output.
Output Voltage Full Scale Settling Time is the time
required from the 50% point on the clock input for a full scale
1
a (mV)
step to settle within an ± / LSB error band.
2
Output Voltage Small Scale Settling Time is the time
GLITCH ENERGY = (a x t)/2
required from the 50% point on the clock input for a 100mV
1
step to settle within an / LSB error band. This is used by
2
t (ns)
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
FIGURE 25. MEASURING GLITCH ENERGY
Glitch Area (GE) is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as a volt • time specification
(typically pV-s).
Applications
Bipolar Applications
To convert the output of the HI5741 to a bipolar 4V swing,
the following applications circuit is recommended. The
reference can only provide 125µA of drive, so it must be
buffered to create the bipolar offset current needed to
generate the -2V output with all bits ‘off’. The output current
must be converted to a voltage and then gained up and
offset to produce the proper swing. Care must be taken to
compensate for the voltage swing and error.
Differential Gain (∆A ) is the gain error from an ideal sine
V
wave with a normalized amplitude.
Differential Phase (∆Φ) is the phase error from an ideal sine
wave.
FN4071.12
September 20, 2006
11
HI5741
Signal to Noise Ratio (SNR) is the ratio of a fundamental to
Multi-Tone Power Ratio (MTPR) is the amplitude difference
from peak amplitude to peak distortion (either harmonic or
non-harmonic). An 8 tone pattern is loaded into the D/A. The
tone spacing of this pattern (∆f) is created such that tones 1
through 4 and 5 through 8 are spaced equally, with tones 4
and 5 spaced at 2∆f. MTPR is measured as the dynamic
range from peak power to peak distortion in the 2∆f gap.
the noise floor of the analog output. The first 5 harmonics
1
are ignored, and an output filter of / the clock frequency is
2
used to eliminate alias products.
Total Harmonic Distortion (THD) is the ratio of the DAC
output fundamental to the RMS sum of the harmonics. The
1
first 5 harmonics are included, and an output filter of / the
2
clock frequency is used to eliminate alias products.
Intermodulation Distortion (IMD) is the measure of the
sum and difference products produced when a two tone
input is driven into the D/A. The distortion products created
will arise at sum and difference frequencies of the two tones.
IMD can be calculated using the following equation:
Spurious Free Dynamic Range (SFDR) is the amplitude
difference from a fundamental to the largest harmonically or
non-harmonically related spur. A sine wave is loaded into
1
the D/A and the output filtered at / the clock frequency to
2
20Log (RMS of Sum and Difference Distortion Products)
eliminate noise from clocking alias terms.
IMD = ------------------------------------------------------------------------------------------------------------------------------------------------------
(RMS Amplitude of the Fundamental)
U2
K9
33 MSPS
CLK
CLK
C11
B11
C10
TO RF
UP-CONVERT
STAGE
MOD2
MOD1
BASEBAND
BIT
STREAM
FILTER
ENCODER
U1
DV
MOD0
16
R
1
V
CC
CC
L1
21
20
A11
I
DACSTRB
OUT
/
PMSEL
K3
L2
L3
L4
J5
K5
L5
K6
J6
J7
L7
L6
L8
K8
L9
L10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
64
F10
F9
F11
H11
G11
G9
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
SIN15
SIN14
SIN13
SIN12
SIN11
SIN10
SIN9
SIN8
SIN7
SIN6
SIN5
SIN4
SIN3
SIN2
SIN1
SIN0
ENPOREG
ENOFREG
ENCFREG
ENPHAC
ENTIREG
INHOFR
R
2
I
OUT
64
24
25
C AMP IN
-5.2V_A
-5.2V_A
J11
G10
C
0.1µF
0.01µF
2
1
INITPAC
INITTAC
C AMP OUT
C
D10
J10
TEST
V
PARSER
BINFMT
CC
26
23
19
CONTROLLER
K11
REF OUT
D0 (LSB)
R
3
R
B8
A8
B6
B7
A7
C7
C6
A6
A5
C5
A4
B4
A3
A2
B3
A1
15
SET
C15_MSB
C4
CLK
976
R
50
4
28
17
DGND
DGND
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
ARET
27
22
AV
AV
SS
C2
B1
C1
D1
E3
E2
E1
F2
F3
G3
G1
G2
H1
H2
J1
COS15
COS14
COS13
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
COS3
COS2
COS1
COS0
18
-5.2V_A
DV
EE
EE
-5.2V_D
HI5741
L
1
-5.2V_D
-5.2V_A
10µH
C2
C1
C0
B10
B9
A10
E11
E9
A2
A1
A0
CS
WR
L
2
10µH
K1
H10
B2
V
V
PACI
TICO
CC
K2
J2
OES
OEC
CC
HSP45106
FIGURE 27. PSK MODULATOR USING THE HI5741 AND HSP45106 16-BIT NCO
FN4071.12
September 20, 2006
12
HI5741
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
0.7125 17.70
3
-A-
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
µ
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4071.12
September 20, 2006
13
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