FDC37C68X_技术文档

FDC37C68x

128 Pin Enhanced Super I/O Controller Supporting

GPI/O Pins

FEATURES

-

2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,

250 Kbps Data Rates

Programmable Precompensation Modes

·

5 Volt Operation

PC98/99 and ACPI Compliant

SMI Support

Intelligent Auto Power Management

2.88MB Super I/O Floppy Disk Controller

Relocatable to 480 Different Addresses

15 IRQ Options (using Serial IRQ)

Three DMA Options

-

·

8042 Keyboard Controller

-

2K Program ROM

256 Bytes Data RAM

Asynchronous Access to Two Data

Registers and One Status Register

Supports Interrupt and Polling Access

8 Bit Timer/Counter

-

Licensed CMOS 765B Floppy Disk

Controller

Advanced Digital Data Separator

Software and Register Compatible with

SMSC's Proprietary 82077AA

Compatible Core

Sophisticated Power Control Circuitry

(PCC) Including Multiple Powerdown

Modes for Reduced Power Consumption

Game Port Select Logic

Supports Two Floppy Drives Directly

24mA AT Bus Drivers

Low Power CMOS Design

Supports Vertical Recording Format

16 Byte Data FIFO

100% IBM® Compatibility

Detects All Overrun and Underrun

Conditions

Port 92 Support

-

·

Serial Ports

-

Relocatable to 480 Different Addresses

15 IRQ Options (Using Serial IRQ)

Two High Speed NS16C550 Compatible

UARTs with Send/Receive 16 Byte

FIFOs

Programmable Baud Rate Generator

Modem Control Circuitry Including 230K

and 460K Baud

-

IrDA, HP-SIR, ASK-IR Support

Multi-ModeÔ Parallel Port with ChiProtect

Relocatable to 480 Different Addresses

15 IRQ Options (Using Serial IRQ)

Three DMA Options

·

-

Enhanced Mode

Standard Mode: IBM PC/XT^®, PC/AT^®,

and PS/2Ô Compatible Bidirectional

ParallelPort

-

24mA Drivers and Schmitt Trigger Inputs

DMA Enable Logic

Data Rate and Drive Control Registers

Floppy Disk Available on Parallel Port Pins

Enhanced Digital Data Separator

Low Cost Implementation

-

Enhanced Parallel Port (EPP)

Compatible EPP 1.7 and EPP 1.9 (IEEE

1284 Compliant)

High Speed Mode

Microsoft and Hewlett Packard

·

-

No Filter Components Required

Extended Capabilities Port (ECP)

Compatible (IEEE 1284 Compliant)

Incorporates ChiProtectÔ Circuitry for

Protection Against Damage Due to

Printer Power-On

·

ISA Host Interface

16 Bit Address Qualification

Serial IRQ Compatible with “Serialized IRQ

Support for PCI Systems”

ISA Plug-and-Play Compatible Register Set

31 GPI/O Pins

-

·

ISA

12 mA Output Drivers

128 Pin QFP Package

GENERAL DESCRIPTION

a keyboard The FDC37C68x provides support for the ISA

The FDC37C68x incorporates

interface, SMSC's true CMOS 765B floppy disk

controller, advanced digital data separator, 16

byte data FIFO, two 16C550 compatible UARTs,

one Multi-Mode parallel port which includes

ChiProtect circuitry plus EPP and ECP support,

on-chip 24 mA AT bus drivers, game port chip

select and two floppy direct drive support, as

well as SMI support. The true CMOS 765B core

provides 100% compatibility with IBM PC/XT

and PC/AT architectures in addition to providing

data overflow and underflow protection. The

SMSC advanced digital data separator

incorporates SMSC's patented data separator

technology, allowing for ease of testing and use.

Both on-chip UARTs are compatible with the

NS16C550. The parallel port, and the game port

select logic are compatible with IBM PC/AT

architecture, as well as EPP and ECP. The

FDC37C68x incorporates sophisticated power

control circuitry (PCC). The PCC supports

multiple low power down modes.

Plug-and-Play Standard (Version 1.0a) and

provides for the recommended functionality to

support Windows '95. Through internal

configuration

registers,

each

of

the

FDC37C68x's logical device's I/O address, DMA

channel and IRQ channel may be programmed.

There are 480 I/O address location options, 15

IRQ options, and three DMA channel options for

each logical device.

The FDC37C68x does not require any external

filter components and is, therefore, easy to use

and offers lower system cost and reduced board

area. The FDC37C68x is software and register

compatible with SMSC's proprietary 82077AA

core.

IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark

of International Business Machines Corporation

SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode

are trademarks of Standard Microsystems Corporation

2

TABLE OF CONTENTS

FEATURES........................................................................................................................................1

GENERAL DESCRIPTION .................................................................................................................2

PIN CONFIGURATION.......................................................................................................................4

DESCRIPTION OF PIN FUNCTIONS .................................................................................................5

FUNCTIONAL DESCRIPTION..........................................................................................................13

SUPER I/O REGISTERS ..................................................................................................................13

HOST PROCESSOR INTERFACE....................................................................................................13

FLOPPY DISK CONTROLLER .........................................................................................................15

FDC INTERNAL REGISTERS...........................................................................................................15

INSTRUCTION SET .........................................................................................................................42

SERIAL PORT (UART).....................................................................................................................69

INFRARED INTERFACE ..................................................................................................................83

PARALLEL PORT............................................................................................................................84

IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES ....................................................86

EXTENDED CAPABILITIES PARALLEL PORT.................................................................................92

AUTO POWER MANAGEMENT.....................................................................................................108

GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION...............................................................114

8042 KEYBOARD CONTROLLER FUNCTIONAL DESCRIPTION..................................................127

SYSTEM MANAGEMENT INTERRUPT (SMI)................................................................................134

SMI TIMEOUT OVERRIDE.............................................................................................................135

SERIAL INTERRUPTS...................................................................................................................136

CONFIGURATION .........................................................................................................................140

OPERATIONAL DESCRIPTION.....................................................................................................176

TIMING DIAGRAMS ......................................................................................................................180

ECP PARALLEL PORT TIMING ....................................................................................................200

3

PIN CONFIGURATION

IOCHRDY

TC

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

PD3

PD2

PD1

PD0

DRQ_C

nDAK_C

DRQ_B

nDAK_B

DRQ_A

nDAK_A

RST_DRV

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

VSS

AEN

nIOW

nIOR

VCC

nSLCTIN

nINIT

nERROR

nALF

nSTROBE

RXD1

FDC37C68x

128 Pin QFP

TXD1

nDSR1

nRTS1/SYSOPT

nCTS1

nDTR1

nRI1

nDCD1

RXD2

TXD2

nDSR2

nRTS2

nCTS2

nDTR2

nRI2

VCC

SA12

SA11

SA10

SA9

nDCD2

4

DESCRIPTION OF PIN FUNCTIONS

NAME

SYMBOL

BUFFER TYPE

NO./QFP

PROCESSOR/HOST INTERFACE

48:55

30:42,

22:24

46

System Data Bus

SD[0:7]

I/O24

I

System Address Bus

SA[0:15]

Address Enable (DMA master has bus

control)

AEN

I

64

56

I/O Channel Ready

Reset Drive

IOCHRDY

RESET_DRV

DRQ_A-C

OD24

IS

58,60,

62

DMA Requests

O24

57,59,

61

DMA Acknowledge

nDAK_A-C

I

63

44

45

25

21

26

Terminal Count

TC

I

I/O Read

nIOR

nIOW

HCLK

CLKIN

14CLK

I

I/O Write

High Speed Clock Out 24/48MHz

14.318MHz Clock Input

14.318MHz Clock Output

O20

ICLK

O16SR

SERIAL IRQ

Serial IRQ

28

27

SERIRQ

PCICLK

I/O8

PCI Clock

ICLK

POWER PINS

+5V Supply Voltage

20,43,

75,93,

107

VCC

GND

1, 8, 29,

47,69,98

Ground

FDD INTERFACE

Read Disk Data

17

12

nRDATA

nWGATE

IS

Write Gate

O24/OD24

5

DESCRIPTION OF PIN FUNCTIONS

NAME SYMBOL

BUFFER TYPE

NO./QFP

11

13

9

Write Disk Data

nWDATA

nHDSEL

nDIR

O24/OD24

024/OD24

IS

Head Select (1 = side 0 )

Step Direction (1 = out )

Step Pulse

10

18

5,6

7,4

16

15

14

3,2

nSTEP

Disk Change

nDSKCHG

nDS[1:0]

nMTR[1:0]

nWPROT

nTR0

Drive Select Lines

Motor On Lines

O24/OD24

IS

Write Protected

Track 0

IS

Index Pulse Input

Drive Density Select [1:0]

nINDEX

IS

DRVDEN

[1:0]

O24/OD24

SERIAL PORT 1 INTERFACE

113

114

116

Receive Serial Data 1

Transmit Serial Data 1

Request to Send 1

RXD1

TXD1

I

O4

O4/I

nRTS1/

SYSOPT

117

118

115

120

119

Clear to Send 1

nCTS1

nDTR1

nDSR1

nDCD1

nRI1

I

Data Terminal Ready 1

Data Set Ready 1

Data Carrier Detect 1

Ring Indicator 1

O4

I

SERIAL PORT 2 INTERFACE

121

122

124

125

126

123

128

Receive Serial Data 2 (Note 2)

Transmit Serial Data 2 (Note 2)

Request to Send 2 (Note 2)

Clear to Send 2 (Note 2)

RXD2

I

TXD2

O24

nRTS2

nCTS2

nDTR2

nDSR2

nDCD2

O4

I

Data Terminal Ready 2 (Note 2)

Data Set Ready 2 (Note 2)

Data Carrier Detect 2 (Note 2)

O4

I

6

DESCRIPTION OF PIN FUNCTIONS

NAME

SYMBOL

BUFFER TYPE

NO./QFP

127

Ring Indicator 2 (Note 2)

nRI2

I

PARALLEL PORT INTERFACE

106:99

108

109

111

112

96

Parallel Port Data Bus

PD[0:7]

nSLCTIN

nINIT

I/O24

Printer Select

OD24/O24

Initiate Output

Auto Line Feed

Strobe Signal

OD24/O24

nALF

OD24/O24

nSTB

OD24/O24

Busy Signal

BUSY

nACK

PE

I

97

Acknowledge Handshake

Paper End

95

94

Printer Selected

Error at Printer

SLCT

110

nERROR

KEYBOARD/MOUSE

65

66

67

68

Keyboard Data

Keyboard Clock

Mouse Data

KDAT

KCLK

MDAT

MCLK

I/OD16P

Mouse Clock

GENERAL PURPOSE I/O

70

71

72

73

74

76

77

G P I/O; IRQ in (Note 2)

GP10

GP11

I/O4

I/O24

I/O4

G P I/O; WD Timer Output /IRRX (Note 2) GP12

G P I/O; Power Led output /IRTX (Note 2) GP13

G P I/O; GP Address Decode (Note 2)

GP14

G P I/O; GP Write Strobe; WDT2 (Note 2) GP15

G P I/O; Joy Read Strobe/JOYCS (Note GP16

2)

78

79

80

81

G P I/O; Joy Write Strobe (Note 2)

G P I/O; 8042 P20 (Note 2)

G P I/O; (Note 2)

GP17

GP20

GP21

GP22

I/O4

I/O8

G P I/O; (Note 2)

7

DESCRIPTION OF PIN FUNCTIONS

NAME SYMBOL

BUFFER TYPE

NO./QFP

82

83

84

85

86

87

88

89

90

91

92

19

G P I/O; (Note 2)

GP23

GP24

GP25

GP60

GP61

GP62

GP63

GP64

GP65

GP66

GP67

GP47

I/O4

I/O24

G P I/O; 8042 P21 (Note 2)

G P I/O; Power LED Output (Note2)

G P I/O; WDT (Note 2)

G P I/O; 8042 - P12 (Note 2)

G P I/O; 8042 - P13 (Note 2)

G P I/O; 8042 - P14 (Note 2)

G P I/O; 8042 - P15 (Note 2)

G P I/O; 8042 - P16 (Note 2)

G P I/O; 8042 - P17 (Note 2)

G P I/O; nSMI

Note 1:

Note 2:

nYY - The "n" as the first letter of a signal name indicates an "Active Low" signal.

See Table of Multifunction Pins with GPI/O.

8

Description of Multifunction Pins with GPI/O and Other Alternate Functions

PIN NO./

QFP

19

Original

Function

Alternate

Function 1

Alternate

Function 2

Buffer

Type

Default

Index

Register

GPI/O

GPIO

GPI/O

IRQ in

nSMI

-

I/O24

I/O4

input

GP4

GP1

GP47

GP10

GP11

GP12

70

71

WDT Timer

Output/ IRRX

Power LED

Output/ IRTX

GP Address

Decode

GP Write

Strobe

Joy Read

Strobe

72

-

73

74

76

77

78

GPI/O

-

I/O24

I/O4

input

GP1

GP13

GP14

GP15

GP16

GP17

-

WDT2

JOYCS

-

Joy Write

Strobe

-

79

80

GPI/O

8042 P20

-

input

GP2

GP20

GP21

-

I/O8/

OD8

I/O8/

OD8

I/O4

-

81

GPI/O

-

input

GP2

GP22

-

82

83

84

85

GPI/O

float

-

input

float

GP2

GP6

GP23

GP24

GP25

GP60

I/O4

8042 P21

GPI/O

Power LED

Output

86

87

88

89

90

91

92

127

float

nRI2

GPI/O

WDT

I/O4

I/O8

float

GP6

GP7

GP61

GP62

GP63

GP64

GP65

GP66

GP67

GP70

8042 - P12

8042 - P13

8042 - P14

8042 - P15

8042 - P16

8042 - P17

-

input

(1)

9

PIN NO./

QFP

Original

Function

Alternate

Function 1

Alternate

Function 2

Buffer

Type

Default

Index

Register

GPI/O

128

nDCD2

RXD2

GPI/O

-

I/O8

input

(1)

GP7

GP71

GP72

GP73

GP74

GP75

GP76

GP77

121

122

123

124

125

126

input

(1)

TXD2

input

(1) (2)

nDSR2

nRTS2

nCTS2

nDTR2

input

(1)

input

(1) (2)

input

(1)

input

(1) (2)

Note (1):These pins are input (high-z) until programmed for second serial port.

Note (2):These pins cannot be programmed as open drain pins in their original function.

Note:

No pins in their original function can be programmed as inverted input or inverted

output.

10

Buffer Type Descriptions

I

IS

Input, TTL compatible.

Input with Schmitt trigger.

I/OD16P Input/Output, 16mA sink, 90uA pull-up.

I/O24

I/O4

O4

Input/Output, 24mA sink, 12mA source.

Input/Output, 4mA sink, 2mA source.

Output, 4mA sink, 2mA source.

O16SR Output, 16mA sink, 8mA source with Slew Rate Limiting.

O20

O24

OD24

ICLK

Output, 20mA sink, 10mA source.

Output, 24mA sink, 12mA source.

Output, Open Drain, 24mA sink.

Clock Input

11

nGPA

nGPCS*

nSMI*

SMI

nGPWR*

POWER

MANAGEMENT

DECODER

PD0-7

MULTI-MODE

PARALLEL

PORT/FDC

MUX

BUSY, SLCT, PE,

nERROR, nACK

DATA BUS

nSTB, nSLCTIN,

nINIT, nALF

GP1[0:7]*

GP2[0:5]*

GENERAL

PURPOSE

I/O

ADDRESS BUS

GP47*

SERIRQ

PCICLK

nIOR

SERIAL

IRQ

GP6[0:7]*, GP7[0:7]*

CONFIGURATION

REGISTERS

TXD1, nCTS1, nRTS1

RXD1

16C550

COMPATIBLE

SERIAL

PORT 1

nDSR1, nDCD1, nRI1, nDTR1

CONTROL BUS

nIOW

AEN

IRRX*, IRTX*

WDATA

16C550

COMPATIBLE

SERIAL

PORT 2 WITH

INFRARED

TXD2(IRTX), nCTS2, nRTS2

RXD2(IRRX)

SA[0:15]

SD[O:7]

DRQ[A-C]

nDACK[A-C]

TC

WCLOCK

HOST

CPU

SMSC

PROPRIETARY

82077

COMPATIBLE

VERTICAL

FLOPPYDISK

CONTROLLER

CORE

nDSR2, nDCD2, nRI2, nDTR2

DIGITAL

DATA

INTERFACE

SEPARATOR

WITH WRITE

PRECOM-

PENSATION

RCLOCK

RDATA

KCLK

KDATA

RESET_DRV

IOCHRDY

MCLK

MDATA

P20*, P21*

CLOCK

8042

GEN

P12*, P13*, P14*,P15*, P16*, P17*

DENSEL

nDIR

nINDEX

nTRK0

nDS0,1

nMTR0,1

*Multi-Function I/O Pin - Optional

nWDATA nRDATA

nDSKCHG

nWRPRT

nWGATE

nSTEP DRVDEN0

DRVDEN1

Vcc Vss

nHDSEL

CLKIN

(14.318)

HCLK

14CLK

(14.318)

FDC37C68x BLOCK DIAGRAM

12

FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

HOST PROCESSOR INTERFACE

The address map, shown below in Table 1,

shows the addresses of the different blocks of

the Super I/O immediately after power up. The

base addresses of the FDC, serial and parallel

ports, and auxiliary I/O can be moved via the

configuration registers. Some addresses are

used to access more than one register.

The host processor communicates with the

FDC37C68x through a series of read/write

registers. The range of base I/O port addresses

for these registers are shown in Table 1.

Register access is accomplished through

programmed I/O or DMA transfers. All registers

are 8 bits wide. All host interface output buffers

are capable of sinking a minimum of 12 mA.

Table 1 - I/O Base Address Configuration Register Description

LOGICAL REGISTER

DEVICE INDEX

LOGICAL

DEVICE

NUMBER

0x00

BASE I/O RANGE

(NOTE 3)

FIXED BASE

OFFSETS

FDC

0x60,0x61

[0x100:0xFF8]

+0 : SRA

+1 : SRB

ON 8 BYTE

+2 : DOR

BOUNDARIES

+3 : TSR

+4 : MSR/DSR

+5 : FIFO

+7 : DIR/CCR

+0 : Data / ecpAfifo

+1 : Status

+2 : Control

+400h :

0x03

Parallel Port

0x60,0x61

[0x100:0x0FFC]

ON 4 BYTE

BOUNDARIES

(EPP Not

Supported)

cfifo / ecpDfifo / tfifo

/ cnfgA

or

[0x100:0xFF8]

ON 8 BYTE

BOUNDARIES

(all modes

+401h : cnfgB

+402h : ecr

+3 : EPP Address

+4 : EPP Data 0

supported, EPP is

only available when +5 : EPP Data 1

the base address is +6 : EPP Data 2

on an 8-byte

boundary)

+7 : EPP Data 3

13

LOGICAL

DEVICE

NUMBER

0x04

LOGICAL

DEVICE

REGISTER

INDEX

BASE I/O RANGE

(NOTE 3)

[0x100:0xFF8]

FIXED BASE

OFFSETS

+0 : RB/TBILSB div

+1 : IERIMSB div

+2 : IIR/FCR

+3 : LCR

+4 : MSR

+5 : LSR

+6 : MSR

+7 : SCR

+0 : RB/TBILSB div

+1 : IERIMSB div

+2 : IIR/FCR

+3 : LCR

+4 : MSR

+5 : LSR

+6 : MSR

+7 : SCR

+0 : Data Register

+4 :

Command/Status

Reg.

Serial Port 1

0x60,0x61

N/A

ON 8 BYTE

BOUNDARIES

0x05

Serial Port 2

[0x100:0xFF8]

ON 8 BYTE

BOUNDARIES

0x07

0x08

KYBD

Not Relocatable

Fixed Base

Address: 60,64

Aux. I/O

0x60,0x61

0x62,0x63

[0x00:0xFFF]

ON 1 BYTE

BOUNDARIES

[0x00:0xFFF]

ON 1 BYTE

+0 : GPR

+0 : GPW

BOUNDARIES

14

FLOPPY DISK CONTROLLER

FDC INTERNAL REGISTERS

The Floppy Disk Controller (FDC) provides the

interface between a host microprocessor and

the floppy disk drives. The FDC integrates the

functions of the Formatter/Controller, Digital

Data Separator, Write Precompensation and

Data Rate Selection logic for an IBM XT/AT

compatible FDC. The true CMOS 765B core

guarantees 100% IBM PC XT/AT compatibility

in addition to providing data overflow and

underflow protection.

The Floppy Disk Controller contains eight

internal registers which facilitate the interfacing

between the host microprocessor and the disk

drive. Table 2 shows the addresses required to

access these registers. Registers other than the

ones shown are not supported. The rest of the

description assumes that the primary addresses

have been selected.

Note:

FINTR refers to the IRQ used by the

FDC.

The FDC is compatible to the 82077AA using

SMSC's proprietary floppy disk controller core.

Table 2 - Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

SECONDARY

PRIMARY

ADDRESS

R/W

REGISTER

3F0

3F1

3F2

3F3

3F4

3F5

3F6

3F7

370

371

372

373

374

375

376

377

R

R/W

R

Status Register A (SRA)

Status Register B (SRB)

Digital Output Register (DOR)

Tape Drive Register (TSR)

Main Status Register (MSR)

Data Rate Select Register (DSR)

Data (FIFO)

Reserved

Digital Input Register (DIR)

Configuration Control Register (CCR)

W

R/W

R

W

15

interface pins in PS/2 and Model 30 modes. The

SRA can be accessed at any time when in PS/2

mode. In the PC/AT mode the data bus pins D0

- D7 are held in a high impedance state for a

read of address 3F0.

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state

of the FINTR and several disk

PS/2 Mode

7

6

5

4

3

2

1

0

INT

nDRV2 STEP nTRK0 HDSEL nINDX nWP

DIR

PENDING

RESET

COND.

0

N/A N/A N/A N/A

0

BIT 0 DIRECTION

BIT 4 nTRACK 0

Active high status indicating the direction of

head movement. A logic "1" indicates inward

direction; a logic "0" indicates outward direction.

Active low status of the TRK0 disk interface

input.

BIT 5 STEP

BIT 1 nWRITE PROTECT

Active high status of the STEP output disk

interface output pin.

Active low status of the WRITE PROTECT disk

interface input. A logic "0" indicates that the disk

is write protected.

BIT 6 nDRV2

Active low status of the DRV2 disk interface

input pin, indicating that a second drive has

been installed.

BIT 2 nINDEX

Active low status of the INDEX disk interface

input.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy

Disk Interrupt output.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface

input. A logic "1" selects side 1 and a logic "0"

selects side 0.

16

PS/2 Model 30 Mode

7

6

5

4

3

2

1

0

INT

PENDING

DRQ STEP TRK0 nHDSEL INDX

F/F

WP

nDIR

RESET

COND.

0

N/A

1

N/A

1

BIT 0 nDIRECTION

BIT 4 TRACK 0

Active low status indicating the direction of head

movement. logic "0" indicates inward

Active high status of the TRK0 disk interface

input.

A

direction; a logic "1" indicates outward direction.

BIT 5 STEP

BIT 1 WRITE PROTECT

Active high status of the latched STEP disk

interface output pin. This bit is latched with the

STEP output going active, and is cleared with a

read from the DIR register, or with a hardware

or software reset.

Active high status of the WRITE PROTECT disk

interface input. A logic "1" indicates that the disk

is write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface

input.

BIT 6 DMA REQUEST

Active high status of the DRQ output pin.

BIT 3 nHEAD SELECT

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy

Disk Interrupt output.

Active low status of the HDSEL disk interface

input. A logic "0" selects side 1 and a logic "1"

selects side 0.

17

Model 30 modes. The SRB can be accessed at

any time when in PS/2 mode. In the PC/AT

mode the data bus pins D0 - D7 are held in a

high impedance state for a read of address 3F1.

STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state

of several disk interface pins in PS/2 and

PS/2 Mode

7

1

6

1

5

4

3

2

1

0

DRIVE WDATA RDATA WGATE MOT

SEL0 TOGGLE TOGGLE

MOT

EN0

EN1

RESET

COND.

1

0

BIT 0 MOTOR ENABLE 0

BIT 4 WRITE DATA TOGGLE

Active high status of the MTR0 disk interface

output pin. This bit is low after a hardware reset

and unaffected by a software reset.

Every inactive edge of the WDATA input causes

this bit to change state.

BIT 5 DRIVE SELECT 0

BIT 1 MOTOR ENABLE 1

Reflects the status of the Drive Select 0 bit of

the DOR (address 3F2 bit 0). This bit is cleared

after a hardware reset and it is unaffected by a

software reset.

Active high status of the MTR1 disk interface

output pin. This bit is low after a hardware reset

and unaffected by a software reset.

BIT 2 WRITE GATE

BIT 6 RESERVED

Active high status of the WGATE disk interface

output.

Always read as a logic "1".

BIT 7 RESERVED

BIT 3 READ DATA TOGGLE

Always read as a logic "1".

Every inactive edge of the RDATA input causes

this bit to change state.

18

PS/2 Model 30 Mode

7

6

5

4

3

2

1

0

nDRV2 nDS1 nDS0 WDATA RDATA WGATE nDS3 nDS2

F/F

RESET

COND.

N/A

1

0

1

BIT 0 nDRIVE SELECT 2

BIT 4 WRITE DATA

Active low status of the DS2 disk interface

output.

Active high status of the latched WDATA output

signal. This bit is latched by the inactive going

edge of WDATA and is cleared by the read of

the DIR register. This bit is not gated with

WGATE.

BIT 1 nDRIVE SELECT 3

Active low status of the DS3 disk interface

output.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface

output.

BIT 2 WRITE GATE

Active high status of the latched WGATE output

signal. This bit is latched by the active going

edge of WGATE and is cleared by the read of

the DIR register.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface

output.

BIT 3 READ DATA

Active high status of the latched RDATA output

signal. This bit is latched by the inactive going

edge of RDATA and is cleared by the read of the

DIR register.

BIT 7 nDRV2

Active low status of the DRV2 disk interface

input.

19

DIGITAL OUTPUT REGISTER (DOR)

also contains the enable for the DMA logic and a

software reset bit. The contents of the DOR are

unaffected by a software reset. The DOR can

be written to at any time.

Address 3F2 READ/WRITE

The DOR controls the drive select and motor

enables of the disk interface outputs. It

7

6

5

4

3

2

1

0

MOT

EN3

MOT

EN2

MOT

EN1

MOT DMAEN nRESE DRIVE DRIVE

EN0

T

SEL1

SEL0

RESET

COND.

0

BIT 0 and 1 DRIVE SELECT

BIT 4 MOTOR ENABLE 0

These two bits are binary encoded for the four drive

selects DS0 -DS3, thereby allowing only one drive to

be selected at one time.

This bit controls the MTR0 disk interface output. A

logic "1" in this bit will cause the output pin to go

active.

BIT 2 nRESET

BIT 5 MOTOR ENABLE 1

A logic "0" written to this bit resets the Floppy disk

controller. This reset will remain active until a logic

"1" is written to this bit. This software reset does not

affect the DSR and CCR registers, nor does it affect

the other bits of the DOR register. The minimum

reset duration required is 100ns, therefore toggling

this bit by consecutive writes to this register is a valid

method of issuing a software reset.

This bit controls the MTR1 disk interface output. A

logic "1" in this bit will cause the output pin to go

active.

BIT 6 MOTOR ENABLE 2

This bit controls the MTR2 disk interface output. A

logic “1” in this bit will cause the output pin to go

active.

BIT 3 DMAEN

BIT 7 MOTOR ENABLE 3

PC/AT and Model 30 Mode:

This bit controls the MTR3 disk interface output. A

logic “1” in this bit will cause the output pin to go

active.

Writing this bit to logic "1" will enable the DRQ,

nDACK, TC and FINTR outputs. This bit being a

logic "0" will disable the nDACK and TC inputs, and

hold the DRQ and FINTR outputs in

a high

Table 3 - Drive Activation Values

impedance state. This bit is a logic "0" after a reset

and in these modes.

DRIVE

DOR VALUE

0

1

2

3

1CH

2DH

4EH

8FH

PS/2 Mode: In this mode the DRQ, nDACK, TC and

FINTR outputs are always enabled. During a reset,

the DRQ, nDACK, TC, and FINTR will remain

enabled, but this bit will be cleared to a logic "0".

20

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

Table 4- Tape Select Bits

This register is included for 82077 software

compatability. The robust digital data separator

used in the FDC does not require its

characteristics modified for tape support. The

contents of this register are not used internal to

DRIVE

SELECTED

TAPE SEL1

TAPE SEL2

0

1

0

1

0

1

None

1

2

3

the device.

The TDR is unaffected by a

Bits 2-7 are tri-stated when

software reset.

read in this mode.

Table 5 - Internal 2 Drive Decode - Normal

DIGITAL OUTPUT REGISTER

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

1

Bit1

0

Bit 0

nDS1

nDS0

nMTR1

nMTR0

nBIT 4

0

1

0

1

X

1

0

1

0

1

nBIT 5

X

1

X

0

X

1

X

1

X

1

0

X

Table 6 - Internal 2 Drive Decode - Drives 0 and 1 Swapped

DIGITAL OUTPUT REGISTER

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

1

Bit1

0

Bit 0

nDS1

nDS0

nMTR1

nMTR0

nBIT 5

0

1

0

1

X

0

1

0

1

nBIT 4

X

1

X

0

X

1

X

1

X

1

0

X

21

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a

high impedance.

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

REG 3F3 Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state tape sel1 tape sel0

Enhanced Floppy Mode 2 (OS2)

Register 3F3 for Enhanced Floppy Mode 2 operation.

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

REG 3F3

Media

ID1

Media

ID0

Drive Type ID

Floppy Boot Drive

tape sel1 tape sel0

For this mode, MEDIA_ID[1:0] bits are tied high

(bits 6 and 7 of the 3F3 register). These two

bits are not affected by a hard or soft reset.

BITS 3 and 2 Floppy Boot Drive - These bits

reflect the value of L0-CRF1. Bit 3 = L0-CRF1-

B7. Bit 2 = L0-CRF1-B6.

BIT 7 MEDIA ID 1 READ ONLY (See Table 7)

BIT 6 MEDIA ID 0 READ ONLY (See Table 8)

Bits

(READ/WRITE).

Enhanced Floppy Mode. 1.

1

and

0

-

Tape Drive Select

Same as in Normal and

BITS 5 and 4 Drive Type ID - These bits reflect

two of the bits of L0-CRF1. Which two bits

these are depends on the last drive selected in

the Digital Output Register (3F2). (See Table 9)

Note: L0-CRF1-B5

= Logical Device 0,

Configuration Register F1, Bit 5

Table 8 - Media ID0

Table 7 - Media ID1

MEDIA ID1

MEDIA ID0

BIT 6

BIT 7

CRF1-B4

= 1

L0-CRF1-B5 L0-CRF1-B5

= 0

= 1

1

0

1

0

22

Table 9 - Drive Type ID

Digital Output Register Register 3F3 - Drive Type ID

Bit 1

Bit 0

Bit 5

Bit 4

0

1

0

1

0

1

L0-CRF2 - B1

L0-CRF2 - B3

L0-CRF2 - B5

L0-CRF2 - B7

L0-CRF2 - B0

L0-CRF2 - B2

L0-CRF2 - B4

L0-CRF2 - B6

Note:

L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

23

30 and Microchannel applications.

Other

DATA RATE SELECT REGISTER (DSR)

applications can set the data rate in the DSR.

The data rate of the floppy controller is the most

recent write of either the DSR or CCR. The DSR

is unaffected by a software reset. A hardware

reset will set the DSR to 02H, which

corresponds to the default precompensation

setting and 250 Kbps.

Address 3F4 WRITE ONLY

This register is write only. It is used to program

the data rate, amount of write precompensation,

power down status, and software reset. The

data

rate

is

programmed

using

the

Configuration Control Register (CCR) not the

DSR,

for

PC/AT and PS/2 Model

7

6

5

0

4

3

2

1

0

S/W POWER

RESET DOWN

PRE-

PRE- DRATE DRATE

COMP2 COMP1 COMP0 SEL1

SEL0

RESET

COND.

0

1

0

separator circuits will be turned off.

The

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy

controller. See Table 11 for the settings

corresponding to the individual data rates. The

data rate select bits are unaffected by a

software reset, and are set to 250 Kbps after a

hardware reset.

controller will come out of manual low power

mode after a software reset or access to the

Data Register or Main Status Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the

DOR RESET (DOR bit 2) except that this bit is

self clearing.

BIT

2

through

4

PRECOMPENSATION

SELECT

Table 10 - Precompensation Delays

These three bits select the value of write

precompensation that will be applied to the

WDATA output signal. Table 10 shows the

precompensation values for the combination of

these bits settings. Track 0 is the default

starting track number to start precompensation.

this starting track number can be changed by

the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy

controller into manual low power mode. The

floppy controller clock and data

PRECOMP

432

PRECOMPENSATION

DELAY (nsec)

<2Mbps

2Mbps

111

001

010

011

100

101

110

000

0.00

41.67

83.34

125.00

166.67

208.33

250.00

Default

0

20.8

41.7

62.5

83.3

104.2

125

Default

Default: See Table 12

24

Table 11 - Data Rates

DATA RATE DATA RATE

DRIVE RATE

DRATE(1)

DENSEL

DRT1

DRT0

SEL1 SEL0

MFM

FM

1

0

1

0

1

0

1

0

1Meg

500

---

1

0

1

0

1

0

1

0

250

150

125

300

250

0

1

0

1

0

1

0

1Meg

500

---

1

0

1

0

1

0

1

0

250

125

500

250

1

0

1

0

1

0

1

0

1Meg

500

---

250

---

1

0

1

0

1

0

1

0

2Meg

250

125

Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format

01 = 3-Mode Drive

10 = 2 Meg Tape

Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.

Table 12 - DRVDEN Mapping

DRVDEN1

(1)

DRVDEN0

(1)

DT1

DT0

DRIVE TYPE

4/2/1 MB 3.5"

0

DRATE0

DENSEL

2/1 MB 5.25" FDDS

2/1.6/1 MB 3.5" (3-MODE)

1

0

1

0

1

DRATE0

DRATE1

nDENSEL

DRATE0

PS/2

25

Table 13 - Default Precompensation Delays

PRECOMPENSATION

DATA RATE

DELAYS

2 Mbps

1 Mbps

500 Kbps

300 Kbps

250 Kbps

20.8 ns

41.67 ns

125 ns

26

read at any time. The MSR indicates when the

disk controller is ready to receive data via the

Data Register. It should be read before each

byte transferring to or from the data register

except in DMA mode. No delay is required

when reading the MSR after a data transfer.

MAIN STATUS REGISTER

Address 3F4 READ ONLY

The Main Status Register is a read-only register

and indicates the status of the disk controller.

The Main Status Register can be

7

6

5

4

3

2

1

0

RQM

DIO

NON

DMA

CMD

BUSY

DRV3

BUSY

DRV2

BUSY

DRV1

BUSY

DRV0

BUSY

BIT 0 - 3 DRV x BUSY

BIT 5 NON-DMA

These bits are set to 1s when a drive is in the

seek portion of a command, including implied

and overlapped seeks and recalibrates.

This mode is selected in the SPECIFY

command and will be set to a 1 during the

execution phase of a command. This is for

polled data transfers and helps differentiate

between the data transfer phase and the reading

of result bytes.

BIT 4 COMMAND BUSY

This bit is set to a 1 when a command is in

progress. This bit will go active after the

command byte has been accepted and goes

inactive at the end of the results phase. If there

is no result phase (Seek, Recalibrate

commands), this bit is returned to a 0 after the

last command byte.

BIT 6 DIO

Indicates the direction of a data transfer once a

RQM is set. A 1 indicates a read and a 0

indicates a write is required.

BIT 7 RQM

Indicates that the host can transfer data if set to

a 1. No access is permitted if set to a 0.

27

FIFO. The data is based upon the following

formula:

DATA REGISTER (FIFO)

Address 3F5 READ/WRITE

Threshold # x

1

x 8

- 1.5 ms = DELAY

All command parameter information, disk data

and result status are transferred between the

host processor and the floppy disk controller

through the Data Register.

DATA RATE

At the start of a command, the FIFO action is

always disabled and command parameters

must be sent based upon the RQM and DIO bit

settings. As the command execution phase is

entered, the FIFO is cleared of any data to

ensure that invalid data is not transferred.

Data transfers are governed by the RQM and

DIO bits in the Main Status Register.

The Data Register defaults to FIFO disabled

mode after any form of reset. This maintains

PC/AT hardware compatibility.

The default

An overrun or underrun will terminate the

current command and the transfer of data. Disk

writes will complete the current sector by

generating a 00 pattern and valid CRC. Reads

require the host to remove the remaining data

so that the result phase may be entered.

values can be changed through the Configure

command (enable full FIFO operation with

threshold control). The advantage of the FIFO

is that it allows the system a larger DMA

latency without causing a disk error. Table 14

gives several examples of the delays with a

Table 14 - FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT 2

Mbps DATA RATE (The 2 Mbps data

rate is only available if V_CC= 5V)

1 byte

2 bytes

8 bytes

15 bytes

1 x 4 ms - 1.5 ms = 2.5 ms

2 x 4 ms - 1.5 ms = 6.5 ms

8 x 4 ms - 1.5 ms = 30.5 ms

15 x 4 ms - 1.5 ms = 58.5 ms

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT 1

Mbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 8 ms - 1.5 ms = 6.5 ms

2 x 8 ms - 1.5 ms = 14.5 ms

8 x 8 ms - 1.5 ms = 62.5 ms

15 x 8 ms - 1.5 ms = 118.5 ms

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT

500 Kbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 16 ms - 1.5 ms = 14.5 ms

2 x 16 ms - 1.5 ms = 30.5 ms

8 x 16 ms - 1.5 ms = 126.5 ms

15 x 16 ms - 1.5 ms = 238.5 ms

28

DIGITAL INPUT REGISTER (DIR)

Address 3F7 READ ONLY

This register is read-only in all modes.

PC-AT Mode

7

6

5

4

3

2

1

0

DSK

CHG

RESET

COND.

N/A

BIT 0 - 6 UNDEFINED

BIT 7 DSKCHG

The data bus outputs D0 - 6 will remain in a

high impedance state during a read of this

register.

This bit monitors the pin of the same name and

reflects the opposite value seen on the disk

cable.

PS/2 Mode

7

6

1

5

1

4

1

3

1

2

1

0

DSK

CHG

DRATE DRATE nHIGH

SEL1

SEL0 nDENS

RESET

COND.

N/A

1

software reset, and are set to 250 Kbps after a

hardware reset.

BIT 0 nHIGH DENS

This bit is low whenever the 500 Kbps or 1 Mbps

data rates are selected, and high when 250

Kbps and 300 Kbps are selected.

BITS 3 - 6 UNDEFINED

Always read as a logic "1"

BITS 1 - 2 DATA RATE SELECT

These bits control the data rate of the floppy

BIT 7 DSKCHG

controller.

See Table 11 for the settings

This bit monitors the pin of the same name and

reflects the opposite value seen on the disk

cable.

corresponding to the individual data rates. The

data rate select bits are unaffected by a

29

Model 30 Mode

7

DSK

CHG

6

0

5

0

4

0

3

2

1

0

DMAEN NOPREC DRATE DRATE

SEL1

SEL0

RESET

COND.

N/A

0

1

0

BITS 0 - 1 DATA RATE SELECT

These bits control the data rate of the floppy

controller. See Table 11 for the settings

BIT 3 DMAEN

This bit reflects the value of DMAEN bit set in

the DOR register bit 3.

corresponding to the individual data rates. The

data rate select bits are unaffected by a

software reset, and are set to 250 Kbps after a

hardware reset.

BITS 4 - 6 UNDEFINED

Always read as a logic "0"

BIT 7 DSKCHG

This bit monitors the pin of the same name and

reflects the opposite value seen on the pin.

BIT 2 NOPREC

This bit reflects the value of NOPREC bit set in

the CCR register.

30

CONFIGURATION CONTROL REGISTER (CCR)

Address 3F7 WRITE ONLY

PC/AT and PS/2 Modes

7

6

5

4

3

2

1

0

DRATE DRATE

SEL1

SEL0

RESET

COND.

N/A

1

0

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy

controller. See Table 11 for the appropriate

values.

BIT 2 - 7 RESERVED

Should be set to a logical "0"

PS/2 Model 30 Mode

7

6

5

4

3

2

1

0

NOPREC DRATE DRATE

SEL1

SEL0

RESET

COND.

N/A

1

0

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy

controller. See Table 11 for the appropriate

values.

BIT 3 - 7 RESERVED

Should be set to a logical "0"

Table 12 shows the state of DENSEL. DENSEL

is set high after a hardware reset and is

unaffected by the DOR and the DSR resets.

BIT 2 NO PRECOMPENSATION

This bit can be set by software, but it has no

functionality. It can be read by bit 2 of the DSR

when in Model 30 register mode. Unaffected by

software reset.

31

STATUS REGISTER ENCODING

During the Result Phase of certain commands, the Data Register contains data bytes that give the

status of the command just executed.

Table 15 - Status Register 0

BIT NO.

SYMBOL

IC

NAME

DESCRIPTION

7,6

Interrupt

Code

00 - Normal termination of command. The specified

command was properly executed and completed

without error.

01 - Abnormal termination of command. Command

execution was started, but was not successfully

completed.

10 - Invalid command. The requested command

could not be executed.

11 - Abnormal termination caused by Polling.

5

4

SE

EC

Seek End

The FDC completed a Seek, Relative Seek or

Recalibrate command (used during a Sense Interrupt

Command).

Equipment

Check

The TRK0 pin failed to become a "1" after:

1. 80 step pulses in the Recalibrate command.

2. The Relative Seek command caused the FDC to

step outward beyond Track 0.

3

2

Unused. This bit is always "0".

The current head address.

H

Head

Address

1,0

DS1,0

Drive Select

The current selected drive.

32

Table 16 - Status Register 1

NAME

End of

BIT NO.

SYMBOL

EN

DESCRIPTION

7

The FDC tried to access a sector beyond the final

sector of the track (255D). Will be set if TC is not

issued after Read or Write Data command.

Cylinder

6

5

Unused. This bit is always "0".

DE

OR

Data Error

The FDC detected a CRC error in either the ID field or

the data field of a sector.

4

Overrun/

Underrun

Becomes set if the FDC does not receive CPU or DMA

service within the required time interval, resulting in

data overrun or underrun.

3

2

Unused. This bit is always "0".

ND

No Data

Any one of the following:

1. Read Data, Read Deleted Data command - the

FDC did not find the specified sector.

2. Read ID command - the FDC cannot read the ID

field without an error.

3. Read A Track command - the FDC cannot find

the proper sector sequence.

1

0

NW

MA

Not Writable WP pin became a "1" while the FDC is executing a

Write Data, Write Deleted Data, or Format A Track

command.

Missing

Any one of the following:

Address Mark 1. The FDC did not detect an ID address mark at the

specified track after encountering the index pulse

from the IDX pin twice.

2. The FDC cannot detect a data address mark or a

deleted data address mark on the specified track.

33

Table 17 - Status Register 2

NAME

BIT NO.

SYMBOL

DESCRIPTION

Unused. This bit is always "0".

Control Mark Any one of the following:

1. Read Data command - the FDC encountered a

7

6

CM

deleted data address mark.

2. Read Deleted Data command

encountered a data address mark.

-

the FDC

5

4

DD

Data Error in The FDC detected a CRC error in the data field.

Data Field

WC

Wrong

The track address from the sector ID field is different

from the track address maintained inside the FDC.

Cylinder

3

2

1

Unused. This bit is always "0".

BC

Bad Cylinder The track address from the sector ID field is different

from the track address maintained inside the FDC and

is equal to FF hex, which indicates a bad track with a

hard error according to the IBM soft-sectored format.

0

MD

Missing Data The FDC cannot detect a data address mark or a

Address Mark deleted data address mark.

34

Table 18- Status Register 3

NAME DESCRIPTION

BIT NO.

SYMBOL

7

6

Unused. This bit is always "0".

Write Protected Indicates the status of the WP pin.

Unused. This bit is always "1".

WP

5

4

T0

Track 0

Indicates the status of the TRK0 pin.

Unused. This bit is always "1".

3

2

HD

Head Address

Drive Select

Indicates the status of the HDSEL pin.

Indicates the status of the DS1, DS0 pins.

1,0

DS1,0

RESET

DOR Reset vs. DSR Reset (Software Reset)

There are three sources of system reset on the

FDC: the RESET pin of the FDC, a reset

generated via a bit in the DOR, and a reset

generated via a bit in the DSR. At power on, a

Power On Reset initializes the FDC. All resets

take the FDC out of the power down state.

These two resets are functionally the same.

Both will reset the FDC core, which affects drive

status information and the FIFO circuits. The

DSR reset clears itself automatically while the

DOR reset requires the host to manually clear it.

DOR reset has precedence over the DSR reset.

The DOR reset is set automatically upon a pin

reset. The user must manually clear this reset

bit in the DOR to exit the reset state.

All operations are terminated upon a RESET,

and the FDC enters an idle state. A reset while

a disk write is in progress will corrupt the data

and CRC.

MODES OF OPERATION

On exiting the reset state, various internal

registers are cleared, including the Configure

command information, and the FDC waits for a

new command. Drive polling will start unless

disabled by a new Configure command.

The FDC has three modes of operation, PC/AT

mode, PS/2 mode and Model 30 mode. These

are determined by the state of the IDENT and

MFM bits 6 and 5 respectively of CRxx.

PC/AT mode - (IDENT high, MFM a "don't

care")

RESET Pin (Hardware Reset)

The PC/AT register set is enabled, the DMA

enable bit of the DOR becomes valid (FINTR

and DRQ can be hi Z), and TC and DENSEL

become active high signals.

The RESET pin is a global reset and clears all

registers except those programmed by the

Specify command.

The DOR reset bit is

enabled and must be cleared by the host to exit

the reset state.

35

Burst mode is enabled via Bit[1] of CRF0 in

Logical Device 0. Setting Bit[1]=0 enables burst

mode; the default is Bit[1]=1, for non-burst

mode.

PS/2 mode - (IDENT low, MFM high)

This mode supports the PS/2 models 50/60/80

configuration and register set. The DMA bit of

the DOR becomes a "don't care", (FINTR and

DRQ are always valid), TC and DENSEL

become active low.

CONTROLLER PHASES

For simplicity, command handling in the FDC

can be divided into three phases: Command,

Execution, and Result. Each phase is described

in the following sections.

Model 30 mode - (IDENT low, MFM low)

This mode supports PS/2 Model 30

configuration and register set. The DMA enable

bit of ther DOR becomes valid (FINTR and DRQ

can be hi Z), TC is active high and DENSEL is

active low.

Command Phase

After a reset, the FDC enters the command

phase and is ready to accept a command from

the host. For each of the commands, a defined

set of command code bytes and parameter

bytes has to be written to the FDC before the

command phase is complete. (Please refer to

Table 19 for the command set descriptions.)

These bytes of data must be transferred in the

order prescribed.

DMA TRANSFERS

DMA transfers are enabled with the Specify

command and are initiated by the FDC by

activating the FDRQ pin during a data transfer

command. The FIFO is enabled directly by

asserting nDACK and addresses need not be

valid.

Note that if the DMA controller (i.e. 8237A) is

programmed to function in verify mode, a

pseudo read is performed by the FDC based

only on nDACK. This mode is only available

when the FDC has been configured into byte

mode (FIFO disabled) and is programmed to do

a read. With the FIFO enabled, the FDC can

perform the above operation by using the new

Verify command; no DMA operation is needed.

Before writing to the FDC, the host must

examine the RQM and DIO bits of the Main

Status Register. RQM and DIO must be equal

to "1" and "0" respectively before command

bytes may be written. RQM is set false by the

FDC after each write cycle until the received

byte is processed. The FDC asserts RQM again

to request each parameter byte of the command

unless an illegal command condition is

detected.

After the last parameter byte is

The FDC37C68x supports two DMA transfer

modes for the FDC: Single Transfer and Burst

Transfer. In the case of the single transfer, the

DMA Req goes active at the start of the DMA

cycle, and the DMA Req is deasserted after the

nDACK. In the case of the burst transfer, the

Req is held active until the last transfer

(independent of nDACK). See timing diagrams

for more information.

received, RQM remains "0" and the FDC

automatically enters the next phase as defined

by the command definition.

The FIFO is disabled during the command

phase to provide for the proper handling of the

"Invalid Command" condition.

36

until the last byte is transferred out of the FIFO.

The FDC will deactivate the FINT pin and RQM

bit when the FIFO becomes empty.

Execution Phase

All data transfers to or from the FDC occur

during the execution phase, which can proceed

in DMA or non-DMA mode as indicated in the

Specify command.

Non-DMA Mode - Transfers from the Host to the

FIFO

The FINT pin and RQM bit in the Main Status

Register are activated upon entering the

execution phase of data transfer commands.

The host must respond to the request by writing

data into the FIFO. The FINT pin and RQM bit

remain true until the FIFO becomes full. They

are set true again when the FIFO has

<threshold> bytes remaining in the FIFO. The

FINT pin will also be deactivated if TC and

nDACK both go inactive. The FDC enters the

result phase after the last byte is taken by the

FDC from the FIFO (i.e. FIFO empty condition).

After a reset, the FIFO is disabled. Each data

byte is transferred by an FINT or FDRQ

depending on the DMA mode. The Configure

command can enable the FIFO and set the

FIFO threshold value.

The following paragraphs detail the operation of

the FIFO flow control. In these descriptions,

<threshold> is defined as the number of bytes

available to the FDC when service is requested

from the host and ranges from 1 to 16. The

parameter FIFOTHR, which the user programs,

is one less and ranges from 0 to 15.

DMA Mode - Transfers from the FIFO to the

Host

A low threshold value (i.e. 2) results in longer

periods of time between service requests, but

requires faster servicing of the request for both

read and write cases. The host reads (writes)

from (to) the FIFO until empty (full), then the

transfer request goes inactive. The host must

be very responsive to the service request. This

is the desired case for use with a "fast" system.

The FDC activates the DDRQ pin when the

FIFO contains (16 - <threshold>) bytes, or the

last byte of a full sector transfer has been

placed in the FIFO. The DMA controller must

respond to the request by reading data from the

FIFO. The FDC will deactivate the DDRQ pin

when the FIFO becomes empty. FDRQ goes

inactive after nDACK goes active for the last

byte of a data transfer (or on the active edge of

nIOR, on the last byte, if no edge is present on

nDACK). A data underrun may occur if FDRQ

is not removed in time to prevent an unwanted

cycle.

A high value of threshold (i.e. 12) is used with a

"sluggish" system by affording a long latency

period after a service request, but results in

more frequent service requests.

Non-DMA Mode - Transfers from the FIFO to

the Host

DMA Mode - Transfers from the Host to the

FIFO

The FINT pin and RQM bits in the Main Status

Register are activated when the FIFO contains

(16-<threshold>) bytes or the last bytes of a full

sector have been placed in the FIFO. The FINT

pin can be used for interrupt-driven systems,

and RQM can be used for polled systems. The

host must respond to the request by reading

data from the FIFO. This process is repeated

The FDC activates the FDRQ pin when entering

the execution phase of the data transfer

commands. The DMA controller must respond

by activating the nDACK and nIOW pins and

placing data in the FIFO. FDRQ remains active

until the FIFO becomes full. FDRQ is again set

37

true when the FIFO has <threshold> bytes

remaining in the FIFO. The FDC will also

deactivate the FDRQ pin when TC becomes true

(qualified by nDACK), indicating that no more

data is required. FDRQ goes inactive after

nDACK goes active for the last byte of a data

transfer (or on the active edge of nIOW of the

last byte, if no edge is present on nDACK). A

data overrun may occur if FDRQ is not removed

in time to prevent an unwanted cycle.

"abnormal termination" result status.

status indications can be ignored if they were

expected.

Such

Note that when the host is sending data to the

FIFO of the FDC, the internal sector count will

be complete when the FDC reads the last byte

from its side of the FIFO. There may be a delay

in the removal of the transfer request signal of

up to the time taken for the FDC to read the last

16 bytes from the FIFO. The host must tolerate

this delay.

Data Transfer Termination

The FDC supports terminal count explicitly

through the TC pin and implicitly through the

underrun/overrun and end-of-track (EOT)

functions. For full sector transfers, the EOT

parameter can define the last sector to be

transferred in a single or multi-sector transfer.

Result Phase

The generation of FINT determines the

beginning of the result phase. For each of the

commands, a defined set of result bytes has to

be read from the FDC before the result phase is

complete. These bytes of data must be read out

for another command to start.

If the last sector to be transferred is a partial

sector, the host can stop transferring the data in

mid-sector, and the FDC will continue to

complete the sector as if a hardware TC was

received. The only difference between these

implicit functions and TC is that they return

RQM and DIO must both equal "1" before the

result bytes may be read. After all the result

bytes have been read, the RQM and DIO bits

switch to "1" and "0" respectively, and the CB bit

is cleared, indicating that the FDC is ready to

accept the next command.

38

COMMAND SET/DESCRIPTIONS

interrupt is issued. The user sends a Sense

Interrupt Status command which returns an

invalid command error. Refer to Table 19 for

explanations of the various symbols used. Table

20 lists the required parameters and the results

associated with each command that the FDC is

capable of performing.

Commands can be written whenever the FDC is

in the command phase. Each command has a

unique set of needed parameters and status

results. The FDC checks to see that the first

byte is a valid command and, if valid, proceeds

with the command. If it is invalid, an

Table 19 - Description of Command Symbols

NAME DESCRIPTION

Cylinder Address The currently selected address; 0 to 255.

Data Pattern The pattern to be written in each sector data field during

SYMBOL

C

D

formatting.

D0, D1, D2, Drive Select 0-3

D3

Designates which drives are perpendicular drives on the

Perpendicular Mode Command. A "1" indicates a perpendicular

drive.

DIR

Direction Control If this bit is 0, then the head will step out from the spindle during a

relative seek. If set to a 1, the head will step in toward the spindle.

DS0, DS1

Disk Drive Select

DS1

DS0

DRIVE

drive 0

drive 1

drive 2

drive 3

0

1

0

1

0

1

DTL

Special Sector

Size

By setting N to zero (00), DTL may be used to control the number

of bytes transferred in disk read/write commands. The sector size

(N = 0) is set to 128. If the actual sector (on the diskette) is larger

than DTL, the remainder of the actual sector is read but is not

passed to the host during read commands; during write

commands, the remainder of the actual sector is written with all

zero bytes. The CRC check code is calculated with the actual

sector. When N is not zero, DTL has no meaning and should be

set to FF HEX.

EC

Enable Count

Enable FIFO

When this bit is "1" the "DTL" parameter of the Verify command

becomes SC (number of sectors per track).

EFIFO

EIS

This active low bit when a 0, enables the FIFO. A "1" disables the

FIFO (default).

Enable Implied

Seek

When set, a seek operation will be performed before executing any

read or write command that requires the C parameter in the

command phase. A "0" disables the implied seek.

39

Table 19 - Description of Command Symbols

NAME DESCRIPTION

SYMBOL

EOT

End of Track

The final sector number of the current track.

GAP

GPL

Alters Gap 2 length when using Perpendicular Mode.

Gap Length

The Gap 3 size. (Gap 3 is the space between sectors excluding

the VCO synchronization field).

H/HDS

HLT

Head Address

Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector

ID field.

Head Load Time The time interval that FDC waits after loading the head and before

initializing a read or write operation. Refer to the Specify

command for actual delays.

HUT

Head Unload

Time

The time interval from the end of the execution phase (of a read or

write command) until the head is unloaded. Refer to the Specify

command for actual delays.

LOCK

Lock defines whether EFIFO, FIFOTHR,

and PRETRK

parameters of the CONFIGURE COMMAND can be reset to their

default values by a "software Reset". (A reset caused by writing to

the appropriate bits of either tha DSR or DOR)

MFM

MT

MFM/FM Mode

Selector

A one selects the double density (MFM) mode. A zero selects

single density (FM) mode.

Multi-Track

Selector

When set, this flag selects the multi-track operating mode. In this

mode, the FDC treats a complete cylinder under head 0 and 1 as

a single track. The FDC operates as this expanded track started

at the first sector under head 0 and ended at the last sector under

head 1. With this flag set, a multitrack read or write operation will

automatically continue to the first sector under head 1 when the

FDC finishes operating on the last sector under head 0.

N

Sector Size Code This specifies the number of bytes in a sector. If this parameter is

"00", then the sector size is 128 bytes. The number of bytes

transferred is determined by the DTL parameter. Otherwise the

sector size is (2 raised to the "N'th" power) times 128. All values

up to "07" hex are allowable. "07"h would equal a sector size of

16k. It is the user's responsibility to not select combinations that

are not possible with the drive.

NCN

New Cylinder

Number

The desired cylinder number.

40

Table 19 - Description of Command Symbols

NAME DESCRIPTION

SYMBOL

ND

Non-DMA Mode

Flag

When set to 1, indicates that the FDC is to operate in the non-

DMA mode. In this mode, the host is interrupted for each data

transfer. When set to 0, the FDC operates in DMA mode,

interfacing to a DMA controller by means of the DRQ and nDACK

signals.

OW

Overwrite

The bits D0-D3 of the Perpendicular Mode Command can only be

modified if OW is set to 1. OW id defined in the Lock command.

PCN

Present Cylinder The current position of the head at the completion of Sense

Number

Interrupt Status command.

POLL

PRETRK

Polling Disable

When set, the internal polling routine is disabled. When clear,

polling is enabled.

Precompensation Programmable from track 00 to FFH.

Start Track

Number

R

Sector Address

The sector number to be read or written. In multi-sector transfers,

this parameter specifies the sector number of the first sector to be

read or written.

RCN

SC

Relative Cylinder Relative cylinder offset from present cylinder as used by the

Number

Relative Seek command.

Number of

The number of sectors per track to be initialized by the Format

Sectors Per Track command. The number of sectors per track to be verified during a

Verify command when EC is set.

SK

Skip Flag

When set to 1, sectors containing a deleted data address mark will

automatically be skipped during the execution of Read Data. If

Read Deleted is executed, only sectors with a deleted address

mark will be accessed. When set to "0", the sector is read or

written the same as the read and write commands.

SRT

Step Rate Interval The time interval between step pulses issued by the FDC.

Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms

at the 1 Mbit data rate. Refer to the SPECIFY command for actual

delays.

ST0

ST1

ST2

ST3

Status 0

Status 1

Status 2

Status 3

Registers within the FDC which store status information after a

command has been executed. This status information is available

to the host during the result phase after command execution.

WGATE

Write Gate

Alters timing of WE to allow for pre-erase loads in perpendicular

drives.

41

INSTRUCTION SET

Table 20 - Instruction Set

READ DATA

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5 D4 D3 D2 D1 D0

Command

W

MT MFM SK

0

1

0

Command Codes

0

HDS DS1 DS0

-------- C --------

Sector ID information prior to

Command execution.

W

-------- H --------

-------- R --------

-------- N --------

------- EOT -------

------- GPL -------

------- DTL -------

Execution

Result

Data transfer between the

FDD and system.

R

------- ST0 -------

Status information after

Command execution.

R

------- ST1 -------

------- ST2 -------

-------- C --------

Sector ID information after

Command execution.

R

-------- H --------

-------- R --------

-------- N --------

42

READ DELETED DATA

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5 D4 D3 D2 D1 D0

Command

W

MT MFM SK

0

1

0

1

0

Command Codes

0

HDS DS1 DS0

-------- C --------

Sector ID information prior to

Command execution.

W

-------- H --------

-------- R --------

-------- N --------

------- EOT -------

------- GPL -------

------- DTL -------

Execution

Result

Data transfer between the

FDD and system.

R

------- ST0 -------

Status information after

Command execution.

R

------- ST1 -------

------- ST2 -------

-------- C --------

Sector ID information after

Command execution.

R

-------- H --------

-------- R --------

-------- N --------

43

WRITE DATA

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5 D4 D3 D2 D1 D0

Command

W

MT MFM

0

1

0

1

Command Codes

0

HDS DS1 DS0

-------- C --------

Sector ID information prior to

Command execution.

W

-------- H --------

-------- R --------

-------- N --------

------- EOT -------

------- GPL -------

------- DTL -------

Execution

Result

Data transfer between the

FDD and system.

R

------- ST0 -------

Status information after

Command execution.

R

------- ST1 -------

------- ST2 -------

-------- C --------

Sector ID information after

Command execution.

R

-------- H --------

-------- R --------

-------- N --------

44

WRITE DELETED DATA

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5 D4 D3

D2

D1

D0

Command

W

MT MFM

0

1

0

1

Command Codes

0

HDS DS1 DS0

-------- C --------

Sector ID information

prior to Command

execution.

W

-------- H --------

-------- R --------

-------- N --------

------- EOT -------

------- GPL -------

------- DTL -------

Execution

Result

Data transfer between

the FDD and system.

R

------- ST0 -------

Status information after

Command execution.

R

------- ST1 -------

------- ST2 -------

-------- C --------

Sector ID information

after Command

execution.

R

-------- H --------

-------- R --------

-------- N --------

45

READ A TRACK

DATA BUS

PHASE

R/W

REMARKS

D7

0

D6

MFM

0

D5 D4 D3

D2

D1

D0

Command

W

0

1

0

Command Codes

0

HDS DS1 DS0

-------- C --------

Sector ID information

prior to Command

execution.

W

-------- H --------

-------- R --------

-------- N --------

------- EOT -------

------- GPL -------

------- DTL -------

Execution

Result

Data transfer between

the FDD and system.

FDC reads all of

cylinders' contents from

index hole to EOT.

R

------- ST0 -------

Status information after

Command execution.

R

------- ST1 -------

------- ST2 -------

-------- C --------

Sector ID information

after Command

execution.

R

-------- H --------

-------- R --------

-------- N --------

46

VERIFY

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5 D4 D3

D2

D1

D0

Command

W

MT MFM SK

1

0

1

0

Command Codes

EC

0

HDS DS1 DS0

-------- C --------

Sector ID information

prior to Command

execution.

W

-------- H --------

-------- R --------

-------- N --------

------- EOT -------

------- GPL -------

------ DTL/SC ------

Execution

Result

No data transfer takes

place.

R

------- ST0 -------

Status information after

Command execution.

R

------- ST1 -------

------- ST2 -------

-------- C --------

Sector ID information

after Command

execution.

R

-------- H --------

-------- R --------

-------- N --------

VERSION

DATA BUS

PHASE

R/W

REMARKS

D7

0

D6

0

D5 D4 D3

D2

0

D1

0

D0

0

Command

Result

W

R

0

1

0

Command Code

1

0

Enhanced Controller

47

FORMAT A TRACK

DATA BUS

PHASE

R/W

REMARKS

D7

0

D6

MFM

0

D5 D4 D3

D2

D1

D0

Command

W

0

1

0

1

0

1

Command Codes

0

HDS DS1 DS0

-------- N --------

-------- SC --------

------- GPL -------

-------- D --------

Bytes/Sector

Sectors/Cylinder

Gap 3

Filler Byte

Execution for

Each Sector

Repeat:

W

-------- C --------

Input Sector

Parameters

W

-------- H --------

-------- R --------

-------- N --------

FDC formats an entire

cylinder

Result

R

------- ST0 -------

Status information after

Command execution

R

------- ST1 -------

------- ST2 -------

------ Undefined ------

48

RECALIBRATE

DATA BUS

PHASE

Command

Execution

R/W

REMARKS

D7 D6 D5 D4 D3 D2

D1

D0

W

0

1

0

1

Command Codes

DS1 DS0

Head retracted to Track 0

Interrupt.

SENSE INTERRUPT STATUS

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3 D2 D1 D0

Command

Result

W

R

0

1

0

Command Codes

------- ST0 -------

Status information at the end

of each seek operation.

R

------- PCN -------

SPECIFY

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3 D2 D1 D0

Command

W

0

1

Command Codes

--- SRT ---

--- HUT ---

------ HLT ------

ND

49

SENSE DRIVE STATUS

DATA BUS

PHASE

Command

Result

R/W

REMARKS

D7 D6 D5 D4 D3

D2

D1

D0

W

R

0

1

0

Command Codes

HDS DS1 DS0

------- ST3 -------

Status information about

FDD

SEEK

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3

D2

D1

D0

Command

W

0

1

0

1

Command Codes

HDS DS1 DS0

------- NCN -------

Execution

Head positioned over

proper cylinder on

diskette.

CONFIGURE

DATA BUS

PHASE

R/W

REMARKS

D0

D7 D6

D5

D4

D3

D2

D1

Command

W

0

1

0

1

Configure

Information

W

0

EIS EFIFO POLL

--- FIFOTHR ---

Execution

--------- PRETRK ---------

50

RELATIVE SEEK

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3

D2

D1

D0

Command

W

1

0

DIR

0

1

0

1

HDS DS1 DS0

------- RCN -------

DUMPREG

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5

D4

D3 D2

D1

D0

Command

W

0

1

0

*Note:

Registers

placed in

FIFO

Execution

Result

R

------ PCN-Drive 0 -------

------ PCN-Drive 1 -------

------ PCN-Drive 2 -------

------ PCN-Drive 3 -------

---- SRT ----

------- HLT -------

------- SC/EOT -------

D3 D2 D1 D0

EIS EFIFO POLL

--- HUT ---

ND

LOCK

0

GAP WGATE

-- FIFOTHR --

-------- PRETRK --------

51

READ ID

DATA BUS

PHASE

Command

Execution

R/W

REMARKS

Commands

D7

0

D6

MFM

0

D5 D4 D3

D2

D1

D0

W

0

1

0

1

0

HDS DS1 DS0

The first correct ID

information on the

Cylinder is stored in

Data Register

Result

R

-------- ST0 --------

Status information after

Command execution.

Disk status after the

Command has

completed

R

-------- ST1 --------

-------- ST2 --------

-------- C --------

-------- H --------

-------- R --------

-------- N --------

52

PERPENDICULAR MODE

DATA BUS

PHASE

R/W

REMARKS

D7

0

D6 D5 D4 D3 D2

D1

D0

Command

W

0

1

0

1

0

Command Codes

OW

D3 D2 D1 D0

GAP WGATE

INVALID CODES

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3 D2 D1 D0

Command

W

----- Invalid Codes -----

Invalid Command Codes

(NoOp - FDC goes into

Standby State)

Result

R

------- ST0 -------

ST0 = 80H

LOCK

DATA BUS

PHASE

R/W

REMARKS

D7

LOCK

0

D6 D5

D4

1

D3 D2 D1 D0

Command

Result

W

R

0

1

0

Command Codes

LOCK

SC is returned if the last command that was issued was the Format command. EOT is returned if the

last command was a Read or Write.

NOTE: These bits are used internally only. They are not reflected in the Drive Select pins. It is the

user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).

53

54

N determines the number of bytes per sector

(see Table 21 below). If N is set to zero, the

sector size is set to 128. The DTL value

determines the number of bytes to be

transferred. If DTL is less than 128, the FDC

transfers the specified number of bytes to the

host. For reads, it continues to read the entire

128-byte sector and checks for CRC errors.

For writes, it completes the 128-byte sector by

filling in zeros. If N is not set to 00 Hex, DTL

should be set to FF Hex and has no impact on

the number of bytes transferred.

DATA TRANSFER COMMANDS

All of the Read Data, Write Data and Verify

type commands use the same parameter

bytes and return the same results information,

the only difference being the coding of bits 0-4

in the first byte.

An implied seek will be executed if the feature

was enabled by the Configure command. This

seek is completely transparent to the user.

The Drive Busy bit for the drive will go active

in the Main Status Register during the seek

portion of the command. If the seek portion

fails, it is reflected in the results status

normally returned for a Read/Write Data

command. Status Register 0 (ST0) would

contain the error code and C would contain the

cylinder on which the seek failed.

Table 21 - Sector Sizes

The amount of data which can be handled with

a single command to the FDC depends upon

MT (multi-track) and

bytes/sector).

N

(number of

N

SECTOR SIZE

Read Data

00

01

02

03

..

128 bytes

256 bytes

512 bytes

1024 bytes

...

A set of nine (9) bytes is required to place the

FDC in the Read Data Mode. After the Read

Data command has been issued, the FDC

loads the head (if it is in the unloaded state),

waits the specified head settling time (defined

in the Specify command), and begins reading

ID Address Marks and ID fields. When the

sector address read off the diskette matches

with the sector address specified in the

command, the FDC reads the sector's data

field and transfers the data to the FIFO.

07

16 Kbytes

The Multi-Track function (MT) allows the FDC

to read data from both sides of the diskette.

For

a

particular cylinder, data will be

transferred starting at Sector 1, Side 0 and

completing the last sector of the same track at

Side 1.

After completion of the read operation from

the current sector, the sector address is

incremented by one and the data from the next

logical sector is read and output via the FIFO.

This continuous read function is called "Multi-

Sector Read Operation". Upon receipt of TC,

or an implied TC (FIFO overrun/underrun), the

FDC stops sending data but will continue to

read data from the current sector, check the

CRC bytes, and at the end of the sector,

terminate the Read Data Command.

If the host terminates a read or write operation

in the FDC, the ID information in the result

phase is dependent upon the state of the MT

bit and EOT byte. Refer to Table 22.

At the completion of the Read Data command,

the head is not unloaded until after the Head

Unload Time Interval (specified in the Specify

command) has elapsed. If the host issues

55

another

command

before the head

After reading the ID and Data Fields in each

sector, the FDC checks the CRC bytes. If

a CRC error occurs in the ID or data field, the

FDC sets the IC code in Status Register 0 to

"01" indicating abnormal termination, sets the

DE bit flag in Status Register 1 to "1", sets the

DD bit in Status Register 2 to "1" if CRC is

incorrect in the ID field, and terminates the

Read Data Command. Table 23 describes the

effect of the SK bit on the Read Data

command execution and results. Except where

noted in Table 23, the C or R value of the

sector address is automatically incremented

(see Table 25).

unloads, then the head settling time may be

saved between subsequent reads.

If the FDC detects a pulse on the nINDEX pin

twice without finding the specified sector

(meaning that the diskette's index hole passes

through index detect logic in the drive twice),

the FDC sets the IC code in Status Register 0

to "01" indicating abnormal termination, sets

the ND bit in Status Register 1 to "1" indicating

a sector not found, and terminates the Read

Data Command.

Table 22 - Effects of MT and N Bits

MT

N

MAXIMUM TRANSFER

CAPACITY

FINAL SECTOR READ

FROM DISK

0

1

0

1

0

1

2

3

256 x 26 = 6,656

256 x 52 = 13,312

512 x 15 = 7,680

512 x 30 = 15,360

1024 x 8 = 8,192

1024 x 16 = 16,384

26 at side 0 or 1

26 at side 1

15 at side 0 or 1

15 at side 1

8 at side 0 or 1

16 at side 1

Table 23 - Skip Bit vs Read Data Command

DATA ADDRESS

MARK TYPE

RESULTS

SK BIT

VALUE

ENCOUNTERED

SECTOR

READ?

CM BIT OF

ST2 SET?

DESCRIPTION OF

RESULTS

0

Normal Data

Deleted Data

Yes

No

Normal termination.

Address not

incremented. Next

sector not searched

for.

Yes

Normal termination.

Sector not read

("skipped").

1

Normal Data

Deleted Data

Yes

No

Yes

56

Table 24 describes the effect of the SK bit on

the Read Deleted Data command execution

and results.

Read Deleted Data

This command is the same as the Read Data

command, only it operates on sectors that

contain a Deleted Data Address Mark at the

beginning of a Data Field.

Except where noted in Table 24, the C or R

value of the sector address is automatically

incremented (see Table 25).

Table 24 - Skip Bit vs. Read Deleted Data Command

DATA ADDRESS

RESULTS

SK BIT

VALUE

MARK TYPE

ENCOUNTERED

SECTOR CM BIT OF

DESCRIPTION

OF RESULTS

READ?

ST2 SET?

0

Normal Data

Yes

Address not

incremented.

Next sector not

searched for.

Normal

0

1

Deleted Data

Normal Data

Yes

No

termination.

Normal

Yes

termination.

Sector not read

("skipped").

Normal

1

Deleted Data

Yes

No

termination.

Multi-track or skip operations are not allowed

with this command. The MT and SK bits (bits

D7 and D5 of the first command byte

respectively) should always be set to "0".

Read A Track

This command is similar to the Read Data

command except that the entire data field is

read continuously from each of the sectors of

a track. Immediately after encountering a

pulse on the nINDEX pin, the FDC starts to

read all data fields on the track as continuous

blocks of data without regard to logical sector

numbers. If the FDC finds an error in the ID or

DATA CRC check bytes, it continues to read

data from the track and sets the appropriate

error bits at the end of the command. The

FDC compares the ID information read from

each sector with the specified value in the

command and sets the ND flag of Status

Register 1 to a "1" if there is no comparison.

This command terminates when the EOT

specified number of sectors has not been

read. If the FDC does not find an ID Address

Mark on the diskette after the second

occurrence of a pulse on the IDX pin, then it

sets the IC code in Status Register 0 to "01"

(abnormal termination), sets the MA bit in

Status Register 1 to "1", and terminates the

command.

57

Table 25 - Result Phase Table

ID INFORMATION AT RESULT PHASE

FINAL SECTOR

MT

HEAD

TRANSFERRED TO

HOST

C

H

R

N

0

Less than EOT

Equal to EOT

Less than EOT

Equal to EOT

Less than EOT

Equal to EOT

Less than EOT

Equal to EOT

NC

LSB

NC

LSB

R + 1

01

NC

C + 1

NC

1

0

1

R + 1

01

C + 1

NC

1

R + 1

01

NC

R + 1

01

C + 1

NC: No Change, the same value as the one at the beginning of command execution.

LSB: Least Significant Bit, the LSB of H is complemented.

sector and checks the CRC bytes. If it detects

a CRC error in ne of the ID fields,

Write Data

it sets the IC code in Status Register 0 to "01"

(abnormal termination), sets the DE bit of

Status Register 1 to "1", and terminates the

Write Data command.

After the Write Data command has been

issued, the FDC loads the head (if it is in the

unloaded state), waits the specified head load

time if unloaded (defined in the Specify

command), and begins reading ID fields.

When the sector address read from the

diskette matches the sector address specified

in the command, the FDC reads the data from

the host via the FIFO and writes it to the

sector's data field.

The Write Data command operates in much

the same manner as the Read Data

command. The following items are the same.

Please refer to the Read Data Command for

details:

·

Transfer Capacity

EN (End of Cylinder) bit

ND (No Data) bit

Head Load, Unload Time Interval

ID information when the host terminates

the command

Definition of DTL when N = 0 and when N

does not = 0

After writing data into the current sector, the

FDC computes the CRC value and writes it

into the CRC field at the end of the sector

transfer. The Sector Number stored in "R" is

incremented by one, and the FDC continues

writing to the next data field. The FDC

continues this "Multi-Sector Write Operation".

Upon receipt of a terminal count signal or if a

FIFO over/under run occurs while a data field

is being written, then the remainder of the data

field is filled with zeros. The FDC reads the ID

field of each

·

Write Deleted Data

This command is almost the same as the

Write Data command except that a Deleted

Data Address Mark is written at the beginning

of the Data Field instead of the normal Data

58

Address Mark. This command is typically

used to mark a bad sector containing an error

on the floppy disk.

implicit TC will occur when the SC value

has decremented to 0 (an SC value of 0 will

verify 256 sectors). This command can also

be terminated by setting the EC bit to "0" and

the EOT value equal to the final sector to be

checked. If EC is set to "0", DTL/SC should

be programmed to 0FFH. Refer to Table 25

and Table 26 for information concerning the

values of MT and EC versus SC and EOT

value.

Verify

The Verify command is used to verify the data

stored on a disk. This command acts exactly

like a Read Data command except that no

data is transferred to the host. Data is read

from the disk and CRC is computed and

checked against the previously-stored value.

Definitions:

# Sectors Per Side = Number of formatted

sectors per each side of the disk.

Because data is not transferred to the host, TC

cannot be used to terminate this command.

By setting the EC bit to "1", an implicit TC

will be issued to the FDC. This

# Sectors Remaining = Number of formatted

sectors left which can be read, including side 1

of the disk if MT is set to "1".

Table 26 - Verify Command Result Phase Table

SC/EOT VALUE TERMINATION RESULT

Success Termination

MT

EC

0

SC = DTL

Result Phase Valid

EOT £ # Sectors Per Side

0

1

0

1

0

1

SC = DTL

EOT > # Sectors Per Side

Unsuccessful Termination

Result Phase Invalid

Successful Termination

Result Phase Valid

SC £ # Sectors Remaining AND

EOT £ # Sectors Per Side

SC > # Sectors Remaining OR

EOT > # Sectors Per Side

Unsuccessful Termination

Result Phase Invalid

SC = DTL

EOT £ # Sectors Per Side

Successful Termination

Result Phase Valid

SC = DTL

EOT > # Sectors Per Side

Unsuccessful Termination

Result Phase Invalid

Successful Termination

Result Phase Valid

SC £ # Sectors Remaining AND

EOT £ # Sectors Per Side

SC > # Sectors Remaining OR

EOT > # Sectors Per Side

Unsuccessful Termination

Result Phase Invalid

NOTE: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors

on Side 0, verifying will continue on Side 1 of the disk.

59

After formatting each sector, the host must

send new values for C, H, R and N to the FDC

for the next sector on the track. The R value

(sector number) is the only value that must be

changed by the host after each sector is

Format A Track

The Format command allows an entire track

to be formatted. After a pulse from the IDX

pin is detected, the FDC starts writing data on

the disk including gaps, address marks, ID

fields, and data fields per the IBM System 34

or 3740 format (MFM or FM respectively). The

particular values that will be written to the gap

and data field are controlled by the values

programmed into N, SC, GPL, and D which

are specified by the host during the command

phase. The data field of the sector is filled

with the data byte specified by D. The ID field

for each sector is supplied by the host; that is,

four data bytes per sector are needed by the

FDC for C, H, R, and N (cylinder, head, sector

number and sector size respectively).

formatted.

formatted with nonsequential sector addresses

(interleaving). This incrementing and

This allows the disk to be

formatting continues for the whole track until

the FDC encounters a pulse on the IDX pin

again and it terminates the command.

Table 27 contains typical values for gap fields

which are dependent upon the size of the

sector and the number of sectors on each

track. Actual values can vary due to drive

electronics.

FORMAT FIELDS

SYSTEM 34 (DOUBLE DENSITY) FORMAT

DATA

GAP4a SYNC

IAM

GAP1 SYNC IDAM

C

Y

L

H

D

S

E

C

N

O

C

R

C

GAP2 SYNC

AM

C

R

C

80x

4E

12x

00

50x

4E

12x

00

22x

4E

12x

00

DATA

GAP3 GAP 4b

3x FC

C2

3x FE

A1

3x FB

A1 F8

SYSTEM 3740 (SINGLE DENSITY) FORMAT

DATA

AM

GAP4a SYNC

IAM

FC

GAP1 SYNC IDAM

C

Y

L

H

D

S

E

C

N

O

C

R

C

GAP2 SYNC

C

R

C

40x

FF

6x

00

26x

FF

6x

00

11x

FF

6x

00

FE

FB or

F8

PERPENDICULAR FORMAT

DATA

AM

GAP4a SYNC

IAM

GAP1 SYNC IDAM

C

Y

L

H

D

S

E

C

N

O

C

R

C

GAP2 SYNC

C

R

C

80x

4E

12x

00

50x

4E

12x

00

41x

4E

12x

00

3x FC

C2

3x FE

A1

3x FB

A1 F8

60

Table 27 - Typical Values for Formatting

FORMAT SECTOR SIZE

N

SC

GPL1

GPL2

128

512

1024

2048

4096

...

00

02

03

04

05

...

12

10

08

04

02

01

07

10

18

46

C8

09

19

30

87

FF

FM

5.25"

Drives

256

01

02

03

04

05

...

12

10

09

04

02

01

0A

20

2A

80

C8

0C

32

50

F0

FF

512*

1024

2048

4096

...

MFM

128

256

512

0

1

2

0F

09

05

07

0F

1B

2A

3A

FM

3.5"

Drives

256

512**

1024

1

2

3

0F

09

05

0E

1B

35

36

54

74

MFM

GPL1 = suggested GPL values in Read and Write commands to avoid splice point

between data field and ID field of contiguous sections.

GPL2 = suggested GPL value in Format A Track command.

*PC/AT values (typical)

**PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives.

NOTE: All values except sector size are in hex.

61

more than one Recalibrate command to return

the head back to physical Track 0.

CONTROL COMMANDS

Control commands differ from the other

commands in that no data transfer takes

place. Three commands generate an interrupt

when complete: Read ID, Recalibrate, and

Seek. The other control commands do not

generate an interrupt.

The Recalibrate command does not have a

result phase.

The Sense Interrupt Status

command must be issued after the Recalibrate

command to effectively terminate it and to

provide verification of the head position (PCN).

During the command phase of the recalibrate

operation, the FDC is in the BUSY state, but

during the execution phase it is in a NON-

BUSY state. At this time, another Recalibrate

command may be issued, and in this manner

parallel Recalibrate operations may be done

on up to four drives at once.

Read ID

The Read ID command is used to find the

present position of the recording heads. The

FDC stores the values from the first ID field it

is able to read into its registers. If the FDC

does not find an ID address mark on the

diskette after the second occurrence of a pulse

on the nINDEX pin, it then sets the IC code in

Upon power up, the software must issue a

Recalibrate command to properly initialize all

drives and the controller.

Status Register

0

to "01" (abnormal

termination), sets the MA bit in Status Register

1 to "1", and terminates the command.

Seek

The read/write head within the drive is moved

from track to track under the control of the

Seek command. The FDC compares the

PCN, which is the current head position, with

the NCN and performs the following operation

if there is a difference:

The following commands will generate an

interrupt upon completion. They do not return

any result bytes. It is highly recommended

that control commands be followed by the

Sense Interrupt Status command. Otherwise,

valuable interrupt status information will be

lost.

PCN < NCN: Direction signal to drive set

to "1" (step in) and

Recalibrate

issues step pulses.

PCN > NCN: Direction signal to drive set

to "0" (step out) and

This command causes the read/write head

within the FDC to retract to the track 0

position. The FDC clears the contents of the

PCN counter and checks the status of the

nTR0 pin from the FDD. As long as the nTR0

pin is low, the DIR pin remains 0 and step

pulses are issued. When the nTR0 pin goes

high, the SE bit in Status Register 0 is set to

"1" and the command is terminated. If the

nTR0 pin is still low after 79 step pulses have

been issued, the FDC sets the SE and the EC

bits of Status Register 0 to "1" and terminates

the command. Disks capable of handling

more than 80 tracks per side may require

issues step pulses.

The rate at which step pulses are issued is

controlled by SRT (Stepping Rate Time) in the

Specify command. After each step pulse is

issued, NCN is compared against PCN, and

when NCN = PCN the SE bit in Status

Register 0 is set to "1" and the command is

terminated.

During the command phase of the seek or

recalibrate operation, the FDC is in the BUSY

62

state, but during the execution phase it is in

the NON-BUSY state. At this time, another

Seek or Recalibrate command may be issued,

and in this manner, parallel seek operations

may be done on up to four drives at once.

2. End of Seek, Relative Seek, or Recalibrate

command

3. FDC requires a data transfer during the

execution phase in the non-DMA mode

Note that if implied seek is not enabled, the

read and write commands should be preceded

by:

The Sense Interrupt Status command resets

the interrupt signal and, via the IC code and

SE bit of Status Register 0, identifies the

cause of the interrupt.

1) Seek command - Step to the proper track

2) Sense Interrupt Status command

Terminate the Seek command

3) Read ID - Verify head is on proper track

4) Issue Read/Write command.

-

Table 28 - Interrupt Identification

SE

IC

INTERRUPT DUE TO

0

1

11

00

Polling

Normal termination of Seek

or Recalibrate command

Abnormal termination of

Seek or Recalibrate

command

The Seek command does not have a result

phase. Therefore, it is highly recommended

that the Sense Interrupt Status command be

issued after the Seek command to terminate it

and to provide verification of the head position

(PCN). The H bit (Head Address) in ST0 will

1

01

always return to

a

"0".

When exiting

POWERDOWN mode, the FDC clears the

PCN value and the status information to zero.

Prior to issuing the POWERDOWN

command, it is highly recommended that the

user service all pending interrupts through the

Sense Interrupt Status command.

The Seek, Relative Seek, and Recalibrate

commands have no result phase. The Sense

Interrupt Status command must be issued

immediately after these commands to

terminate them and to provide verification of

the head position (PCN).

The H (Head

Address) bit in ST0 will always return a "0". If

a Sense Interrupt Status is not issued, the

drive will continue to be BUSY and may affect

the operation of the next command.

Sense Interrupt Status

An interrupt signal on FINT is generated by the

FDC for one of the following reasons:

1. Upon entering the Result Phase of:

a. Read Data command

b. Read A Track command

c. Read ID command

d. Read Deleted Data command

e. Write Data command

f. Format A Track command

g. Write Deleted Data command

h. Verify command

63

from the end of the execution phase of one of

the read/write commands to the head unload

state. The SRT (Step Rate Time) defines the

time interval between adjacent step pulses.

Note that the spacing between the first and

second step pulses may be shorter than the

remaining step pulses. The HLT (Head Load

Time) defines the time between when the

Head Load signal goes high and the read/write

operation starts. The values change with

Sense Drive Status

Sense Drive Status obtains drive status

information. It has not execution phase and

goes directly to the result phase from the

command phase. Status Register 3 contains

the drive status information.

Specify

the

data

rate speedselection and are

The Specify command sets the initial values

for each of the three internal times. The HUT

(Head Unload Time) defines the time

documented in Table 29. The values are the

same for MFM and FM.

Table 29 - Drive Control Delays (ms)

HUT

SRT

2M

1M

500K 300K 250K

2M

1M

500K 300K 250K

0

1

..

E

F

64

4

..

56

60

128

8

..

112

120

256

16

..

224

240

426

26.7

..

373

400

512

32

..

448

480

4

3.75

..

0.5

0.25

8

7.5

..

1

0.5

16

15

..

2

1

26.7

25

..

3.33

1.67

32

30

..

4

2

HLT

2M

1M

500K

300K

250K

00

01

02

..

64

0.5

1

128

1

2

256

2

4

426

3.3

6.7

..

512

4

8

..

.

7F

63

63.5

126

127

252

254

420

423

504

508

The choice of DMA or non-DMA operations is

made by the ND bit. When this bit is "1", the

non-DMA mode is selected, and when ND is

"0", the DMA mode is selected. In DMA mode,

data transfers are signalled by the FDRQ pin.

Non-DMA mode uses the RQM bit and the

FINT to signal data transfers.

command need not be issued if the default

values of the FDC meet the system

requirements.

Configure Default Values:

EIS - No Implied Seeks

EFIFO - FIFO Disabled

Configure

POLL - Polling Enabled

FIFOTHR - FIFO Threshold Set to 1 Byte

PRETRK - Pre-Compensation Set to Track 0

The Configure command is issued to select

the special features of the FDC. A Configure

64

DIR

ACTION

EIS - Enable Implied Seek. When set to "1",

the FDC will perform a Seek operation before

executing a read or write command. Defaults

to no implied seek.

0

1

Step Head Out

Step Head In

EFIFO - A "1" disables the FIFO (default).

This means data transfers are asked for on a

byte-by-byte basis. Defaults to "1", FIFO

disabled. The threshold defaults to "1".

RCN Relative

Cylinder

Number

that

determines how many tracks to step

the head in or out from the current

track number.

POLL - Disable polling of the drives. Defaults

to "0", polling enabled. When enabled, a

single interrupt is generated after a reset. No

polling is performed while the drive head is

loaded and the head unload delay has not

expired.

The Relative Seek command differs from the

Seek command in that it steps the head the

absolute number of tracks specified in the

command instead of making a comparison

against an internal register.

command is good for drives that support a

maximum of 256 tracks. Relative Seeks

The Seek

FIFOTHR

- The FIFO threshold in the

cannot be overlapped with other Relative

Seeks. Only one Relative Seek can be active

at a time. Relative Seeks may be overlapped

with Seeks and Recalibrates. Bit 4 of Status

Register 0 (EC) will be set if Relative Seek

attempts to step outward beyond Track 0.

execution phase of read or write commands.

This is programmable from 1 to 16 bytes.

Defaults to one byte. A "00" selects one byte;

"0F" selects 16 bytes.

PRETRK - Pre-Compensation Start Track

Number. Programmable from track 0 to 255.

Defaults to track 0. A "00" selects track 0;

"FF" selects track 255.

As an example, assume that a floppy drive

has 300 useable tracks. The host needs to

read track 300 and the head is on any track

(0-255). If a Seek command is issued, the

head will stop at track 255. If a Relative Seek

command is issued, the FDC will move the

head the specified number of tracks,

regardless of the internal cylinder position

register (but will increment the register). If the

head was on track 40 (d), the maximum track

that the FDC could position the head on using

Relative Seek will be 295 (D), the initial track +

255 (D). The maximum count that the head

can be moved with a single Relative Seek

command is 255 (D).

Version

The Version command checks to see if the

controller is an enhanced type or the older

type (765A). A value of 90 H is returned as

the result byte.

Relative Seek

The command is coded the same as for Seek,

except for the MSB of the first byte and the

DIR bit.

The internal register, PCN, will overflow as the

cylinder number crosses track 255 and will

contain 39 (D). The resulting PCN value is

thus (RCN + PCN) mod 256. Functionally, the

FDC starts counting from 0 again as the track

DIR

Head Step Direction Control

65

number goes above 255 (D). It is the user's

responsibility to compensate FDC functions

(precompensation track number) when

accessing tracks greater than 255. The FDC

does not keep track that it is working in an

"extended track area" (greater than 255). Any

command issued will use the current PCN

value except for the Recalibrate command,

which only looks for the TRACK0 signal.

Recalibrate will return an error if the head is

farther than 79 due to its limitation of issuing a

maximum of 80 step pulses. The user simply

these drives. Table 30 describes the effects of

the WGATE and GAP bits for the

Perpendicular Mode command. Upon a reset,

the FDC will default to the conventional mode

(WGATE = 0, GAP = 0).

Selection of the 500 Kbps and 1 Mbps

perpendicular modes is independent of the

actual data rate selected in the Data Rate

Select Register. The user must ensure that

these two data rates remain consistent.

needs to issue

a

second Recalibrate

The Gap2 and VCO timing requirements for

perpendicular recording type drives are

dictated by the design of the read/write head.

In the design of this head, a pre-erase head

precedes the normal read/write head by a

distance of 200 micrometers. This works out

to about 38 bytes at a 1 Mbps recording

density. Whenever the write head is enabled

by the Write Gate signal, the pre-erase head is

also activated at the same time. Thus, when

the write head is initially turned on, flux

transitions recorded on the media for the first

38 bytes will not be preconditioned with the

pre-erase head since it has not yet been

command. The Seek command and implied

seeks will function correctly within the 44 (D)

track (299-255) area of the "extended track

area". It is the user's responsibility not to

issue a new track position that will exceed the

maximum track that is present in the extended

area.

To return to the standard floppy range (0-255)

of tracks, a Relative Seek should be issued to

cross the track 255 boundary.

A Relative Seek can be used instead of the

normal Seek, but the host is required to

calculate the difference between the current

head location and the new (target) head

location. This may require the host to issue a

Read ID command to ensure that the head is

physically on the track that software assumes

it to be. Different FDC commands will return

different cylinder results which may be difficult

to keep track of with software without the Read

ID command.

activated.

To accommodate this head

activation and deactivation time, the Gap2

field is expanded to a length of 41 bytes. The

format field shown on Page 57 illustrates the

change in the Gap2 field size for the

perpendicular format.

On the read back by the FDC, the controller

must begin synchronization at the beginning of

the sync field. For the conventional mode, the

internal PLL VCO is enabled (VCOEN)

approximately 24 bytes from the start of the

Gap2 field. But, when the controller operates

in the 1 Mbps perpendicular mode (WGATE =

1, GAP = 1), VCOEN goes active after 43

bytes to accommodate the increased Gap2

field size. For both cases, and approximate

two-byte cushion is maintained from the

beginning of the sync field for the purposes of

avoiding write splices in the presence of motor

speed variation.

Perpendicular Mode

The Perpendicular Mode command should be

issued prior to executing Read/Write/Format

commands that access a disk drive with

perpendicular recording capability. With this

command, the length of the Gap2 field and

VCO enable timing can be altered to

accommodate the unique requirements of

66

When both GAP and WGATE bits of the

PERPENDICULAR MODE COMMAND are

both programmed to "0" (Conventional mode),

then D0, D1, D2, D3, and D4 can be

programmed independently to "1" for that drive

to be set automatically to Perpendicular mode.

In this mode the following set of conditions

also apply:

1. The GAP2 written to a perpendicular drive

during a write operation will depend upon

the programmed data rate.

2. The write pre-compensation given to a

perpendicular mode drive will be 0ns.

3. For D0-D3 programmed to "0" for

conventional mode drives any data written

will be at the currently programmed write

pre-compensation.

For the Write Data case, the FDC activates

Write Gate at the beginning of the sync field

under the conventional mode. The controller

then writes a new sync field, data address

mark, data field, and CRC as shown on page

57.

With the pre-erase head of the

perpendicular drive, the write head must be

activated in the Gap2 field to insure a proper

write of the new sync field. For the 1 Mbps

perpendicular mode (WGATE = 1, GAP = 1),

38 bytes will be written in the Gap2 space.

Since the bit density is proportional to the data

rate, 19 bytes will be written in the Gap2 field

for the 500 Kbps perpendicular mode

(WGATE = 1, GAP =0).

It should be noted that none of the alterations

in Gap2 size, VCO timing, or Write Gate

Note: Bits D0-D3 can only be overwritten

when OW is programmed as a "1". If

either GAP or WGATE is a "1" then

D0-D3 are ignored.

timing affect normal program flow.

The

information provided here is just for

background purposes and is not needed for

normal operation. Once the Perpendicular

Mode command is invoked, FDC software

behavior from the user standpoint is

unchanged.

Software and hardware resets have the

following effect on the PERPENDICULAR

MODE COMMAND:

1. "Software" resets (via the DOR or DSR

registers) will only clear GAP and WGATE

bits to "0". D0-D3 are unaffected and

retain their previous value.

The perpendicular mode command is

enhanced to allow specific drives to be

designated Perpendicular

recording drives.

This enhancement allows data transfers

between Conventional and Perpendicular

drives without having to issue Perpendicular

mode commnds between the accesses of the

different drive types, nor having to change

write pre-compensation values.

2. "Hardware" resets will clear all bits ( GAP,

WGATE and D0-D3) to "0", i.e all

conventional mode.

67

Table 30 - Effects of WGATE and GAP Bits

PORTION OF

GAP 2

LENGTH OF

GAP2

FORMAT

FIELD

WRITTEN BY

WRITE DATA

OPERATION

WGATE GAP

MODE

0

1

Conventional

Perpendicular

(500 Kbps)

Reserved

(Conventional)

Perpendicular

(1 Mbps)

22 Bytes

0 Bytes

19 Bytes

1

0

1

22 Bytes

41 Bytes

0 Bytes

38 Bytes

LOCK

ENHANCED DUMPREG

In order to protect systems with long DMA

latencies against older application software

that can disable the FIFO the LOCK

Command has been added. This command

should only be used by the FDC routines, and

application software should refrain from using

it. If an application calls for the FIFO to be

disabled then the CONFIGURE command

should be used.

The DUMPREG command is designed to

support system run-time diagnostics and

application software development and debug.

To accommodate the LOCK command and

the enhanced PERPENDICULAR MODE

command the eighth byte of the DUMPREG

command has been modified to contain the

additional data from these two commands.

COMPATIBILITY

The LOCK command defines whether the

EFIFO, FIFOTHR, and PRETRK parameters

of the CONFIGURE command can be RESET

by the DOR and DSR registers. When the

LOCK bit is set to logic "1" all subsequent

"software RESETS by the DOR and DSR

registers will not change the previously set

The FDC37C68x was designed with software

compatibility in mind. It is a fully backwards-

compatible solution with the older generation

765A/B disk controllers. The FDC also

implements

on-board

registers

for

compatibility with the PS/2, as well as PC/AT

and PC/XT, floppy disk controller subsystems.

After a hardware reset of the FDC, all

registers, functions and enhancements default

parameters to their default values.

All

"hardware" RESET from the RESET pin will

set the LOCK bit to logic "0" and return the

EFIFO, FIFOTHR, and PRETRK to their

default values. A status byte is returned

to

a

PC/AT, PS/2 or PS/2 Model 30

compatible operating mode, depending on

how the IDENT and MFM bits are configured

by the system BIOS.

immediately after issuing

a

LOCK

command. This byte reflects the value of the

LOCK bit set by the command byte.

68

SERIAL PORT (UART)

The FDC37C68x incorporates two full function

UARTs. They are compatible with the

NS16450, the 16450 ACE registers and the

NS16550A. The UARTS perform serial-to-

parallel conversion on received characters and

parallel-to-serial conversion on transmit

by programming OUT2 of that UART to a logic

"1". OUT2 being a logic "0" disables that

UART's interrupt. The second UART also

supports IrDA, HP-SIR and ASK-IR infrared

modes of operation.

characters. The data rates are independently

programmable from 460.8K baud down to 50

baud. The character options are programmable

for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky

or no parity; and prioritized interrupts. The

UARTs each contain a programmable baud rate

generator that is capable of dividing the input

clock or crystal by a number from 1 to 65535.

The UARTs are also capable of supporting the

MIDI data rate. Refer to the Configuration

Registers for information on disabling, power

down and changing the base address of the

UARTs. The interrupt from a UART is enabled

Note: The UARTs may be configured to share

an interrupt. Refer to the Configuration section

for more information.

REGISTER DESCRIPTION

Addressing of the accessible registers of the

Serial Port is shown below.

The base

addresses of the serial ports are defined by the

configuration registers (see Configuration

section). The Serial Port registers are located at

sequentially increasing addresses above these

base addresses. The FDC37C68x contains two

serial ports, each of which contain a register set

as described below.

Table 31 - Addressing the Serial Port

DLAB*

A2

0

1

0

A1

0

1

0

1

0

A0

0

1

0

1

0

1

0

1

0

1

REGISTER NAME

0

Receive Buffer (read)

Transmit Buffer (write)

Interrupt Enable (read/write)

Interrupt Identification (read)

FIFO Control (write)

0

X

1

Line Control (read/write)

Modem Control (read/write)

Line Status (read/write)

Modem Status (read/write)

Scratchpad (read/write)

Divisor LSB (read/write)

Divisor MSB (read/write

1

*NOTE: DLAB is Bit 7 of the Line Control Register

69

The following section describes the operation of

the registers.

Bit 0

This bit enables the Received Data Available

Interrupt (and timeout interrupts in the FIFO

mode) when set to logic "1".

RECEIVE BUFFER REGISTER (RB)

Address Offset = 0H, DLAB = 0, READ ONLY

Bit 1

This bit enables the Transmitter Holding

Register Empty Interrupt when set to logic "1".

Bit 2

This bit enables the Received Line Status

Interrupt when set to logic "1". The error

sources causing the interrupt are Overrun,

Parity, Framing and Break. The Line Status

Register must be read to determine the source.

Bit 3

This register holds the received incoming data

byte. Bit 0 is the least significant bit, which is

transmitted and received first. Received data is

double buffered; this uses an additional shift

register to receive the serial data stream and

convert it to a parallel 8 bit word which is

transferred to the Receive Buffer register. The

shift register is not accessible.

This bit enables the MODEM Status Interrupt

when set to logic "1". This is caused when one

of the Modem Status Register bits changes

state.

Bits 4 through 7

These bits are always logic "0".

TRANSMIT BUFFER REGISTER (TB)

Address Offset = 0H, DLAB = 0, WRITE ONLY

This register contains the data byte to be

transmitted.

The transmit buffer is double

buffered, utilizing an additional shift register (not

accessible) to convert the 8 bit data word to a

serial format. This shift register is loaded from

the Transmit Buffer when the transmission of

the previous byte is complete.

FIFO CONTROL REGISTER (FCR)

Address Offset = 2H, DLAB = X, WRITE

This is a write only register at the same location

as the IIR. This register is used to enable and

clear the FIFOs, set the RCVR FIFO trigger

level. Note: DMA is not supported.

INTERRUPT ENABLE REGISTER (IER)

Address Offset = 1H, DLAB = 0, READ/WRITE

Bit 0

The lower four bits of this register control the

enables of the five interrupt sources of the Serial

Port interrupt. It is possible to totally disable the

interrupt system by resetting bits 0 through 3 of

this register. Similarly, setting the appropriate

bits of this register to a high, selected interrupts

can be enabled. Disabling the interrupt system

inhibits the Interrupt Identification Register and

disables any Serial Port interrupt out of the

FDC37C68x. All other system functions operate

in their normal manner, including the Line

Status and MODEM Status Registers. The

contents of the Interrupt Enable Register are

described below.

Setting this bit to a logic "1" enables both the

XMIT and RCVR FIFOs. Clearing this bit to a

logic "0" disables both the XMIT and RCVR

FIFOs and clears all bytes from both FIFOs.

When changing from FIFO Mode to non-FIFO

(16450) mode, data is automatically cleared

from the FIFOs. This bit must be a 1 when

other bits in this register are written to or they

will not be properly programmed.

Bit 1

Setting this bit to a logic "1" clears all bytes in

the RCVR FIFO and resets its counter logic to 0.

The shift register is not cleared. This bit is self-

clearing.

70

3. Transmitter Holding Register Empty

4. MODEM Status (lowest priority)

Bit 2

Setting this bit to a logic "1" clears all bytes in

the XMIT FIFO and resets its counter logic to 0.

The shift register is not cleared. This bit is self-

clearing.

Information indicating that a prioritized interrupt

is pending and the source of that interrupt is

stored in the Interrupt Identification Register

(refer to Interrupt Control Table). When the CPU

accesses the IIR, the Serial Port freezes all

interrupts and indicates the highest priority

pending interrupt to the CPU. During this CPU

access, even if the Serial Port records new

interrupts, the current indication does not

change until access is completed. The contents

of the IIR are described below.

Bit 3

Writting to this bit has no effect on the operation

of the UART. The RXRDY and TXRDY pins are

not available on this chip.

Bit 4,5

Reserved

Bit 6,7

These bits are used to set the trigger level for

the RCVR FIFO interrupt.

INTERRUPT IDENTIFICATION REGISTER

(IIR)

Bit 0

This bit can be used in either a hardwired

prioritized or polled environment to indicate

whether an interrupt is pending. When bit 0 is a

logic "0", an interrupt is pending and the

contents of the IIR may be used as a pointer to

the appropriate internal service routine. When

bit 0 is a logic "1", no interrupt is pending.

Bits 1 and 2

Address Offset = 2H, DLAB = X, READ

Bit 7 Bit 6

RCVR FIFO

Trigger Level

(BYTES)

0

1

0

1

0

1

4

These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated by

the Interrupt Control Table.

8

Bit 3

In non-FIFO mode, this bit is a logic "0". In

FIFO mode this bit is set along with bit 2 when a

timeout interrupt is pending.

14

Bits 4 and 5

These bits of the IIR are always logic "0".

Bits 6 and 7

These two bits are set when the FIFO

CONTROL Register bit 0 equals 1.

By accessing this register, the host CPU can

determine the highest priority interrupt and its

source. Four levels of priority interrupt exist.

They are in descending order of priority:

1. Receiver Line Status (highest priority)

2. Received Data Ready

71

Table 32 - Interrupt Control Table

FIFO

INTERRUPT

MODE IDENTIFICATION

ONLY

REGISTER

INTERRUPT SET AND RESET FUNCTIONS

BIT

3

BIT

2

BIT

1

BIT PRIORIT

INTERRUPT

TYPE

INTERRUPT

SOURCE

INTERRUPT

RESET

0

Y LEVEL

CONTROL

0

1

0

1

0

-

None

-

Highest

Receiver Line

Status

Overrun Error,

Parity Error,

Reading the Line

Status Register

Framing Error or

Break Interrupt

0

1

0

Second

Received Data

Available

Receiver Data

Available

Read Receiver

Buffer or the

FIFO drops below

the trigger level.

Character

Timeout

Indication

No Characters

Have Been

Removed From

or Input to the

RCVR FIFO

Reading the

Receiver Buffer

Register

during the last 4

Char times and

there is at least 1

char in it during

this time

0

1

0

Third

Transmitter

Reading the IIR

Holding Register Holding Register Register (if

Empty

Source of

Interrupt) or

Writing the

Transmitter

Holding Register

Fourth

MODEM Status

Clear to Send or Reading the

Data Set Ready MODEM Status

or Ring Indicator Register

or Data Carrier

Detect

72

(The parity bit is used to generate an even or

odd number of 1s when the data word bits and

the parity bit are summed).

LINE CONTROL REGISTER (LCR)

Address Offset = 3H, DLAB = 0, READ/WRITE

This register contains the format information of

the serial line. The bit definitions are:

Bits 0 and 1

These two bits specify the number of bits in

each transmitted or received serial character.

The encoding of bits 0 and 1 is as follows:

Bit 4

Even Parity Select bit. When bit 3 is a logic "1"

and bit 4 is a logic "0", an odd number of logic

"1"'s is transmitted or checked in the data word

bits and the parity bit. When bit 3 is a logic "1"

and bit 4 is a logic "1" an even number of bits is

transmitted and checked.

Bit 5

BIT 1 BIT 0 WORD LENGTH

Stick Parity bit. When bit 3 is a logic "1" and bit

5 is a logic "1", the parity bit is transmitted and

then detected by the receiver in the opposite

state indicated by bit 4.

0

1

0

1

0

1

5 Bits

6 Bits

7 Bits

8 Bits

Bit 6

Set Break Control bit. When bit 6 is a logic "1",

the transmit data output (TXD) is forced to the

Spacing or logic "0" state and remains there

(until reset by a low level bit 6) regardless of

other transmitter activity. This feature enables

The Start, Stop and Parity bits are not included

in the word length.

Bit 2

the Serial Port to alert

communications system.

Bit 7

a terminal in a

This bit specifies the number of stop bits in each

transmitted or received serial character. The

following table summarizes the information.

Divisor Latch Access bit (DLAB). It must be set

high (logic "1") to access the Divisor Latches of

the Baud Rate Generator during read or write

operations. It must be set low (logic "0") to

access the Receiver Buffer Register, the

Transmitter Holding Register, or the Interrupt

Enable Register.

NUMBER OF

STOP BITS

BIT 2 WORD LENGTH

0

1

--

1

1.5

2

5 bits

6 bits

7 bits

8 bits

MODEM CONTROL REGISTER (MCR)

Address Offset = 4H, DLAB = X, READ/WRITE

This 8 bit register controls the interface with the

MODEM or data set (or device emulating a

MODEM). The contents of the MODEM control

register are described below.

2

Note: The receiver will ignore all stop bits

beyond the first, regardless of the number used

in transmitting.

Bit 0

This bit controls the Data Terminal Ready

(nDTR) output. When bit 0 is set to a logic "1",

the nDTR output is forced to a logic "0". When

bit 0 is a logic "0", the nDTR output is forced to

a logic "1".

Bit 3

Parity Enable bit. When bit 3 is a logic "1", a

parity bit is generated (transmit data) or

checked (receive data) between the last data

word bit and the first stop bit of the serial data.

73

Register instead of the MODEM Control inputs.

The interrupts are still controlled by the Interrupt

Enable Register.

Bits 5 through 7

These bits are permanently set to logic zero.

Bit 1

This bit controls the Request To Send (nRTS)

output. Bit 1 affects the nRTS output in a

manner identical to that described above for bit

0.

Bit 2

This bit controls the Output 1 (OUT1) bit. This

bit does not have an output pin and can only be

read or written by the CPU.

LINE STATUS REGISTER (LSR)

Address Offset = 5H, DLAB = X, READ/WRITE

Bit 0

Bit 3

Data Ready (DR). It is set to a logic "1"

whenever a complete incoming character has

been received and transferred into the Receiver

Buffer Register or the FIFO. Bit 0 is reset to a

logic "0" by reading all of the data in the Receive

Buffer Register or the FIFO.

Output 2 (OUT2). This bit is used to enable an

UART interrupt. When OUT2 is a logic "0", the

serial port interrupt output is forced to a high

impedance state - disabled. When OUT2 is a

logic "1", the serial port interrupt outputs are

enabled.

Bit 1

Bit 4

Overrun Error (OE). Bit 1 indicates that data in

the Receiver Buffer Register was not read before

the next character was transferred into the

register, thereby destroying the previous

character. In FIFO mode, an overrunn error will

occur only when the FIFO is full and the next

character has been completely received in the

shift register, the character in the shift register is

overwritten but not transferred to the FIFO. The

OE indicator is set to a logic "1" immediately

upon detection of an overrun condition, and

reset whenever the Line Status Register is read.

Bit 2

Parity Error (PE). Bit 2 indicates that the

received data character does not have the

correct even or odd parity, as selected by the

even parity select bit. The PE is set to a logic

"1" upon detection of a parity error and is

reset to a logic "0" whenever the Line Status

Register is read. In the FIFO mode this error is

associated with the particular character in the

FIFO it applies to. This error is indicated when

the associated character is at the top of the

FIFO.

This bit provides the loopback feature for

diagnostic testing of the Serial Port. When bit 4

is set to logic "1", the following occur:

1. The TXD is set to the Marking State(logic

"1").

2. The receiver Serial Input (RXD) is

disconnected.

3. The output of the Transmitter Shift Register

is "looped back" into the Receiver Shift

Register input.

4. All MODEM Control inputs (nCTS, nDSR,

nRI and nDCD) are disconnected.

5. The four MODEM Control outputs (nDTR,

nRTS, OUT1 and OUT2) are internally

connected to the four MODEM Control

inputs (nDSR, nCTS, RI, DCD).

6. The Modem Control output pins are forced

inactive high.

7. Data that is transmitted is immediately

received.

This feature allows the processor to verify the

transmit and receive data paths of the Serial

Port. In the diagnostic mode, the receiver and

the transmitter interrupts are fully operational.

The MODEM Control Interrupts are also

operational but the interrupts' sources are now

the lower four bits of the MODEM Control

Bit 3

Framing Error (FE). Bit 3 indicates that the

received character did not have a valid stop bit.

Bit 3 is set to a logic "1" whenever the stop bit

following the last data bit or parity bit is detected

74

as a zero bit (Spacing level). The FE is reset to

a logic "0" whenever the Line Status Register is

read. In the FIFO mode this error is associated

with the particular character in the FIFO it

applies to. This error is indicated when the

associated character is at the top of the FIFO.

The Serial Port will try to resynchronize after a

framing error. To do this, it assumes that the

framing error was due to the next start bit, so it

samples this 'start' bit twice and then takes in

the 'data'.

Bit 5

Transmitter Holding Register Empty (THRE). Bit

5 indicates that the Serial Port is ready to accept

a new character for transmission. In addition,

this bit causes the Serial Port to issue an

interrupt when the Transmitter Holding Register

interrupt enable is set high. The THRE bit is set

to a logic "1" when a character is transferred

from the Transmitter Holding Register into the

Transmitter Shift Register. The bit is reset to

logic "0" whenever the CPU loads the

Transmitter Holding Register. In the FIFO mode

this bit is set when the XMIT FIFO is empty, it is

cleared when at least 1 byte is written to the

XMIT FIFO. Bit 5 is a read only bit.

Bit 4

Break Interrupt (BI). Bit 4 is set to a logic "1"

whenever the received data input is held in the

Spacing state (logic "0") for longer than a full

word transmission time (that is, the total time of

the start bit + data bits + parity bits + stop bits).

The BI is reset after the CPU reads the contents

of the Line Status Register. In the FIFO mode

this error is associated with the particular

character in the FIFO it applies to. This error is

indicated when the associated character is at

the top of the FIFO. When break occurs only

one zero character is loaded into the FIFO.

Restarting after a break is received, requires the

serial data (RXD) to be logic "1" for at least 1/2

bit time.

Bit 6

Transmitter Empty (TEMT). Bit 6 is set to a

logic "1" whenever the Transmitter Holding

Register (THR) and Transmitter Shift Register

(TSR) are both empty. It is reset to logic "0"

whenever either the THR or TSR contains a data

character. Bit 6 is a read only bit. In the FIFO

mode this bit is set whenever the THR and TSR

are both empty,

Bit 7

This bit is permanently set to logic "0" in the 450

mode. In the FIFO mode, this bit is set to a

logic "1" when there is at least one parity error,

framing error or break indication in the FIFO.

This bit is cleared when the LSR is read if there

are no subsequent errors in the FIFO.

Note:Bits 1 through 4 are the error conditions

that produce a Receiver Line Status Interrupt

whenever any of the corresponding conditions

are detected and the interrupt is enabled.

MODEM STATUS REGISTER (MSR)

Address Offset = 6H, DLAB = X, READ/WRITE

This 8 bit register provides the current state of

the control lines from the MODEM (or peripheral

device).

In addition to this current state

information, four bits of the MODEM Status

Register (MSR) provide change information.

These bits are set to logic "1" whenever a

control input from the MODEM changes state.

They are reset to logic "0" whenever the

MODEM Status Register is read.

75

Detect (nDCD) input. If bit 4 of the MCR is set

to logic "1", this bit is equivalent to OUT2 in the

MCR.

Bit 0

Delta Clear To Send (DCTS). Bit 0 indicates

that the nCTS input to the chip has changed

state since the last time the MSR was read.

Bit 1

SCRATCHPAD REGISTER (SCR)

Delta Data Set Ready (DDSR). Bit 1 indicates

that the nDSR input has changed state since the

last time the MSR was read.

Bit 2

Trailing Edge of Ring Indicator (TERI). Bit 2

indicates that the nRI input has changed from

logic "0" to logic "1".

Address Offset =7H, DLAB =X, READ/WRITE

This 8 bit read/write register has no effect on the

operation of the Serial Port. It is intended as a

scratchpad register to be used by the

programmer to hold data temporarily.

PROGRAMMABLE BAUD RATE GENERATOR

(AND DIVISOR LATCHES DLH, DLL)

Bit 3

Delta Data Carrier Detect (DDCD).

indicates that the nDCD input to the chip has

changed state.

Bit 3

The Serial Port contains a programmable Baud

Rate Generator that is capable of taking any

clock input (DC to 3 MHz) and dividing it by any

divisor from 1 to 65535. This output frequency

of the Baud Rate Generator is 16x the Baud

rate. Two 8 bit latches store the divisor in 16 bit

binary format. These Divisor Latches must be

loaded during initialization in order to insure

desired operation of the Baud Rate Generator.

Upon loading either of the Divisor Latches, a 16

bit Baud counter is immediately loaded. This

prevents long counts on initial load. If a 0 is

loaded into the BRG registers the output divides

the clock by the number 3. If a 1 is loaded the

output is the inverse of the input oscillator. If a

two is loaded the output is a divide by 2 signal

with a 50% duty cycle. If a 3 or greater is

loaded the output is low for 2 bits and high for

the remainder of the count. The input clock to

the BRG is a 1.8462 MHz clock.

NOTE: Whenever bit 0, 1, 2, or 3 is set to a

logic "1",

generated.

Bit 4

a

MODEM Status Interrupt is

This bit is the complement of the Clear To Send

(nCTS) input. If bit 4 of the MCR is set to logic

"1", this bit is equivalent to nRTS in the MCR.

Bit 5

This bit is the complement of the Data Set

Ready (nDSR) input. If bit 4 of the MCR is set

to logic "1", this bit is equivalent to DTR in the

MCR.

Bit 6

This bit is the complement of the Ring Indicator

(nRI) input. If bit 4 of the MCR is set to logic

"1", this bit is equivalent to OUT1 in the MCR.

Bit 7

Table 33 shows the baud rates possible with a

1.8462 MHz crystal.

This bit is the complement of the Data Carrier

Effect Of The Reset on Register File

The Reset Function Table (Table 34) details the

effect of the Reset input on each of the registers

of the Serial Port.

76

B. Character times are calculated by using the

RCLK input for a clock signal (this makes

the delay proportional to the baudrate).

FIFO INTERRUPT MODE OPERATION

When the RCVR FIFO and receiver interrupts

are enabled (FCR bit 0 = "1", IER bit 0 = "1"),

RCVR interrupts occur as follows:

C. When a timeout interrupt has occurred it is

cleared and the timer reset when the CPU

reads one character from the RCVR FIFO.

A. The receive data available interrupt will be

issued when the FIFO has reached its

programmed trigger level; it is cleared as

soon as the FIFO drops below its

programmed trigger level.

D. When a timeout interrupt has not occurred

the timeout timer is reset after a new

character is received or after the CPU reads

the RCVR FIFO.

B. The IIR receive data available indication also

occurs when the FIFO trigger level is

reached. It is cleared when the FIFO drops

below the trigger level.

When the XMIT FIFO and transmitter interrupts

are enabled (FCR bit 0 = "1", IER bit 1 = "1"),

XMIT interrupts occur as follows:

A. The transmitter holding register interrupt

(02H) occurs when the XMIT FIFO is empty;

it is cleared as soon as the transmitter

holding register is written to (1 of 16

characters may be written to the XMIT FIFO

while servicing this interrupt) or the IIR is

read.

C. The receiver line status interrupt (IIR=06H),

has higher priority than the received data

available (IIR=04H) interrupt.

D. The data ready bit (LSR bit 0)is set as soon

as a character is transferred from the shift

register to the RCVR FIFO. It is reset when

the FIFO is empty.

B. The transmitter FIFO empty indications will

be delayed 1 character time minus the last

stop bit time whenever the following occurs:

THRE=1 and there have not been at least

two bytes at the same time in the transmitter

When RCVR FIFO and receiver interrupts are

enabled, RCVR FIFO timeout interrupts occur

as follows:

FIFO since the last THRE=1.

transmitter interrupt after changing FCR0

will be immediate, if it is enabled.

The

A. A FIFO timeout interrupt occurs if all the

following conditions exist:

-at least one character is in the FIFO

-The most recent serial character received was

longer than 4 continuous character times

ago. (If 2 stop bits are programmed, the

second one is included in this time delay.)

-The most recent CPU read of the FIFO was

longer than 4 continuous character times

ago.

Character timeout and RCVR FIFO trigger level

interrupts have the same priority as the current

received data available interrupt; XMIT FIFO

empty has the same priority as the current

transmitter holding register empty interrupt.

FIFO POLLED MODE OPERATION

This will cause a maximum character received

to interrupt issued delay of 160 msec at 300

BAUD with a 12 bit character.

With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or

3 or all to zero puts the UART in the FIFO

Polled Mode of operation. Since the RCVR and

XMITTER are controlled separately, either one

or both can be in the polled mode of operation.

77

the same way as when in the interrupt

mode, the IIR is not affected since EIR bit

2=0.

-Bit 5 indicates when the XMIT FIFO is empty.

-Bit 6 indicates that both the XMIT FIFO and

shift register are empty.

In this mode, the user's program will check

RCVR and XMITTER status via the LSR. LSR

definitions for the FIFO Polled Mode are as

follows:

-Bit 0=1 as long as there is one byte in the

RCVR FIFO.

-Bit 7 indicates whether there are any errors in

the RCVR FIFO.

-Bits 1 to 4 specify which error(s) have occurred.

Character error status is handled

There is no trigger level reached or timeout

condition indicated in the FIFO Polled Mode,

however, the RCVR and XMIT FIFOs are still

fully capable of holding characters.

Table 33 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock

for 115.2k ; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k

DESIRED

BAUD RATE

DIVISOR USED TO

GENERATE 16X CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL*

CRxx:

BIT 7 OR 6

50

75

2304

1536

1047

857

768

384

192

96

0.001

X

1

-

110

-

134.5

150

0.004

-

300

-

600

-

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

57600

115200

230400

460800

-

64

-

58

0.005

48

-

32

-

24

16

-

12

-

6

-

3

0.030

0.16

2

1

32770

32769

1

*Note: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.

78

Table 34 - Reset Function Table

RESET CONTROL

REGISTER/SIGNAL

Interrupt Enable Register

Interrupt Identification Reg.

FIFO Control

RESET STATE

RESET

All bits low

RESET

Bit 0 is high; Bits 1 - 7 low

RESET

All bits low

Line Control Reg.

RESET

All bits low

MODEM Control Reg.

Line Status Reg.

RESET

All bits low

RESET

All bits low except 5, 6 high

MODEM Status Reg.

TXD1, TXD2

RESET

Bits 0 - 3 low; Bits 4 - 7 input

RESET

High

INTRPT (RCVR errs)

RESET/Read LSR

Low

INTRPT (RCVR Data Ready) RESET/Read RBR

Low

INTRPT (THRE)

OUT2B

RESET/ReadIIR/Write THR

Low

RESET

High

RTSB

High

DTRB

High

OUT1B

High

RCVR FIFO

RESET/

All Bits Low

FCR1*FCR0/_FCR0

XMIT FIFO

RESET/

All Bits Low

FCR1*FCR0/_FCR0

79

Table 35 - Register Summary for an Individual UART Channel

REGISTER

ADDRESS*

REGISTER NAME

SYMBOL

BIT 0

BIT 1

ADDR = 0

DLAB = 0

Receive Buffer Register (Read Only)

RBR

Data Bit 0

(Note 1)

Data Bit 1

ADDR = 0

DLAB = 0

Transmitter Holding Register (Write Only)

Interrupt Enable Register

THR

IER

Data Bit 0

Data Bit 1

Enable

ADDR = 1

DLAB = 0

Enable

Received Data Transmitter

Available

Interrupt

(ERDAI)

Holding

Register

Empty

Interrupt

(ETHREI)

ADDR = 2

ADDR = 3

Interrupt Ident. Register (Read Only)

FIFO Control Register (Write Only)

Line Control Register

IIR

"0" if Interrupt Interrupt ID Bit

Pending

FCR

LCR

FIFO Enable

RCVR FIFO

Reset

Word Length

Select Bit 0

(WLS0)

Word Length

Select Bit 1

(WLS1)

ADDR = 4

ADDR = 5

MODEM Control Register

Line Status Register

MCR

LSR

Data Terminal Request to

Ready (DTR) Send (RTS)

Data Ready

(DR)

Overrun Error

(OE)

ADDR = 6

ADDR = 7

MODEM Status Register

MSR

Delta Clear to Delta Data Set

Send (DCTS) Ready

(DDSR)

Scratch Register (Note 4)

Divisor Latch (LS)

SCR

DDL

DLM

Bit 0

Bit 8

Bit 1

Bit 9

ADDR = 0

DLAB = 1

ADDR = 1

DLAB = 1

Divisor Latch (MS)

*DLAB is Bit 7 of the Line Control Register (ADDR = 3).

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.

80

Table 35 - Register Summary for an Individual UART Channel (continued)

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bit 2

Data Bit 3

Data Bit 4

0

Data Bit 5

0

Data Bit 6

0

Data Bit 7

0

Enable Receiver Enable MODEM

Line Status Status Interrupt

Interrupt (ELSI) (EMSI)

Interrupt ID Bit

(Note 5)

0

FIFOs Enabled

(Note 5)

FIFOs Enabled

(Note 5)

XMIT FIFO

Reset

DMA Mode

Select (Note 6)

Reserved

RCVR Trigger

LSB

RCVR Trigger

MSB

Number of Stop Parity Enable

Even Parity

Select (EPS)

Stick Parity

Set Break

Divisor Latch

Access Bit

(DLAB)

Bits (STB)

(PEN)

OUT1

OUT2

Loop

0

(Note 3)

Parity Error (PE) Framing Error

(FE)

Break Interrupt

(BI)

Transmitter

Holding Register Empty (TEMT)

(THRE) (Note 2)

Transmitter

Error in RCVR

FIFO (Note 5)

Trailing Edge

Ring Indicator

(TERI)

Delta Data

Carrier Detect

(DDCD)

Clear to Send

(CTS)

Data Set Ready Ring Indicator

Data Carrier

Detect (DCD)

(DSR)

(RI)

Bit 2

Bit 10

Bit 3

Bit 11

Bit 4

Bit 12

Bit 5

Bit 13

Bit 6

Bit 14

Bit 7

Bit 15

Note 3: This bit no longer has a pin associated with it.

Note 4: When operating in the XT mode, this register is not available.

Note 5: These bits are always zero in the non-FIFO mode.

Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.

81

NOTES ON SERIAL PORT OPERATION

FIFO MODE OPERATION:

the FIFO, concurrently. When interrupt will

be activated without a one character delay.

Rx support functions and operation are quite

different from those described for the

transmitter. The Rx FIFO receives data until the

number of bytes in the FIFO equals the selected

GENERAL

The RCVR FIFO will hold up to 16 bytes

regardless of which trigger level is selected.

interrupt trigger level.

At that time if Rx

interrupts are enabled, the UART will issue an

interrupt to the CPU. The Rx FIFO will continue

to store bytes until it holds 16 of them. It will

not accept any more data when it is full. Any

more data entering the Rx shift register will set

the Overrun Error flag. Normally, the FIFO

depth and the programmable trigger levels will

give the CPU ample time to empty the Rx FIFO

before an overrun occurs.

TX AND RX FIFO OPERATION

The Tx portion of the UART transmits data

through TXD as soon as the CPU loads a byte

into the Tx FIFO. The UART will prevent

loads to the Tx FIFO if it currently holds 16

characters. Loading to the Tx FIFO will again

be enabled as soon as the next character is

transferred to the Tx shift register. These

capabilities account for the largely autonomous

operation of the Tx.

One side-effect of having a Rx FIFO is that the

selected interrupt trigger level may be above the

data level in the FIFO. This could occur when

data at the end of the block contains fewer bytes

than the trigger level. No interrupt would be

issued to the CPU and the data would remain in

the UART. To prevent the software from

having to check for this situation the chip

incorporates a timeout interrupt.

The UART starts the above operations typically

with a Tx interrupt. The chip issues a Tx

interrupt whenever the Tx FIFO is empty and the

Tx interrupt is enabled, except in the following

instance. Assume that the Tx FIFO is empty

and the CPU starts to load it. When the first

byte enters the FIFO the Tx FIFO empty

interrupt will transition from active to inactive.

Depending on the execution speed of the service

routine software, the UART may be able to

transfer this byte from the FIFO to the shift

register before the CPU loads another byte. If

this happens, the Tx FIFO will be empty again

and typically the UART's interrupt line would

transition to the active state. This could cause a

system with an interrupt control unit to record a

Tx FIFO empty condition, even though the CPU

is currently servicing that interrupt. Therefore,

after the first byte has been loaded into the

FIFO the UART will wait one serial character

transmission time before issuing a new Tx

FIFO empty interrupt. This one character Tx

interrupt delay will remain active until at

least two bytes have the Tx FIFO empties

after this condition, the Tx been loaded into

The timeout interrupt is activated when there is

a least one byte in the Rx FIFO, and neither the

CPU nor the Rx shift register has accessed the

Rx FIFO within 4 character times of the last

byte. The timeout interrupt is cleared or reset

when the CPU reads the Rx FIFO or another

character enters it.

These FIFO related features allow optimization

of CPU/UART transactions and are especially

useful given the higer baud rate capability (256

kbaud).

82

INFRARED INTERFACE

The infrared interface provides a two-way

wireless communications port using infrared

as transmission medium. Two IR

implementations have been provided for the

second UART in this chip (logical device 5),

IrDA and Amplitude Shift Keyed IR. The IR

transmission can use the standard UART2 TX

and RX pins or optional IRTX2 and IRRX2

pins. These can be selected through the

configuration registers.

by sending a 500khz waveform for

the

duration of the serial bit time. A one is

signaled by sending no transmission the bit

time. Please refer to the AC timing for the

parameters of the ASK-IR waveform.

a

If the Half Duplex option is chosen, there is a

time-out when the direction of the

transmission is changed. This time-out starts

at the last bit transferred during a transmission

and blocks the receiver input until the timeout

expires. If the transmit buffer is loaded with

more data before the time-out expires, the

timer is restarted after the new byte is

transmitted. If data is loaded into the transmit

buffer while a character is being received, the

transmission will not start until the time-out

expires after the last receive bit has been

received. If the start bit of another character is

received during this time-out, the timer is

restarted after the new character is received.

The IR half duplex time-out is programmable

via CRF2 in Logical Device 5. This register

allows the time-out to be programmed to any

value between 0 and 10msec in 100usec

increments.

IrDA allows serial communication at baud

rates up to 115K Baud. Each word is sent

serially beginning with a zero value start bit. A

zero is signaled by sending a single IR pulse

at the beginning of the serial bit time. A one is

signaled by sending no IR pulse during the bit

time. Please refer to the AC timing for the

parameters of these pulses and the IrDA

waveform.

The Amplitude Shift Keyed IR allows serial

communication at baud rates up to 19.2K

Baud. Each word is sent serially beginning

with a zero value start bit. A zero is signaled

83

PARALLEL PORT

The parallel port also incorporates SMSC's

The FDC37C68x incorporates an IBM XT/AT

compatible parallel port. This supports the

optional PS/2 type bi-directional parallel port

(SPP), the Enhanced Parallel Port (EPP) and

the Extended Capabilities Port (ECP) parallel

ChiProtect circuitry, which prevents possible

damage to the parallel port due to printer power-

up.

The functionality of the Parallel Port is achieved

through the use of eight addressable ports,

with their associated registers and control

gating. The control and data port are read/write

by the CPU, the status port is read/write in the

EPP mode. The address map of the Parallel

Port is shown below:

port modes.

Refer to the Configuration

Registers for information on disabling, power

down, changing the base address of the parallel

port, and selecting the mode of operation.

The FDC37C68x also provides a mode for

support of the floppy disk controller on the

parallel port.

DATA PORT

BASE ADDRESS + 00H

BASE ADDRESS + 01H

BASE ADDRESS + 02H

BASE ADDRESS + 03H

EPP DATA PORT 0

EPP DATA PORT 1

EPP DATA PORT 2

EPP DATA PORT 3

BASE ADDRESS + 04H

BASE ADDRESS + 05H

BASE ADDRESS + 06H

BASE ADDRESS + 07H

STATUS PORT

CONTROL PORT

EPP ADDR PORT

The bit map of these registers is:

D0

D1

PD1

0

D2

PD2

0

D3

D4

D5

PD5

PE

D6

D7

PD7

Note

DATA PORT

PD0

PD3

PD4

PD6

1

STATUS

PORT

TMOUT

nERR

SLCT

nACK

nBUSY

CONTROL

PORT

STROBE AUTOFD

nINIT

PD2

SLC

PD3

IRQE

PD4

PCD

PD5

0

1

EPP ADDR

PORT

PD0

PD1

PD6

AD7

PD7

2,3

EPP DATA

PORT 0

EPP DATA

PORT 1

EPP DATA

PORT 2

EPP DATA

PORT 3

Note 1: These registers are available in all modes.

Note 2: These registers are only available in EPP mode.

Note 3 : For EPP mode, IOCHRDY must be connected to the ISA bus.

84

Table 36 - Parallel Port Connector

HOST

CONNECTOR

PIN NUMBER

STANDARD

nStrobe

EPP

ECP

1

nWrite

PData<0:7>

Intr

nStrobe

2-9

10

11

12

PData<0:7>

nAck

PData<0:7>

nAck

Busy

nWait

Busy, PeriphAck(3)

PE

(NU)

PError,

nAckReverse(3)

13

14

Select

(NU)

Select

nAutofd

nDatastb

nAutoFd,

HostAck(3)

15

16

17

nError

nInit

(NU)

nFault(1)

nPeriphRequest(3)

(NU)

nInit(1)

nReverseRqst(3)

nSelectin

nAddrstrb

nSelectIn(1,3)

(1) = Compatible Mode

(3) = High Speed Mode

Note:

For the cable interconnection required for ECP support and the Slave Connector pin

numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev.

1.14, July 14, 1993. This document is available from Microsoft.

85

BIT 3 nERR - nERROR

The level on the nERROR input is read by the

CPU as bit 3 of the Printer Status Register. A

logic 0 means an error has been detected; a

logic 1 means no error has been detected.

IBM XT/AT COMPATIBLE, BI-

DIRECTIONAL AND EPP MODES

DATA PORT

ADDRESS OFFSET = 00H

BIT 4 SLCT - PRINTER SELECTED STATUS

The level on the SLCT input is read by the CPU

as bit 4 of the Printer Status Register. A logic 1

means the printer is on line; a logic 0 means it is

not selected.

The Data Port is located at an offset of '00H'

from the base address. The data register is

cleared at initialization by RESET. During a

WRITE operation, the Data Register latches the

contents of the data bus with the rising edge of

the nIOW input. The contents of this register

are buffered (non inverting) and output onto the

PD0 - PD7 ports. During a READ operation in

SPP mode, PD0 - PD7 ports are buffered (not

latched) and output to the host CPU.

BIT 5 PE - PAPER END

The level on the PE input is read by the CPU as

bit 5 of the Printer Status Register. A logic 1

indicates a paper end; a logic 0 indicates the

presence of paper.

BIT 6 nACK - nACKNOWLEDGE

STATUS PORT

ADDRESS OFFSET = 01H

The level on the nACK input is read by the CPU

as bit 6 of the Printer Status Register. A logic 0

means that the printer has received a character

and can now accept another. A logic 1 means

that it is still processing the last character or has

not received the data.

The Status Port is located at an offset of '01H'

from the base address. The contents of this

register are latched for the duration of an nIOR

read cycle. The bits of the Status Port are

defined as follows:

BIT 7 nBUSY - nBUSY

The complement of the level on the BUSY input

is read by the CPU as bit 7 of the Printer Status

Register. A logic 0 in this bit means that the

printer is busy and cannot accept a new

character. A logic 1 means that it is ready to

accept the next character.

BIT 0 TMOUT - TIME OUT

This bit is valid in EPP mode only and indicates

that a 10 usec time out has occured on the EPP

bus. A logic O means that no time out error has

occured; a logic 1 means that a time out error

has been detected. This bit is cleared by a

RESET. Writing a one to this bit clears the time

out status bit. On a write, this bit is self clearing

and does not require a write of a zero. Writing a

zero to this bit has no effect.

CONTROL PORT

ADDRESS OFFSET = 02H

The Control Port is located at an offset of '02H'

from the base address. The Control Register is

initialized by the RESET input, bits 0 to 5 only

being affected; bits 6 and 7 are hard wired low.

BITS 1, 2 - are not implemented as register bits,

during a read of the Printer Status Register

these bits are a low level.

86

register is cleared at initialization by RESET.

During a WRITE operation, the contents of DB0-

DB7 are buffered (non inverting) and output onto

the PD0 - PD7 ports, the leading edge of nIOW

causes an EPP ADDRESS WRITE cycle to be

performed, the trailing edge of IOW latches the

data for the duration of the EPP write cycle.

During a READ operation, PD0 - PD7 ports are

read, the leading edge of IOR causes an EPP

ADDRESS READ cycle to be performed and the

data output to the host CPU, the deassertion of

ADDRSTB latches the PData for the duration of

the IOR cycle. This register is only available in

EPP mode.

BIT 0 STROBE - STROBE

This bit is inverted and output onto the

nSTROBE output.

BIT 1 AUTOFD - AUTOFEED

This bit is inverted and output onto the

nAUTOFD output. A logic 1 causes the printer

to generate a line feed after each line is printed.

A logic 0 means no autofeed.

BIT 2 nINIT - nINITIATE OUTPUT

This bit is output onto the nINIT output without

inversion.

BIT 3 SLCTIN - PRINTER SELECT INPUT

This bit is inverted and output onto the nSLCTIN

output. A logic 1 on this bit selects the printer; a

logic 0 means the printer is not selected.

EPP DATA PORT 0

ADDRESS OFFSET = 04H

The EPP Data Port 0 is located at an offset of

'04H' from the base address. The data register

is cleared at initialization by RESET. During a

WRITE operation, the contents of DB0-DB7 are

buffered (non inverting) and output onto the PD0

- PD7 ports, the leading edge of nIOW causes

an EPP DATA WRITE cycle to be performed,

the trailing edge of IOW latches the data for the

duration of the EPP write cycle. During a READ

operation, PD0 - PD7 ports are read, the leading

edge of IOR causes an EPP READ cycle to be

performed and the data output to the host CPU,

the deassertion of DATASTB latches the PData

for the duration of the IOR cycle. This register

is only available in EPP mode.

BIT 4 IRQE - INTERRUPT REQUEST ENABLE

The interrupt request enable bit when set to a

high level may be used to enable interrupt

requests from the Parallel Port to the CPU. An

interrupt request is generated on the IRQ port by

a positive going nACK input. When the IRQE

bit is programmed low the IRQ is disabled.

BIT

5

PCD

-

PARALLEL CONTROL

DIRECTION

Parallel Control Direction is not valid in printer

mode. In printer mode, the direction is always

out regardless of the state of this bit. In bi-

directional, EPP or ECP mode, a logic 0 means

that the printer port is in output mode (write); a

logic 1 means that the printer port is in input

mode (read).

EPP DATA PORT 1

ADDRESS OFFSET = 05H

The EPP Data Port 1 is located at an offset of

'05H' from the base address. Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

EPP DATA PORT 2

Bits 6 and 7 during a read are a low level, and

cannot be written.

EPP ADDRESS PORT

ADDRESS OFFSET = 03H

ADDRESS OFFSET = 06H

The EPP Address Port is located at an offset of

'03H' from the base address. The address

The EPP Data Port 2 is located at an offset of

'06H' from the base address. Refer to EPP

87

EPP DATA PORT 2

Software Constraints

ADDRESS OFFSET = 06H

Before an EPP cycle is executed, the software

must ensure that the control register bit PCD is

a logic "0" (ie a 04H or 05H should be written to

the Control port). If the user leaves PCD as a

logic "1", and attempts to perform an EPP write,

the chip is unable to perform the write (because

PCD is a logic "1") and will appear to perform an

EPP read on the parallel bus, no error is

indicated.

The EPP Data Port 2 is located at an offset of

'06H' from the base address. Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

EPP DATA PORT 3

ADDRESS OFFSET = 07H

The EPP Data Port 3 is located at an offset of

'07H' from the base address. Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

EPP 1.9 Write

The timing for a write operation (address or

data) is shown in timing diagram EPP Write

Data or Address cycle. IOCHRDY is driven

active low at the start of each EPP write and is

released when it has been determined that the

write cycle can complete. The write cycle can

complete under the following circumstances:

EPP 1.9 OPERATION

When the EPP mode is selected in the

configuration register, the standard and bi-

directional modes are also available. If no EPP

Read, Write or Address cycle is currently

executing, then the PDx bus is in the standard or

bi-directional mode, and all output signals

(STROBE, AUTOFD, INIT) are as set by the

SPP Control Port and direction is controlled by

PCD of the Control port.

1. If the EPP bus is not ready (nWAIT is active

low) when nDATASTB or nADDRSTB goes

active then the write can complete when

nWAIT goes inactive high.

2. If the EPP bus is ready (nWAIT is inactive

high) then the chip must wait for it to go

active low before changing the state of

nDATASTB, nWRITE or nADDRSTB. The

write can complete once nWAIT is

determined inactive.

In EPP mode, the system timing is closely

coupled to the EPP timing. For this reason, a

watchdog timer is required to prevent system

lockup. The timer indicates if more than 10usec

have elapsed from the start of the EPP cycle

(nIOR or nIOW asserted) to nWAIT being

deasserted (after command). If a time-out

occurs, the current EPP cycle is aborted and the

time-out condition is indicated in Status bit 0.

Write Sequence of operation

1. The host selects an EPP register, places

data on the SData bus and drives nIOW

active.

2. The chip drives IOCHRDY inactive (low).

3. If WAIT is not asserted, the chip must wait

until WAIT is asserted.

During an EPP cycle, if STROBE is active, it

overrides the EPP write signal forcing the PDx

bus to always be in a write mode and the

nWRITE signal to always be asserted.

4. The chip places address or data on PData

bus and asserts nWRITE.

88

5. Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus contains valid

information, and the WRITE signal is valid.

6. Peripheral deasserts nWAIT, indicating that

any setup requirements have been satisfied

and the chip may begin the termination

phase of the cycle.

Read Sequence of Operation

1. The host selects an EPP register and drives

nIOR active.

2. The chip drives IOCHRDY inactive (low).

3. If WAIT is not asserted, the chip must wait

until WAIT is asserted.

7. a) The chip deasserts nDATASTB or

nADDRSTRB, this marks the beginning

of the termination phase. If it has not

already done so, the peripheral should

latch the information byte now.

4. The chip tri-states the PData bus and

deasserts nWRITE.

5. Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus is tri-stated and

the nWRITE signal is valid.

b) The chip latches the data from the

SData bus for the PData bus and

asserts (releases) IOCHRDY allowing

the host to complete the write cycle.

6. Peripheral drives PData bus valid.

7. Peripheral deasserts nWAIT, indicating that

PData is valid and the chip may begin the

termination phase of the cycle.

8. Peripheral asserts nWAIT, indicating to the

host that any hold time requirements have

been satisfied and acknowledging the

termination of the cycle.

9. Chip may modify nWRITE and nPDATA in

preparation for the next cycle.

8. a) The chip latches the data from the

PData bus for the SData bus and

deasserts nDATASTB or nADDRSTRB.

This marks the beginning of the

termination phase.

b) The chip drives the valid data onto the

SData bus and asserts (releases)

IOCHRDY allowing the host to

complete the read cycle.

EPP 1.9 Read

9. Peripheral tri-states the PData bus and

asserts nWAIT, indicating to the host that

the PData bus is tri-stated.

10. Chip may modify nWRITE and nPDATA in

preparation for the next cycle.

The timing for a read operation (data) is shown

in timing diagram EPP Read Data cycle.

IOCHRDY is driven active low at the start of

each EPP read and is released when it has been

determined that the read cycle can complete.

The read cycle can complete under the following

circumstances:

EPP 1.7 OPERATION

1

If the EPP bus is not ready (nWAIT is active

low) when nDATASTB goes active then the

read can complete when nWAIT goes

inactive high.

When the EPP 1.7 mode is selected in the

configuration register, the standard and bi-

directional modes are also available. If no EPP

Read, Write or Address cycle is currently

executing, then the PDx bus is in the standard or

bi-directional mode, and all output signals

(STROBE, AUTOFD, INIT) are as set by the

SPP Control Port and direction is controlled by

PCD of the Control port.

2. If the EPP bus is ready (nWAIT is inactive

high) then the chip must wait for it to go

active low before changing the state of

WRITE or before nDATASTB goes active.

The read can complete once nWAIT is

determined inactive.

89

In EPP mode, the system timing is closely

coupled to the EPP timing. For this reason, a

watchdog timer is required to prevent system

lockup. The timer indicates if more than 10usec

have elapsed from the start of the EPP cycle

(nIOR or nIOW asserted) to the end of the cycle

5. If nWAIT is asserted, IOCHRDY is

deasserted until the peripheral deasserts

nWAIT or a time-out occurs.

6. When the host deasserts nIOW the chip

deasserts nDATASTB or nADDRSTRB and

latches the data from the SData bus for the

PData bus.

nIOR or nIOW deasserted).

If a time-out

occurs, the current EPP cycle is aborted and the

time-out condition is indicated in Status bit 0.

7. Chip may modify nWRITE and nPDATA in

preparation of the next cycle.

Software Constraints

EPP 1.7 Read

Before an EPP cycle is executed, the software

must ensure that the control register bits D0, D1

and D3 are set to zero. Also, bit D5 (PCD) is a

logic "0" for an EPP write or a logic "1" for and

EPP read.

The timing for a read operation (data) is shown

in timing diagram EPP 1.7 Read Data cycle.

IOCHRDY is driven active low when nWAIT is

active low during the EPP cycle. This can be

used to extend the cycle time. The read cycle

can complete when nWAIT is inactive high.

EPP 1.7 Write

Read Sequence of Operation

The timing for a write operation (address or

data) is shown in timing diagram EPP 1.7 Write

Data or Address cycle. IOCHRDY is driven

active low when nWAIT is active low during the

EPP cycle. This can be used to extend the cycle

1. The host sets PDIR bit in the control

register to a logic "1". This deasserts

nWRITE and tri-states the PData bus.

2. The host selects an EPP register and drives

nIOR active.

time.

The write cycle can complete when

3. Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus is tri-stated and

the nWRITE signal is valid.

nWAIT is inactive high.

Write Sequence of Operation

4. If nWAIT is asserted, IOCHRDY is

deasserted until the peripheral deasserts

nWAIT or a time-out occurs.

5. The Peripheral drives PData bus valid.

6. The Peripheral deasserts nWAIT, indicating

that PData is valid and the chip may begin

the termination phase of the cycle.

1. The host sets PDIR bit in the control

register to a logic "0".

nWRITE.

This asserts

2. The host selects an EPP register, places

data on the SData bus and drives nIOW

active.

7. When the host deasserts nIOR the chip

deasserts nDATASTB or nADDRSTRB.

8. Peripheral tri-states the PData bus.

9. Chip may modify nWRITE and nPDATA in

preparation of the next cycle.

3. The chip places address or data on PData

bus.

4. Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus contains valid

information, and the WRITE signal is valid.

90

Table 37 - EPP Pin Descriptions

EPP

SIGNAL

EPP NAME

nWrite

TYPE

EPP DESCRIPTION

This signal is active low. It denotes a write operation.

nWRITE

PD<0:7>

INTR

O

Address/Data

Interrupt

I/O

I

Bi-directional EPP byte wide address and data bus.

This signal is active high and positive edge triggered. (Pass

through with no inversion, Same as SPP.)

WAIT

nWait

I

This signal is active low. It is driven inactive as a positive

acknowledgement from the device that the transfer of data

is completed. It is driven active as an indication that the

device is ready for the next transfer.

DATASTB nData Strobe

RESET nReset

O

This signal is active low. It is used to denote data read or

write operation.

This signal is active low.

When driven active, the EPP

device is reset to its initial operational mode.

ADDRSTB nAddress

Strobe

This signal is active low. It is used to denote address read

or write operation.

PE

Paper End

I

Same as SPP mode.

SLCT

Printer

Selected

Status

nERR

Error

I

Same as SPP mode.

Note 1: SPP and EPP can use 1 common register.

Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP

cycle. For correct EPP read cycles, PCD is required to be a low.

91

reverse: Peripheral to Host communication

Pword: A port word; equal in size to

the width of the ISA

interface. For this implementation, PWord

is always 8 bits.

EXTENDED CAPABILITIES PARALLEL

PORT

ECP provides a number of advantages, some of

which are listed below. The individual features

are explained in greater detail in the remainder

of this section.

1

0

A high level.

A low level.

These terms may be considered synonymous:

·

High performance half-duplex forward and

reverse channel

Interlocked handshake, for fast reliable

transfer

Optional single byte RLE compression for

improved throughput (64:1)

Channel addressing for low-cost peripherals

Maintains link and data layer separation

Permits the use of active output drivers

Permits the use of adaptive signal timing

Peer-to-peer capability

·

PeriphClk, nAck

HostAck, nAutoFd

PeriphAck, Busy

nPeriphRequest, nFault

nReverseRequest, nInit

nAckReverse, PError

Xflag, Select

ECPMode, nSelectln

HostClk, nStrobe

·

Reference Document: IEEE 1284 Extended

Capabilities Port Protocol and ISA Interface

Standard, Rev 1.14, July 14, 1993.

document is available from Microsoft.

Vocabulary

The following terms are used in this document:

This

assert: When a signal asserts it transitions to a

"true" state, when a signal deasserts it

transitions to a "false" state.

The bit map of the Extended Parallel Port

registers is shown in the table on the following

page.

forward: Host to Peripheral communication.

92

D7

PD7

D6

D5

D4

D3

D2

D1

D0

Note

data

PD6

PD5

PD4

PD3

PD2

PD1

PD0

ecpAFifo

dsr

Addr/RLE

nBusy

0

Address or RLE field

2

1

2

nAck

0

PError

Select

nFault

ackIntEn SelectIn

Parallel Port Data FIFO

ECP Data FIFO

0

dcr

Direction

nInit

autofd

strobe

cFifo

ecpDFifo

tFifo

Test FIFO

cnfgA

cnfgB

ecr

0

1

0

compress

intrValue

MODE

Parallel Port IRQ

nErrIntrEn dmaEn

Parallel Port DMA

serviceIntr full

empty

Note 1: These registers are available in all modes.

Note 2: All FIFOs use one common 16 byte FIFO.

Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration

Registers.

negotiation, rather it provides an automatic high

burst-bandwidth channel that supports DMA for

ECP in both the forward and reverse directions.

ISA IMPLEMENTATION STANDARD

This specification describes the standard ISA

interface to the Extended Capabilities Port

(ECP). All ISA devices supporting ECP must

meet the requirements contained in this section

or the port will not be supported by Microsoft.

For a description of the ECP Protocol, please

refer to the IEEE 1284 Extended Capabilities

Port Protocol and ISA Interface Standard, Rev.

1.14, July 14, 1993. This document is available

from Microsoft.

Small FIFOs are employed in both forward and

reverse directions to smooth data flow and

improve the maximum bandwidth requirement.

The size of the FIFO is 16 bytes deep. The port

supports an automatic handshake for the

standard parallel port to improve compatibility

mode transfer speed.

The port also supports run length encoded

(RLE) decompression (required) in hardware.

Compression is accomplished by counting

identical bytes and transmitting an RLE byte

that indicates how many times the next byte is

to be repeated. Decompression simply

intercepts the RLE byte and repeats the

following byte the specified number of times.

Hardware support for compression is optional.

Description

The port is software and hardware compatible

with existing parallel ports so that it may be

used as a standard LPT port if ECP is not

required. The port is designed to be simple and

requires a small number of gates to implement.

it

does

not

do

any

"protocol"

93

Table 38 - ECP Pin Descriptions

DESCRIPTION

NAME

nStrobe

TYPE

O

During write operations nStrobe registers data or address into the slave

on the asserting edge (handshakes with Busy).

PData 7:0

nAck

I/O

I

Contains address or data or RLE data.

Indicates valid data driven by the peripheral when asserted. This signal

handshakes with nAutoFd in reverse.

PeriphAck (Busy)

I

This signal deasserts to indicate that the peripheral can accept data.

This signal handshakes with nStrobe in the forward direction. In the

reverse direction this signal indicates whether the data lines contain

ECP command information or data. The peripheral uses this signal to

flow control in the forward direction. It is an "interlocked" handshake

with nStrobe. PeriphAck also provides command information in the

reverse direction.

PError

Used to acknowledge a change in the direction the transfer (asserted =

(nAckReverse)

forward).

nReverseRequest.

The peripheral drives this signal low to acknowledge

It is an "interlocked" handshake with

nReverseRequest. The host relies upon nAckReverse to determine

when it is permitted to drive the data bus.

Select

I

Indicates printer on line.

nAutoFd

O

Requests a byte of data from the peripheral when asserted,

(HostAck)

handshaking with nAck in the reverse direction. In the forward direction

this signal indicates whether the data lines contain ECP address or

data. The host drives this signal to flow control in the reverse direction.

It is an "interlocked" handshake with nAck. HostAck also provides

command information in the forward phase.

nFault

(nPeriphRequest)

I

Generates an error interrupt when asserted. This signal provides a

mechanism for peer-to-peer communication. This signal is valid only in

the forward direction. During ECP Mode the peripheral is permitted

(but not required) to drive this pin low to request a reverse transfer. The

request is merely a "hint" to the host; the host has ultimate control over

the transfer direction. This signal would be typically used to generate

an interrupt to the host CPU.

nInit

O

Sets the transfer direction (asserted = reverse, deasserted = forward).

This pin is driven low to place the channel in the reverse direction. The

peripheral is only allowed to drive the bi-directional data bus while in

ECP Mode and HostAck is low and nSelectIn is high.

nSelectIn

Always deasserted in ECP mode.

94

to avoid conflict with standard ISA devices. The

port is equivalent to a generic parallel port

interface and may be operated in that mode.

The port registers vary depending on the mode

field in the ecr. The table below lists these

dependencies. Operation of the devices in

modes other that those specified is undefined.

Register Definitions

The register definitions are based on the

standard IBM addresses for LPT. All of the

standard printer ports are supported.

additional registers attach to an upper bit

decode of the standard LPT port definition

The

Table 39 - ECP Register Definitions

ADDRESS (Note 1) ECP MODES

NAME

FUNCTION

Data Register

data

+000h R/W

+001h R/W

+002h R/W

+400h R/W

+400h R

000-001

011

All

ecpAFifo

dsr

ECP FIFO (Address)

Status Register

dcr

All

Control Register

cFifo

ecpDFifo

tFifo

010

011

110

111

All

Parallel Port Data FIFO

ECP FIFO (DATA)

Test FIFO

cnfgA

cnfgB

ecr

Configuration Register A

Configuration Register B

Extended Control Register

+401h R/W

+402h R/W

Note 1: These addresses are added to the parallel port base address as selected by configuration

register or jumpers.

Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.

Table 40 - Mode Descriptions

MODE

000

001

010

011

100

101

110

111

DESCRIPTION*

SPP mode

PS/2 Parallel Port mde

Parallel Port Data FIFO mode

ECP Parallel Port mode

EPP mode (If this option is enabled in the configuration registers)

(Reserved)

Test mode

Configuration mode

*Refer to ECR Register Description

95

DATA and ecpAFifo PORT

ADDRESS OFFSET = 00H

BIT 5 PError

The level on the PError input is read by the CPU

as bit 5 of the Device Status Register. Printer

Status Register.

Modes 000 and 001 (Data Port)

BIT 6 nAck

The Data Port is located at an offset of '00H'

from the base address. The data register is

cleared at initialization by RESET. During a

WRITE operation, the Data Register latches the

contents of the data bus on the rising edge of

the nIOW input. The contents of this register

are buffered (non inverting) and output onto the

PD0 - PD7 ports. During a READ operation,

PD0 - PD7 ports are read and output to the host

CPU.

The level on the nAck input is read by the CPU

as bit 6 of the Device Status Register.

BIT 7 nBusy

The complement of the level on the BUSY input

is read by the CPU as bit 7 of the Device Status

Register.

DEVICE CONTROL REGISTER (dcr)

ADDRESS OFFSET = 02H

The Control Register is located at an offset of

'02H' from the base address. The Control

Register is initialized to zero by the RESET

input, bits 0 to 5 only being affected; bits 6 and

7 are hard wired low.

BIT 0 STROBE - STROBE

This bit is inverted and output onto the

nSTROBE output.

Mode 011 (ECP FIFO - Address/RLE)

A data byte written to this address is placed in

the FIFO and tagged as an ECP Address/RLE.

The hardware at the ECP port transmitts this

byte to the peripheral automatically.

The

operation of this register is ony defined for the

forward direction (direction is 0). Refer to the

ECP Parallel Port Forward Timing Diagram,

located in the Timing Diagrams section of this

data sheet .

BIT 1 AUTOFD - AUTOFEED

This bit is inverted and output onto the

nAUTOFD output. A logic 1 causes the printer

to generate a line feed after each line is printed.

A logic 0 means no autofeed.

BIT 2 nINIT - nINITIATE OUTPUT

This bit is output onto the nINIT output without

inversion.

DEVICE STATUS REGISTER (dsr)

ADDRESS OFFSET = 01H

The Status Port is located at an offset of '01H'

from the base address. Bits 0 - 2 are not

implemented as register bits, during a read of

the Printer Status Register these bits are a low

level. The bits of the Status Port are defined as

follows:

BIT 3 SELECTIN

This bit is inverted and output onto the nSLCTIN

output. A logic 1 on this bit selects the printer; a

logic 0 means the printer is not selected.

BIT 4 ackIntEn - INTERRUPT REQUEST

ENABLE

The interrupt request enable bit when set to a

high level may be used to enable interrupt

requests from the Parallel Port to the CPU due

to a low to high transition on the nACK input.

Refer to the description of the interrupt under

Operation, Interrupts.

BIT 3 nFault

The level on the nFault input is read by the CPU

as bit 3 of the Device Status Register.

BIT 4 Select

The level on the Select input is read by the CPU

as bit 4 of the Device Status Register.

96

tFIFO may be displayed on the parallel port data

lines.

BIT 5 DIRECTION

If mode=000 or mode=010, this bit has no effect

and the direction is always out regardless of the

state of this bit. In all other modes, Direction is

valid and a logic 0 means that the printer port is

in output mode (write); a logic 1 means that the

printer port is in input mode (read).

The tFIFO will not stall when overwritten or

underrun. If an attempt is made to write data to

a full tFIFO, the new data is not accepted into

the tFIFO. If an attempt is made to read data

from an empty tFIFO, the last data byte is re-

read again. The full and empty bits must

always keep track of the correct FIFO state.

The tFIFO will transfer data at the maximum

ISA rate so that software may generate

performance metrics.

BITS 6 and 7 during a read are a low level, and

cannot be written.

cFifo (Parallel Port Data FIFO)

ADDRESS OFFSET = 400h

Mode = 010

The FIFO size and interrupt threshold can be

determined by writing bytes to the FIFO and

checking the full and serviceIntr bits.

Bytes written or DMAed from the system to this

FIFO are transmitted by a hardware handshake

to the peripheral using the standard parallel port

protocol.

Transfers to the FIFO are byte

The writeIntrThreshold can be derermined by

starting with a full tFIFO, setting the direction bit

to 0 and emptying it a byte at a time until

serviceIntr is set. This may generate a spurious

interrupt, but will indicate that the threshold has

been reached.

aligned. This mode is only defined for the

forward direction.

ecpDFifo (ECP Data FIFO)

ADDRESS OFFSET = 400H

Mode = 011

The readIntrThreshold can be derermined by

setting the direction bit to 1 and filling the empty

tFIFO a byte at a time until serviceIntr is set.

This may generate a spurious interrupt, but will

indicate that the threshold has been reached.

Bytes written or DMAed from the system to this

FIFO, when the direction bit is 0, are transmitted

by a hardware handshake to the peripheral

using the ECP parallel port protocol. Transfers

to the FIFO are byte aligned.

Data bytes are always read from the head of

tFIFO regardless of the value of the direction bit.

For example if 44h, 33h, 22h is written to the

FIFO, then reading the tFIFO will return 44h,

33h, 22h in the same order as was written.

cnfgA (Configuration Register A)

Data bytes from the peripheral are read under

automatic hardware handshake from ECP into

this FIFO when the direction bit is 1. Reads or

DMAs from the FIFO will return bytes of ECP

data to the system.

ADDRESS OFFSET = 400H

Mode = 111

tFifo (Test FIFO Mode)

ADDRESS OFFSET = 400H

Mode = 110

This register is a read only register. When read,

10H is returned. This indicates to the system

that this is an 8-bit implementation. (PWord = 1

byte)

Data bytes may be read, written or DMAed to or

from the system to this FIFO in any direction.

Data in the tFIFO will not be transmitted to the

to the parallel port lines using a hardware

protocol handshake.

However, data in the

cnfgB (Configuration Register B)

97

ADDRESS OFFSET = 401H

Mode = 111

BIT 3 dmaEn

Read/Write

1: Enables DMA (DMA starts when serviceIntr

is 0).

0: Disables DMA unconditionally.

BIT 2 serviceIntr

Read/Write

BIT 7 compress

This bit is read only. During a read it is a low

level. This means that this chip does not

support hardware RLE compression. It does

support hardware de-compression!

BIT 6 intrValue

Returns the value on the ISA iRq line to

determine possible conflicts.

BITS [3:0] Parallel Port IRQ

Refer to Table 41B.

1: Disables DMA and all of the service

interrupts.

0: Enables one of the following 3 cases of

interrupts. Once one of the 3 service

interrupts has occurred serviceIntr bit shall

be set to a 1 by hardware. It must be reset

to 0 to re-enable the interrupts. Writing this

bit to a 1 will not cause an interrupt.

case dmaEn=1:

During DMA (this bit is set to a 1 when

terminal count is reached).

case dmaEn=0 direction=0:

This bit shall be set to 1 whenever there are

writeIntrThreshold or more bytes free in the

FIFO.

case dmaEn=0 direction=1:

This bit shall be set to 1 whenever there are

readIntrThreshold or more valid bytes to be

read from the FIFO.

BIT 1 full

Read only

BITS [2:0] Parallel Port DMA

Refer to Table 41C.

ecr (Extended Control Register)

ADDRESS OFFSET = 402H

Mode = all

This register controls the extended ECP parallel

port functions.

BITS 7,6,5

These bits are Read/Write and select the Mode.

BIT 4 nErrIntrEn

Read/Write (Valid only in ECP Mode)

1: Disables the interrupt generated on the

asserting edge of nFault.

0: Enables an interrupt pulse on the high to

low edge of nFault. Note that an interrupt

will be generated if nFault is asserted

(interrupting) and this bit is written from a 1

to a 0. This prevents interrupts from being

lost in the time between the read of the ecr

and the write of the ecr.

1: The FIFO cannot accept another byte or the

FIFO is completely full.

0: The FIFO has at least 1 free byte.

BIT 0 empty

Read only

1: The FIFO is completely empty.

0: The FIFO contains at least 1 byte of data.

98

Table 41A - Extended Control Register

MODE

R/W

000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers

are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction

bit will not tri-state the output drivers in this mode.

001: PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the

data lines and reading the data register returns the value on the data lines and not the

value in the data register. All drivers have active pull-ups (push-pull).

010: Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to

the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol.

Note that this mode is only useful when direction is 0. All drivers have active pull-ups

(push-pull).

011: ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the

ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted

automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1)

bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All

drivers have active pull-ups (push-pull).

100: Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in

configuration register L3-CRF0. All drivers have active pull-ups (push-pull).

101: Reserved

110: Test Mode. In this mode the FIFO may be written and read, but the data will not be

transmitted on the parallel port. All drivers have active pull-ups (push-pull).

111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and

0x401. All drivers have active pull-ups (push-pull).

Table 41B

CONFIG REG B

Table 41C

CONFIG REG B

IRQ SELECTED

BITS 5:3

BITS 2:0

DMA SELECTED

15

110

101

100

011

010

001

111

000

C

B

A

010

001

000

14

11

10

9

7

5

All Others

99

carried out under program control in mode

000.

OPERATION

Mode Switching/Software Control

After negotiation, it is necessary to initialize

some of the port bits. The following are

required:

Software will execute P1284 negotiation and

all operation prior to a data transfer phase

under programmed I/O control (mode 000 or

001). Hardware provides an automatic control

line handshake, moving data between the

FIFO and the ECP port only in the data

transfer phase (modes 011 or 010).

·

Set Direction = 0, enabling the drivers.

Set strobe = 0, causing the nStrobe

signal to default to the deasserted state.

Set autoFd = 0, causing the nAutoFd

signal to default to the deasserted state.

Set mode = 011 (ECP Mode)

·

Setting the mode to 011 or 010 will cause the

hardware to initiate data transfer.

ECP address/RLE bytes or data bytes may be

sent automatically by writing the ecpAFifo or

ecpDFifo respectively.

If the port is in mode 000 or 001 it may switch

to any other mode. If the port is not in mode

000 or 001 it can only be switched into mode

000 or 001. The direction can only be

changed in mode 001.

Note that all FIFO data transfers are byte wide

and byte aligned. Address/RLE transfers are

byte-wide and only allowed in the forward

direction.

Once in an extended forward mode the

software should wait for the FIFO to be empty

before switching back to mode 000 or 001. In

this case all control signals will be deasserted

before the mode switch. In an ecp reverse

mode the software waits for all the data to be

read from the FIFO before changing back to

The host may switch directions by first

switching to mode = 001, negotiating for the

forward or reverse channel, setting direction

to 1 or 0, then setting mode = 011. When

direction is 1 the hardware shall handshake

for each ECP read data byte and attempt to fill

the FIFO. Bytes may then be read from the

ecpDFifo as long as it is not empty.

mode 000 or 001.

Since the automatic

hardware ecp reverse handshake only cares

about the state of the FIFO it may have

acquired extra data which will be discarded. It

may in fact be in the middle of a transfer when

the mode is changed back to 000 or 001. In

this case the port will deassert nAutoFd

independent of the state of the transfer. The

design shall not cause glitches on the

handshake signals if the software meets the

constraints above.

ECP transfers may also be accomplished

(albeit slowly) by handshaking individual bytes

under program control in mode = 001, or 000.

Termination from ECP Mode

Termination from ECP Mode is similar to the

termination from Nibble/Byte Modes. The host

is permitted to terminate from ECP Mode only

in specific well-defined states. The termination

can only be executed while the bus is in the

forward direction. To terminate while the

channel is in the reverse direction, it must first

be transitioned into the forward direction.

ECP Operation

Prior to ECP operation the Host must

negotiate on the parallel port to determine if

the peripheral supports the ECP protocol.

This is a somewhat complex negotiation

100

When in the forward direction, normal data is

transferred when HostAck is high and an 8-bit

command is transferred when HostAck is

low.

Command/Data

ECP Mode supports two advanced features to

improve the effectiveness of the protocol for

some applications. The features are

implemented by allowing the transfer of

normal 8-bit data or 8-bit commands.

The most significant bit of the command

indicates whether it is a run-length count (for

compression) or a channel address.

When in the reverse direction, normal data is

transferred when PeriphAck is high and an

8-bit command is transferred when PeriphAck

is low. The most significant bit of the

command is always zero. Reverse channel

addresses are seldom used and may not be

supported in hardware.

101

Table 42

Forward Channel Commands (HostAck Low)

Reverse Channel Commands (PeripAck Low)

D7

D[6:0]

0

Run-Length Count (0-127)

(mode 0011 0X00 only)

1

Channel Address (0-127)

Data Compression

Pin Definition

The ECP port supports run length encoded

(RLE) decompression in hardware and can

transfer compressed data to a peripheral. Run

length encoded (RLE) compression in hardware

is not supported. To transfer compressed data

in ECP mode, the compression count is written

to the ecpAFifo and the data byte is written to

the ecpDFifo.

The drivers for nStrobe, nAutoFd, nInit and

nSelectIn are open-collector in mode 000 and

are push-pull in all other modes.

ISA Connections

The interface can never stall causing the host to

hang. The width of data transfers is strictly

controlled on an I/O address basis per this

specification. All FIFO-DMA transfers are byte

wide, byte aligned and end on a byte boundary.

(The PWord value can be obtained by reading

Configuration Register A, cnfgA, described in

the next section.) Single byte wide transfers

are always possible with standard or PS/2

mode using program control of the control

signals.

Compression is accomplished by counting

identical bytes and transmitting an RLE byte

that indicates how many times the next byte is

to be repeated.

Decompression simply

intercepts the RLE byte and repeats the

following byte the specified number of times.

When a run-length count is received from a

peripheral, the subsequent data byte is

replicated the specified number of times. A

run-length count of zero specifies that only one

byte of data is represented by the next data

byte, whereas a run-length count of 127

indicates that the next byte should be expanded

to 128 bytes. To prevent data expansion,

however, run-length counts of zero should be

avoided.

Interrupts

The interrupts are enabled by serviceIntr in the

ecr register.

serviceIntr = 1 Disables the DMA and all of the

service interrupts.

serviceIntr = 0 Enables the selected interrupt

condition. If the interrupting

condition is valid, then the

interrupt

is

generated

102

immediately when this bit is

changed from a 1 to a 0. This

can occur during Programmed

I/O if the number of bytes

removed or added from/to the

FIFO does not cross the

threshold.

FIFO Operation

The FIFO threshold is set in the chip

configuration registers. All data transfers to or

from the parallel port can proceed in DMA or

Programmed I/O (non-DMA) mode as indicated

by the selected mode. The FIFO is used by

selecting the Parallel Port FIFO mode or ECP

Parallel Port Mode. (FIFO test mode will be

addressed separately.) After a reset, the FIFO

is disabled. Each data byte is transferred by a

Programmed I/O cycle or PDRQ depending on

the selection of DMA or Programmed I/O mode.

The interrupt generated is ISA friendly in that it

must pulse the interrupt line low, allowing for

interrupt sharing.

After a brief pulse low

following the interrupt event, the interrupt line is

tri-stated so that other interrupts may assert.

An interrupt is generated when:

The following paragraphs detail the operation of

the FIFO flow control. In these descriptions,

1. For DMA transfers: When serviceIntr is 0,

dmaEn is 1 and the DMA TC is received.

<threshold> ranges from

parameter FIFOTHR, which the user programs,

is one less and ranges from 0 to 15.

1

to 16.

The

2. For Programmed I/O:

a.

When serviceIntr is 0, dmaEn is 0,

direction is and there are

writeIntrThreshold or more free bytes in

the FIFO. Also, an interrupt is

generated when serviceIntr is cleared

to whenever there are

A low threshold value (i.e. 2) results in longer

periods of time between service requests, but

requires faster servicing of the request for both

read and write cases. The host must be very

responsive to the service request. This is the

0

desired case for use with a "fast" system.

A

writeIntrThreshold or more free bytes in

the FIFO.

high value of threshold (i.e. 12) is used with a

"sluggish" system by affording a long latency

period after a service request, but results in

more frequent service requests.

b.(1)

When serviceIntr is 0, dmaEn is 0,

direction is 1 and there are

readIntrThreshold or more

bytes in the FIFO. Also, an

interrupt is generated when

DMA TRANSFERS

serviceIntr is cleared to

whenever there

readIntrThreshold or more

bytes in the FIFO.

0

are

DMA transfers are always to or from the

ecpDFifo, tFifo or CFifo. DMA utilizes the

standard PC DMA services. To use the DMA

transfers, the host first sets up the direction and

state as in the programmed I/O case. Then it

programs the DMA controller in the host with the

desired count and memory address. Lastly it

sets dmaEn to 1 and serviceIntr to 0. The ECP

requests DMA transfers from the host by

activating the PDRQ pin. The DMA will empty

or fill the FIFO using the appropriate direction

and mode. When the terminal count in the DMA

controller is reached, an interrupt is generated

3. When nErrIntrEn is 0 and nFault transitions

from high to low or when nErrIntrEn is set

from 1 to 0 and nFault is asserted.

4. When ackIntEn is 1 and the nAck signal

transitions from a low to a high.

103

and serviceIntr is asserted, disabling DMA. In

order to prevent possible blocking of refresh

requests dReq shall not be asserted for more

than 32 DMA cycles in a row. The FIFO is

enabled directly by asserting nPDACK and

addresses need not be valid. PINTR is

generated when a TC is received. PDRQ must

not be asserted for more than 32 DMA cycles in

a row. After the 32nd cycle, PDRQ must be

kept unasserted until nPDACK is deasserted for

a minimum of 350nsec. (Note: The only way to

properly terminate DMA transfers is with a TC.)

been re-enabled. (Note: A data underrun may

occur if PDRQ is not removed in time to prevent

an unwanted cycle.)

Programmed I/O Mode or Non-DMA Mode

The ECP or parallel port FIFOs may also be

operated using interrupt driven programmed I/O.

Software can determine the writeIntrThreshold,

readIntrThreshold, and FIFO depth by

accessing the FIFO in Test Mode.

Programmed I/O transfers are to the ecpDFifo

at 400H and ecpAFifo at 000H or from the

ecpDFifo located at 400H, or to/from the tFifo at

400H. To use the programmed I/O transfers,

the host first sets up the direction and state, sets

dmaEn to 0 and serviceIntr to 0.

The ECP requests programmed I/O transfers

from the host by activating the PINTR pin. The

programmed I/O will empty or fill the FIFO using

the appropriate direction and mode.

DMA may be disabled in the middle of a transfer

by first disabling the host DMA controller. Then

setting serviceIntr to 1, followed by setting

dmaEn to 0, and waiting for the FIFO to

become empty or full. Restarting the DMA is

accomplished by enabling DMA in the host,

setting dmaEn to 1, followed by setting

serviceIntr to 0.

DMA Mode - Transfers from the FIFO to the

Host

Note: A threshold of 16 is equivalent to a

threshold of 15. These two cases are treated

the same.

(Note: In the reverse mode, the peripheral may

not continue to fill the FIFO if it runs out of data

to transfer, even if the chip continues to request

more data from the peripheral.)

Programmed I/O - Transfers from the FIFO to

the Host

The ECP activates the PDRQ pin whenever

there is data in the FIFO. The DMA controller

must respond to the request by reading data

from the FIFO. The ECP will deactivate the

PDRQ pin when the FIFO becomes empty or

when the TC becomes true (qualified by

nPDACK), indicating that no more data is

required. PDRQ goes inactive after nPDACK

goes active for the last byte of a data transfer

(or on the active edge of nIOR, on the last byte,

if no edge is present on nPDACK). If PDRQ

goes inactive due to the FIFO going empty, then

PDRQ is active again as soon as there is one

byte in the FIFO. If PDRQ goes inactive due to

the TC, then PDRQ is active again when there

is one byte in the FIFO, and serviceIntr has

In the reverse direction an interrupt occurs when

serviceIntr is 0 and readIntrThreshold bytes

are available in the FIFO. If at this time the

FIFO is full it can be emptied completely in a

single burst, otherwise readIntrThreshold bytes

may be read from the FIFO in a single burst.

readIntrThreshold =(16-<threshold>) data bytes

in FIFO

An interrupt is generated when serviceIntr is 0

and the number of bytes in the FIFO is greater

than or equal to (16-<threshold>). (If the

threshold

= 12, then the interrupt is set

whenever there are 4-16 bytes in the FIFO). The

PINT pin can be used for interrupt-driven

104

systems. The host must respond to the request

by reading data from the FIFO. This process is

repeated until the last byte is transferred out of

the FIFO. If at this time the FIFO is full, it can

writeIntrThreshold = (16-<threshold>)

bytes in FIFO

free

An interrupt is generated when serviceIntr is 0

and the number of bytes in the FIFO is less than

or equal to <threshold>. (If the threshold = 12,

then the interrupt is set whenever there are 12 or

less bytes of data in the FIFO.) The PINT can

be used for interrupt-driven systems. The host

must respond to the request by writing data to

the FIFO. If at this time the FIFO is empty, it

can be completely filled in a single burst,

otherwise a minimum of (16-<threshold>) bytes

may be written to the FIFO in a single burst.

This process is repeated until the last byte is

transferred into the FIFO.

be completely emptied in

a single burst,

otherwise a minimum of (16-<threshold>) bytes

may be read from the FIFO in a single burst.

Programmed I/O - Transfers from the Host to

the FIFO

In the forward direction an interrupt occurs when

serviceIntr is 0 and there are writeIntrThreshold

or more bytes free in the FIFO. At this time if

the FIFO is empty it can be filled with a single

burst before the empty bit needs to be re-read.

Otherwise

it

may

be

filled

with

writeIntrThreshold bytes.

105

PARALLEL PORT FLOPPY DISK CONTROLLER

The following parallel port pins are read as

In this mode, the Floppy Disk Control signals

are available on the parallel port pins. When

this mode is selected, the parallel port is not

available. There are two modes of operation,

PPFD1 and PPFD2. These modes can be

selected in the Parallel Port Mode Register, as

defined in the Parallel Port Mode Register,

Logical Device 3, at 0xF1. PPFD1 has only

drive 1 on the parallel port pins; PPFD2 has

drive 0 and 1 on the parallel port pins.

follows by a read of the parallel port register:

1. Data Register (read) = last Data Register

(write)

2. Control Register read as "cable not

connected" STROBE, AUTOFD and

SLC = 0 and nINIT =1

3. Status Register reads: nBUSY = 0, PE =

0, SLCT = 0, nACK = 1, nERR = 1.

The following FDC pins are all in the high

impedence state when the PPFDC is actually

selected by the drive select register:

When the PPFDC is selected the following

pins are set as follows:

1. nPDACK: high-Z

1. nWDATA, DENSEL, nHDSEL, nWGATE,

nDIR, nSTEP, nDS1, nDS0, nMTR0,

nMTR1.

2. PDRQ: not ECP = high-Z, ECP & dmaEn

= 0, ECP & not dmaEn = high-Z

3. PINTR: not active, this is hi-Z or Low

depending on settings.

2. If PPFDx is selected, then the parallel port

can not be used as a parallel port until

"Normal" mode is selected.

Note:

nPDACK, PDRQ and PINTR refer to

the nDACK, DRQ and IRQ chosen

for the parallel port.

The FDC signals are muxed onto the Parallel

Port pins as shown in Table F1.

106

Table F1. FDC Parallel Port Pins

CHIP PIN # SPP MODE

FDC MODE

CONNECTOR

PIN #

PIN DIRECTION

1

2

112

106

105

104

103

102

101

100

99

nSTB

PD0

I/O

I

(nDS0)

nINDEX

nTRK0

I/(O) note1

I

3

PD1

I

4

PD2

nWP

I

5

PD3

nRDATA

nDSKCHG

nMEDIA_ID0

(nMTR0)

MEDIA_ID1

nDS1

I

6

PD4

I

7

PD5

I

8

PD6

I/(O) note1

9

PD7

I

10

11

12

13

14

15

16

17

97

nACK

BUSY

PE

O

96

I

nMTR1

95

I

nWDATA

nWGATE

DRVDEN0

nHDSEL

nDIR

94

SLCT

nALF

nERROR

nINIT

nSLCTIN

I

111

110

109

108

I/O

I

I/O

nSTEP

Note 1. These pins are outputs in mode PPFD2, inputs in mode PPFD1.

107

AUTO POWER MANAGEMENT

Power management capabilities are provided for

DSR From Powerdown

the following logical devices: floppy disk, UART

1, UART 2 and the parallel port. For each

logical device, two types of power management

are provided; direct powerdown and auto

powerdown.

If DSR powerdown is used when the part is in

auto powerdown, the DSR powerdown will

override the auto powerdown. However, when

the part is awakened from DSR powerdown, the

auto powerdown will once again become

effective.

FDC Power Management

Direct power management is controlled by

CR22. Refer to CR22 for more information.

Wake Up From Auto Powerdown

If the part enters the powerdown state through

the auto powerdown mode, then the part can be

awakened by reset or by appropriate access to

certain registers.

Auto Power Management is enabled by CR23-

B0. When set, this bit allows FDC to enter

powerdown when all of the following conditions

have been met:

If a hardware or software reset is used then the

part will go through the normal reset sequence.

If the access is through the selected registers,

then the FDC resumes operation as though it

was never in powerdown. Besides activating the

RESET pin or one of the software reset bits in

the DOR or DSR, the following register

accesses will wake up the part:

1. The motor enable pins of register 3F2H are

inactive (zero).

2. The part must be idle; MSR=80H and INT =

0 (INT may be high even if MSR = 80H due

to polling interrupts).

3. The head unload timer must have expired.

1. Enabling any one of the motor enable bits

in the DOR register (reading the DOR does

not awaken the part).

4. The Auto powerdown timer (10msec) must

have timed out.

An internal timer is initiated as soon as the auto

powerdown command is enabled. The part is

then powered down when all the conditions are

met.

2. A read from the MSR register.

3. A read or write to the Data register.

Once awake, the FDC will reinitiate the auto

powerdown timer for 10 ms. The part will

powerdown again when all the powerdown

conditions are satisfied.

Disabling the auto powerdown mode cancels the

timer and holds the FDC block out of auto

powerdown.

108

Register Behavior

Pin Behavior

Table 43 reiterates the AT and PS/2 (including

Model 30) configuration registers available. It

also shows the type of access permitted. In

order to maintain software transparency, access

to all the registers must be maintained. As

Table 43 shows, two sets of registers are

distinguished based on whether their access

results in the part remaining in powerdown state

or exiting it.

The FDC37C68x is specifically designed for

portable PC systems in which power

conservation is a primary concern. This makes

the behavior of the pins during powerdown very

important.

The pins of the FDC37C68x can be divided into

two major categories: system interface and

floppy disk drive interface. The floppy disk drive

pins are disabled so that no power will be drawn

through the part as a result of any voltage

applied to the pin within the part's power supply

range. Most of the system interface pins are left

active to monitor system accesses that may

wake up the part.

Access to all other registers is possible without

awakening the part. These registers can be

accessed during powerdown without changing

the status of the part. A read from these

registers will reflect the true status as shown in

the register description in the FDC description.

A write to the part will result in the part retaining

the data and subsequently reflecting it when the

System Interface Pins

part awakens.

Accessing the part during

Table 44 gives the state of the system interface

pins in the powerdown state. Pins unaffected by

the powerdown are labeled "Unchanged". Input

pins are "Disabled" to prevent them from

causing currents internal to the FDC37C68x

when they have indeterminate input values.

powerdown may cause an increase in the power

consumption by the part. The part will revert

back to its low power mode when the access

has been completed.

109

Table 43 - PC/AT and PS/2 Available Registers

Base + Address Available Registers Access Permitted

PC-AT PS/2 (Model 30)

Access to these registers DOES NOT wake up the part

00H

01H

02H

03H

04H

06H

07H

----

SRA

SRB

R

DOR (1)

---

DOR (1)

---

R/W

---

W

DSR (1)

---

DSR (1)

---

R

DIR

CCR

W

Access to these registers wakes up the part

04H

05H

MSR

Data

MSR

Data

R

R/W

Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor

enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part.

Table 44 - State of System Pins in Auto Powerdown

System Pins

State in Auto Powerdown

Input Pins

nIOR

nIOW

Unchanged

SA[0:15]

SD[0:7]

RESET_DRV

nDACKx

TC

AEN

Output Pins

SD[0:7]

DRQx

Unchanged

Unchanged (low)

Unchanged (n/a)

IOCHRDY

110

FDD Interface Pins

Pins used for local logic control or part

programming are unaffected. Table 45 depicts

the state of the floppy disk drive interface pins in

the powerdown state.

All pins in the FDD interface which can be

connected directly to the floppy disk drive itself

are either DISABLED or TRISTATED.

Table 45 - State of Floppy Disk Drive Interface Pins in Powerdown

FDD Pins

State in Auto Powerdown

Input Pins

nRDATA

nWPROT

nTRK0

Input

nINDEX

nDSKCHG

Output Pins

nMTR[0:1]

nDS[0:1]

nDIR

Tristated

Active

nSTEP

Active

nWDATA

nWGATE

nHDSEL

DRVDEN[0:1]

Tristated

Active

111

UART Power Management

Parallel Port

Direct power management is controlled by

CR22. Refer to CR22 for more information.

Direct power management is controlled by

CR22. Refer to CR22 for more information.

Auto Power Management is enabled by CR23-

B4 and B5. When set, these bits allow the

following auto power management operations:

Auto Power Management is enabled by CR23-

B3. When set, this bit allows the ECP or EPP

logical parallel port blocks to be placed into

powerdown when not being used.

1. The transmitter enters auto powerdown

when the transmit buffer and shift register

are empty.

The EPP logic is in powerdown under any of the

following conditions:

2. The receiver enters powerdown when the

following conditions are all met:

1. EPP is not enabled in the configuration

registers.

A. Receive FIFO is empty

B. The receiver is waiting for a start bit.

2. EPP is not selected through ecr while in

ECP mode.

Note:

While in powerdown the Ring Indicator

interrupt is still valid and transitions

when the RI input changes.

The ECP logic is in powerdown under any of the

following conditions:

1. ECP is not enabled in the configuration

registers.

Exit Auto Powerdown

2

SPP, PS/2 Parallel port or EPP mode is

selected through ecr while in ECP mode.

The transmitter exits powerdown on a write to

the XMIT buffer.

The receiver exits auto

powerdown when RXDx changes state.

Exit Auto Powerdown

The parallel port logic can change powerdown

modes when the ECP mode is changed through

the ecr register or when the parallel port mode is

changed through the configuration registers.

112

In 8042 mode, the pins can be programmed

as open drain. When programmed in open

drain mode, the port enables do not come into

play. If the port signal is 0 the output will be 0.

If the port signal is 1, the output tristates: an

external pull-up can pull the pin high, and the

pin can be shared i.e., P12 and nSMI can be

externally tied together. In 8042 mode, the

pins cannot be programmed as input nor

inverted through the GP configuration

registers.

8042 Functions

The second alternate function for pins 113-118

are the 8042 functions P12-P17. These are

implemented as in a true 8042 part. Reference

the 8042 spec for all timing. A port signal of 0

drives the output to 0. A port signal of 1

causes the port enable signal to drive the

output to 1 within 20-30nsec. After several (#

TBD) clocks, the port enable goes away and

the internal 90µA pull-up maintains the output

signal as 1.

113

GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION

The FDC37C68x provides a set of flexible

General Purpose I/O Ports

Input/Output control functions to the system

designer through a set of General Purpose I/O

pins (GPI/O). These GPI/O pins may perform

simple I/O or may be individually configured to

The

independently programmable general purpose

I/O ports (GPI/O). Each GPI/O port is

FDC37C68x

has

14

dedicated,

provide

a

predefined alternate function.

represented as a bit in one of two GPI/O 8-bit

registers, GP1 or GP2. Only 6 bits of GP2 are

implemented. Each GPI/O port and its alternate

function is listed in Table 46A.

Power-on reset configures all GPI/O pins as

simple non-inverting inputs.

Table 46A - General Purpose I/O Port Assignments

Number

Original

Function

Alternate

Function 1

Alternate Function

2

Alternate

Function 3

Register

Assignment

70

71

72

73

74

76

77

78

79

80

81

82

83

84

GP10

GP11

GP12

GP13

GP14

GP15

GP16

GP17

GP20

GP21

GP22

GP23

GP24

GP25

Interrupt Steering*

-

GP1, bit 0

GP1, bit 1

GP1, bit 2

GP1, bit 3

GP1, bit 4

GP1, bit 5

GP1, bit 6

GP1, bit 7

GP2, bit 0

GP2, bit 1

GP2, bit 2

GP2, bit 3

GP2, bit 4

GP2, bit 5

Interrupt Steering*

-

WD Timer Output

IRRX Input

Power LED

IRTX Output

GP Address Decoder

-

GP Write Strobe

-

Joystick RD Strobe

Joystick Chip Sel

Joystick WR Strobe

-

8042 P20

-

8042 P21

Note 1: 8042 P21 is normally used for Gate A20

Note 2: 8042 P20 is normally used for the Keyboard Reset Output

* These are input-type alternate functions; all other GP I/O pins contain output-type alternate

functions.

114

The FDC37C68x also has 13 GPI/O ports that are the first alternate functions of pins with other default

functions. These pins are listed in Table 46B below.

Table 46B - Multifunction GPI/O Pins

Number

Original

Function

Alternate

Function 1

Alternate

Function 2

Alternate

Function 3

GPI/O

Register

Assignment

19

85

GPIO

-

GP47

GP60

nSMI

-

GP4, bit 7

GP6, bit 0

Power LED

Output

86

87

-

GP61

GP62

GP63

GP64

GP65

GP66

GP67

GP70

GP71

GP72

GP73

GP74

GP75

GP76

GP77

WDT

-

GP6, bit 1

GP6, bit 2

GP6, bit 3

GP6, bit 4

GP6, bit 5

GP6, bit 6

GP6, bit 7

GP7, bit 0

GP7, bit 1

GP7, bit 2

GP7, bit 3

GP7, bit 4

GP7, bit 5

GP7, bit 6

GP7, bit 7

-

8042 - P12

88

-

8042 - P13

89

8042 - P14

90

-

8042 - P15

91

-

8042 - P16

92

-

8042 - P17

127

128

121

122

123

124

125

126

nRI2 (1)

nDCD2 (1)

RXD2 (1)

TXD2 (1) (2)

nDSR2 (1)

nRTS2 (1) (2)

nCTS2 (1)

nDTR2 (1) (2)

-

Note (1): These pins are input (high-z) until programmed for second serial port.

Note (2): These pins cannot be programmed as open drain pins in their original function.

Note: No pins in their original function can be programmed as inverted input or inverted output.

115

GPI/O registers GP1 through GP4, GP6 and 7,

as well as WDT2_VAL and SMI Enable and

Status Registers can be accessed by the host

when the chip is in the normal run mode if CR03

Bit[7]=1. The host uses an Index and Data

register to access these registers. The Power

on default Index and Data registers are 0xEA

and 0xEB respectively. In configuration mode

the Index address may be programmed to

reside on addresses 0xE0, 0xE2, 0xE4 or 0xEA.

The Data address is automatically set to the

To access the GP1 register when in normal

(run) mode, the host should perform an IOW of

0x01 to the Index register (at 0xEX) to select

GP1 and then read or write the Data register (at

Index+1) to access the GP1 register. To access

GP2 the host should perform an IOW of 0x02 to

the Index register and then access GP2 through

the Data register. GP4, GP6, GP7 and the

WDT2_VAL and SMI Registers are acessed

similarly. Additionally the host can access the

WDT_CTRL (Watch Dog Timer Control)

Configuration Register while in the normal (run)

mode by writing an 0x03 to the index register.

Index address

+

1.

Upon exiting the

configuration mode the new Index and Data

registers are used to access registers GP1

through GP4, GP6 and 7, WDT2_VAL and SMI

Enable and Status Registers.

The GP registers can also be accessed by the

host when in configuration mode through CRF6-

FB of Logical Device 8.

Table 47A - Index and Data Register

REGISTER

Index

ADDRESS

NORMAL (RUN) MODE

0xE0, E2, E4, EA

Index address + 1

0x01-0x0F

Data

Access to GP1, GP2,

Watchdog Timer Control,

GP4, GP6, GP7,

WDT2_VAL and SMI

Enable and Status

Registers (see Table 47B)

116

Table 47B - Index and Data Register Normal (Run) Mode

NORMAL (RUN) MODE

INDEX

0x01

0x02

0x03

0x04

0x06

0x07

0x08

0x0C

0x0D

0x0E

0x0F

Access to GP1 (L8 - CRF6)

Access to GP2 (L8 - CRF7)

Access to Watchdog Timer Control (L8 - CRF4)

Access to GP4 (L8 - CRF8)

Access to GP6 (L8 - CRFA)

Access to GP7 (L8 - CRFB)

Access to Watchdog Timer 2, Timeout Value Register (L8-CRB0)

Access to SMI Enable Register 1 (L8-CRB4)

Access to SMI Enable Register 2 (L8-CRB5)

Access to SMI Status Register 1 (L8-CRB6)

Access to SMI Status Register 2 (L8-CRB7)

Note 1: These registers can also be accessed through the configuration registers

at L8 - CRxx shown in the table above.

117

GPI/O ports contain alternate functions which

are either output-type or input-type. The GPI/O

illustrated in the following two figures. Note: the

input pin buffer is always enabled.

port

structure

for

each

type is

GPI/O

Configuration

Register bit-1

(Polarity)

Configuration

Register bit-0

(Input/Output)

SD-bit

nIOW

D-TYPE

GPI/O

0

Transparent

0

1

nIOR

GPI/O

Register

Bit-n

GPI/O

GPIO

Configuration

Register bit-2

(Int En)

Configuration

Register bit-3

(Alt Function)

Alternate

Input

Function

To GP Interrupt

GPI/O having an input-type alternate function.

[GP10, GP11, GP12, GP21]

118

GPIO

GPI/O

Configuration

Register bit-3

(Alt Function)

Configuration

Register bit-0

(Input/Output)

Configuration

Register bit-1

(Polarity)

Alternate

Output

Function

1

0

SD-bit

nIOW

D-TYPE

GPI/O

0

1

Transparent

0

1

nIOR

GPI/O

Register

Bit-n

GPI/O

Configuration

Register bit-2

(Int En)

To GP Interrupt

GPI/O having an output-type alternate function.

[GP12--GP17, GP20, GP22--GP25]

119

In addition, the GPI/O port may be optionally

programmed to steer its signal to a Combined

General Purpose Interrupt request output pin on

the FDC37C68x. The interrupt channel for the

Combined Interrupt is selected by the GP_INT

General Purpose I/O Configuration Registers

Assigned to each GPI/O port is an 8-bit GPI/O

Configuration Register which is used to

independently program each I/O port. The

GPI/O Configuration Registers are only

accessible when the FDC37C68x is in the

Configuration Mode; more information can be

found in the Configuration section of this

specification.

Configuration

Register

defined

in

the

FDC37C68x System Configuration Section. The

Combined Interrupt is the "ORed" function of the

interrupt enabled GPI/O ports and will represent

a standard ISA interrupt (edge high).

Each GPI/O port may be programmed as either

a simple inverting or non-inverting input or

output port, or as an alternate function port. The

least-significant four bits of each GPI/O

Configuration Register define the operation of

the respective GPI/O port. The basic GPI/O

operations are outlined in Table 48.

When programmed as an input steered onto

the General Purpose Combined Interrupt (GP

IRQ), the Interrupt Circuitry contains

a

selectable debounce/digital filter circuit in

order that switches or push-buttons may be

directly connected to the chip. This filter shall

reject signals with pulse widths of 1ms or less.

Table 48 - GPI/O Configuration Register Bits [3:0]

ALT FUNC

BIT 3

INT EN

BIT 2

POLARITY

BIT 1

I/O

BIT 0

0=DIS-

ABLE

1=SELECT

0=DISABLE

1=ENABLE

0=NO

INVERT

1=INVERT

1=INPUT

0=OUTPUT

GPI/O PORT

OPERATION

0

1

0

1

0

1

0

1

0

simple non-inverting output

simple non-inverting input

simple inverting output

simple inverting input

non-inverting output steered back to GP

IRQ

0

1

0

1

0

1

0

1

0

non-inverting input steered to GP IRQ

inverting output steered back to GP IRQ

inverting input steered to GP IRQ

Alternate Function Output-type :

Alternate non-inverted output.

Alternate Function Input-type

:Alternate function not valid, GPI/O pin

acts as a simple non-inverting output.

120

Table 48 - GPI/O Configuration Register Bits [3:0]

ALT FUNC

BIT 3

INT EN

BIT 2

POLARITY

BIT 1

I/O

BIT 0

0=DIS-

ABLE

1=SELECT

0=DISABLE

1=ENABLE

0=NO

INVERT

1=INVERT

1=INPUT

0=OUTPUT

GPI/O PORT

OPERATION

1

0

1

0

Alternate Function Output-type :

Alternate function not valid, GPI/O pin

acts as a simple non-inverting input.

Alternate Function Input-type :

Alternate non-inverting input.

1

Alternate Function Output-type :

Alternate output function with inverted

sense

Alternate Function Input-type :

Alternate function not valid, GPI/O pin

acts as a simple inverting output.

1

0

1

0

1

0

1

Alternate Function Output-type :

Alternate output function not valid,

GPI/O pin acts as a simple inverting

input.

Alternate Function Input-type

:Inverting input to alternate input

function.

Alternate Function Output-type :

Alternate output function with non

inverted sense steered to GP IRQ

Alternate Function Input-type

:Alternate function not valid, GPI/O pin

acts as a simple non-inverting output

steered to GP IRQ

Alternate Function Output-type :

Alternate output function not valid,

GPI/O pin acts as a simple non-inverting

input steered to GP IRQ.

Alternate Function Input-type :Non-

inverting input to alternate input function

also steered to the GP IRQ.

121

Table 48 - GPI/O Configuration Register Bits [3:0]

ALT FUNC

BIT 3

INT EN

BIT 2

POLARITY

BIT 1

I/O

BIT 0

0=DIS-

ABLE

1=SELECT

0=DISABLE

1=ENABLE

0=NO

INVERT

1=INVERT

1=INPUT

0=OUTPUT

GPI/O PORT

OPERATION

1

0

1

Alternate Function Output-type :

Alternate output function with inverted

sense steered to GP IRQ

Alternate Function Input-type

:Alternate function not valid, GPI/O pin

acts as a simple inverting output steered

to GP IRQ.

1

Alternate Function Output-type :

Alternate output function not valid,

GPI/O pin acts as a simple inverting

input steered to GP IRQ.

Alternate Function Input-type :

Inverting input to alternate input function

also steered to the GP IRQ.

The alternate function of GP10 and GP11 allows

these GPI/O port pins to be mapped to their own

configuration registers is used to select the

active interrupt channel for each of these ports

as shown in the Configuration section of this

specification.

independent interrupt channels.

nibble of the GP10 and

The upper

GP11 GPI/O

122

effect. When a GPI/O port is programmed as

an output, the logic value written into the GPI/O

register is either output to or inverted to the

GPI/O pin; when read the result will reflect the

contents of the GPI/O register bit. This is

sumarized in Table 49.

Reading and Writing GPI/O Ports

When a GPI/O port is programmed as an input,

reading it through the GPI/O register latches

either the inverted or non-inverted logic value

present at the GPI/O pin; writing it has no

Table 49 - GPI/O Read/Write Behavior

GPI/O INPUT PORT

HOST OPERATION

GPI/O OUTPUT PORT

bit value in GP register

bit placed in GP register

Read

Write

latched value of GPI/O pin

no effect

WATCH DOG TIMER/POWER LED CONTROL

Basic Functions

Watch Dog Timer

The FDC37C68x's WDT has a programmable

time-out ranging from 1 to 255 minutes with one

minute resolution, or 1 to 255 seconds with 1

The FDC37C68x contains a Watch Dog Timer

(WDT) and also has the capability to directly

drive the system's Power-on LED.

second resolution.

The units of the WDT

timeout value are selected via bit[7] of the

GPA_GPW_EN register (located at 0xF1 of

Logical Device 8). The WDT time-out value is

set through the WDT_VAL Configuration

register. Setting the WDT_VAL register to 0x00

disables the WDT function (this is its power on

default). Setting the WDT_VAL to any other

non-zero value will cause the WDT to reload

and begin counting down from the value loaded.

When the WDT count value reaches zero the

counter stops and sets the Watchdog time-out

status bit in the WDT_CTRL Configuration

Register. Note: Regardless of the current state

of the WDT, the WDT time-out status bit can be

directly set or cleared by the Host CPU.

The Watch Dog Time-out status bit

(WDT_CTRL bit-0) is mapped to GP12 when

the alternate function bit of the GP12

Configuration Register is set "and" bit-6 of the

IR Options Register = 0. In addition, the Watch

Dog Time-out status bit may be mapped to an

interrupt through the WDT_CFG Configuration

Register.

GP13 may be configured as a high current LED

driver to drive the Power LED.

This is

accomplished by setting the alternate function

bit of the GP13 Configuration Register "and"

clearing bit-6 of the IR Options Register.

There are three system events which can reset

the WDT, these are a Keyboard Interrupt, a

Mouse Interrupt, or I/O reads/writes to address

0x201 (the internal or an external Joystick Port).

The effect on the WDT for each of these system

events may be individually enabled or disabled

through bits in the WDT_CFG configuration

register. When a system event is enabled

through the WDT_CFG register, the occurence

The Infared signals, IRRX and IRTX, are

mapped to GP12 and GP13 when the alternate

function bit of the GP12 and GP13

Configuration Registers is set "and" bit-6 of the

IR Options Register is set.

123

of that event will cause the WDT to reload the

value stored in WDT_VAL and reset the WDT

time-out status bit if set. If all three system

events are disabled the WDT will inevitably time

out.

WDT_CTRL (Force WD Time-out) Configuration

Register. Writting a "1" to this bit forces the

WDT count value to zero and sets bit 0 of the

WDT_CTRL (Watch Dog Status). Bit 2 of the

WDT_CTRL is self-clearing.

The Watch Dog Timer may be configured to

generate an interrupt on the rising edge of the

Time-out status bit. The WDT interrupt is

mapped to an interrupt channel through the

Power LED Toggle

Setting bit 1 of the WDT_CTRL configuration

register will cause the Power LED output driver

to toggle at 1 Hertz with a 50 percent duty cycle.

When this bit is cleared the Power LED output

will drive continuously unless it has been

configured to toggle on Watch Dog time-out

conditions. Setting bit 3 of the WDT_CFG

configuration register will cause the Power LED

output driver to toggle at 1 Hertz with a 50

percent duty cycle whenever the WDT time-out

status bit is set. The truth table below clarifies

the conditions for which the Power LED will

toggle.

WDT_CFG Configuration Register.

When

mapped to an interrupt the interrupt request pin

reflects the value of the WDT time-out status bit.

When the polarity bit is 0, GP12 reflect the value

of the Watch Dog Time-out status bit, however

when the polarity bit is 1, GP12 reflects the

inverted value of the Watch Dog Time-out status

bit. This is also true for the other pin used for

WDT, GP61.

The host may force a Watch Dog time-out to

occur by writting

a "1" to bit 2 of the

When the polarity bit is 0, the Power LED output

asserts or drives low. If the polarity bit is 1 then

the Power LED output asserts or drives high.

Table 50 - LED Toggle Truth Table

WDT_CFG BIT[3]

POWER LED

TOGGLE ON WDT

WDT_CTRL BIT[0]

WDT T/O STATUS BIT

WDT_CTRL BIT[1]

POWER LED

TOGGLE

POWER LED STATE

1

0

X

0

1

X

0

1

Toggle

Continuous

Toggle

124

Table 51 - Watchdog Timer/Power LED Configuration Registers

CONFIG REG.

WDT_VAL

BIT FIELD

Bits[7:0]

DESCRIPTION

Binary coded time-out value, 0x00 disables the WDT.

Joystick enable

WDT_CFG

Bit[0]

Bit[1]

Keyboard enable

Bit[2]

Mouse enable

Bit[3]

Power LED toggle on WDT time-out

Bits[7:4]

WDT interrupt mapping,

0000b = diables irq mapping

WDT_CTRL

Bit[0]

Bit[1]

Bit[2]

Bit[3]

Bit[4]

WDT time-out status bit

Power LED toggle

Force Timeout, self-clearing

P20 Force Timeout Enable

WDT2 SMI Timeout Enable

polarity may be altered through the polarity bit

in its GPI/O Configuration Register.

General Purpose Address Decoder

General Purpose I/O pin GP14 may be

configured as a General Purpose Address

Decode Pin. The General Purpose Address

Decoder provides an output decoded from bits

A11-A1 of the 12-bit address stored in a two-

byte Base I/O Address Register (logical device 8

config registers 0x60,0x61) qualified with AEN.

Thus, the decoder provides a two address

decode where A0=X. This General Purpose

output is normally active low, however the

polarity may be altered through the polarity bit in

its GPI/O Configuration Register.

The GPA_GPW_EN Configuration Register

contains two bits which allow the General

Purpose Address Decode and Write functions to

be independently enabled or disabled.

Joystick Control

The Base I/O address of the Joystick (Game)

Port is fixed at address 0x201.

GP16 Joystick Function

General Purpose Write

The FDC37C68x may be configured to generate

either a Joystick Chip Select or a Joystick Read

Strobe on GP16. The polarity is programmable

through a bit in the GP16 confiugration register.

When configured as a Joystick Chip Select the

output is simply a decode of the address =

General Purpose I/O pin GP15 may be

configured as a General Purpose Write pin. The

General Purpose Write provides an output

decoded from the 12-bit address stored in a

two-byte Base I/O Address Register (logical

device 8 config registers 0x62,0x63) qualified

with IOW and AEN. This General Purpose

output is normally active low, however the

0x201 qualified by AEN active.

When

configured as a Joystick Read Strobe the output

is a decode of the address = 0x201 qualified by

IOR and AEN both active. The Joystick Chip

Select or Read Strobe is normally active low,

125

however its polarity is programmable through a

bit in the configuration register.

The Joystick Write Strobe is normally active

low, however its polarity is programmable

through a bit in the GP17 configuration register.

GP17 Joystick Function

GATEA20

The FDC37C68x may be configured to generate

a

Joystick Write Strobe on GP17. When

GATEA20 is an internal signal from the

Keyboard controller (Port 21). The FDC37C68x

may be configured to drive this signal onto

GP25 by programming its GPI/O Configuration

Register. See the 8042 Keyboard Controller

Section for more information.

configured as a Joystick Write Strobe the output

is a decode of the address = 0x201 qualified by

IOW and AEN both active.

126

8042 KEYBOARD CONTROLLER FUNCTIONAL DESCRIPTION

The FDC37C68x is a Super I/O and Universal

Keyboard Controller that is designed for

intelligent keyboard management in desktop

computer applications. The Super I/O supports

a Floppy Disk Controller, two 16550 type serial

ports and one ECP/EPP Parallel Port.

The Universal Keyboard Controller uses an

8042 microcontroller CPU core. This section

concentrates on the FDC37C68x enhancements

to the 8042. For general information about the

8042, refer to the "Hardware Description of the

8042" in the 8-Bit Embedded Controller Hand-

book.

P24

P25

P21

P20

KIRQ

MIRQ

GP25

GP20 (WD Timer)

8042A

LS05

P27

P10

KDAT

KCLK

MCLK

MDAT

P26

TST0

P23

TST1

P22

P11

Keyboard and Mouse Interface

KIRQ is the Keyboard IRQ

MIRQ is the Mouse IRQ

GP25 - Port 21 is GP25's alternate function output, and can be used to create a GATEA20 signal from

the FDC37C68x.

GP20 - This General purpose output can be configured as the 8042 Port 2.0 which is typically used to

create a "keyboard reset" signal. The 8042's P20 can be used to optionally reset the Watch Dog

Timer.

127

KEYBOARD ISA INTERFACE

Input Data register, and Output Data register.

Table 52 shows how the interface decodes the

control signals. In addition to the above signals,

the host interface includes keyboard and mouse

IRQs.

The FDC37C68x ISA interface is functionally

compatible with the 8042 style host interface. It

consists of the D0-7 data bus; the nIOR, nIOW

and

the

Status

register,

Table 52 - ISA I/O Address Map

ISA ADDRESS

nIOW

nIOR

BLOCK

KDATA

KDCTL

FUNCTION (NOTE 1)

Keyboard Data Write (C/D=0)

Keyboard Data Read

0x60

0

1

0

1

0

1

0

0x64

Keyboard Command Write (C/D=1)

Keyboard Status Read

Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and

Data Read.

Keyboard Data Write

Keyboard Command Write

This is an 8 bit write only register. When

written, the C/D status bit of the status register

is cleared to zero and the IBF bit is set.

This is an 8 bit write only register. When

written, the C/D status bit of the status register

is set to one and the IBF bit is set.

Keyboard Data Read

Keyboard Status Read

This is an 8 bit read only register. If enabled by

"ENABLE FLAGS", when read, the KIRQ output

is cleared and the OBF flag in the status register

is cleared. If not enabled, the KIRQ and/or

AUXOBF1 must be cleared in software.

This is an 8 bit read only register. Refer to the

description of the Status Register for more

information.

128

CPU-to-Host Communication

to this register automatically sets Bit 0 (OBF) in

the Status register. See Table 53.

The FDC37C68x CPU can write to the Output

Data register via register DBB. A write

Table 53 - Host Interface Flags

8042 INSTRUCTION

FLAG

OUT DBB

Set OBF, and, if enabled, the KIRQ output signal goes high

Host-to-CPU Communication

MIRQ

The host system can send both commands and

data to the Input Data register. The CPU

differentiates between commands and data by

reading the value of Bit 3 of the Status register.

When bit 3 is "1", the CPU interprets the register

contents as a command. When bit 3 is "0", the

CPU interprets the register contents as data.

During a host write operation, bit 3 is set to "1" if

SA2 = 1 or reset to "0" if SA2 = 0.

If "EN FLAGS" has been executed and P25 is

set to a one:; IBF is inverted and gated onto

MIRQ. The MIRQ signal can be connected to

system interrupt to signify that the FDC37C68x

CPU has read the DBB register.

If "EN FLAGS” has not been executed, MIRQ is

controlled by P25, Writing a zero to P25 forces

MIRQ low, a high forces MIRQ high. (MIRQ is

normally selected as IRQ12 for mouse support.)

KIRQ

Gate A20

If "EN FLAGS" has been executed and P24 is

set to a one: the OBF flag is gated onto KIRQ.

The KIRQ signal can be connected to system

interrupt to signify that the FDC37C68x CPU

has written to the output data register via "OUT

DBB,A". If P24 is set to a zero, KIRQ is forced

low. On power-up, after a valid RST pulse has

been delivered to the device, KIRQ is reset to 0.

KIRQ will normally reflects the status of writes

"DBB". (KIRQ is normally selected as IRQ1 for

keyboard support.)

A general purpose P21 can be routed out to the

general purpose pin GP25 for use as a software

controlled Gate A20 or user defined output.

EXTERNAL

INTERFACE

KEYBOARD

AND

MOUSE

Industry-standard PC-AT-compatible keyboards

employ a two-wire, bidirectional TTL interface

for data transmission. Several sources also

supply PS/2 mouse products that employ the

same type of interface. To facilitate system

expansion, the FDC37C68x provides four signal

pins that may be used to implement this

interface directly for an external keyboard and

mouse.

If "EN FLAGS” has not been executed: KIRQ

can be controlled by writing to P24. Writing a

zero to P24 forces KIRQ low; a high forces

KIRQ high.

The FDC37C68x has four high-drive, open-drain

output, bidirectional port pins that can be used for

external serial interfaces, such as ISA external

keyboard and PS/2-type mouse interfaces. They are

129

KCLK, KDAT, MCLK, and MDAT. P26 is inverted and

output as KCLK. The KCLK pin is connected to

TEST0. P27 is inverted and output as KDAT. The

KDAT pin is connected to P10. P23 is inverted and

output as MCLK. The MCLK pin is connected to

TEST1. P22 is inverted and output as MDAT. The

MDAT pin is connected to P11. NOTE: External pull-

ups may be required.

Hard Power Down Mode

This mode is entered by executing

a STOP

instruction. The oscillator is stopped by disabling

the oscillator driver cell. When either RESET is

driven active or a data byte is written to the DBBIN

register by a master CPU, this mode will be exited

(as above). However, as the oscillator cell will require

an initialization time, either RESET must be held

active for sufficient time to allow the oscillator to

stabilise. Program execution will resume as above.

KEYBOARD POWER MANAGEMENT

The keyboard provides support for two power-saving

modes: soft powerdown mode and hard powerdown

mode. In soft powerdown mode, the clock to the ALU

is stopped but the timer/counter and interrupts are still

active. In hard power down mode the clock to the

8042 is stopped. Efforts must be made to reduce

power wherever possible!

INTERRUPTS

The FDC37C68x provides the two 8042 interrupts.

IBF and the Timer/Counter Overflow.

MEMORY CONFIGURATIONS

Soft Power Down Mode

The FDC37C68x provides 2K of on-chip ROM and

256 bytes of on-chip RAM.

This mode is entered by executing

a HALT

Register Definitions

instruction. The execution of program code is halted

until either RESET is driven active or a data byte is

written to the DBBIN register by a master CPU. If

this mode is exited using the interrupt, and the IBF

interrupt is enabled, then program execution resumes

with a CALL to the interrupt routine, otherwise the

next instruction is executed. If it is exited using

RESET then a normal reset sequence is initiated and

program execution starts from program memory

location 0.

Host I/F Data Register

The Input Data register and Output Data register are

each 8 bits wide. A write to this 8 bit register will load

the Keyboard Data Read Buffer, set the OBF flag and

set the KIRQ output if enabled. A read of this register

will read the data from the Keyboard Data or

Command Write Buffer and clear the IBF flag. Refer

to the KIRQ and Status register descriptions for more

information.

Host I/F Status Register

The Status register is 8 bits wide. Table 54 shows

the contents of the Status register.

Table 54 - Status Register

D4 D3 D2

UD C/D UD

D7

D6

D5

D1

D0

UD

IBF

OBF

130

OBF

(Output Buffer Full)- This flag is set to

1 whenever the FDC37C68x CPU

write to the output data register (DBB).

When the host system reads the

output data register, this bit is

automatically reset.

Status Register

This register is cleared on a reset. This register

is read-only for the Host and read/write by the

FDC37C68x CPU.

UD Writable by FDC37C68x CPU. These bits

are user-definable.

EXTERNAL CLOCK SIGNAL

C/D (Command Data)-This bit specifies whether

the input data register contains data or

a command (0 = data, 1 = command).

During a host data/command write

operation, this bit is set to "1" if SA2 =

1 or reset to "0" if SA2 = 0.

The Keyboard Controller clock source is a 12

MHz clock generated from a 14.318 MHz clock.

The reset pulse must last for at least 24 16

MHz clock periods.

requirement applies to both internally (Vcc POR)

and externally generated reset signals. In

The pulse-width

powerdown mode, the external clock signal is

not loaded by the chip.

IBF (Input Buffer Full)- This flag is set to 1

whenever the host system writes data

into the input data register. Setting this

flag activates the FDC37C68x CPU's

nIBF (MIRQ) interrupt if enabled.

When the FDC37C68x CPU reads the

input data register (DBB), this bit is

automatically reset and the interrupt is

DEFAULT RESET CONDITIONS

The FDC37C68x has one source of reset: an

external reset via the RESET pin. Refer to

Table 55 for the effect of each type of reset on

the internal registers.

cleared.

There is no output pin

associated with this internal signal.

Table 55 - Resets

DESCRIPTION

KCLK

HARDWARE RESET (RESET)

Weak High

N/A

KDAT

MCLK

MDAT

Host I/F Data Reg

Host I/F Status Reg

00H

NC: No Change

N/A: Not Applicable

131

GATEA20 AND KEYBOARD RESET

Generated GateA20 and KRESET and Port 92

Fast GateA20 and KRESET.

The FDC37C68x provides two options for

GateA20 and Keyboard Reset: 8042 Software

GATEA20 AND KEYBOARD RESET

Port 92 Register

This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register

(Logical Device 7, 0xF0) set to 1.

This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20)

functions.

Name

Port 92

92h

24h

Read/Write

8 bits

Location

Default Value

Attribute

Size

Port 92 Register

Function

Reserved. Returns 00 when read.

Bit

7:6

5

4

3

2

1

Reserved. Returns a 1 when read.

Reserved. Returns a 0 when read.

Reserved. Returns a 1 when read.

ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven

low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.

Alternate System Reset. This read/write bit provides an alternate system reset function.

This function provides an alternate means to reset the system CPU to effect a mode

switch from Protected Virtual Address Mode to the Real Address Mode. This provides a

faster means of reset than is provided by the Keyboard controller. This bit is set to a 0

by a system reset. Writing a 1 to this bit will cause the nALT_RST signal to pulse acitive

(low) for a minimum of 1 µs after a delay of 500 ns. Before another nALT_RST pulse

can be generated, this bit must be written back to a 0.

0

nGATEA20

8042

ALT_A20

System

P21

nA20M

0

1

0

1

0

1

0

1

132

Bit 0 of Port 92, which generates the nALT_RST

signal, is used to reset the CPU under program

In addition, if Port 92 is enabled, i.e., bit 2 of

KRST_GA20 is set to 1, then a pulse is also

generated by writing a 1 to bit 0 of the Port 92

Register and this pulse is AND’ed with the pulse

generated above. This pulse is output on pin

KRESET and its polarity is controlled by the

GPI/O polarity configuration.

control.

This signal is AND’ed together

externally with the reset signal (nKBDRST) from

the keyboard controller to provide a software

means of resetting the CPU. This provides a

faster means of reset than is provided by the

keyboard controller. Writing a 1 to bit 0 in the

Port 92 Register causes this signal to pulse low

for a minimum of 6µs, after a delay of a

minimum of 14µs. Before another nALT_RST

pulse can be generated, bit 0 must be set to 0

either by a system reset of a write to Port 92.

Upon reset, this signal is driven inactive high (bit

0 in the Port 92 Register is set to 0).

Bit 1 of Port 92, the ALT_A20 signal, is used to

force nA20M to the CPU low for support of real

mode compatible software.

This signal is

externally OR’ed with the A20GATE signal from

the keyboard controller and CPURST to control

the nA20M input of the CPU. Writing a 0 to bit 1

of the Port 92 Register forces ALT_A20 low.

ALT_A20 low drives nA20M to the CPU low, if

A20GATE from the keyboard controller is also

low. Writing a 1 to bit 1 of the Port 92 Register

forces ALT_A20 high. ALT_A20 high drives

nA20M to the CPU high, regardless of the state

of A20GATE from the keyboard controller. Upon

reset, this signal is driven low.

If Software control is selected the reset pulse is

generated by the 8042 upon writing an FE

command to register 64. This pulse is output on

pin KRESET and its polarity is controlled by the

GPI/O polarity configuration.

133

SYSTEM MANAGEMENT INTERRUPT (SMI)

The FDC37C68x implements a group nSMI output pin. The System Management Interrupt is a non-

maskable interrupt with the highest priority level used for transparent power management. The nSMI

group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip.

The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 and 2. The

nSMI output is then enabled onto the group nSMI output pin via bit[7] in the SMI Enable Register 2.

The logic equation for the nSMI output is as follows:

nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or

(EN_FINT and IRQ_FINT) or (EN_GPINT2 and IRQ_GPINT2) or (EN_GPINT1 and

IRQ_GPINT1) or (EN_WDT and IRQ_WDT) or (EN_MINT and IRQ_MINT) or (EN_KINT and

IRQ_KINT) or (EN_IRINT and IRQ_IRINT)

SMI Status Registers

REGISTERS

The following registers can be accessed when in

configuration mode at Logical Device 8,

Registers B4-B7 and when not in configuration

they can be accessed through the Index and

Data Register.

SMI Status Register 1

(Configuration Register B6, Logical Device 8)

This register is used to read the status of the

SMI input events. Note: The status bit gets set

whether or not the interrupt is enabled onto the

group SMI output.

SMI Enable Registers

SMI Status Register 2

SMI Enable Register 1

(Configuration Register B7, Logical Device 8)

This register is used to read the status of the

SMI input events. Note: The status bit gets set

whether or not the interrupt is enabled onto the

group SMI output.

(Configuration Register B4, Logical Device 8)

This register is used to enable the different

interrupt sources onto the group nSMI output.

SMI Enable Register 2

(Configuration Register B5, Logical Device 8)

This register is used to enable additional

interrupt sources onto the group nSMI output.

This register is also used to enable the group

nSMI output onto the nSMI GPI/O pin and the

routing of 8042 P12 internally to nSMI.

134

SMI Timeout Override

A new feature is to be added which will prevent

configured for an active high or active low

output, or as an input in order to inhibit the

pulse from affecting the system, if desired. This

pin defaults to an input. The WDT2_VAL will

stay at 0x00 in this case until the chip is reset.

a hung system from having to be unplugged.

This new feature functions as follows: When the

chip generates an nSMI via the SMI IRQ routing

registers from any block including Combined

IRQs1 & 2 from the GPIOs, a second watch dog

timer, WDT2

enabled.

will begin counting down, if

The WDT2 SMI Timeout function is disabled by

setting bit 4 of the WDT_CTRL register =0

(default).

If the SMM code does not stop and reset the

counter, a pulse will be generated that can be

used to gate-off POWER_GOOD to the entire

system, causing a cold boot (i.e., if a WDT2

Timeout occurs, a 1ms (min) pulse is generated

to the alternate function of GP15).

The WDT2 function is selected on the GP15 pin

via the GP15 configuration register (LD8, 0xE5)

Reading the WDT2_VAL register will return the

current value while counting. To read the current

count value, the software must leave

WDT_CTRL bit[4] = 1 and read the WDT2_VAL

register until it obtains two consecutive identical

This feature is controlled through Bit 4 of the

WDT_CTRL register, Logical Device 8 0xF4.

The timeout value is programmed via the

WDT2_VAL register in Logical Device 8 at 0xB0.

This register is located at the run-time index

0x08.

values.

The software must first clear

WDT_CTRL bit[4] to zero before writing a value

to the WDT2_VAL register. If the chip can be

kept from being reset after it deasserts

POWER_GOOD, then POST code will be able

to tell what has occurred by reading a 0x00 from

WDT2_VAL, and a 1 in Bit[4]. When the chip is

reset both values will be "0".

The WDT2 SMI timeout function is enabled by

setting bit 4 of the WDT_CTRL register =1. If a

WDT2 Timeout occurs, a 1ms (min) to 250msec

(max) pulse is generated to the alternate

function of GP15. This pin can be

135

SERIAL INTERRUPTS

MSIO will support the serial interrupt scheme, which is adopted by several companies, to transmit

interrupt information to the system. The serial interrupt scheme adheres to the “Serial IRQ

Specification for PCI Systems” Version 6.0.

Timing Diagrams For IRQSER Cycle

PCICLK = 33Mhz_IN pin

IRQSER = SERIRQ pin

A) Start Frame timing with source sampled a low pulse on IRQ1

START FRAME

IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME

SL

or

H

R

T

S

R

T

S

R

T

S

R

T

H

PCICLK

START¹

IRQSER

IRQ1 Host Controller

SL=Slave Control

None

R=Recovery

IRQ1

T=Turn-around

None

Drive Source

H=Host Control

1)

S=Sample

Start Frame pulse can be 4-8 clocks wide.

B) Stop Frame Timing with Host using 17 IRQSER sampling period

IRQ14

FRAME

R

IRQ15

FRAME

R

IOCHCK#

FRAME

STOP FRAME

NEXT CYCLE

I ²

S

T

S

T

S

R

T

H

R

T

PCICLK

IRQSER

Driver

STOP¹

START³

I= Idle.

None

IRQ15

None

136

Host Controller

H=Host Control

R=Recovery

T=Turn-around

S=Sample

1)

2)

3)

Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.

There may be none, one or more Idle states during the Stop Frame.

The next IRQSER cycle’s Start Frame pulse may or may not start immediately after the

turn-around clock of the Stop Frame.

IRQSER Cycle Control

There are two modes of operation for the IRQSER Start Frame.

1)

Quiet (Active) Mode : Any device may initiate a Start Frame by driving the IRQSER low for

one clock, while the IRQSER is Idle. After driving low for one clock the IRQSER must immediately be

tri-stated without at any time driving high. A Start Frame may not be initiated while the IRQSER is

Active. The IRQSER is Idle between Stop and Start Frames. The IRQSER is Active between Start

and Stop Frames. This mode of operation allows the IRQSER to be Idle when there are no IRQ/Data

transitions which should be most of the time.

Once a Start Frame has been initiated the Host Controller will take over driving the IRQSER low in the

next clock and will continue driving the IRQSER low for a programmable period of three to seven

clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will

drive the IRQSER back high for one clock, then tri-state.

Any IRQSER Device (i.e., The FDC37C68x) which detects any transition on an IRQ/Data line for

which it is responsible must initiate a Start Frame in order to update the Host Controller unless the

IRQSER is already in an IRQSER Cycle and the IRQ/Data transition can be delivered in that IRQSER

Cycle.

2)

Continuous (Idle) Mode : Only the Host controller can initiate a Start Frame to update

IRQ/Data line information. All other IRQSER agents become passive and may not initiate a Start

Frame. IRQSER will be driven low for four to eight clocks by Host Controller. This mode has two

functions. It can be used to stop or idle the IRQSER or the Host Controller can operate IRQSER in a

continuous mode by initiating a Start Frame at the end of every Stop Frame.

An IRQSER mode transition can only occur during the Stop Frame. Upon reset, IRQSER bus is

defaulted to Continuous mode, therefore only the Host controller can initiate the first Start

Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next

IRQSER Cycle’s mode.

IRQSER Data Frame

Once a Start Frame has been initiated, the FDC37C68x will watch for the rising edge of the Start

Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample

phase, Recovery phase, and Turn-around phase. During the Sample phase the FDC37C68x must

drive the IRQSER (SERIRQ pin) low, if and only if, its last detected IRQ/Data value was low. If its

detected IRQ/Data value is high, IRQSER must be left tri-stated. During the Recovery phase the

FDC37C68x must drive the SERIRQ high, if and only if, it had driven the IRQSER low during the

previous Sample Phase. During the Turn-around Phase the FDC37C68x must tri-state the SERIRQ.

137

The FDC37C68x will drive the IRQSER line low at the appropriate sample point if its associated

IRQ/Data line is low, regardless of which device initiated the Start Frame.

The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a

number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock

is the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock after the rising edge of the Start Pulse.)

IRQSER Sampling Periods

IRQSER Period

Signal

Sampled

Not Used

IRQ1

# of clocks past Start

1

2

5

3

4

5

6

7

8

9

10

11

12

13

14

15

16

nSMI / IRQ2

IRQ3

8

11

14

17

20

23

26

29

32

35

38

41

44

47

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

The SERIRQ data frame will now support IRQ2 from a logical device, previously IRQSER Period 3

was reserved for use by the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the

user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI

the user should not configure any logical devices as using IRQ2.

Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port 1), 5 (Ser Port 2), and 7 (KBD) shall have IRQ13 as

a choice for their primary interrupt.

Stop Cycle Control

Once all IRQ/Data Frames have completed the Host Controller will terminate IRQSER activity by

initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is

indicated when the IRQSER is low for two or three clocks. If the Stop Frame’s low time is two clocks

then the next IRQSER Cycle’s sampled mode is the Quiet mode; and any IRQSER device may initiate

a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. If the Stop

Frame’s low time is three clocks then the next IRQSER Cycle’s sampled mode is the Continuos mode;

and only the Host Controller may initiate a Start Frame in the second clock or more after the rising

edge of the Stop Frame’s pulse.

138

Latency

Latency for IRQ/Data updates over the IRQSER bus in bridge-less systems with the minimum

IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84uS with a 25MHz PCI Bus or 2.88uS

with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for

IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous

buses, and approximately double for asynchronous buses.

EOI/ISR Read Latency

Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency

could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could

cause a system fault. The host interrupt controller is responsible for ensuring that these latency

issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt

controller by the same amount as the IRQSER Cycle latency in order to ensure that these events do

not occur out of order.

AC/DC Specification Issue

All IRQSER agents must drive / sample IRQSER synchronously related to the rising edge of PCI bus

clock. IRQSER (SERIRQ) pin uses the electrical specification of PCI bus. Electrical parameters will

follow PCI spec. section 4, sustained tri-state.

Reset and Initialization

The IRQSER bus uses RESET_DRV as its reset signal. The IRQSER pin is tri-stated by all agents

while RESET_DRV is active. With reset, IRQSER Slaves are put into the (continuous) IDLE mode.

The Host Controller is responsible for starting the initial IRQSER Cycle to collect system’s IRQ/Data

default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse

width) for subsequent IRQSER Cycles. It is Host Controller’s responsibility to provide the default

values to 8259’s and other system logic before the first IRQSER Cycle is performed. For IRQSER

system suspend, insertion, or removal application, the Host controller should be programmed into

Continuous (IDLE) mode first. This is to guarantee IRQSER bus is in IDLE state before the system

configuration changes.

139

CONFIGURATION

The Configuration of the FDC37C68x is very

The BIOS uses these configuration ports to

initialize the logical devices at POST. The

INDEX and DATA ports are only valid when the

FDC37C68x is in Configuration Mode.

flexible and is based on the configuration

architecture implemented in typical Plug-and-

Play components. The FDC37C68x is designed

for motherboard applications in which the

resources required by their components are

known. With its flexible resource allocation

architecture, the FDC37C68x allows the BIOS to

assign resources at POST.

The SYSOPT pin is latched on the falling edge

of the RESET_DRV or on Vcc Power On Reset

to determine the configuration register's base

address. The SYSOPT pin is used to select the

CONFIG PORT's I/O address at power-up.

Once powered up the configuration port base

address can be changed through configuration

registers CR26 and CR27. The SYSOPT pin

is a hardware configuration pin which is

shared with the nRTS1 signal on pin 116.

During reset this pin is a weak active low signal

which sinks 30µA. Note: All I/O addresses are

qualified with AEN.

SYSTEM ELEMENTS

Primary Configuration Address Decoder

After a hard reset (RESET_DRV pin asserted) or

Vcc Power On Reset the FDC37C68x is in the

Run Mode with all logical devices disabled. The

logical devices may be configured through two

standard Configuration I/O Ports (INDEX and

DATA) by placing the FDC37C68x into

Configuration Mode.

The INDEX and DATA ports are effective only

when the chip is in the Configuration State.

PORT NAME

SYSOPT= 0

(Pull-down resistor)

Refer to Note 1

SYSOPT= 1

(10K Pull-up resistor)

TYPE

CONFIG PORT (Note 2) 0x03F0

0x0370

Write

INDEX PORT (Note 2)

DATA PORT

0x03F0

Read/Write

INDEX PORT + 1

Note 1: If using TTL RS232 drivers use 1K pull-down. If using CMOS RS232 drivers use

10K pull-down.

Note 2: The configuration port base address can be relocated through CR26 and CR27.

Entering the Configuration State

Exiting the Configuration State

The device enters the Configuration State when

the following Config Key is successfully written

to the CONFIG PORT.

The device exits the Configuration State when

the following Config Key is successfully written

to the CONFIG PORT.

Config Key = < 0x55 >

Config Key = < 0xAA>

CONFIGURATION SEQUENCE

140

To program the configuration registers, the

following sequence must be followed:

1. Enter Configuration Mode

2. Configure the Configuration Registers

3. Exit Configuration Mode.

Exit Configuration Mode

To exit the Configuration State the system

writes 0xAA to the CONFIG PORT. The chip

returns to the RUN State. Note: Only two

states are defined (Run and Configuration.) In

the Run State the chip will always be ready to

enter the Configuration State.

Enter Configuration Mode

To

place

the

chip

into

the

Configuration State the Config Key is sent to

the chip's CONFIG PORT. The config key

consists of one write of 0x55 data to the

CONFIG PORT. Once the initiation key is

received correctly the chip enters into the

Configuration State (The auto Config ports

are enabled).

Programming Example

The following is an example of a configuration

program in Intel 8086 assembly language.

;--------------------------------------------------.

; ENTER CONFIGURATION MODE |

;--------------------------------------------------'

MOV

OUT

DX,3F0H

AX,055H

DX,AL

Configuration Mode

The system sets the logical device information

and activates desired logical devices through

the INDEX and DATA ports. In configuration

mode, the INDEX PORT is located at the

CONFIG PORT address and the DATA PORT

is at INDEX PORT address + 1.

;--------------------------------------------------.

; CONFIGURE REGISTER CRE0,

; LOGICAL DEVICE 8

|

;--------------------------------------------------'

MOV

OUT

MOV

OUT

;

DX,3F0H

AL,07H

DX,AL ; Point to LD# Config Reg

DX,3F1H

AL, 08H

The desired configuration registers are

accessed in two steps:

DX,AL ; Point to Logical Device 8

a. Write the index of the Logical Device

Number Configuration Register (i.e., 0x07)

to the INDEX PORT and then write the

number of the desired logical device to the

DATA PORT

MOV

OUT

MOV

OUT

DX,3F0H

AL,E0H

DX,AL ; Point to CRE0

DX,3F1H

AL,02H

b. Write the address of the desired

configuration register within the logical

device to the INDEX PORT and then write

or read the configuration register through

the DATA PORT.

DX,AL ; Update CRE0

;-------------------------------------------------.

; EXIT CONFIGURATION MODE

;-------------------------------------------------'

|

MOV

OUT

DX,3F0H

AX,0AAH

DX,AL

Note: if accessing the Global Configuration

Registers, step (a) is not required.

141

Notes: 1. HARD RESET: RESET_DRV pin asserted

2. SOFT RESET: Bit 0 of Configuration Control register set to one

3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing

Diagram)

Table 56 - Configuration Registers

HARD RESET

/ Vcc POR

INDEX

TYPE

Vcc POR

SOFT

RESET

CONFIGURATION REGISTER

GLOBAL CONFIGURATION REGISTERS

0x02

0x03

0x07

0x20

0x21

0x22

0x23

0x24

0x26

W

0x00

0x03

0x00

0x48

0x01

0x00

0x04

-

0x00

Config Control

R/W

R

Index Address

0x00

0x48

0x01

0x00

Logical Device Number

Device ID - hard wired

Device Rev - hard wired

Power Control

R

R/W

Power Mgmt

OSC

Sysopt=0:

0xF0

Sysopt=1:

0x70

Sysopt=0:

0x03

-

Configuration Port Address Byte 0

0x27

R/W

-

Configuration Port Address Byte 1

Sysopt=1:

0x03

0x28

0x2C

0x2D

0x2E

0x2F

R/W

0x00

-

0x00

Clock Mask Register

TEST 4

-

TEST 1

TEST 2

0x00

TEST 3

LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD)

0x30

R/W

0x00

-

0x00

Activate

0x60,

0x61

0x03,

0xF0

0x03,

0xF0

Primary Base I/O Address (Note 2)

0x70

0x74

0xF0

R/W

0x06

0x02

0x0E

-

0x06

0x02

-

Primary Interrupt Select

DMA Channel Select

FDD Mode Register

142

Table 56 - Configuration Registers

HARD RESET

/ Vcc POR

INDEX

TYPE

Vcc POR

SOFT

RESET

CONFIGURATION REGISTER

0xF1

0xF2

0xF4

0xF5

R/W

0x00

0xFF

0x00

-

FDD Option Register

FDD Type Register

FDD0

FDD1

LOGICAL DEVICE 1 CONFIGURATION REGISTERS RESERVED

LOGICAL DEVICE 2 CONFIGURATION REGISTERS RESERVED

LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port)

0x30

R/W

0x00

-

0x00

Activate

0x60,

0x61

0x00,

0x00

0x00,

0x00

Primary Base I/O Address (Note 2)

0x70

0x74

0xF0

0xF1

R/W

0x00

0x04

0x3C

0x00

-

0x00

Primary Interrupt Select

DMA Channel Select

0x04

-

Parallel Port Mode Register

Parallel Port Mode Register 2

LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1)

0x30

R/W

0x00

-

0x00

Activate

0x60,

0x61

0x00,

0x00

0x00,

0x00

Primary Base I/O Address (Note 2)

0x70

0xF0

R/W

0x00

-

0x00

-

Primary Interrupt Select

Serial Port 1 Mode Register

LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2)

0x30

R/W

0x00

-

0x00

Activate

0x60,

0x61

0x00,

0x00

0x00,

0x00

Primary Base I/O Address (Note 2)

0x70

0xF0

0xF1

0xF2

R/W

0x00

0x02

0x03

-

0x00

Primary Interrupt Select

Serial Port 2 Mode Register

IR Options Register

-

IR Half Duplex Timeout

LOGICAL DEVICE 6 CONFIGURATION REGISTERS RESERVED

LOGICAL DEVICE 7 CONFIGURATION REGISTERS (Keyboard)

0x30

0x70

R/W

0x00

-

0x00

Activate

Primary Interrupt Select

143

Table 56 - Configuration Registers

HARD RESET

/ Vcc POR

INDEX

TYPE

Vcc POR

SOFT

RESET

CONFIGURATION REGISTER

0x72

0xF0

R/W

0x00

-

0x00

-

Second Interrupt Select

KRESET and GateA20 Select

LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O)

0x30

R/W

0x00

-

0x00

Activate

0x60,

0x61

0x00,

0x00

0x00,

0x00

Primary Base I/O Address (Note 2)

0x62,

0x63

R/W

0x00,

0x00

-

0x00,

0x00

Second Base I/O Address (Note 2)

0xB0

0xB4

0xB5

0xB6

0xB7

0xC7

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

0xDF

0xE0

0xE1

R/W

-

0x00

-

WDT2_VAL

SMI Enable Register 1

SMI Enable Register 2

SMI Status Register 1

SMI Status Register 2

GP47

-

0x01

GP60

GP61

GP62

GP63

GP64

GP65

GP66

GP67

GP70

GP71

GP72

GP73

GP74

GP75

GP76

GP77

GP10

GP11

144

Table 56 - Configuration Registers

HARD RESET

/ Vcc POR

INDEX

TYPE

Vcc POR

SOFT

RESET

CONFIGURATION REGISTER

GP12

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF6

0xF7

0xF8

0xFA

0xFB

R/W

R/W^Note1

R/W

-

0x01

0x00

-

GP13

-

GP14

-

GP15

-

GP16

-

GP17

-

GP20

-

GP21

-

GP22

GP23

-

GP24

-

GP25

-

GP_INT2

GP_INT1

GPR_GPW_EN

WDT_VAL

WDT_CFG

WDT_CTRL

GP1

-

0x00

-

0x00

-

0x00

-

GP2

-

GP4

-

GP6

-

GP7

Note 1: this register contains some bits which are read or write only.

Note 2 : Registers 60 and 62 are the high byte; 61 and 63 are the low byte.

For example to set the primary base address to 1234h, write 12h into 60, and 34h into 61.

145

bits ignore writes and return zero when read.

The INDEX PORT is used to select

Chip Level (Global) Control/Configuration

Registers[0x00-0x2F]

a

configuration register in the chip. The DATA

PORT is then used to access the selected

register. These registers are accessable only in

the Configuration Mode.

The chip-level (global) registers lie in the

address range [0x00-0x2F]. The design MUST

use all 8 bits of the ADDRESS Port for register

selection.

All unimplemented registers and

Table 57 - Chip Level Registers

ADDRESS DESCRIPTION

REGISTER

STATE

Chip (Global) Control Registers

0x00 -

0x01

Reserved - Writes are ignored, reads return 0.

Config Control

0x02 W

The hardware automatically clears this bit after the

write, there is no need for software to clear the bits.

Bit 0 = 1: Soft Reset. Refer to the "Configuration

Registers" table for the soft reset value for each

register.

C

Default = 0x00

on Vcc POR or

Reset_Drv

Index Address

0x03 R/W Bit[7]

= 1 Enable GP1, GP2, WDT_CTRL, GP4, GP6,

GP7, WDT2_VAL and SMI Enable and

Status Register access when not in

configuration mode

Default = 0x03

on Vcc POR or

Reset_Drv

= 0 Disable GP1, GP2, WDT_CTRL, GP4, GP6,

GP7, WDT2_VAL and SMI Enable and

Status Register access when not in

configuration mode (Default)

Bits [6:2]

Reserved - Writes are ignored, reads return 0.

Bits[1:0]

Sets GP index register address, used when in Run

mode (not in Configuration Mode).

= 11

= 10

= 01

= 00

0xEA (Default)

0xE4

0xE2

0xE0

0x04 - 0x06

Reserved - Writes are ignored, reads return 0.

Logical Device #

0x07 R/W A write to this register selects the current logical

device. This allows access to the control and

configuration registers for each logical device.

Note: the Activate command operates only on the

C

Default = 0x00

on Vcc POR or

146

Table 57 - Chip Level Registers

REGISTER

Reset_Drv

ADDRESS

DESCRIPTION

STATE

selected logical device.

Card Level

Reserved

0x08 - 0x1F

0x20 R

Reserved - Writes are ignored, reads return 0.

Chip Level, SMSC Defined

Device ID

A

read only register which provides device

C

identification. Bits[7:0] = 0x48 when read

Hard wired

= 0x48

Device Rev

0x21 R

A read only register which provides device revision

information. Bits[7:0] = 0x01 when read

Hard wired

= 0x01

PowerControl

0x22 R/W Bit[0] FDC Power

Bit[1] Reserved (read as 0)

Default = 0x00.

on Vcc POR or

Reset_Drv hardware

signal.

Bit[2] Reserved (read as 0)

Bit[3] Parallel Port Power

Bit[4] Serial Port 1 Power

Bit[5] Serial Port 2 Power

Bit[6] Reserved (read as 0)

Bit[7] Reserved (read as 0)

= 0

= 1

Power off or disabled

Power on or enabled

Power Mgmt

0x23 R/W Bit[0] FDC

Bit[1] Reserved (read as 0)

C

Default = 0x00.

on Vcc POR or

Reset_Drv hardware

signal

Bit[2] Reserved (read as 0)

Bit[3] Parallel Port

Bit[4] Serial Port 1

Bit[5] Serial Port 2

Bit[6:7] Reserved (read as 0)

= 0 Intelligent Pwr Mgmt off

= 1

Intelligent Pwr Mgmt on

147

Table 57 - Chip Level Registers

DESCRIPTION

REGISTER

OSC

ADDRESS

STATE

0x24 R/W

C

Bit[0] 24/48MHz Clock Select

Default = 0x04, on

Vcc POR or

Reset_Drv hardware

signal.

= 0

= 1

24MHz (Default)

48MHz

Bit [1] PLL Control

= 0 PLL is on (backward Compatible)

= 1 PLL is off

Bits[3:2] OSC

= 01

= 10

= 00

= 11

Osc is on, BRG clock is on.

Same as above (01) case.

Osc is on, BRG Clock Enabled.

Osc is off, BRG clock is disabled.

Bit [6:4] Reserved, set to zero

Bit[7] IRQ8 Polarity

= 0 IRQ8 is active high

= 1 IRQ8 is active low

Chip Level

Vendor Defined

0x25

0x26

Reserved - Writes are ignored, reads return 0.

Bits[7:1] Configuration Address Bits [7:1]

Bit[0] = 0

See Note 1 Below

Configuration

Address Byte 0

C

Default

=0xF0 (Sysopt=0)

=0x70 (Sysopt=1)

on Vcc POR or

Reset_Drv

Configuration

Address Byte 1

0x27

Bit[7:0] Configuration Address Bits [15:8]

See Note 1 Below

Default = 0x03

on Vcc POR or

Reset_Drv

148

Table 57 - Chip Level Registers

DESCRIPTION

REGISTER

Clock Mask

Register

ADDRESS

STATE

Mask clocks as defined below.

0= Clock On, 1= Clock Masked (pin tri-states)

Bit[0] 14.318MHz Clock Output 1

Bits[3:1] Reserved, writes are ignored, reads return

0.

Bit[4] High Speed Clock Out 24/48MHz

Bits[7:5] Reserved - Writes are ignored, reads

return 0.

0x28

Default = 0x00

on VCC POR and

Hard Reset

Chip Level

0x29 -0x2B Reserved - Writes are ignored, reads return 0.

Vendor Defined

TEST 4

TEST 1

TEST 2

TEST 3

0x2C R/W Test Modes: Reserved for SMSC. Users should not

write to this register, may produce undesired

results.

0x2D R/W Test Modes: Reserved for SMSC. Users should not

write to this register, may produce undesired

results.

C

0x2E R/W Test Modes: Reserved for SMSC. Users should not

write to this register, may produce undesired

results.

0x2F R/W Test Modes: Reserved for SMSC. Users should not

write to this register, may produce undesired

results.

Default = 0x00, on

Vcc POR or

Reset_Drv hardware

signal.

Note 1: To allow the selection of the configuration address to a user defined location, these

Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0

is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the

configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte 1;

writing CR27 changes the base address). The configuration address is only reset to its default

address upon a Hard Reset or Vcc POR.

Note: the default configuration address is either 3F0 or 370, as specified by the SYSOPT pin.

This change affects SMSC Mode only.

149

exists for each logical device and is selected

with the Logical Device # Register (0x07).

Logical

Registers [0x30-0xFF]

Device

Configuration/Control

The INDEX PORT is used to select a specific

logical device register. These registers are then

accessed through the DATA PORT.

Used to access the registers that are assigned

to each logical unit. This chip supports six

logical units and has six sets of logical device

registers. The six logical devices are Floppy,

The Logical Device registers are accessible only

when the device is in the Configuration State.

The logical register addresses are:

Parallel, Serial

Controller, and Auxiliary_I/O. A separate set

(bank) of control and configuration registers

1 and Serial 2, Keyboard

Table 58 - Logical Device Registers

LOGICAL DEVICE

REGISTER

ADDRESS

DESCRIPTION

STATE

Activate^Note1

(0x30)

Bits[7:1] Reserved, set to zero.

Bit[0]

C

Default = 0x00

= 1 Activates the logical device currently

selected through the Logical Device

# register.

on Vcc POR or

Reset_Drv

= 0

Logical device currently selected is

inactive

Logical Device Control

Mem Base Addr

(0x31-0x37) Reserved - Writes are ignored, reads return

0.

C

(0x38-0x3f) Vendor Defined - Reserved - Writes are

ignored, reads return 0.

(0x40-0x5F) Reserved - Writes are ignored, reads return

0.

I/O Base Addr.

(0x60-0x6F) Registers 0x60 and 0x61 set the base

address for the device. If more than one

(see Device Base I/O

Address Table)

0x60,2,... = base address is required, the second base

addr[15:8]

address is set by registers 0x62 and 0x63.

Refer to Table 64 for the number of base

address registers used by each device.

Default = 0x00

0x61,3,... =

addr[7:0]

on Vcc POR or

Reset_Drv

Unused registers will ignore writes and return

zero when read.

150

Table 58 - Logical Device Registers

LOGICAL DEVICE

REGISTER

ADDRESS

(0x70,072)

DESCRIPTION

STATE

Interrupt Select

0x70 is implemented for each logical device.

Refer to Interrupt Configuration Register

description. Only the keyboard controller

uses Interrupt Select register 0x72. Unused

register (0x72) will ignore writes and return

zero when read. Interrupts default to edge

high (ISA compatible).

C

Defaults :

0x70 = 0x00,

on Vcc POR or

Reset_Drv

0x72 = 0x00,

on Vcc POR or

Reset_Drv

(0x71,0x73) Reserved - not implemented. These register

locations ignore writes and return zero when

read.

DMA Channel Select

(0x74,0x75) Only 0x74 is implemented for FDC, Serial

C

Port 2 and Parallel port.

0x75 is not

Default = 0x04

on Vcc POR or

Reset_Drv

implemented and ignores writes and returns

zero when read. Refer to DMA Channel

Configuration.

32-Bit Memory Space

Configuration

(0x76-0xA8) Reserved - not implemented. These register

locations ignore writes and return zero when

read.

Logical Device

Logical Device Config.

Reserved

(0xA9-0xDF) Reserved - not implemented. These register

locations ignore writes and return zero when

read.

C

(0xE0-0xFE) Reserved - Vendor Defined (see SMSC

defined

Logical

Device

Configuration

Registers)

0xFF

Reserved

Note 1: A logical device will be active and powered up according to the following equation:

DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).

The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting

or clearing one sets or clears the other. If the I/O Base Addr of the logical device is

not within the Base I/O range as shown in the Logical Device I/O map, then read or

write is not valid and is ignored.

151

Table 59 - I/O Base Address Configuration Register Description

LOGICAL LOGICAL REGISTER

BASE I/O

RANGE

FIXED

BASE OFFSETS

DEVICE

INDEX

NUMBER

(NOTE3)

0x00

FDC

0x60,0x61

[0x100:0x0FF8]

+0 : SRA

+1 : SRB

ON 8 BYTE BOUNDARIES +2 : DOR

+3 : TSR

+4 : MSR/DSR

+5 : FIFO

+7 : DIR/CCR

0x03

Parallel

Port

0x60,0x61

[0x100:0x0FFC]

ON 4 BYTE BOUNDARIES +1 : Status

+0 : Data|ecpAfifo

(EPP Not supported)

or

+2 : Control

+3 : EPP Address

+4 : EPP Data 0

[0x100:0x0FF8]

ON 8 BYTE BOUNDARIES +5 : EPP Data 1

(all modes supported, +6 : EPP Data 2

EPP is only available when +7 : EPP Data 3

the base address is on an 8- +400h : cfifo|ecpDfifo|tfifo

byte boundary)

|cnfgA

+401h : cnfgB

+402h : ecr

0x04

0x05

0x07

Serial Port 0x60,0x61

1

[0x100:0x0FF8]

+0 : RB/TB|LSB div

+1 : IER|MSB div

ON 8 BYTE BOUNDARIES +2 : IIR/FCR

+3 : LCR

+4 : MSR

+5 : LSR

+6 : MSR

+7 : SCR

Serial Port 0x60,0x61

2

[0x100:0x0FF8]

+0 : RB/TB|LSB div

+1 : IER|MSB div

ON 8 BYTE BOUNDARIES +2 : IIR/FCR

+3 : LCR

+4 : MSR

+5 : LSR

+6 : MSR

+7 : SCR

KYBD

Not Relocatable

+0 : Data Register

n/a

Fixed Base Address: 60,64 +4 : Command/Status Reg.

152

Table 59 - I/O Base Address Configuration Register Description

LOGICAL LOGICAL REGISTER

BASE I/O

RANGE

FIXED

BASE OFFSETS

DEVICE

INDEX

NUMBER

(NOTE3)

0x08

Aux. I/O

0x60,0x61

0x62,0x63

[0x00:0xFFF]

ON 1 BYTE BOUNDARIES

+0 : GPR

+0 : GPW

[0x00:0xFFF]

ON 1 BYTE BOUNDARIES

Note:

This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical

devices.

153

Table 60 - Interrupt Select Configuration Register Description

NAME

Interrupt

REG INDEX

DEFINITION

STATE

0x70 (R/W)

Bits[3:0] selects which interrupt level is used for

C

Request Level

Select 0

Interrupt 0.

0x00=no interrupt selected.

0x01=IRQ1

0x02=IRQ2

0x03=IRQ3

Default = 0x00

on Vcc POR or

Reset_Drv

•

0x0D=IRQ13

0x0E=IRQ14

0x0F=IRQ15

Note: All interrupts are edge high (except ECP/EPP)

Note:

An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero

value AND :

for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.

for the PP logical device by setting IRQE, bit D4 of the Control Port and in addition

for the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.

for the Serial Port logical device by setting any combination of bits D0-D3 in the IER

and by setting the OUT2 bit in the UART's Modem Control (MCR) Register.

for the RTC by (refer to the RTC section of this spec.)

for the KYBD by (refer to the KYBD controller section of this spec.)

IRQs must be disabled if not used/selected by any Logical Device. Refer to Note A.

Note:

Table 61 - DMA Channel Select Configuration Register Description

NAME

REG INDEX

DEFINITION

STATE

DMA Channel

Select

0x74 (R/W)

Bits[2:0] select the DMA Channel.

0x00=DMA_A

C

0x01=DMA_B

0x02=DMA_C

0x03-0x07= No DMA active

Default = 0x04

on Vcc POR or

Reset_Drv

Note:

A DMA channel is activated by setting the DMA Channel Select register to [0x00-0x03] AND :

for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.

for the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.

Note:

DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.

Note A. Logical Device IRQ and DMA Operation

154

1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a

register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to

the IRQ and DACK disabled by the Configuration Registers (active bit or address not valid).

a. FDC: For the following cases, the IRQ and DACK used by the FDC are disabled (high

impedance). Will not respond to the DREQ

I. Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".

II. The FDC is in power down (disabled).

b. Serial Port 1 and 2:

Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the

serial port interrupt is forced to a high impedance state - disabled.

c. Parallel Port:

I. SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is

disabled (high impedance).

ii. ECP Mode:

(1) (DMA) dmaEn from ecr register. See table.

(2) IRQ - See table.

MODE

IRQ PIN

PDREQ PIN

(FROM ECR REGISTER)

CONTROLLED BY CONTROLLED BY

000

001

010

011

100

101

110

111

PRINTER

SPP

IRQE

(on)

dmaEn

FIFO

ECP

(on)

EPP

IRQE

(on)

RES

TEST

CONFIG

IRQE

d. Game Port and ADDR: no IRQ or DACK used.

e. Keyboard Controller: Refer to the KBD section of this spec.

155

Registers reset to their default values only on

hard resets generated by Vcc or VTR POR (as

shown) or the RESET_DRV signal. These

registers are not affected by soft resets.

SMSC Defined Logical Device Configuration

Registers

The

SMSC

Specific

Logical

Device

Configuration

Table 62 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00]

NAME

REG INDEX

DEFINITION

STATE

FDD Mode Register

0xF0 R/W Bit[0] Floppy Mode

C

= 0 Normal Floppy Mode (default)

= 1 Enhanced Floppy Mode 2 (OS2)

Bit[1] FDC DMA Mode

Default = 0x0E

on Vcc POR or

Reset_Drv

= 0

= 1

Burst Mode is enabled

Non-Burst Mode (default)

Bit[3:2] Interface Mode

= 11

= 10

= 01

= 00

AT Mode (default)

(Reserved)

PS/2

Model 30

Bit[4] Swap Drives 0,1 Mode

= 0

= 1

No swap (default)

Drive and Motor sel 0 and 1 are

swapped.

Bit[5] Reserved, set to zero.

Bit[6] FDC Output Type Control

= 0

= 1

FDC outputs are OD24 open drain (default)

FDC outputs are O24 push-pull

Bit[7] FDC Output Control

= 0

= 1

FDC outputs active (default)

FDC outputs tri-stated

Note: Bits 6 & 7 do not affect the parallel port FDC

pins

FDD Option

Register

0xF1 R/W Bits[1:0] Reserved, set to zero

Bits[3:2] Density Select

C

= 00

= 01

= 10

= 11

Normal (default)

Default = 0x00

Normal (reserved for users)

1 (forced to logic "1")

0 (forced to logic "0")

on Vcc POR or

Reset_Drv

Bit[4] Media ID 0 Polarity

= 0: Don’t invert (default)

= 1: Invert

Bit[5] Media ID 1 Polarity

= 0: Don’t invert (default)

156

Table 62 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00]

NAME

REG INDEX

DEFINITION

STATE

= 1: Invert

Bits[7:6] Boot Floppy

= 00

= 01

= 10

FDD 0 (default)

FDD 1

Reserved (neither drive A or B is a boot

drive).

= 11

Reserved (neither drive A or B is a boot

drive).

FDD Type Register

Default = 0xFF

0xF2 R/W Bits[1:0] Floppy Drive A Type

Bits[3:2] Floppy Drive B Type

C

Bits[5:4] Reserved (could be used to store Floppy

Drive C type)

Bits[7:6] Reserved (could be used to store Floppy

Drive D type)

on Vcc POR or

Reset_Drv

Note: The FDC37C68x supports two

floppy drives

0xF3 R

Reserved, Read as 0 (read only)

C

FDD0

0xF4 R/W Bits[1:0] Drive Type Select: DT1, DT0

Bits[2] Read as 0 (read only)

Default = 0x00

Bits[4:3] Data Rate Table Select: DRT1, DRT0

Bits[5] Read as 0 (read only)

Bits[6] Precompensation Disable PTS

=0 Use Precompensation

on Vcc POR or

Reset_Drv

=1 No Precompensation

Bits[7] Read as 0 (read only)

FDD1

0xF5 R/W Refer to definition and default for 0xF4

C

Reserved, Logical Device 1 [Logical Device Number 0x01]

Reserved. Logical Device 2 [Logical Device Number 0x02]

157

Table 63 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03]

NAME

REG INDEX

DEFINITION

STATE

PP Mode Register

0xF0 R/W Bits[2:0] Parallel Port Mode

= 100 Printer Mode (default)

C

Default = 0x3C

= 000 Standard and Bi-directional (SPP) Mode

= 001 EPP-1.9 and SPP Mode

= 101 EPP-1.7 and SPP Mode

= 010 ECP Mode

on Vcc POR or

Reset_Drv

= 011 ECP and EPP-1.9 Mode

= 111 ECP and EPP-1.7 Mode

Bit[6:3] ECP FIFO Threshold

0111b (default)

Bit[7] PP Interupt Type

Not valid when the parallel port is in the Printer

Mode (100) or the Standard & Bi-directional Mode

(000).

= 1 Pulsed Low, released to high-Z.

= 0 IRQ follows nACK when parallel port in EPP

Mode or [Printer,SPP, EPP] under ECP.

IRQ level type when the parallel port is in ECP,

TEST, or Centronics FIFO Mode.

Bits[1:0] PPFDC - muxed PP/FDC control

= 00 Normal Parallel Port Mode

= 01 PPFD1: Drive 0 is on the FDC pins

Drive 1 is on the Parallel port pins

Drive 2 is on the FDC pins

PP Mode Register 2

0xF1 R/W

Default = 0x00

on Vcc POR or

Reset_Drv

Drive 3 is on the FDC pins

= 10 PPFD2: Drive 0 is on the Parallel port pins

Drive 1 is on the Parallel port pins

Drive 2 is on the FDC pins

Drive 3 is on the FDC pins

Bits[7:2] Reserved. Set to zero.

158

Table 64 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]

NAME

REG INDEX

DEFINITION

STATE

Serial Port 1

0xF0 R/W Bit[0] MIDI Mode

C

Mode Register

= 0 MIDI support disabled (default)

= 1 MIDI support enabled

Default = 0x00

Bit[1] High Speed

= 0 High Speed Disabled(default)

= 1 High Speed Enabled

on Vcc POR or

Reset_Drv

Bit[6:2] Reserved, set to zero

Bit[7]: Share IRQ

=0 UARTS use different IRQs

=1 UARTS share a common IRQ

see Note 1 below.

Note 1: To properly share and IRQ,

1. Configure UART1 (or UART2) to use the desired IRQ pin.

2. Configure UART2 (or UART1) to use No IRQ selected.

3. Set the share IRQ bit.

Note: If both UARTs are configured to use different IRQ pins and the share IRQ bit is set,

both of the UART IRQ pins will assert when either UART generates an interrupt.

then

UART Interrupt Operation Table

Table 65 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]

NAME

REG INDEX

DEFINITION

STATE

Serial Port 2

0xF0 R/W Bit[0] MIDI Mode

C

Mode Register

= 0 MIDI support disabled (default)

= 1 MIDI support enabled

Bit[1] High Speed

Default = 0x00

= 0 High Speed disabled(default)

= 1 High Speed enabled

Bit[7:2] Reserved, set to zero

on Vcc POR or

Reset_Drv

159

Table 65 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]

NAME

REG INDEX

DEFINITION

STATE

IR Option Register

0xF1 R/W Bit[0] Receive Polarity

= 0 Active High (Default)

= 1 Active Low

C

Default = 0x02

on Vcc POR or

Reset_Drv

Bit[1] Transmit Polarity

= 0 Active High

= 1 Active Low (Default)

Bit[2] Duplex Select

= 0 Full Duplex (Default)

= 1 Half Duplex

Bits[5:3] IR Mode

= 000 Standard (Default)

= 001 IrDA

= 010 ASK-IR

= 011 Reserved

= 1xx

Reserved

Bit[6] IR Location Mux

= 0 Use Serial port TX2 and RX2 (Default)

= 1 Use alternate IRRX (GP12) and IRTX (GP13)

Bit[7] Reserved, write 0.

IR Half Duplex

Timeout

0xF2

Bits [7:0]

These bits set the half duplex time-out for the IR port.

This value is 0 to 10msec in 100usec increments.

0= blank during transmit/receive

1= blank during transmit/receive + 100usec

. . .

Default = 0x03

on Vcc POR or

Reset_Drv

160

Reserved, Logical Device 6 [Logical Device Number = 0x06]

Table 66 - KYBD, Logical Device 7 [Logical Device Number = 0x07]

NAME

REG INDEX

0xF0

DEFINITION

KRESET and GateA20 Select

STATE

KRST_GA20

R/W

Bit[7] Polarity Select for P12

= 0 P12 active low (default)

= 1 P12 active high

Default = 0x00

on Vcc POR or

Reset_Drv

Bits[6:3] Reserved

Bit[2] Port 92 Select

= 0 Port 92 Disabled

= 1 Port 92 Enabled

Bit[1:0] Reserved

0xF1 -

0xFF

Reserved - read as ‘0’

Table 67 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG

INDEX

DEFINITION

STATE

WDT2_VAL

(Note 1)

0xB0 R/W

Watchdog Timer 2 Timeout Value Binary coded, units

= 250 msec

0x00 Timeout = 64 Seconds

0x01 Timeout = 250 msec

……

Default = 0x00 on

Vcc POR or

Reset_Drv

0xFF Timeout = 63.75 seconds

SMI Enable

Register 1 (Note 1)

0xB4 R/W

This register is used to enable the different interrupt

sources onto the group nSMI output.

C

1=Enable

0=Disable

Default = 0x00

on VCC POR

Bit[0] RESERVED

Bit[1] EN_PINT

Bit[2] EN_U2INT

Bit[3] EN_U1INT

Bit[4] EN_FINT

Bit[5] EN_GPINT2

Bit[6] EN_GPINT1

Bit[7] EN_WDT

161

Table 67 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG

INDEX

DEFINITION

STATE

SMI Enable

Register 2 (Note 1)

0xB5 R/W

This register is used to enable the different interrupt

sources onto the group nSMI output, and the group

nSMI output onto the nSMI GPI/O pin.

C

Default = 0x00

on VCC POR

Unless otherwise noted,

1=Enable

0=Disable

Bit[0] EN_MINT

Bit[1] EN_KINT

Bit[2] EN_IRINT

Bit[3] RESERVED

Bit[4] EN_P12: Enable 8042 P1.2 to route internally

to nSMI. 0=Do not route to nSMI, 1=Enable

routing to nSMI.

Bit[5] RESERVED

Bit[6] EN_SMI_S: Enable the group nSMI output

onto the Serial IRQ SMI Frame.

Bit[7] EN_SMI: Enable the group nSMI output onto

the nSMI GPI/O pin. 0=SMI pin floats,

1=Enable group nSMI output onto nSMI

GPI/O pin.

SMI Status

Register 1 (Note 1)

0xB6 R/W

This register is used to read the status of the SMI

inputs.

C

Default = 0x00

on VCC POR

The following bits must be cleared at their source.

Bit[0] RESERVED

Bit[1] PINT (Parallel Port Interrupt)

Bit[2] U2INT (UART 2 Interrupt)

Bit[3] U1INT (UART 1 Interrupt)

Bit[4] FINT (Floppy Disk Controller Interrupt)

Bit[5] GPINT2 (Group Interrupt 2)

Bit[6] GPINT1 (Group Interrupt 1)

Bit[7] WDT (Watch Dog Timer)

162

Table 67 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG

INDEX

DEFINITION

STATE

SMI Status

Register 2 (Note 1)

0xB7 R/W

This register is used to read the status of the SMI

inputs.

C

Bit[0] MINT: Mouse Interrupt. Cleared at source.

Bit[1] KINT: Keyboard Interrupt. Cleared at source.

Bit[2] IRINT: This bit is set by a transition on the IR

pin (RDX2 or GP12 as selected in CR L5-F1-

B6 i.e., after the MUX). Cleared by a read of

this register.

Default = 0x00

on VCC POR

Bit[3] Reserved

Bit[4] P12: 8042 P1.2. Cleared at source

Bits[5:7] Reserved

Note 1: WDT2_VAL, SMI enable and Status Registers are also available at index 08-0F when not

in configuration mode. See Table 47B.

163

Unless otherwise noted, the Definition for the GP Registers below all have the following form:

Bit[0] In/Out: =1 Input, =0 Output

Bit[1] Polarity: =1 Invert, =0 No Invert

Bit[2] Int En 1:

=1 Enable Combined IRQ 1

=0 Disable Combined IRQ 1

Bits[4:3] Function Select

=00 Original Function

=01 Alternate Function 1

=10 Alternate Function 2 (or Reserved)

=11 Alternate Function 3 (or Reserved)

Bit[5] Reserved

Bit[6] Int En 2

=1 Enable Combined IRQ 2

=0 Disable Combined IRQ 2

Bit[7] Open Collector: =1 Open Collector, =0 Push Pull

Therefore, unless otherwise required, only Bits[4:3] are defined in the following table.

164

Table 67 (cont’d) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

0xC0-0xC6

0xC7

DEFINITION

STATE

Reserved

C

GP47

General Purpose I/O bit 4.7

Bits[4:3] Function Select

=00 GP I/O

Default = 0x01

on VCC POR

=01 GPI/O

=10 nSMI

=11 Reserved

0xC8-0xCF

0xD0

Reserved

C

GP60

General Purpose I/O bit 6.0

Bits[4:3] Function Select

=00 Reserved

Default = 0x01

on VCC POR

=01 GPI/O

=10 Power Led Output

=11 Reserved

GP61

0xD1

0xD2

0xD3

0xD4

General Purpose I/O bit 6.1

Bits[4:3] Function Select

=00 Reserved

=01 GPI/O

=10 WDT

C

Default = 0x01

on VCC POR

=11 Reserved

GP62

General Purpose I/O bit 6.2

Bits[4:3] Function Select

=00 Reserved

=01 GPI/O

=10 8042 - P12

=11 Reserved

General Purpose I/O bit 6.3

Bits[4:3] Function Select

=00 Reserved

=01 GPI/O

=10 8042 - P13

=11 Reserved

Default = 0x01

on VCC POR

GP63

Default = 0x01

on VCC POR

GP64

General Purpose I/O bit 6.4

Bits[4:3] Function Select

=00 Reserved

Default = 0x01

on VCC POR

=01 GPI/O

=10 8042 - P14

=11 Reserved

165

Table 67 (cont’d) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

GP65

REG INDEX

DEFINITION

General Purpose I/O bit 6.5

Bits[4:3] Function Select

=00 Reserved

STATE

0xD5

C

Default = 0x01

on VCC POR

=01 GPI/O

=10 8042 - P15

=11 Reserved

GP66

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

General Purpose I/O bit 6.6

Bits[4:3] Function Select

=00 Reserved

=01 GPI/O

=10 8042 - P16

C

Default = 0x01

on VCC POR

=11 Reserved

GP67

General Purpose I/O bit 6.7

Bits[4:3] Function Select

=00 Reserved

=01 GPI/O

=10 8042 - P17

Default = 0x01

on VCC POR

=11 Reserved

GP70

General Purpose I/O bit 7.0

Bits[4:3] Function Select

=00 nRI2

=01 GPI/O

=10 Reserved

Default = 0x01

on VCC POR

=11 Reserved

GP71

General Purpose I/O bit 7.1

Bits[4:3] Function Select

=00 nDCD2

=01 GPI/O

=10 Reserved

Default = 0x01

on VCC POR

=11 Reserved

GP72

General Purpose I/O bit 7.2

Bits[4:3] Function Select

=00 RXD2

=01 GPI/O

=10 Reserved

Default = 0x01

on VCC POR

=11 Reserved

GP73

General Purpose I/O bit 7.3

Bits[4:3] Function Select

=00 TXD2

Default = 0x01

on VCC POR

=01 GPI/O

=10 Reserved

=11 Reserved

166

Table 67 (cont’d) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

GP74

REG INDEX

DEFINITION

General Purpose I/O bit 7.4

Bits[4:3] Function Select

=00 nDSR2

STATE

0xDC

C

Default = 0x01

on VCC POR

=01 GPI/O

=10 Reserved

=11 Reserved

GP75

0xDD

0xDE

0xDF

General Purpose I/O bit 7.5

Bits[4:3] Function Select

=00 nRTS2

=01 GPI/O

=10 Reserved

C

Default = 0x01

on VCC POR

=11 Reserved

GP76

General Purpose I/O bit 7.6

Bits[4:3] Function Select

=00 nCTS2

=01 GPI/O

=10 Reserved

Default = 0x01

on VCC POR

=11 Reserved

GP77

General Purpose I/O bit 7.7

Bits[4:3] Function Select

=00 nDTR2

Default = 0x01

on VCC POR

=01 GPI/O

=10 Reserved

=11 Reserved

167

Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

General Purpose I/0 bit 1.0

STATE

GP10

0xE0

C

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

Default = 0x01

on VCC POR

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bit[3] Alt Func

(If configured as input, the input signal is steered to

the selected IRQ)

=1 Select alternate function

=0 Select basic I/O function

Bits[7:4] Alt Fuct IRQ mapping

1111 = IRQ15

.........

0011 = IRQ3

0010 = IRQ2

0001 = IRQ1

0000 = Disable

GP11

0xE1

General Purpose I/0 bit 1.1

C

Default = 0x01

Bit[0] In/Out: =1 input, =0 Output

on VCC POR

Bit[1] Polarity: =1 invert, =0 No invert

Bit[2] Int En

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bit[3-7] These bits are used for selection of the pin

function as follows:

Bit

7 6 5 4 3 Function Output type IRQ Mapping

0 x x 0 0 GPIO

1 x x 0 0 GPIO

0 x x 1 0 Reserved

1 x x 1 0 Reserved

1 1 1 1 1 IRQIN

1 1 1 0 1 IRQIN

1 1 0 1 1 IRQIN

.....

Push Pull

N/A

Open Collector N/A

Push Pull

IRQ15

IRQ14

IRQ13

0 0 1 1 1 IRQIN

Push Pull

IRQ3

168

Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

Push Pull

STATE

0 0 1 0 1 IRQIN

0 0 0 1 1 IRQIN

0 0 0 0 1 IRQIN

IRQ2

IRQ1

Disable

GP12

0xE2

General Purpose I/0 bit 1.2

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity :=1 Invert, =0 No Invert

Bit[2] Int En

=1 Enable Combined IRQ

=0 Disable Combined IRQ

C

Default = 0x01

on VCC POR

Bit[3] Alt Func : WDT output or IRRX input.

=1 Select alternate function

=0 Select basic I/O function

(IRRX - if bit-6 of the IR Options Register is set)

Bits[7:4] : Reserved = 0000

GP13

0xE3

0xE4

0xE5

General Purpose I/0 bit 1.3

C

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bit[3] Alt Func : Power LED or IRTX output

=1 Select alternate function

=0 Select basic I/O function

(IRTX - if bit-6 of the IR Options Register is set)

Bits[7:4] Reserved = 0000

Default = 0x01

on VCC POR

GP14

General Purpose I/0 bit 1.4

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bit[3] Alt Func: General Purpose Address Decode

(Active Low) Decodes two address bytes

=1 Select alternate function

=0 Select basic I/O function

Bits[7:4] Reserved = 0000

Default = 0x01

on VCC POR

GP15

General Purpose I/0 bit 1.5

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

Default = 0x01

on VCC POR

=1 Enable Combined IRQ

169

Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

=0 Disable Combined IRQ

STATE

Bits[4:3] Alt Function Select

=00 Basic I/O Function

=01 GP Write Strobe

=10 WDT2

=11 Reserved

Bits[7:5] Reserved = 0000

GP16

0xE6

General Purpose I/0 bit 1.6

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

C

Default = 0x01

on VCC POR

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bit[4:3] Alt Func: Joystick (Active Low)

=01 Joystick RD Stb function

=10 Joystick CS function

=00 Select basic I/O function

Bits[7:5] Reserved = 000

GP17

0xE7

General Purpose I/0 bit 1.7

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

C

Default = 0x01

on VCC POR

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bit[3] Alt Function Select

=1 Select Joystick Write Strobe

=0 Select basic I/O function

Bits[7:4] Reserved = 0000

GP20

0xE8

General Purpose I/0 bit 2.0

C

Bit[0] In/Out :

=1 Input, =0 Output

Default = 0x01

on VCC POR

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En :=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bit[3] Reserved

Bit[4] Alt func: 8042 P20, Typically used to generate

a "Keyboard Reset" used by systems in order to

switch from "protected mode" back to "real mode"

=1 Select alternate function

=0 Select basic I/O function

Bits[7:5] Reserved = 0000

GP21

0xE9

General Purpose I/0 bit 2.1

C

170

Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

STATE

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bits[6:3] Reserved = 0000

Default = 0x01

on VCC POR

Bit[7] Open Collector:

=1 Open Collector,

=0 Push Pull

GP22

0xEA

General Purpose I/0 bit 2.2

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bits[6:3] Reserved = 0000

C

Default = 0x01

on VCC POR

Bit[7] Open Collector:

=1 Open Collector,

=0 Push Pull

GP23

0xEB

0xEC

0xED

General Purpose I/0 bit 2.3

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bits[7:3] Reserved = 00000

C

Default = 0x01

on VCC POR

GP24

General Purpose I/0 bit 2.4

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En

=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bits[7:3] Reserved = 00000

Default = 0x01

on VCC POR

GP25

General Purpose I/0 bit 2.5

Bit[0] In/Out :

=1 Input, =0 Output

Default = 0x01

on VCC POR

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Int En :=1 Enable Combined IRQ

=0 Disable Combined IRQ

Bit[3] Alt Func: GATEA20

=1 Select alternate function

171

Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

STATE

=0 Select basic I/O function

Bits[7:4] : Reserved, = 0000

0xEE

0xEF

Reserved

C

GP_INT2

General Purpose I/O Combined Interrupt 2

Bits[2:0] Reserved, = 000

Default = 0x00

on VCC POR

Bit[3] GP IRQ Filter Select

0 = Debounce Filter Bypassed

1 = Debounce Filter Enabled

Bits[7:4] Combined IRQ mapping

1111 = IRQ15

.........

0011 = IRQ3

0010 = IRQ2

0001 = IRQ1

0000 = Disable

GP_INT1

0xF0

General Purpose I/O Combined Interrupt 1

Bits[2:0] Reserved, = 000

C

Default = 0x00

on VCC POR

Bit[3] GP IRQ Filter Select

0 = Debounce Filter Bypassed

1 = Debounce Filter Enabled

Bits[7:4] Combined IRQ mapping

1111 = IRQ15

.........

0011 = IRQ3

0010 = IRQ2

0001 = IRQ1

0000 = Disable

GPA_GPW_EN

Default = 0x00

0xF1

General Purpose Read/Write enable

C

Bit[0]

=0 disable GPA decoder.

Bit[1] =1 enable GPW, =0 disable GPW

Bits[6:2] Reserved, = 00000

=1 enable GP Addr Decoder

on Vcc POR or

Reset_Drv

Bit[7] WDT Time-out Value Units Select

= 0 250 msec (default)

= 1 Seconds

Note: if the logical device's activate bit is not set then

bits 0 and 1 have no effect.

WDT_VAL

0xF2

Watch-dog Timer Time-out Value

C

172

Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

STATE

Binary coded, units = 250 msec. or seconds,

selectable via Bit[7] of Reg 0xF1, LD 8.

0x00 Time out disabled

0x01 Time-out = 1 second or 250msec.

.........

Default = 0x00

on Vcc POR or

Reset_Drv

0xFF Time-out = 255 seconds or 63.75 sec

WDT_CFG

0xF3

Watch-dog timer Configuration

Bit[0] Joy-stick Enable

C

Default = 0x00

=1 WDT is reset upon an I/O read or write of the

Game Port

=0 WDT is not affected by I/O reads or writes to the

Game Port.

on Vcc POR or

Reset_Drv

Bit[1] Keyboard Enable

=1 WDT is reset upon a Keyboard interrupt.

=0 WDT is not affected by Keyboard interrupts.

Bit[2] Mouse Enable

=1 WDT is reset upon a Mouse interrupt

=0 WDT is not affected by Mouse interrupts.

Bit[3] PWRLED Time-out enable

=1 Enables the Power LED to toggle at a 1Hz rate

with 50 percent duty cycle while the Watch-

dog Status bit is set.

=0 Disables the Power LED toggle during Watch-

dog timeout status.

Bits[7:4] WDT Interrupt Mapping

1111 = IRQ15

.........

0011 = IRQ3

0010 = IRQ2

0001 = IRQ1

0000 = Disable

WDT_CTRL

(Note 1)

0xF4

Watch-dog timer Control

Bit[0] Watch-dog Status Bit, R/W

=1 WD timeout occured

C

Default = 0x00

=0 WD timer counting

Bit[1] Power LED Toggle Enable, R/W

=1 Toggle Power LED at 1Hz rate with 50 percent

duty cycle. (1/2 sec. on, 1/2 sec. off)

=0 Disable Power LED Toggle

Cleared by VCC

POR

Bit[2] Force Timeout, W

=1 Forces WD timeout event; this bit is self-clearing

Bit[3] P20 Force Timeout Enable, R/W

173

Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

STATE

= 1 Allows rising edge of P20, from the Keyboard

Controller, to force the WD timeout event. A

WD timeout event may still be forced by

setting the Force Timeout Bit, bit 2.

= 0 P20 activity does not generate the WD timeout

event.

Note: The P20 signal will remain high for a minimum

of 1us and can remain high indefinitely. Therefore,

when P20 forced timeouts are enabled, a self-

clearing edge-detect circuit is used to generate a

signal which is ORed with the signal generated by

the Force Timeout Bit.

Bit[4] WDT2 SMI Timeout Enable

=0 Disable WDT2 (default)

=1 Enable WDT2

Bit[7:5] Reserved. Set to 0

This register is used to directly access the GP1x pins

(Note 2).

bit 0: GP10

bit 1: GP11

GP1 (Note 1)

0xF6

Default = 0x00

on Vcc POR or

Reset_Drv

bit 2: GP12

bit 3: GP13

bit 4: GP14

bit 5: GP15

bit 6: GP16

bit 7: GP17

This register is used to directly access the GP2x pins

(Note 2).

GP2 (Note 1)

0xF7

bit 0: GP20

bit 1: GP21

bit 2: GP22

bit 3: GP23

bit 4: GP24

bit 5: GP25

bits 6,7: Reserved

Default = 0x00

on Vcc POR or

Reset_Drv

GP4 (Note 1)

0xF8

0xFA

This register is used to directly access the GP4x pin

(Note 2).

bits 0-6: Reserved

bit 7: GP47

Default = 0x00

on Vcc POR or

Reset_Drv

This register is used to directly access the GP6x pins

174

GP6 (Note 1)

Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

STATE

(Note 2).

bit 0: GP60

bit 1: GP61

bit 2: GP62

bit 3: GP63

bit 4: GP64

bit 5: GP65

bit 6: GP66

bit 7: GP67

Default = 0x00

on Vcc POR or

Reset_Drv

This register is used to directly access the GP7x pins

(Note 2).

GP7 (Note 1)

0xFB

bit 0: GP70

bit 1: GP71

bit 2: GP72

bit 3: GP73

bit 4: GP74

bit 5: GP75

bit 6: GP76

bit 7: GP77

Default = 0x00

on Vcc POR or

Reset_Drv

Note1: Registers GP1-2, WDT_CTRL, GP4, GP6, GP7 are also available at index 01-07 when not in

configuration mode. See Table 47B.

Note 2: When a GPI/O port is programmed as an input, reading it through the GPI/O register latches

either the inverted or non-inverted logic value present at the GPI/O pin; writing it has no effect. When

a GPI/O port is programmed as an output, the logic value written into the GPI/O register is either

output to or inverted to the GPI/O pin; when read the result will reflect the contents of the GPI/O

register bit.

175

OPERATIONAL DESCRIPTION

MAXIMUM GUARANTEED RATINGS*

Operating Temperature Range......................................................................................... 0^oC to +70^oC

Storage Temperature Range..........................................................................................-55^oto +150^oC

Lead Temperature Range (soldering, 10 seconds) ....................................................................+325^oC

Positive Voltage on any pin, with respect to Ground................................................................V_cc+0.3V

Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V

Maximum V_cc................................................................................................................................. +7V

*Stresses above those listed above could cause permanent damage to the device. This is a stress

rating only and functional operation of the device at any other condition above those indicated in the

operation sections of this specification is not implied.

Note: When powering this device from laboratory or system power supplies, it is important that the

Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit

voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage

transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested

that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS (T_A= 0°C - 70°C, V_cc= +5 V ± 10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

COMMENTS

I Type Input Buffer

V_ILI

V_IHI

0.8

V

TTL Levels

Low Input Level

2.0

High Input Level

IS Type Input Buffer

V_ILIS

V_IHIS

V_HYS

0.8

0.4

V

Schmitt Trigger

Low Input Level

High Input Level

2.2

250

mV

Schmitt Trigger Hysteresis

ICLK Input Buffer

V_ILCK

V_IHCK

V

Low Input Level

High Input Level

2.2

176

PARAMETER

Input Leakage

SYMBOL

MIN

TYP

MAX

UNITS

COMMENTS

(All I and IS buffers)

I_IL

-10

+10

V_IN= 0

Low Input Leakage

mA

I_IH

V_IN= V_CC

High Input Leakage

O4 Type Buffer

V_OL

V_OH

I_OL

0.4

V

I_OL= 4 mA

I_OH= -2 mA

Low Output Level

High Output Level

Output Leakage

2.4

-10

+10

V_IN= 0 to V_CC

(Note 1)

mA

O20 Type Buffer

Low Output Level

High Output Level

V_OL

V_OH

I_OL

0.4

V

I_OL= 20 mA

I_OH= -10 mA

2.4

-10

+10

0.4

Output Leakage

mA

O24 Type Buffer

V_OL

V_OH

I_OL

V

I_OL= 24 mA

I_OH= -12 mA

Low Output Level

High Output Level

Output Leakage

2.4

-10

+10

V_IN= 0 to V_CC

(Note 1)

mA

O16SR Type Buffer

Low Output Level

High Output Level

Output Leakage

Rise Time

V_OL

V_OH

I_OL

0.4

V

I_OL= 16 mA

I_OH= -16 mA

2.4

-10

5

+10

V_IN= 0 to V_CC

(Note 1)

mA

ns

T_RT

T_FL

5

Fall Time

177

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

COMMENTS

OD16P Type Buffer

V_OL

I_OL

0.4

V

I_OL= 16 mA

Low Output Level

Output Leakage

I_OH= 90 mA

V_IN= 0 to V_CC

(Note 1)

-10

+10

mA

OD24 Type Buffer

Low Output Level

Output Leakage

V_OL

I_OL

0.4

V

I_OL= 24 mA

+10

V_IN= 0 to V_CC

(Note 1)

mA

I_IL

± 10

V_CC= 0V

V_IN= 6V Max

ChiProtect

mA

(SLCT, PE, BUSY, nACK, nERROR)

V_CC= 0V

V_IN= 6V Max

Backdrive

(nSTROBE, nAUTOFD, nINIT,

nSLCTIN)

I_IL

± 10

V_CC= 0V

V_IN= 6V Max

Backdrive

(PD0-PD7)

mA

Suppy Current Active

I_CCI

mA

All outputs open.

4.5

70

90

Note 1: All output leakages are measured with the current pins in high impedance

Note 2: Output leakage is measured with the low driving output off, either for a high level output or a

high impedance state.

Note 3: KBCLK, KBDATA, MCLK, MDATA contain 90uA min pull-ups.

178

CAPACITANCE T_A= 25°C; fc = 1MHz; V_CC= 5V

PARAMETER

SYMBOL

UNIT

TEST CONDITION

LIMITS

TYP

MIN

MAX

Clock Input Capacitance

C_IN

20

pF

All pins except pin

under test tied to AC

ground

Input Capacitance

Output Capacitance

C_IN

10

20

pF

C_OUT

179

TIMING DIAGRAMS

For the Timing Diagrams shown, the following capacitive loads are used.

CAPACITANCE

NAME

TOTAL (pF)

SD[0:7]

IOCHRDY

SERIRQ

DRQ[0:3]

HCLK

240

150

120

50

14CLK

50

nWGATE

nWDATA

nHDSEL

nDIR

nSTEP

nDS[1:0]

nMTR[1:0]

DRVDEN[1:0]

TXD1

nRTS1

nDTR1

TXD2

nRTS2

nDTR2

PD[0:7]

nSLCTIN

nINIT

240

100

240

nALF

nSTB

KDAT

KCLK

MDAT

MCLK

180

t 1

t 2

V c c

t 3

A l l H o s t

A c c e s s e s

FIGURE 1 - POWER-UP TIMING

NAME

DESCRIPTION

Vcc Slew from 4.5V to 0V

MIN

300

100

125

TYP

MAX

UNITS

ms

t1

t2

t3

Vcc Slew from 0V to 4.5V

ms

All Host Accesses After Powerup (Note 1)

500

ms

Note 1: Internal write-protection period after Vcc passes 4.5 volts on power-up

181

t10

AEN

t3

SA[x]

t2

t1

t4

t6

nIOW

SD[x]

t11

t5

DATA VALID

GP I/O

FINTR

t7

t8

PINTR

IBF

t9

FIGURE 2 - ISA WRITE

DESCRIPTION

NAME

t1

MIN

10

TYP

MAX UNITS

SA[x] and AEN valid to nIOW asserted

nIOW asserted to nIOW deasserted

nIOW asserted to SA[x], invalid

ns

t2

80

t3

10

t4

SD[x] Valid to nIOW deasserted

45

t5

SD[x] Hold from nIOW deasserted

0

ns

t6

nIOW deasserted to nIOW asserted

nIOW deasserted to FINTR deasserted (Note 1)

nIOW deasserted to PINTER deasserted (Note 2)

IBF (internal signal) asserted from nIOW deasserted

nIOW deasserted to AEN invalid

25

10

t7

55

260

40

t8

t9

t10

t11

nIOW deasserted to GPI/O out Valid

100

Note 1: FINTR refers to the IRQ used by the floppy disk.

Note 2: PINTR refers to the IRQ used by the parallel port

182

t13

AEN

t3

SA[x]

t1

t7

t2

t6

nIOR

SD[x]

t4

t5

DATA VALID

PD[x], nERROR,

PE, SLCT, ACK, BUSY

t10

FINTER

PINTER

t9

t11

t12

PCOBF

AUXOBF1

t8

nIOR/nIOW

FIGURE 3 - ISA READ

SEE TIMING PARAMETERS ON NEXT PAGE

183

ISA READ TIMING

DESCRIPTION

NAME

t1

MIN

10

TYP MAX UNITS

SA[x] and AEN valid to nIOR asserted

nIOR asserted to nIOR deasserted

nIOR asserted to SA[x] invalid

ns

t2

50

t3

10

t4

nIOR asserted to Data Valid

50

25

ns

t5

Data Hold/float from nIOR deasserted

nIOR deasserted

10

25

t6

t8

nIOR asserted after nIOW deasserted

nIOR/nIOR, nIOW/nIOW transfers from/to ECP FIFO

Parallel Port setup to nIOR asserted

nIOR asserted to PINTER deasserted

nIOR deasserted to FINTER deasserted

nIOR deasserted to PCOBF deasserted (Notes 3,5)

nIOR deasserted to AUXOBF1 deasserted (Notes 4,5)

nIOW deasserted to AEN invalid

80

t8

150

t7

20

55

t9

t10

t11

t12

t13

260

80

10

Note 1: FINTR refers to the IRQ used by the floppy disk.

Note 2: PINTR refers to the IRQ used by the parallel port.

Note 3: PCOBF is used for the Keyboard IRQ.

Note 4: AUXOBF1 is used for the Mouse IRQ.

Note 5: Applies only if deassertion is performed in hardware.

184

t2

t1

PCOBF

AUXOBF1

nWRT

t3

IBF

nRD

FIGURE 4 - INTERNAL 8042 CPU TIMING

DESCRIPTION MIN

NAME

TYP MAX UNITS

t1

t2

t3

nWRT deasserted to AUXOBF1 asserted (Notes 1,2)

nWRT deasserted to PCOBF asserted (Notes 1,3)

nRD deasserted to IBF deasserted (Note 1)

40

ns

Note 1: IBF, nWRT and nRD are internal signals.

Note 2: PCOBF is used for the Keyboard IRQ.

Note 3: AUXOBF1 is used for the Mouse IRQ.

185

t1

t2

X1K

FIGURE 5A - INPUT CLOCK TIMING

NAME

t1

DESCRIPTION

Clock Cycle Time for 14.318MHZ

MIN

TYP

70

MAX

UNITS

ns

t2

Clock High Time/Low Time for 14.318MHz

Clock Rise Time/Fall Time (not shown)

35

ns

5

ns

t4

RESET

FIGURE 5B - RESET TIMING

NAME

DESCRIPTION

RESET width (Note 1)

MIN

TYP MAX

UNITS

t4

1.5

ms

Note 1: The RESET width is dependent upon the processor clock. The RESET must be active while

the clock is running and stable.

186

t15

AEN

t16

t3

t2

FDRQ,

PDRQ

t1

t4

nDACK

t12

t14

t11

t6

t5

t8

nIOR

or

nIOW

t10

t9

t7

DATA

(DO-D7)

DATA VALID

t13

TC

FIGURE 6A - DMA TIMING (SINGLE TRANSFER MODE)

NAME

t1

DESCRIPTION

nDACK Delay Time from FDRQ High

DRQ Reset Delay from nIOR or nIOW

FDRQ Reset Delay from nDACK Low

nDACK Width

MIN

TYP

MAX

UNITS

ns

0

t2

100

ns

t3

ns

t4

150

0

ns

t5

nIOR Delay from FDRQ High

nIOW Delay from FDRQ High

Data Access Time from nIOR Low

Data Set Up Time to nIOW High

Data to Float Delay from nIOR High

Data Hold Time from nIOW High

nDACK Set Up to nIOW/nIOR Low

nDACK Hold after nIOW/nIOR High

TC Pulse Width

ns

t6

0

ns

t7

100

60

ns

t8

40

10

5

ns

t9

ns

t10

t11

t12

t13

t14

t15

t16

ns

10

60

40

10

ns

AEN Set Up to nIOR/nIOW

ns

AEN Hold from nDACK

ns

TC Active to PDRQ Inactive

100

ns

187

t15

AEN

t16

t2

t3

FDRQ,

PDRQ

t1

t4

nDACK

t12

t14

t11

t6

t5

t8

nIOR

or

nIOW

t10

t9

t7

DATA

(DO-D7)

DATA VALID

t13

TC

FIGURE 6B - DMA TIMING (BURST TRANSFER MODE)

NAME

t1

DESCRIPTION

nDACK Delay Time from FDRQ High

DRQ Reset Delay from nIOR or nIOW

FDRQ Reset Delay from nDACK Low

nDACK Width

MIN

TYP

MAX

UNITS

ns

0

t2

100

ns

t3

ns

t4

150

0

ns

t5

nIOR Delay from FDRQ High

nIOW Delay from FDRQ High

Data Access Time from nIOR Low

Data Set Up Time to nIOW High

Data to Float Delay from nIOR High

Data Hold Time from nIOW High

nDACK Set Up to nIOW/nIOR Low

nDACK Hold after nIOW/nIOR High

TC Pulse Width

ns

t6

0

ns

t7

100

60

ns

t8

40

10

5

ns

t9

ns

t10

t11

t12

t13

t14

t15

t16

ns

10

60

40

10

ns

AEN Set Up to nIOR/nIOW

ns

AEN Hold from nDACK

ns

TC Active to PDRQ Inactive

100

ns

188

t3

nDIR

t4

t1

t2

nSTEP

nDS0-1

t5

t6

t7

t8

nINDEX

nRDATA

nWDATA

nIOW

t9

nDS0-1,

MTR0-1

FIGURE 7 - DISK DRIVE TIMING (AT MODE ONLY)

NAME

t1

DESCRIPTION

MIN

TYP

4

MAX

UNITS

X*

nDIR Set Up to STEP Low

nSTEP Active Time Low

t2

24

96

132

20

2

X*

t3

nDIR Hold Time after nSTEP

nSTEP Cycle Time

X*

t4

X*

t5

nDS0-1 Hold Time from nSTEP Low

nINDEX Pulse Width

X*

t6

X*

t7

nRDATA Active Time Low

nWDATA Write Data Width Low

nDS0-1, MTRO-1 from End of nIOW

40

.5

ns

t8

Y*

t9

25

ns

*X specifies one MCLK period and Y specifies one WCLK period.

MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz)

WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz)

189

nIOW

t1

nRTSx,

nDTRx

t5

IRQx

nCTSx,

nDSRx,

nDCDx

t6

t2

t4

IRQx

nIOW

t3

IRQx

nIOR

nRIx

FIGURE 8 - SERIAL PORT TIMING

NAME

t1

DESCRIPTION

nRTSx, nDTRx Delay from nIOW

MIN

TYP

MAX UNITS

200

100

120

125

100

ns

t2

IRQx Active Delay from nCTSx, nDSRx, nDCDx

IRQx Inactive Delay from nIOR (Leading Edge)

IRQx Inactive Delay from nIOW (Trailing Edge)

IRQx Inactive Delay from nIOW

t3

t4

t5

10

t6

IRQx Active Delay from nRIx

190

PD0- PD7

nIOW

t6

t1

nINIT, nSTROBE.

nAUTOFD, SLCTIN

nACK

t2

nPINTR

(SPP)

t4

t3

PINTR

(ECP or EPP Enabled)

nFAULT (ECP)

nERROR

(ECP)

t5

t2

t3

PINTR

FIGURE 9 - PARALLEL PORT TIMING

NAME

DESCRIPTION

MIN

TYP

MAX

UNITS

t1

PD0-7, nINIT, nSTROBE, nAUTOFD Delay from

nIOW

100

ns

t2

t3

t4

t5

t6

PINTR Delay from nACK, nFAULT

PINTR Active Low in ECP and EPP Modes

PINTR Delay from nACK

60

ns

200

300

105

100

nERROR Active to PINTR Active

PD0 - PD7 Delay from IOW Active

Note:

PINTR refers to the IRQ used by the parallel port.

191

t18

t9

A0-A10

SD<7:0>

t17

t8

t12

t19

nIOW

t10

t11

IOCHRDY

t13

t22

t20

t2

t5

nWRITE

PD<7:0>

t1

t16

t3

t14

t4

nDATAST

nADDRSTB

t15

t6

t7

nWAIT

PDIR

t21

FIGURE 10 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE

SEE TIMING PARAMETERS ON NEXT PAGE

192

EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING

NAME

DESCRIPTION

nIOW Asserted to PDATA Valid

MIN

0

TYP

MAX

50

UNITS

ns

t1

t2

t3

t4

nWAIT Asserted to nWRITE Change (Note 1)

nWRITE to Command Asserted

60

5

185

35

ns

nWAIT Deasserted to Command Deasserted

(Note 1)

60

190

ns

t5

t6

nWAIT Asserted to PDATA Invalid (Note 1)

Time Out

0

10

0

ns

ms

ns

12

t7

Command Deasserted to nWAIT Asserted

SDATA Valid to nIOW Asserted

nIOW Deasserted to DATA Invalid

nIOW Asserted to IOCHRDY Asserted

t8

10

0

t9

t10

t11

0

24

nWAIT Deasserted to IOCHRDY Deasserted

(Note 1)

60

160

t12

t13

t14

t15

t16

t17

t18

t19

t20

t21

t22

IOCHRDY Deasserted to nIOW Deasserted

nIOW Asserted to nWRITE Asserted

nWAIT Asserted to Command Asserted (Note 1)

Command Asserted to nWAIT Deasserted

PDATA Valid to Command Asserted

Ax Valid to nIOW Asserted

10

0

ns

ms

ns

70

210

10

60

0

10

40

10

40

60

0

nIOW Asserted to Ax Invalid

nIOW Deasserted to nIOW or nIOR Asserted

nWAIT Asserted to nWRITE Asserted (Note 1)

nWAIT Asserted to PDIR Low

185

PDIR Low to nWRITE Asserted

0

Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is

considered to have settled after it does not transition for a minimum of 50 nsec.

193

t20

t12

A0-A10

IOR

t19

t11

t22

t13

SD<7:0>

t18

t10

t8

IOCHRDY

t24

t23

t27

t17

PDIR

nWRITE

t9

t21

PData bus driven

by peripheral

t2

t25

t5

t4

t16

PD<7:0>

t28

t26

t1

t14

t3

DATASTB

ADDRSTB

t15

t7

t6

nWAIT

FIGURE 11 - EPP 1.9 DATA OR ADDRESS READ CYCLE

SEE TIMING PARAMETERS ON NEXT PAGE

194

EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS

NAME

DESCRIPTION

PDATA Hi-Z to Command Asserted

MIN

0

TYP

MAX

30

UNITS

ns

t1

t2

t3

nIOR Asserted to PDATA Hi-Z

0

50

ns

nWAIT Deasserted to Command Deasserted

(Note 1)

60

180

ns

t4

t5

Command Deasserted to PDATA Hi-Z

Command Asserted to PDATA Valid

PDATA Hi-Z to nWAIT Deasserted

PDATA Valid to nWAIT Deasserted

nIOR Asserted to IOCHRDY Asserted

nWRITE Deasserted to nIOR Asserted (Note 2)

0

ns

ms

ns

t6

0

t7

0

t8

0

24

t9

0

t10

nWAIT Deasserted to IOCHRDY Deasserted

(Note 1)

60

160

t11

t12

t13

t14

t15

t16

t17

t18

t19

t20

t21

t22

t23

t24

t25

t26

t27

t28

IOCHRDY Deasserted to nIOR Deasserted

nIOR Deasserted to SDATA Hi-Z (Hold Time)

PDATA Valid to SDATA Valid

0

ns

ms

ns

40

75

0

nWAIT Asserted to Command Asserted

Time Out

0

195

12

10

60

0

nWAIT Deasserted to PDATA Driven (Note 1)

nWAIT Deasserted to nWRITE Modified (Notes 1,2)

SDATA Valid to IOCHRDY Deasserted (Note 3)

Ax Valid to nIOR Asserted

190

85

40

10

0

nIOR Deasserted to Ax Invalid

10

nWAIT Asserted to nWRITE Deasserted

nIOR Deasserted to nIOW or nIOR Asserted

nWAIT Asserted to PDIR Set (Note 1)

PDATA Hi-Z to PDIR Set

185

40

60

0

185

nWAIT Asserted to PDATA Hi-Z (Note 1)

PDIR Set to Command

60

0

180

20

nWAIT Deasserted to PDIR Low (Note 1)

nWRITE Deasserted to Command

60

1

180

Note 1: nWAIT is considered to have settled after it does not transition for a minimum of 50 ns.

Note 2: When not executing a write cycle, EPP nWRITE is inactive high.

Note 3: 85 is true only if t7 = 0.

195

t18

t9

A0-A10

SD<7:0>

nIOW

t17

t8

t6

t19

t12

t10

t20

t11

IOCHRDY

nWRITE

t2

t5

t13

t1

PD<7:0>

t16

t3

t4

nDATAST

nADDRSTB

t21

nWAIT

PDIR

FIGURE 12 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE

SEE TIMING PARAMETERS ON NEXT PAGE

196

EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS

NAME

t1

DESCRIPTION

nIOW Asserted to PDATA Valid

MIN

0

TYP

MAX

50

UNITS

ns

ms

ns

ms

ns

t2

Command Deasserted to nWRITE Change

nWRITE to Command

0

40

t3

5

35

t4

nIOW Deasserted to Command Deasserted (Note 2)

Command Deasserted to PDATA Invalid

Time Out

50

t5

50

10

0

t6

12

t8

SDATA Valid to nIOW Asserted

t9

nIOW Deasserted to DATA Invalid

nIOW Asserted to IOCHRDY Asserted

nWAIT Deasserted to IOCHRDY Deasserted

IOCHRDY Deasserted to nIOW Deasserted

nIOW Asserted to nWRITE Asserted

PDATA Valid to Command Asserted

Ax Valid to nIOW Asserted

t10

t11

t12

t13

t16

t17

t18

t19

t20

t21

0

24

40

10

0

50

35

10

40

10

100

nIOW Deasserted to Ax Invalid

nIOW Deasserted to nIOW or nIOR Asserted

nWAIT Asserted to IOCHRDY Deasserted

Command Deasserted to nWAIT Deasserted

45

0

Note 1: nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing

an EPP Write.

Note 2: The number is only valid if nWAIT is active when IOW goes active.

197

t20

A0-A10

nIOR

t15

t11

t22

t19

t13

t12

SD<7:0>

t8

t10

t3

IOCHRDY

nWRITE

t5

t4

PD<7:0>

t23

t2

nDATASTB

nADDRSTB

t21

nWAIT

PDIR

FIGURE 13 - EPP 1.7 DATA OR ADDRESS READ CYCLE

SEE TIMING PARAMETERS ON NEXT PAGE

198

EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS

NAME

t2

DESCRIPTION

nIOR Deasserted to Command Deasserted

nWAIT Asserted to IOCHRDY Deasserted

Command Deasserted to PDATA Hi-Z

Command Asserted to PDATA Valid

nIOR Asserted to IOCHRDY Asserted

nWAIT Deasserted to IOCHRDY Deasserted

IOCHRDY Deasserted to nIOR Deasserted

nIOR Deasserted to SDATA High-Z (Hold Time)

PDATA Valid to SDATA Valid

MIN

TYP

MAX

50

UNITS

ns

t3

0

40

ns

t4

ns

t5

ns

t8

24

50

ns

t10

t11

t12

t13

t15

t19

t20

t21

t22

t23

ns

0

ns

40

12

ns

Time Out

10

40

10

0

ms

Ax Valid to nIOR Asserted

ns

nIOR Deasserted to Ax Invalid

ns

Command Deasserted to nWAIT Deasserted

nIOR Deasserted to nIOW or nIOR Asserted

nIOR Asserted to Command Asserted

ns

40

ns

55

ns

Note:

WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an

EPP Read.

199

ECP PARALLEL PORT TIMING

The host then sets HostClk (nStrobe) high.

Parallel Port FIFO (Mode 101)

The peripheral then accepts

the data and sets PeriphAck (Busy) low,

completing the transfer. This sequence is

shown in Figure 15.

The standard parallel port is run at or near the

peak 500Kbytes/sec allowed in the forward

direction using DMA. The state machine does

not examine nACK and begins the next

transfer based on Busy. Refer to Figure 14.

The timing is designed to provide 3 cable

round-trip times for data setup if Data is driven

simultaneously with HostClk (nStrobe).

ECP Parallel Port Timing

Reverse-Idle Phase

The timing is designed to allow operation at

approximately 2.0 Mbytes/sec over a 15ft

cable. If a shorter cable is used then the

bandwidth will increase.

The peripheral has no data to send and keeps

PeriphClk high. The host is idle and keeps

HostAck low.

Forward-Idle

Reverse Data Transfer Phase

When the host has no data to send it keeps

HostClk (nStrobe) high and the peripheral will

leave PeriphClk (Busy) low.

The interface transfers data and commands

from the peripheral to the host using an inter-

locked HostAck and PeriphClk.

Forward Data Transfer Phase

The Reverse Data Transfer Phase may be en-

tered from the Reverse-Idle Phase. After the

previous byte has beed accepted the host sets

HostAck (nALF) low. The peripheral then sets

PeriphClk (nACK) low when it has data to

send. The data must be stable for the

specified setup time prior to the falling edge of

PeriphClk. When the host is ready to accept a

byte it sets HostAck (nALF) high to

acknowledge the handshake. The peripheral

then sets PeriphClk (nACK) high. After the

host has accepted the data it sets HostAck

(nALF) low, completing the transfer. This

sequence is shown in Figure 16.

The interface transfers data and commands

from the host to the peripheral using an inter-

locked PeriphAck and HostClk. The peripheral

may indicate its desire to send data to the host

by asserting nPeriphRequest.

The Forward Data Transfer Phase may be

entered from the Forward-Idle Phase. While in

the Forward Phase the peripheral may

asynchronously assert the nPeriphRequest

(nFault) to request that the channel be

reversed. When the peripheral is not busy it

sets PeriphAck (Busy) low. The host then sets

HostClk (nStrobe) low when it is prepared to

send data. The data must be stable for the

specified setup time prior to the falling edge of

HostClk. The peripheral then sets PeriphAck

(Busy) high to acknowledge the handshake.

Output Drivers

To facilitate higher performance data transfer,

the use of balanced CMOS active drivers for

critical signals (Data, HostAck, HostClk,

200

PeriphAck, PeriphClk) are used ECP Mode.

Because the use of active drivers can present

totem-pole. The timing for the dynamic driver

change is specified in then IEEE 1284

Extended Capabilities Port Protocol and ISA

Interface Standard, Rev. 1.14, July 14, 1993,

available from Microsoft. The dynamic driver

change must be implemented properly to

prevent glitching the outputs.

compatibility

problems

in Compatible

Mode (the control signals, by tradition, are

specified as open-collector), the drivers are

dynamically changed from open-collector to

t6

t3

PDATA

t1

t2

t5

nSTROBE

t4

BUSY

FIGURE 14 - PARALLEL PORT FIFO TIMING

NAME

t1

DESCRIPTION

DATA Valid to nSTROBE Active

MIN

600

450

TYP

MAX

UNITS

ns

t2

nSTROBE Active Pulse Width

ns

t3

DATA Hold from nSTROBE Inactive (Note 1)

nSTROBE Active to BUSY Active

BUSY Inactive to nSTROBE Active

BUSY Inactive to PDATA Invalid (Note 1)

ns

t4

500

ns

t5

680

80

ns

t6

ns

Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only

applies if another data transfer is pending. If no other data transfer is pending, the data is

held indefinitely.

201

t3

t4

nAUTOFD

PDATA<7:0>

t2

t1

t7

t8

nSTROBE

BUSY

t6

t5

t6

FIGURE 15 - ECP PARALLEL PORT FORWARD TIMING

NAME

DESCRIPTION

MIN

0

TYP

MAX

60

UNITS

ns

t1

t2

t3

nAUTOFD Valid to nSTROBE Asserted

PDATA Valid to nSTROBE Asserted

0

60

ns

BUSY Deasserted to nAUTOFD Changed

(Notes 1,2)

80

180

ns

t4

t5

t6

t7

t8

BUSY Deasserted to PDATA Changed (Notes 1,2)

nSTROBE Deasserted to Busy Asserted

80

0

180

ns

nSTROBE Deasserted to Busy Deasserted

0

BUSY Deasserted to nSTROBE Asserted (Notes 1,2)

BUSY Asserted to nSTROBE Deasserted (Note 2)

80

200

180

Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out.

Note 2: BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130

ns.

202

t2

PDATA<7:0>

t1

t5

t6

nACK

t4

t3

t4

nAUTOFD

FIGURE 16 - ECP PARALLEL PORT REVERSE TIMING

NAME

DESCRIPTION

MIN

0

TYP

MAX

UNITS

ns

t1

t2

t3

PDATA Valid to nACK Asserted

nAUTOFD Deasserted to PDATA Changed

0

ns

nACK Asserted to nAUTOFD Deasserted

(Notes 1,2)

80

200

ns

t4

t5

t6

nACK Deasserted to nAUTOFD Asserted (Note 2)

nAUTOFD Asserted to nACK Asserted

80

0

ns

nAUTOFD Deasserted to nACK Deasserted

0

Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been

received. ECP can stall by keeping nAUTOFD low.

Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130

ns.

203

DATA

0

1

0

1

0

1

0

1

t2

t1

t2

t1

IRRX

n IRRX

Parameter

min

typ

max

units

t1

t2

Pulse Width at 115kbaud

Pulse Width at 57.6kbaud

Pulse Width at 38.4kbaud

Pulse Width at 19.2kbaud

Pulse Width at 9.6kbaud

Pulse Width at 4.8kbaud

Pulse Width at 2.4kbaud

Bit Time at 115kbaud

Bit Time at 57.6kbaud

Bit Time at 38.4kbaud

Bit Time at 19.2kbaud

Bit Time at 9.6kbaud

1.4

1.6

3.22

4.8

2.71

3.69

µs

5.53

9.7

11.07

22.13

44.27

88.55

19.5

39

78

8.68

17.4

26

52

104

208

416

Bit Time at 4.8kbaud

Bit Time at 2.4kbaud

Notes:

1. Receive Pulse Detection Criteria: A received pulse is considered detected if the

received pulse is a minimum of 1.41µs.

2. IRRX: L5, CRF1 Bit 0: 1 = RCV active low

nIRRX: L5, CRF1 Bit 0: 0 = RCV active high (default)

3. This polarity assumes that the GPIO has not been programmed for inverted.

FIGURE 17 - IrDA RECEIVE TIMING

204

DATA

1

0

1

0

1

0

t2

t1

t2

IRTX

n IRTX

Parameter

min

typ

max

units

t1

t2

Pulse W idth at 115kbaud

Pulse W idth at 57.6kbaud

Pulse W idth at 38.4kbaud

Pulse W idth at 19.2kbaud

Pulse W idth at 9.6kbaud

Pulse W idth at 4.8kbaud

Pulse W idth at 2.4kbaud

Bit Time at 115kbaud

Bit Time at 57.6kbaud

Bit Time at 38.4kbaud

Bit Time at 19.2kbaud

Bit Time at 9.6kbaud

1.41

1.6

2.71

3.69

µs

3.22

4.8

5.53

9.7

11.07

22.13

44.27

88.55

19.5

39

78

8.68

17.4

26

52

104

208

416

Bit Time at 4.8kbaud

Bit Time at 2.4kbaud

Notes:

1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX

and 48SX.

2. IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default)

nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high

3. This polarity assumes that the GPIO has not been programmed for inverted.

FIGURE 18 - IrDA TRANSMIT TIMING

205

DATA

0

1

0

1

0

1

0

1

t1

t2

IRRX

n IRRX

t3 t4

MIRRX

t5 t6

nMIRRX

Parameter

min

typ

max

units

t1

t2

t3

t4

t5

t6

Modulated Output Bit Time

Off Bit Time

µs

Modulated Output "On"

Modulated Output "Off"

Modulated Output "On"

Modulated Output "Off"

0.8

1

1.2

Notes:

1. IRRX: L5, CRF1 Bit 0: 1 = RCV active low

nIRRX: L5, CRF1 Bit 0: 0 = RCV active high (default)

MIRRX, nMIRRX are the modulated outputs

2. This polarity assumes that the GPIO has not been programmed for inverted.

FIGURE 19 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING

206

DATA

0

1

0

1

0

1

0

1

t1

t2

IRTX

n IRTX

t3 t4

MIRTX

t5 t6

nMIRTX

Parameter

min

typ

max

units

t1

t2

t3

t4

t5

t6

Modulated Output Bit Time

Off Bit Time

µs

Modulated Output "On"

Modulated Output "Off"

Modulated Output "On"

Modulated Output "Off"

0.8

1

1.2

Notes:

1. IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default)

nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high

MIRTX, nMIRTX are the modulated outputs

2. This polarity assumes that the GPIO has not been programmed for inverted.

FIGURE 20 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING

207

D

3

D1

102

65

103

64

3

DETAIL "A"

R1

R2

0

L

4

L1

E

E1

e

5

D1/4

W

2

E1/4

39

128

38

1

A

A2

H

0

0.10

1

SEE DETAIL "A"

A1

-C-

MIN

NOM MAX

MIN

0.65

NOM MAX

L

3.4

0.8

0.95

A

A1

A2

D

D1

E

E1

H

L1

e

0

W

R1

R2

0.05

2.55

23.65

19.9

17.65

13.9

0.5

3.05

24.15

20.1

18.15

14.1

1.95

0.5BSC

23.9

20

17.9

14

0

7

0.3

0.1

0.13

0.3

Notes:

1) Coplanarity is 0.08 mm or 3.2 mils maximum.

2) Tolerance on the position of the leads is 0.080 mm maximum.

3) Package body dimensions D1 and E1 do not include the mold protrusion. Maximum

mold protrusion is 0.25 mm.

4) Dimensions for foot length L measured at the gauge plane 0.25 mm above the seating plane.

5) Details of pin 1 identifier are optional but must be located within the zone indicated.

6) Controlling dimension: millimeter

FIGURE 21 - 128 PIN QFP PACKAGE OUTLINES

208

Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete

information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed

to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the

purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. SMSC reserves the right

to make changes at any time in order to improve design and supply the best product possible. SMSC products are not designed,

intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to

personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer.

FDC37C68x Rev. 12/4/96


型号：	FDC37C68X
厂家：	ETC
描述：	Peripheral (Multifunction) Controller 外围设备（多功能）控制器\n 控制器
文件：	总210页 (文件大小：721K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FDC37C68X [ETC]

相关型号：

FDC37C75LJP

FDC37C77

FDC37C78

FDC37C78-HT

FDC37C78TQFP

FDC37C78_07

FDC37C922

FDC37C93

FDC37C932FR

FDC37C935

FDC37C93X

FDC37C93XAPM