FDC37C78 [SMSC]
Floppy Disk Controller; 软盘控制器
| 型号： | FDC37C78 |
| 厂家： | 
SMSC CORPORATION |
| 描述： | Floppy Disk Controller |
| 文件： | 总82页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FDC37C78
Floppy Disk Controller
FEATURES
•
•
•
3.3/5 Volt Operation
-
-
-
Swap Drives A and B
Intelligent Auto Power Management
2.88MB FDC37C78 Floppy Disk Controller
Non-Burst Mode DMA Option
Detects All Overrun and Underrun
Conditions
-
Licensed CMOS 765B Floppy Disk
Controller
-
Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power
Consumption
-
Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
-
-
-
-
-
-
Supports Two Floppy Drives Directly
Supports Vertical Recording Format
16 Byte Data FIFO
•
•
Enhanced Digital Data Separator
-
2 Mbps (Only Available When VCC = 5V),
1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps
Data Rates
100% IBM Compatibility
DMA Enable Logic
-
Programmable Precompensation Modes
Data Rate and Drive Control Registers
48 pin TQFP Package
TABLE OF CONTENTS
FEATURES...............................................................................................................................................1
GENERAL DESCRIPTION .......................................................................................................................3
PIN CONFIGURATION.............................................................................................................................4
DESCRIPTION OF PIN FUNCTIONS ......................................................................................................6
FUNCTIONAL DESCRIPTION ...............................................................................................................10
FDC37C78 REGISTERS ..................................................................................................................10
HOST PROCESSOR INTERFACE ..................................................................................................10
FLOPPY DISK CONTROLLER.........................................................................................................11
FLOPPY DISK CONTROLLER INTERNAL REGISTERS.................................................................11
COMMAND SET/DESCRIPTIONS.........................................................................................................29
INSTRUCTION SET ...............................................................................................................................32
AUTO POWER MANAGEMENT.............................................................................................................58
CONFIGURATION..................................................................................................................................62
OPERATIONAL DESCRIPTION.............................................................................................................71
MAXIMUM GUARANTEED RATINGS..............................................................................................71
DC ELECTRICAL CHARACTERISTICS...........................................................................................71
TIMING DIAGRAMS...............................................................................................................................75
2
GENERAL DESCRIPTION
The SMSC FDC37C78 Floppy Disk Controller
The FDC37C78 incorporates sophisticated power
control circuitry (PCC). The PCC supports
multiple low power down modes.
utilizes SMSC's proven SuperCell technology
for increased product reliability and functionality.
The FDC37C78 optimized for motherboard
applications. The FDC37C78 supports both 1
Mbps and 2 Mbps data rates and vertical vertical
recording operation at 1 Mbps Data Rate.
The FDC37C78 Floppy
Disk
Controller
incorporates Software Configurable Logic (SCL)
for ease of use. Use of the SCL feature allows
programmable system configuration of key
functions of FDC
The FDC37C78 incorporates SMSC's true CMOS
765B floppy disk controller, advanced digital data
separator, 16 byte data FIFO, on-chip 12 mA bus
drivers and two floppy direct drive support. The
true CMOS 765B core provides 100%
compatibility with IBM PC/XT and PC/AT
architectures in addition to providing data overflow
and underflow protection. The SMSC advanced
digital data separator incorporates SMSC's
patented data separator technology, allowing for
ease of testing and use.
The FDC37C78 does not require any external
filter components, and is, therefore easy to use
and offers lower system cost and reduced board
area. The FDC37C78 is software and register
compatible with SMSC's proprietary 82077AA
core.
3
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
nMTR0
1
nDACK
D0
2
nDS1/PD
D1
D2
nMTR1/IDLE
3
4
nDIR
D3
VCC
5
VSS
VCC
D4
nSTEP
6
FDC37C78
7
VSS
8
nHDSEL
nWGATE
nWDATA
MEDIA_ID1
D5
9
D6
10
11
D7
12
MEDIA_ID0
VCC
25
13 14 15 16 17 18 19 20 21 22 23 24
4
FDC37C78 PIN OUT
FDC37C78 48 Pin FDC
PIN #
NAME
nDACK
D0
D1
D2
D3
VSS
VCC
D4
D5
D6
D7
VCC
IRQ
TC
nTRK0
nINDEX
nWRTPRT
VSS
PIN #
25
NAME
MEDIA_ID0
MEDIA_ID1
nWDATA
nWGATE
nHDSEL
VSS
nSTEP
VCC
nDIR
nMTR1/IDLE
nDS1/PD
nMTR0
nDS0
RESET
X2
X1
VSS
A2
A1
A0
nCS
nIOR
nIOW
1
2
3
4
5
6
7
8
9
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VCC
nDSKCHG
nRDATA
DRVDEN0
DRVDEN1
DENSEL
DRQ
Note: “n” denotes active low signal.
5
DESCRIPTION OF PIN FUNCTIONS
DESCRIPTION OF PIN FUNCTIONS
BUFFER
PIN NO.
NAME
SYMBOL
TYPE
DESCRIPTION
HOST PROCESSOR INTERFACE
2-5,
8-11
Data Bus 0-7
D0-D7
I/O12
The data bus connection used by the host
microprocessor to transmit data to and from
the chip. These pins are in a high-impedance
state when not in the output mode.
46
47
I/O Read
I/O Write
nIOR
nIOW
A0-A2
I
I
I
This active low signal is issued by the host
microprocessor to indicate a read operation.
This active low signal is issued by the host
microprocessor to indicate a write operation.
44-42 I/O Address
These host address bits determine the I/O
address to be accessed during nIOR and
nIOW cycles.
These bits are latched
internally by the leading edge of nIOR and
nIOW.
48
DMA Request
DRQ
O12
This active high output is the DMA request for
byte transfers of data between the host and
the chip. This signal is cleared on the last
byte of the data transfer by the nDACK signal
going low (or by nIOR going low if nDACK
was already low as in demand mode).
1
n DMA
nDACK
TC
I
An active low input acknowledging the
request for a DMA transfer of data between
the host and the chip. This input enables the
DMA read or write internally.
Acknowledge
14
13
45
Terminal Count
I
O12
I
This signal indicates to the chip that DMA
data transfer is complete.
TC is only
accepted when nDACK is low. TC is active
high.
Interrupt Request IRQ
Chip Select Input nCS
The interrupt request from the logical device
is output on the IRQ signal. Refer to the
configuration registers for more information.
When enabled, this active low pin serves as
an input for an external decoder circuit which
is used to qualify address lines above A2.
6
DESCRIPTION OF PIN FUNCTIONS
BUFFER
PIN NO.
NAME
Reset
SYMBOL
RESET
TYPE
DESCRIPTION
38
IS
This active high signal resets the chip and
must be valid for 500 ns minimum. The effect
on the internal registers is described in the
appropriate section.
The configuration
registers are not affected by this reset.
FLOPPY DISK INTERFACE
21
27
Read Disk Data
nRDATA
IS
Raw serial bit stream from the disk drive, low
active. Each falling edge represents a flux
transition of the encoded data.
Write
Data
nWDATA
OD20 This active low high current driver provides
the encoded data to the disk drive. Each
falling edge causes a flux transition on the
media.
29
33
Head
nHDSEL
nDIR
OD20 This high current output selects the floppy
disk side for reading or writing. A logic "1" on
this pin means side 0 will be accessed, while
Select
a
logic "0" means side 1 will be accessed.
Direction
Control
OD20 This high current low active output determines
the direction of the head movement. A logic
"1" on this pin means outward motion, while a
logic "0" means inward motion.
31
20
Step Pulse
nSTEP
OD20 This active low high current driver issues a
low pulse for each track-to-track movement of
the head.
Disk Change
nDSKCHG
IS
This input senses that the drive door is open
or that the diskette has possibly been
changed since the last drive selection. This
input is inverted and read via bit 7 of I/O
address 3F7H.
22,
23
DRVDEN 0,
DRVDEN 1
DRVDEN0,
DRVDEN1
OD20 Indicates the drive and media selected. Refer
to configuration registers CR03, CR0B,
CR1F.
24
Density Select
DENSEL
OD20 Indicates whether a low (250/300 Kb/s) or
high (500 Kb/s) data rate has been selected.
This is determined by the IDENT bit in
Configuration Register 3.
7
DESCRIPTION OF PIN FUNCTIONS
BUFFER
PIN NO.
25,
NAME
Media ID0,
Media ID1
SYMBOL
MEDIA_ID0,
MEDIA_ID1
TYPE
DESCRIPTION
I
In Floppy Enhanced Mode 2 - These bits are
the Media ID 0,1 inputs. The value of these
bits can be read as bits 6 and 7 of the Floppy
Tape Register.
26
28
Write Gate
nWGATE
OD20 This active low high current driver allows
current to flow through the write head. It
becomes active just prior to writing to the
diskette.
15
16
Track 0
Index
nTRK0
IS
This active low Schmitt Trigger input senses
from the disk drive that the head is positioned
over the outermost track.
This active low Schmitt Trigger input senses
from the disk drive that the head is positioned
over the beginning of a track, as marked by
an index hole.
nINDEX
IS
17
nWrite Protected nWRTPRT
IS
This active low Schmitt Trigger input senses
from the disk drive that a disk is write
protected. Any write command is ignored.
36
37
34
nMotor On 0
nDrive Select 0
nMotor On 1
nMTR0
nDS0
OD20 This active low open drain output selects
motor drive 0.
OD20 This active low open drain output selects drive
0.
nMTR1
OD20 This active low open drain output select motor
drive 0.
This pin indicates that the part is in the IDLE
OD20
Idle
IDLE
state and can be powered down. Whenever
the part is in this state, IDLE pin is active
high. If the part is powered down by the Auto
Powerdown Mode, IDLE pin is set high and if
the part is powered down by setting the DSR
POWERDOWN bit (direct), IDLE pin is set
low.
35
nDrive Select 1
Powerdown
nDS1
PD
OD20 This active low open drain output selects drive
0.
This pin is active high whenever the part is in
OD20
powerdown
state,
either
via
DSR
POWERDOWN bit (direct) or via the Auto
Powerdown Mode. This pin can be used to
disable an external oscillator’s output.
8
DESCRIPTION OF PIN FUNCTIONS
BUFFER
PIN NO.
NAME
CLOCK 1
SYMBOL
TYPE
DESCRIPTION
MISCELLANEOUS
40
X1
ICLK
The external connection for
a
parallel
CMOS
resonant 24 MHz crystal.
A
compatible oscillator is required if crystal is
not used.
39
CLOCK 2
X2
OCLK 24 MHz crystal. If an external clock is used,
this pin should not be connected. This pin
should not be used to drive any other drivers.
7, 12, 19, Power
32
VCC
Positive Supply Voltage.
6, 18, 30, Ground
41
GND
Ground Supply.
BUFFER TYPE DESCRIPTIONS
Note: These values are for 3.3V operation. See Operational Description for 3.3V/5V values.
BUFFER TYPE
DESCRIPTION
Input/output. 12 mA sink; 6 mA source
Output. 12 mA sink; 6 mA source
Open drain. 20 mA sink
Output to external crystal
Input to Crystal Oscillator Circuit (CMOS levels)
Input TTL compatible.
I/O12
O12
OD20
OCLK
ICLK
I
IS
Input with Schmitt Trigger
9
FUNCTIONAL DESCRIPTION
FDC37C78 REGISTERS
HOST PROCESSOR INTERFACE
The address map, shown below in Table 1, shows
the addresses of the different blocks of the
FDC37C78 immediately after power up. Some
addresses are used to access more than one
register.
The host processor communicates with the
FDC37C78 through
a
series of read/write
registers. The port addresses for these registers
are shown in Table 1.
Register access is
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide.
Table 1 - FDC37C78 Block Addresses
BLOCK NAME
ADDRESS
NOTES
+0, +1
Base +0,1
Configuration
Floppy Disk
Write only; Note 1, 2
Read only; Disabled at power
up; Note 2
Base +[2:5, 7]
Floppy Disk
Disabled at power up; Note 2
Note 1: Configuration registers can only be modified in configuration mode, refer to the configuration
register description for more information. Access to status registers A and B of the floppy disk is
disabled in configuration mode.
Note 2: The fdc must be enabled in the configuration registers before accessing the registers.
10
The FDC37C78 is
compatible
to
the
FLOPPY DISK CONTROLLER
82077AA using SMSC's proprietary floppy disk
controller core.
The Floppy Disk Controller (FDC) provides the
interface between a host microprocessor and the
floppy disk drives.
The FDC integrates the
FLOPPY DISK CONTROLLER INTERNAL
REGISTERS
functions of the Formatter/Controller, Digital Data
Separator, Write Precompensation and Data Rate
Selection logic for an IBM XT/AT compatible FDC.
The true CMOS 765B core guarantees 100% IBM
PC XT/AT compatibility in addition to providing
data overflow and underflow protection.
The Floppy Disk Controller contains eight internal
registers which facilitate the interfacing between
the host microprocessor and the disk drive. Table
2 shows the addresses required to access these
registers. Registers other than the ones shown
are not supported.
The rest of the FDC
description assumes the Base I/O Address is 3F0.
Table 2 - Status, Data and Control Registers
BASE I/O
ADDRESS
REGISTER
+0
+1
+2
+3
+4
+4
+5
+6
+7
+7
Reserved
Reserved
R/W
R/W
R
Digital Output Register
Tape Drive Register
Main Status Register
Data Rate Select Register
Data (FIFO)
DOR
TSR
MSR
DSR
FIFO
W
R/W
Reserved
R
Digital Input Register
Configuration Control Register
DIR
W
CCR
11
contains the enable for the DMA logic and
contains a software reset bit. The contents of the
DOR are unaffected by a software reset. The
DOR can be written to at any time.
DIGITAL OUTPUT REGISTER (DOR)
Address 3F2 READ/WRITE
The DOR controls the drive select and motor
enables of the disk interface outputs. It also
7
6
5
4
3
2
1
0
MOT
MOT
MOT
MOT
DMAEN nRESET DRIVE DRIVE
EN3
EN2
EN1
EN0
SEL1
0
SEL0
0
RESET
COND.
0
0
0
0
0
0
BIT 0 and 1 DRIVE SELECT
BIT 4 MOTOR ENABLE 0
These two bit a are binary encoded for the four
drive selects DS0-DS3, thereby allowing only
one drive to be selected at one time.
This bit controls the MTR0 disk interface output. A
logic "1" in this bit will cause the output pin to go
active.
BIT 2 nRESET
BIT 5 MOTOR ENABLE 1
A logic "0" written to this bit resets the Floppy disk
controller. This reset will remain active until a logic
"1" is written to this bit. This software reset does
not affect the DSR and CCR registers, nor does it
affect the other bits of the DOR register. The
minimum reset duration required is 100ns,
therefore toggling this bit by consecutive writes to
this register is a valid method of issuing a software
reset.
This bit controls the MTR1 disk interface output. A
logic "1" in this bit will cause the output pin to go
active.
BIT 6 MOTOR ENABLE 2
This bit controls the MTR2 disk interface output. A
logic "1" in this bit will cause the output pin to go
active.
BIT 7 MOTOR ENABLE 3
BIT 3 DMAEN
This bit controls the MTR3 disk interface output. A
logic "1" in this bit causes the output to go active.
Writing this bit to logic "1" will enable the DRQ,
nDACK, TC and IRQ outputs. This bit being a
logic "0" will disable the nDACK and TC inputs,
and hold the DRQ and IRQ outputs in a high
impedance state. This bit is a logic "0" after a
reset and in these modes.
Table 3 - Drive Activation Values
DRIVE
DOR VALUE
0
1
2
3
1CH
2DH
4EH
8FH
12
TAPE DRIVE REGISTER (TDR)
Address 3F3 READ/WRITE
This register is included for 82077 software
compatability. The robust digital data separator
used in the FDC37C78 does not require its
characteristics modified for tape support. The
contents of this register are not used internal to the
device. The TDR is unaffected by a software
reset. Bits 2-7 are tri-stated when read in this
mode.
Table 4- Tape Select Bits
DRIVE
TAPE SEL1
TAPE SEL2
SELECTED
0
0
1
1
0
1
0
1
None
1
2
3
Table 5 - Internal 4 Drive Decode - Normal
DIGITAL OUTPUT REGISTER
DRIVE SELECT OUTPUTS
(ACTIVE LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
1
Bit1
0
Bit 0
0
nDS3
nDS2
nDS1
nDS0 nMTR3 nMTR2 nMTR1 nMTR0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
nBIT 7
nBIT 7
nBIT 7
nBIT 7
nBIT 7
nBIT 6
nBIT 6
nBIT 6
nBIT 6
nBIT 6
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nBIT 4
nBIT 4
nBIT 4
nBIT 4
nBIT 4
X
X
1
X
0
1
X
1
X
X
1
0
1
X
X
X
1
1
0
0
0
0
X
X
Table 6 - Internal 4 Drive Decode - Drives 0 and 1 Swapped
DIGITAL OUTPUT REGISTER
DRIVE SELECT OUTPUTS
(ACTIVE LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
1
Bit1
0
Bit 0
0
nDS3
nDS2
nDS1
nDS0
nMTR3
nBIT 7
nBIT 7
nBIT 7
nBIT 7
nBIT 7
nMTR2
nBIT 6
nBIT 6
nBIT 6
nBIT 6
nBIT 6
nMTR1
nBIT 4
nBIT 4
nBIT 4
nBIT 4
nBIT 4
nMTR0
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nBIT 5
1
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
0
1
1
1
X
X
1
X
0
1
X
1
X
X
1
0
1
X
X
X
1
1
0
0
0
0
X
X
13
Table 7 - External 2 to 4 Drive Decode - Normal
DRIVE SELECT
OUTPUTS
MOTOR ON OUTPUTS
(ACTIVE LOW)
DIGITAL OUTPUT REGISTER
(ACTIVE LOW)
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
1
Bit1
0
Bit 0
0
nDS1
nDS0
nMTR1
nMTR0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
X
X
1
X
0
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
X
1
X
X
1
0
1
X
X
X
1
1
X
X
X
0
0
0
X
X
0
X
0
1
X
0
X
X
1
0
0
X
X
X
1
1
Table 8 - External 2 to 4 Drive Decode - Drives 0 and 1 Swapped
DRIVE SELECT
OUTPUTS
MOTOR ON OUTPUTS
(ACTIVE LOW)
DIGITAL OUTPUT REGISTER
(ACTIVE LOW)
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
1
Bit1
0
Bit 0
0
nDS1
nDS0
nMTR1
nMTR0
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
X
X
1
X
0
1
X
1
X
X
1
0
1
X
X
X
1
1
X
X
X
0
0
0
X
X
0
X
0
1
X
0
X
X
1
0
0
X
X
X
1
1
14
Normal Floppy Mode
Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high
impedance.
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
REG 3F3 Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state tape sel1 tape sel0
Enhanced Floppy Mode 2 (OS2)
Register 3F3 for Enhanced Floppy Mode 2 operation.
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
REG 3F3
Media
ID1
Media
ID0
Drive Type ID
Floppy Boot Drive
tape sel1 tape sel0
For this mode, DRATE0 and DRATE1 pins are
inputs, and these inputs are gated into bits 6 and 7
of the 3F3 register. These two bits are not
affected by a hard or soft reset.
Bits 1 and 0 - Tape Drive Select (READ/WRITE).
Same as in Normal and Enhanced Floppy Mode.
1.
Table 9a
BIT 7 Media ID 1; Read Only (See Table 9a)
BIT 6 Media ID 0; Read Only (See Table 9b)
Media ID1
Pin 26
Bit 7
CR7-DB3=0
CR7-DB3=1
0
1
0
1
1
0
BITS 5 and 4 Drive Type ID - These Bits reflect
two of the bits of configuration register 6; which
two bits depends on the last drive selected in the
Digital Output Register (3F2). (See Table 11)
Table 9b
Media ID0
Bit 6
Pin 25
BITS 3 and 2 Floppy Boot Drive - These bits
reflect the value of configuration register 7 bits 1,
0. Bit 3 = CR7 Bit DB1. Bit 2 = CR7 Bit DB0.
CR7-DB2=0
CR7-DB2=1
0
1
0
1
1
0
Table 9c - Drive Type ID
Digital Output Register
Register 3F3 - Drive Type ID
Bit 1
Bit 0
Bit 5
Bit 4
0
0
1
1
0
1
0
1
CR6 - Bit 1
CR6 - Bit 3
CR6 - Bit 5
CR6 - Bit 7
CR6 - Bit 0
CR6 - Bit 2
CR6 - Bit 4
CR6 - Bit 6
15
not the DSR, for PC/AT and Microchannel
applications. Other applications can set the data
rate in the DSR. The data rate of the floppy
controller is the most recent write of either the
DSR or CCR. The DSR is unaffected by a
software reset. A hardware reset will set the DSR
to 02H, which corresponds to the default
precompensation setting and 250 kbps.
DATA RATE SELECT REGISTER (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program
the data rate, amount of write precompensation,
power down status, and software reset. The data
rate is programmed using the Configuration
Control
Register
(CCR)
7
6
5
0
4
3
2
1
0
S/W
POWER
PRE-
PRE-
PRE-
DRATE DRATE
RESET DOWN
COMP2 COMP1 COMP0 SEL1
SEL0
0
RESET
COND.
0
0
0
0
0
0
1
floppy controller clock and data separator circuits
will be turned off. The controller will come out of
manual low power mode after a software reset or
access to the Data Register or Main Status
Register.
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
See Table 13 for the settings
corresponding to the individual data rates. The
data rate select bits are unaffected by a software
reset, and are set to 250 kbps after a hardware
reset.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the
DOR RESET (DOR bit 2) except that this bit is self
clearing.
BIT
2
through
4
PRECOMPENSATION
SELECT
These three bits select the value of write
precompensation that will be applied to the
WDATA output signal. Table 12 shows the
precompensation values for the combination of
these bits settings. Track 0 is the default starting
track number to start precompensation. this
starting track number can be changed by the
configure command.
Table 10 - Precompensation Delays
PRECOMP PRECOMPENSATION DELAY
432
111
001
010
011
100
101
110
000
0.00 ns-DISABLED
41.67 ns
83.34 ns
125.00 ns
166.67 ns
BIT 5 UNDEFINED
208.33 ns
Should be written as a logic "0".
250.00 ns
Default (See Table 14)
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy
controller into Manual Low Power mode. The
16
Table 11 - Data Rates
DATA RATE
DRIVE RATE
DATA RATE
DENSEL (1)
DRATE (2)
DRT1
DRT0
SEL1
SEL0
MFM
1Meg
500
300
250
FM
---
250
150
125
---
250
250
125
---
250
---
IDENT=1
IDENT=0
1
1
0
0
1
1
0
0
1
1
0
0
1
2
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1Meg
500
500
250
1Meg
500
2Meg
250
125
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
Note 1: This is for DENSEL in normal mode.
Note 2: This is for DRATE0, DRATE1 when Drive Opt are 00.
Table 12 - Default Precompensation Delays
PRECOMPENSATION
DATA RATE
DELAYS
2 Mbps
1 Mbps
20.8 ns
41.67 ns
125 ns
125 ns
125 ns
500 Kbps
300 Kbps
250 Kbps
*The 2 Mbps data rate is only available if VCC = 5V.
17
time. The MSR indicates when the disk controller
is ready to receive data via the Data Register. It
should be read before each byte transferring to or
from the data register except in DMA mode. NO
delay is required when reading the MSR after a
data transfer.
MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register
and indicates the status of the disk controller. The
Main Status Register can be read at any
7
6
5
4
3
2
1
0
RQM
DIO
NON
CMD
DRV3
DRV2
DRV1
DRV0
DMA
BUSY
BUSY
BUSY
BUSY
BUSY
BIT 0 - 3 DRVx BUSY
BIT 5 NON-DMA
These bits are set to 1s when a drive is in the seek
portion of a command, including implied and
overlapped seeks and recalibrates.
This mode is selected in the SPECIFY command
and will be set to a 1 during the execution phase of
a command. This is for polled data transfers and
helps differentiate between the data transfer phase
and the reading of result bytes.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in
progress. This bit will go active after the command
byte has been accepted and goes inactive at the
end of the results phase. If there is no result
phase (Seek, Recalibrate commands), this bit is
returned to a 0 after the last command byte.
BIT 6 DIO
Indicates the direction of a data transfer once a
RQM is set. A 1 indicates a read and a 0 indicates
a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to a
1. No access is permitted if set to a 0.
18
FIFO. The data is based upon the following
formula:
DATA REGISTER (FIFO)
Address 3F5 READ/WRITE
Threshold # x
1
x 8 - 1.5 µs = DELAY
All command parameter information, disk data and
result status are transferred between the host
processor and the floppy disk controller through
the Data Register.
DATA RATE
At the start of a command, the FIFO action is
always disabled and command parameters must
be sent based upon the RQM and DIO bit settings.
As the command execution phase is entered, the
FIFO is cleared of any data to ensure that invalid
data is not transferred.
Data transfers are governed by the RQM and DIO
bits in the Main Status Register.
The Data Register defaults to FIFO disabled mode
after any form of reset. This maintains PC/AT
hardware compatibility. The default values can be
changed through the Configure command (enable
full FIFO operation with threshold control). The
advantage of the FIFO is that it allows the system
a larger DMA latency without causing a disk error.
Table 15 gives several examples of the delays
with a
An overrun or underrun will terminate the current
command and the transfer of data. Disk writes will
complete the current sector by generating a 00
pattern and valid CRC. Reads require the host to
remove the remaining data so that the result
phase may be entered.
Table 13- FIFO Service Delay
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT
EXAMPLES
2 Mbps* DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 4 µs - 1.5 µs = 2.5 µs
2 x 4 µs - 1.5 µs = 6.5 µs
8 x 4 µs - 1.5 µs = 30.5 µs
15 x 4 µs - 1.5 µs = 58.5 µs
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT
EXAMPLES
1 Mbps DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 8 µs - 1.5 µs = 6.5 µs
2 x 8 µs - 1.5 µs = 14.5 µs
8 x 8 µs - 1.5 µs = 62.5 µs
15 x 8 µs - 1.5 µs = 118.5 µs
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT
EXAMPLES
500 Kbps DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 16 µs - 1.5 µs = 14.5 µs
2 x 16 µs - 1.5 µs = 30.5 µs
8 x 16 µs - 1.5 µs = 126.5 µs
15 x 16 µs - 1.5 µs = 238.5 µs
*The 2 Mbps data rate is only available if VCC = 5V.
19
DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only.
7
6
5
4
3
2
1
0
DSK
CHG
RESET
COND.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
BIT 0 - 6 UNDEFINED
BIT 7 DSKCHG
The data bus outputs D0 - 6 will remain in a high
impedance state during a read of this register.
This bit monitors the pin of the same name and
reflects the opposite value seen on the disk cable.
20
CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
7
6
5
4
3
2
1
0
DRATE DRATE
SEL1
1
SEL0
0
RESET
COND.
N/A
N/A
N/A
N/A
N/A
N/A
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller. See Table 13 for the appropriate
values.
BIT 2 - 7 RESERVED
Should be set to a logical "0" by the DOR and the
DSR resets.
21
STATUS REGISTER ENCODING
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of
the command just executed.
Table 14 - Status Register 0
BIT NO.
SYMBOL
IC
NAME
DESCRIPTION
7,6
Interrupt Code 00 - Normal termination of command. The specified
command was properly executed and completed without
error.
01 - Abnormal termination of command. Command
execution was started, but was not successfully
completed.
10 - Invalid command. The requested command could
not be executed.
11 - Abnormal termination caused by Polling.
5
4
SE
EC
Seek End
The FDC completed a Seek, Relative Seek or
Recalibrate command (used during a Sense Interrupt
Command).
Equipment
Check
The TRK0 pin failed to become a "1" after:
1. 80 step pulses in the Recalibrate command.
2. The Relative Seek command caused the FDC to
step outward beyond Track 0.
3
2
1,0
Unused. This bit is always "0".
Head Address The current head address.
Drive Select The current selected drive.
H
DS1,0
22
Table 15 - Status Register 1
NAME DESCRIPTION
BIT NO.
SYMBOL
EN
7
End of
The FDC tried to access a sector beyond the final sector
of the track (255D*). Will be set if TC is not issued after
Read or Write Data command.
Cylinder
6
5
Unused. This bit is always "0".
The FDC detected a CRC error in either the ID field or
the data field of a sector.
Becomes set if the FDC does not receive CPU or DMA
service within the required time interval, resulting in data
overrun or underrun.
DE
OR
Data Error
4
Overrun/
Underrun
3
2
Unused. This bit is always "0".
Any one of the following:
ND
No Data
1.
2.
3.
Read Data, Read Deleted Data command -
the FDC did not find the specified sector.
Read ID command - the FDC cannot read the
ID field without an error.
Read A Track command - the FDC cannot
find the proper sector sequence.
1
0
NW
MA
Not Writable
Missing
WP pin became a "1" while the FDC is executing a Write
Data, Write Deleted Data, or Format A Track command.
Any one of the following:
Address Mark 1.
The FDC did not detect an ID address mark
at the specified track after encountering the
index pulse from the IDX pin twice.
2.
The FDC cannot detect a data address mark
or
a
deleted data address mark on the
specified track.
* D= Decimal
23
Table 16 - Status Register 2
NAME
BIT NO.
SYMBOL
CM
DESCRIPTION
Unused. This bit is always "0".
7
6
Control Mark Any one of the following:
1.
Read Data command - the FDC encountered a
deleted data address mark.
2.
Read Deleted Data command - the FDC
encountered a data address mark.
5
4
DD
Data Error in
Data Field
The FDC detected a CRC error in the data field.
WC
Wrong
The track address from the sector ID field is different
from the track address maintained inside the FDC.
Cylinder
3
2
1
Unused. This bit is always "0".
Unused. This bit is always "0".
The track address from the sector ID field is different
from the track address maintained inside the FDC and is
equal to FF hex, which indicates a bad track with a hard
error according to the IBM soft-sectored format.
BC
Bad Cylinder
0
MD
Missing Data The FDC cannot detect a data address mark or a deleted
Address Mark data address mark.
24
Table 17 - Status Register 3
NAME
BIT NO.
SYMBOL
WP
DESCRIPTION
Unused. This bit is always "0".
7
6
Write
Indicates the status of the WP pin.
Protected
5
4
3
Unused. This bit is always "1".
Indicates the status of the TRK0 pin.
Unused. This bit is always "1".
T0
Track 0
2
HD
Head Address Indicates the status of the HDSEL pin.
1,0
DS1,0
Drive Select
Indicates the status of the DS1, DS0 pins.
RESET
DOR Reset vs. DSR Reset (Software Reset)
There are three sources of system reset on the
FDC: the RESET pin of the FDC37C78, a reset
generated via a bit in the DOR, and a reset
generated via a bit in the DSR. At power on, a
Power On Reset initializes the FDC. All resets
take the FDC out of the power down state.
These two resets are functionally the same. Both
will reset the FDC core, which affects drive status
information and the FIFO circuits. The DSR reset
clears itself automatically while the DOR reset
requires the host to manually clear it. DOR reset
has precedence over the DSR reset. The DOR
reset is set automatically upon a pin reset. The
user must manually clear this reset bit in the DOR
to exit the reset state.
All operations are terminated upon a RESET, and
the FDC enters an idle state. A reset while a disk
write is in progress will corrupt the data and CRC.
MODE OF OPERATION
On exiting the reset state, various internal
registers are cleared, including the Configure
command information, and the FDC waits for a
new command. Drive polling will start unless
disabled by a new Configure command.
PC/AT mode - (IDENT high, MFM a "don't care")
The PC/AT register set is enabled, the DMA
enable bit of the DOR becomes valid (IRQ and
DRQ can be hi Z), and TC and DENSEL become
active high signals.
RESET Pin (Hardware Reset)
The RESET pin is a global reset and clears all
registers except those programmed by the Specify
command. The DOR reset bit is enabled and
must be cleared by the host to exit the reset state.
25
Before writing to the FDC, the host must examine
the RQM and DIO bits of the Main Status Register.
RQM and DIO must be equal to "1" and "0"
respectively before command bytes may be
written. RQM is set false by the FDC after each
write cycle until the received byte is processed.
The FDC asserts RQM again to request each
parameter byte of the command unless an illegal
command condition is detected. After the last
parameter byte is received, RQM remains "0" and
the FDC automatically enters the next phase as
defined by the command definition.
DMA TRANSFERS
DMA transfers are enabled with the Specify
command and are initiated by the FDC by
activating the DRQ pin during a data transfer
command. The FIFO is enabled directly by
asserting nDACK and addresses need not be
valid.
Note that if the DMA controller (i.e. 8237A) is
programmed to function in verify mode, a pseudo
read is performed by the FDC based only on
nDACK. This mode is only available when the
FDC has been configured into byte mode (FIFO
disabled) and is programmed to do a read. With
the FIFO enabled, the FDC can perform the above
operation by using the new Verify command; no
DMA operation is needed.
The FIFO is disabled during the command phase
to provide for the proper handling of the "Invalid
Command" condition.
Execution Phase
All data transfers to or from the FDC occur during
the execution phase, which can proceed in DMA
or non-DMA mode as indicated in the Specify
command.
CONTROLLER PHASES
For simplicity, command handling in the FDC can
be divided into three phases:
Command,
Execution, and Result. Each phase is described in
the following sections.
After a reset, the FIFO is disabled. Each data byte
is transferred by an IRQ or DRQ depending on the
DMA mode. The Configure command can enable
the FIFO and set the FIFO threshold value.
Command Phase
After a reset, the FDC enters the command phase
and is ready to accept a command from the host.
For each of the commands, a defined set of
command code bytes and parameter bytes has to
be written to the FDC before the command phase
is complete. (Please refer to Table 18 for the
command set descriptions). These bytes of data
must be transferred in the order prescribed.
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
<threshold> is defined as the number of bytes
available to the FDC when service is requested
from the host and ranges from 1 to 16. The
parameter FIFOTHR, which the user programs, is
one less and ranges from 0 to 15.
26
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host reads (writes)
from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must be
very responsive to the service request. This is the
desired case for use with a "fast" system.
DMA Mode - Transfers from the FIFO to the Host
The FDC activates the DDRQ pin when the FIFO
contains (16 - <threshold>) bytes, or the last byte
of a full sector transfer has been placed in the
FIFO. The DMA controller must respond to the
request by reading data from the FIFO. The FDC
will deactivate the DDRQ pin when the FIFO
becomes empty. DRQ goes inactive after nDACK
goes active for the last byte of a data transfer
(or on the active edge of nIOR, on the last byte, if
no edge is present on nDACK). A data underrun
may occur if DRQ is not removed in time to
prevent an unwanted cycle.
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in more
frequent service requests.
Non-DMA Mode - Transfers from the FIFO to the
Host
DMA Mode - Transfers from the Host to the FIFO
The IRQ pin and RQM bits in the Main Status
Register are activated when the FIFO contains
(16-<threshold>) bytes or the last bytes of a full
sector have been placed in the FIFO. The IRQ pin
can be used for interrupt-driven systems, and
RQM can be used for polled systems. The host
must respond to the request by reading data from
the FIFO. This process is repeated until the last
byte is transferred out of the FIFO. The FDC will
deactivate the IRQ pin and RQM bit when the
FIFO becomes empty.
The FDC activates the DRQ pin when entering the
execution phase of the data transfer commands.
The DMA controller must respond by activating the
nDACK and nIOW pins and placing data in the
FIFO.
DRQ remains active until the FIFO
becomes full. DRQ is again set true when the
FIFO has <threshold> bytes remaining in the
FIFO. The FDC will also deactivate the DRQ pin
when TC becomes true (qualified by nDACK),
indicating that no more data is required. DRQ
goes inactive after nDACK goes active for the
last byte of a data transfer (or on the active edge
of nIOW of the last byte, if no edge is present on
nDACK). A data overrun may occur if DRQ is not
removed in time to prevent an unwanted cycle.
Non-DMA Mode - Transfers from the Host to the
FIFO
The IRQ pin and RQM bit in the Main Status
Register are activated upon entering the execution
phase of data transfer commands. The host must
respond to the request by writing data into the
FIFO. The IRQ pin and RQM bit remain true until
the FIFO becomes full. They are set true again
when the FIFO has <threshold> bytes remaining in
the FIFO. The IRQ pin will also be deactivated if
TC and nDACK both go inactive. The FDC
enters the result phase after the last byte is taken
by the FDC from the FIFO (i.e. FIFO empty
condition).
Data Transfer Termination
The FDC supports terminal count explicitly through
the TC pin and implicitly through the
underrun/overrun
and
end-of-track
(EOT)
functions. For full sector transfers, the EOT
parameter can define the last sector to be
transferred in a single or multi-sector transfer.
27
If the last sector to be transferred is a partial
sector, the host can stop transferring the data in
mid-sector, and the FDC will continue to complete
the sector as if a hardware TC was received. The
only difference between these implicit functions
and TC is that they return "abnormal termination"
result status. Such status indications can be
ignored if they were expected.
Result Phase
The generation of IRQ determines the beginning
of the result phase. For each of the commands, a
defined set of result bytes has to be read from the
FDC before the result phase is complete. These
bytes of data must be read out for another
command to start.
Note that when the host is sending data to the
FIFO of the FDC, the internal sector count will be
complete when the FDC reads the last byte from
its side of the FIFO. There may be a delay in the
removal of the transfer request signal of up to the
time taken for the FDC to read the last 16 bytes
from the FIFO. The host must tolerate this delay.
RQM and DIO must both equal "1" before the
result bytes may be read. After all the result bytes
have been read, the RQM and DIO bits switch to
"1" and "0" respectively, and the CB bit is cleared,
indicating that the FDC is ready to accept the next
command.
28
is issued. The user sends a Sense Interrupt
Status command which returns an invalid
command error. Refer to Table 18 or explanations
of the various symbols used. Table 19 lists the
required parameters and the results associated
with each command that the FDC is capable of
performing.
COMMAND SET/DESCRIPTIONS
Commands can be written whenever the FDC is in
the command phase. Each command has a
unique set of needed parameters and status
results. The FDC checks to see that the first byte
is a valid command and, if valid, proceeds with
the command. If it is invalid, an interrupt
Table 18 - Description of Command Symbols
SYMBOL
NAME
DESCRIPTION
C
D
Cylinder Address
Data Pattern
The currently selected address; 0 to 255.
The pattern to be written in each sector data field during formatting.
D0, D1, D2, Drive Select 0-3
Designates which drives are perpendicular drives on the
Perpendicular Mode Command. A "1" indicates a perpendicular
drive.
D3
DIR
Direction Control
Disk Drive Select
If this bit is 0, then the head will step out from the spindle during a
relative seek. If set to a 1, the head will step in toward the spindle.
DS0, DS1
DS1
DS0
DRIVE
drive 0
drive 1
drive 2
drive 3
0
0
1
1
0
1
0
1
DTL
Special Sector
Size
By setting N to zero (00), DTL may be used to control the number of
bytes transferred in disk read/write commands. The sector size (N =
0) is set to 128. If the actual sector (on the diskette) is larger than
DTL, the remainder of the actual sector is read but is not passed to
the host during read commands; during write commands, the
remainder of the actual sector is written with all zero bytes. The CRC
check code is calculated with the actual sector. When N is not zero,
DTL has no meaning and should be set to FF HEX.
EC
Enable Count
Enable FIFO
When this bit is "1" the "DTL" parameter of the Verify command
becomes SC (number of sectors per track).
EFIFO
EIS
This active low bit when a 0, enables the FIFO. A "1" disables the
FIFO (default).
When set, a seek operation will be performed before executing any
read or write command that requires the C parameter in the
command phase. A "0" disables the implied seek.
Enable Implied
Seek
EOT
GAP
GPL
End of Track
The final sector number of the current track.
Alters Gap 2 length when using Perpendicular Mode.
Gap Length
The Gap 3 size. (Gap 3 is the space between sectors excluding the
VCO synchronization field).
H/HDS
Head Address
Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID
29
Table 18 - Description of Command Symbols
SYMBOL
HLT
NAME
DESCRIPTION
field.
Head Load Time
The time interval that FDC waits after loading the head and before
initializing a read or write operation. Refer to the Specify command
for actual delays.
HUT
Head Unload Time The time interval from the end of the execution phase (of a read or
write command) until the head is unloaded. Refer to the Specify
command for actual delays.
LOCK
Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters
of the CONFIGURE COMMAND can be reset to their default values
by a "software Reset". (A reset caused by writing to the appropriate
bits of either tha DSR or DOR)
MFM
MT
MFM/FM Mode
Selector
A one selects the double density (MFM) mode. A zero selects single
density (FM) mode.
Multi-Track
When set, this flag selects the multi-track operating mode. In this
mode, the FDC treats a complete cylinder under head 0 and 1 as a
single track. The FDC operates as this expanded track started at the
first sector under head 0 and ended at the last sector under head 1.
With this flag set, a multitrack read or write operation will
automatically continue to the first sector under head 1 when the FDC
finishes operating on the last sector under head 0.
Selector
N
Sector Size Code This specifies the number of bytes in a sector. If this parameter is
“00”, then the sector size is 128 bytes. The number of bytes
transferred is determined by the DTL parameter. Otherwise the
sector size is (2 raised to the “N’th” power) times 128. All values up
to “07” hes are allowable. “07”H would equal a sector size of 16k. It
is the user’s resposibility to not select combinations that are not
possible with the drive.
N
00
01
02
03
..
SECTOR SIZE
128 bytes
256 bytes
512 bytes
1024 bytes
...
07
16 Kbytes
NCN
ND
New Cylinder
Number
The desired cylinder number.
Non-DMA Mode
When set to 1, indicates that the FDC is to operate in the non-DMA
mode. In this mode, the host is interrupted for each data transfer.
When set to 0, the FDC operates in DMA mode, interfacing to a DMA
controller by means of the DRQ and DACK signals.
Flag
OW
Overwrite
The bits D0-D3 of the Perpendicular Mode Command can only be
30
Table 18 - Description of Command Symbols
SYMBOL
PCN
NAME
DESCRIPTION
modified if OW is set to 1. OW id defined in the Lock command.
Present Cylinder
Number
The current position of the head at the completion of Sense Interrupt
Status command.
POLL
Polling Disable
When set, the internal polling routine is disabled. When clear, polling
is enabled.
PRETRK
Precompensation Programmable from track 00 to FFH.
Start Track
Number
R
Sector Address
The sector number to be read or written. In multi-sector transfers,
this parameter specifies the sector number of the first sector to be
read or written.
RCN
SC
Relative Cylinder
Number
Relative cylinder offset from present cylinder as used by the Relative
Seek command.
Number of Sectors The number of sectors per track to be initialized by the Format
Per Track
Skip Flag
command. The number of sectors per track to be verified during a
Verify command when EC is set.
SK
When set to 1, sectors containing a deleted data address mark will
automatically be skipped during the execution of Read Data. If Read
Deleted is executed, only sectors with a deleted address mark will be
accessed. When set to "0", the sector is read or written the same as
the read and write commands.
SRT
Step Rate Interval The time interval between step pulses issued by the FDC.
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at
the 1 Mbit data rate. Refer to the SPECIFY command for actual
delays.
ST0
Status 0
Status 1
Status 2
Status 3
Write Gate
Registers within the FDC which store status information after a
command has been executed. This status information is available to
the host during the result phase after command execution.
ST1
ST2
ST3
WGATE
Alters timing of WE to allow for pre-erase loads in perpendicular
drives.
31
INSTRUCTION SET
Table 19 - Instruction Set
READ DATA
DATA BUS
PHASE
Command
R/W
REMARKS
Command Codes
D7
D6
D5 D4 D3 D2 D1 D0
W
W
W
MT MFM SK
0
0
0
0
0
1
1
0
0
0
HDS DS1 DS0
──────── C ────────
Sector ID information prior to
Command execution.
W
W
W
W
W
W
──────── H ────────
──────── R ────────
──────── N ────────
─────── EOT ───────
─────── GPL ───────
─────── DTL ───────
Execution
Result
Data transfer between the
FDD and system.
R
─────── ST0 ───────
Status information after Com-
mand execution.
R
R
R
─────── ST1 ───────
─────── ST2 ───────
──────── C ────────
Sector ID information after
Command execution.
R
R
R
──────── H ────────
──────── R ────────
──────── N ────────
32
READ DELETED DATA
DATA BUS
PHASE
Command
R/W
REMARKS
Command Codes
D7
D6
D5 D4 D3 D2 D1 D0
W
W
W
MT MFM SK
0
0
0
1
0
1
0
0
0
0
HDS DS1 DS0
──────── C ────────
Sector ID information prior to
Command execution.
W
W
W
W
W
W
──────── H ────────
──────── R ────────
──────── N ────────
─────── EOT ───────
─────── GPL ───────
─────── DTL ───────
Execution
Result
Data transfer between the
FDD and system.
R
─────── ST0 ───────
Status information after Com-
mand execution.
R
R
R
─────── ST1 ───────
─────── ST2 ───────
──────── C ────────
Sector ID information after
Command execution.
R
R
R
──────── H ────────
──────── R ────────
──────── N ────────
33
WRITE DATA
DATA BUS
PHASE
Command
R/W
REMARKS
Command Codes
D7
MT MFM
0
D6
D5 D4 D3 D2 D1 D0
W
W
W
0
0
0
0
0
0
1
0
1
0
HDS DS1 DS0
──────── C ────────
Sector ID information prior to
Command execution.
W
W
W
W
W
W
──────── H ────────
──────── R ────────
──────── N ────────
─────── EOT ───────
─────── GPL ───────
─────── DTL ───────
Execution
Result
Data transfer between the
FDD and system.
R
─────── ST0 ───────
Status information after Com-
mand execution.
R
R
R
─────── ST1 ───────
─────── ST2 ───────
──────── C ────────
Sector ID information after
Command execution.
R
R
R
──────── H ────────
──────── R ────────
──────── N ────────
34
WRITE DELETED DATA
DATA BUS
PHASE
R/W
REMARKS
D7
D6
D5 D4 D3
D2
D1
D0
Command
W
W
W
MT MFM
0
0
0
0
1
0
0
0
1
Command Codes
0
0
HDS DS1 DS0
──────── C ────────
Sector ID information
prior to Command
execution.
W
W
W
W
W
W
──────── H ────────
──────── R ────────
──────── N ────────
─────── EOT ───────
─────── GPL ───────
─────── DTL ───────
Execution
Result
Data transfer between
the FDD and system.
R
─────── ST0 ───────
Status information after
Command execution.
R
R
R
─────── ST1 ───────
─────── ST2 ───────
──────── C ────────
Sector ID information
after Command
execution.
R
R
R
──────── H ────────
──────── R ────────
──────── N ────────
35
READ A TRACK
DATA BUS
PHASE
Command
R/W
REMARKS
Command Codes
D7
0
0
D6
MFM
0
D5 D4 D3
D2
0
D1
1
D0
0
W
W
W
0
0
0
0
0
0
HDS DS1 DS0
──────── C ────────
Sector ID information
prior to Command
execution.
W
W
W
W
W
W
──────── H ────────
──────── R ────────
──────── N ────────
─────── EOT ───────
─────── GPL ───────
─────── DTL ───────
Execution
Result
Data transfer between
the FDD and system.
FDC reads all of
cylinders' contents from
index hole to EOT.
Status information after
Command execution.
R
─────── ST0 ───────
R
R
R
─────── ST1 ───────
─────── ST2 ───────
──────── C ────────
Sector ID information
after Command
execution.
R
R
R
──────── H ────────
──────── R ────────
──────── N ────────
36
VERIFY
DATA BUS
PHASE
R/W
REMARKS
D7
D6
D5 D4 D3
D2
D1
D0
Command
W
W
W
MT MFM SK
1
0
0
0
1
1
0
Command Codes
EC
0
0
HDS DS1 DS0
──────── C ────────
Sector ID information
prior to Command
execution.
W
W
W
W
W
W
──────── H ────────
──────── R ────────
──────── N ────────
─────── EOT ───────
─────── GPL ───────
────── DTL/SC ──────
Execution
Result
No data transfer takes
place.
R
─────── ST0 ───────
Status information after
Command execution.
R
R
R
─────── ST1 ───────
─────── ST2 ───────
──────── C ────────
Sector ID information
after Command
execution.
R
R
R
──────── H ────────
──────── R ────────
──────── N ────────
VERSION
DATA BUS
PHASE
Command
Result
R/W
W
R
REMARKS
Command Code
Enhanced Controller
D7
0
1
D6
0
0
D5 D4 D3
D2
0
0
D1
0
0
D0
0
0
0
0
1
1
0
0
37
FORMAT A TRACK
DATA BUS
PHASE
Command
R/W
REMARKS
Command Codes
D7
0
0
D6
MFM
0
D5 D4 D3
D2
1
D1
0
D0
1
W
W
W
W
W
W
0
0
0
0
1
0
HDS DS1 DS0
──────── N ────────
──────── SC ────────
─────── GPL ───────
──────── D ────────
Bytes/Sector
Sectors/Cylinder
Gap 3
Filler Byte
Execution for
Each Sector
Repeat:
W
──────── C ────────
Input Sector Parameters
W
W
W
──────── H ────────
──────── R ────────
──────── N ────────
FDC formats an entire
cylinder
Result
R
─────── ST0 ───────
Status information after
Command execution
R
R
R
R
R
R
─────── ST1 ───────
─────── ST2 ───────
────── Undefined ──────
────── Undefined ──────
────── Undefined ──────
────── Undefined ──────
38
RECALIBRATE
DATA BUS
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3 D2
D1
D0
Command
W
W
0
0
0
0
0
0
0
0
0
0
1
0
1
1
Command Codes
DS1 DS0
Execution
Head retracted to Track 0
Interrupt.
SENSE INTERRUPT STATUS
DATA BUS
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3 D2 D1 D0
Command
Result
W
R
0
0
0
0
1
0
0
0
Command Codes
─────── ST0 ───────
Status information at the end
of each seek operation.
R
─────── PCN ───────
SPECIFY
DATA BUS
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3 D2 D1 D0
Command
W
W
W
0
0
0
0
0
0
1
1
Command Codes
─── SRT ───
─── HUT ───
────── HLT ──────
ND
39
SENSE DRIVE STATUS
DATA BUS
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3
D2
D1
D0
Command
W
W
R
0
0
0
0
0
0
0
0
0
0
1
0
0
Command Codes
HDS DS1 DS0
Result
─────── ST3 ───────
Status information about
FDD
SEEK
DATA BUS
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3
D2
D1
D0
Command
W
W
W
0
0
0
0
0
0
0
0
1
0
1
1
1
Command Codes
HDS DS1 DS0
─────── NCN ───────
Execution
Head positioned over
proper cylinder on
diskette.
CONFIGURE
DATA BUS
PHASE
Command
R/W
W
REMARKS
Configure
Information
D7 D6
D5
0
D4
1
D3
0
D2
0
D1
1
D0
1
0
0
W
W
W
0
0
0
0
0
0
0
0
0
EIS EFIFO POLL
─── FIFOTHR ───
Execution
───────── PRETRK ─────────
40
RELATIVE SEEK
DATA BUS
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3
D2
D1
D0
Command
W
W
W
1
0
DIR
0
0
0
0
0
1
0
1
1
1
HDS DS1 DS0
─────── RCN ───────
DUMPREG
DATA BUS
PHASE
R/W
REMARKS
D7
D6
D5
D4
D3 D2
D1
D0
Command
W
0
0
0
0
1
1
1
0
*Note:
Registers
placed in
FIFO
Execution
Result
R
R
R
R
R
R
R
R
R
R
────── PCN-Drive 0 ───────
────── PCN-Drive 1 ───────
────── PCN-Drive 2 ───────
────── PCN-Drive 3 ───────
──── SRT ────
─────── HLT ───────
─────── SC/EOT ───────
D3 D2 D1 D0
EIS EFIFO POLL
──────── PRETRK ────────
─── HUT ───
ND
LOCK
0
0
GAP
WGATE
── FIFOTHR ──
41
READ ID
DATA BUS
PHASE
Command
R/W
W
W
REMARKS
Commands
D7
0
0
D6
MFM
0
D5 D4 D3
D2
0
D1
1
D0
0
0
0
0
0
1
0
HDS DS1 DS0
Execution
Result
The first correct ID
information on the
Cylinder is stored in Data
Register
R
──────── ST0 ────────
Status information after
Command execution.
Disk status after the
Command has
completed
R
R
R
R
R
R
──────── ST1 ────────
──────── ST2 ────────
──────── C ────────
──────── H ────────
──────── R ────────
──────── N ────────
42
PERPENDICULAR MODE
DATA BUS
PHASE
Command
R/W
W
REMARKS
Command Codes
D7
0
OW
D6 D5 D4 D3 D2
D1
1
GAP
D0
0
WGATE
0
0
0
1
0
0
D3 D2 D1 D0
INVALID CODES
DATA BUS
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3 D2 D1 D0
Command
W
───── Invalid Codes ─────
Invalid Command Codes
(NoOp - fdc goes into Standby
State)
Result
R
─────── ST0 ───────
ST0 = 80H
LOCK
DATA BUS
PHASE
Command
Result
R/W
W
R
REMARKS
Command Codes
D7
LOCK
0
D6 D5
D4
1
LOCK
D3 D2 D1 D0
0
0
0
0
0
0
1
0
0
0
0
0
SC is returned if the last command that was issued was the Format command. EOT is returned if the last
command was a Read or Write.
NOTE: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's
responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).
43
N determines the number of bytes per sector (see
Table 22 below). If N is set to zero, the sector size
is set to 128. The DTL value determines the
number of bytes to be transferred. If DTL is less
than 128, the FDC transfers the specified number
of bytes to the host. For reads, it continues to
read the entire 128-byte sector and checks for
CRC errors. For writes, it completes the 128-byte
sector by filling in zeros. If N is not set to 00 Hex,
DTL should be set to FF Hex and has no impact
on the number of bytes transferred.
DATA TRANSFER COMMANDS
All of the Read Data, Write Data and Verify type
commands use the same parameter bytes and
return the same results information, the only
difference being the coding of bits 0-4 in the first
byte.
An implied seek will be executed if the feature was
enabled by the Configure command. This seek is
completely transparent to the user. The Drive
Busy bit for the drive will go active in the Main
Status Register during the seek portion of the
command. If the seek portion fails, it will be
reflected in the results status normally returned for
a Read/Write Data command. Status Register 0
(ST0) would contain the error code and C would
contain the cylinder on which the seek failed.
Table 20 - Sector Sizes
N
SECTOR SIZE
00
01
02
03
..
128 bytes
256 bytes
512 bytes
1024 bytes
...
Read Data
07
16 Kbytes
A set of nine (9) bytes is required to place the FDC
in the Read Data Mode. After the Read Data
command has been issued, the FDC loads the
head (if it is in the unloaded state), waits the
specified head settling time (defined in the Specify
command), and begins reading ID Address Marks
and ID fields. When the sector address read off
the diskette matches with the sector address
specified in the command, the FDC reads the
sector's data field and transfers the data to the
FIFO.
The amount of data which can be handled with a
single command to the FDC depends upon MT
(multi-track) and N (number of bytes/sector).
The Multi-Track function (MT) allows the FDC to
read data from both sides of the diskette. For a
particular cylinder, data will be transferred starting
at Sector 1, Side 0 and completing the last sector
of the same track at Side 1.
After completion of the read operation from the
current sector, the sector address is incremented
by one and the data from the next logical sector is
read and output via the FIFO. This continuous
read function is called "Multi-Sector Read
Operation". Upon receipt of TC, or an implied TC
(FIFO overrun/underrun), the FDC stops sending
data but will continue to read data from the current
sector, check the CRC bytes, and at the end of the
sector, terminate the Read Data Command.
If the host terminates a read or write operation in
the FDC, the ID information in the result phase is
dependent upon the state of the MT bit and EOT
byte. Refer to Table 21.
44
At the completion of the Read Data command, the
head is not unloaded until after the Head Unload
Time Interval (specified in the Specify command)
has elapsed. If the host issues another command
before the head unloads, then the head settling
time may be saved between subsequent reads.
After reading the ID and Data Fields in each
sector, the FDC checks the CRC bytes. If a
CRC error occurs in the ID or data field, the FDC
sets the IC code in Status Register 0 to "01"
indicating abnormal termination, sets the DE bit
flag in Status Register 1 to "1", sets the DD bit in
Status Register 2 to "1" if CRC is incorrect in the
ID field, and terminates the Read Data
Command. Table 22 describes the effect of the
SK bit on the Read Data command execution
and results. Except where noted in Table 22,
If the FDC detects a pulse on the nINDEX pin
twice without finding the specified sector (meaning
that the diskette's index hole passes through index
detect logic in the drive twice), the FDC sets the IC
code in Status Register 0 to "01" indicating
abnormal termination, sets the ND bit in Status
Register 1 to "1" indicating a sector not found, and
terminates the Read Data Command.
the
C or R value of the sector address is
automatically incremented (see Table 24).
Table 21 - Effects of MT and N Bits
MT
N
MAXIMUM TRANSFER
FINAL SECTOR READ
CAPACITY
FROM DISK
0
1
0
1
0
1
1
1
2
2
3
3
256 x 26 = 6,656
256 x 52 = 13,312
512 x 15 = 7,680
512 x 30 = 15,360
1024 x 8 = 8,192
1024 x 16 = 16,384
26 at side 0 or 1
26 at side 1
15 at side 0 or 1
15 at side 1
8 at side 0 or 1
16 at side 1
Table 22 - Skip Bit vs Read Data Command
DATA ADDRESS
RESULTS
SK BIT
MARK TYPE
SECTOR CM BIT OF DESCRIPTION OF
VALUE
ENCOUNTERED
READ?
ST2 SET?
RESULTS
0
Normal Data
Yes
No
Normal
termination.
Address not
incremented. Next
sector not
0
Deleted Data
Yes
Yes
searched for.
Normal
1
1
Normal Data
Deleted Data
Yes
No
No
termination.
Normal
Yes
termination. Sector
not read
("skipped").
45
Table 23describes the effect of the SK bit on the
Read Deleted Data command execution and
results.
Read Deleted Data
This command is the same as the Read Data
command, only it operates on sectors that contain
a Deleted Data Address Mark at the beginning of a
Data Field.
Except where noted in Table 25, the C or R value
of the sector address is automatically incremented
(see Table 26).
Table 23 - Skip Bit vs. Read Deleted Data Command
DATA ADDRESS
RESULTS
SK BIT
VALUE
MARK TYPE
SECTOR CM BIT OF DESCRIPTION OF
ENCOUNTERED
READ?
ST2 SET?
RESULTS
0
Normal Data
Yes
Yes
Address not
incremented. Next
sector not
searched for.
Normal
0
1
Deleted Data
Normal Data
Yes
No
No
termination.
Normal
Yes
termination. Sector
not read
("skipped").
Normal
1
Deleted Data
Yes
No
termination.
Register 1 to a "1" if there is no comparison. Multi-
track or skip operations are not allowed with this
command. The MT and SK bits (bits D7 and D5 of
the first command byte respectively) should always
be set to "0".
Read A Track
This command is similar to the Read Data
command except that the entire data field is read
continuously from each of the sectors of a track.
Immediately after encountering a pulse on the
nINDEX pin, the FDC starts to read all data
fields on the track as continuous blocks of data
without regard to logical sector numbers. If the
FDC finds an error in the ID or DATA CRC check
bytes, it continues to read data from the track and
sets the appropriate error bits at the end of the
command. The FDC compares the ID information
read from each sector with the specified value in
the command and sets the ND flag of Status
This command terminates when the EOT specified
number of sectors has not been read. If the FDC
does not find an ID Address Mark on the diskette
after the second occurrence of a pulse on the IDX
pin, then it sets the IC code in Status Register 0 to
"01" (abnormal termination), sets the MA bit in
Status Register 1 to "1", and terminates the
command.
46
Table 24 - Result Phase Table
FINAL SECTOR
TRANSFERRED TO
HOST
ID INFORMATION AT RESULT PHASE
MT
HEAD
C
H
R
N
Less than EOT
NC
NC
R + 1
NC
0
0
1
Equal to EOT
Less than EOT
Equal to EOT
Less than EOT
C + 1
NC
C + 1
NC
NC
NC
NC
NC
01
R + 1
01
NC
NC
NC
NC
R + 1
1
0
1
Equal to EOT
Less than EOT
Equal to EOT
NC
NC
C + 1
LSB
NC
LSB
01
R + 1
01
NC
NC
NC
NC: No Change, the same value as the one at the beginning of command execution.
LSB: Least Significant Bit, the LSB of H is complemented.
one of the ID fields, it sets the IC code in Status
Register 0 to "01" (abnormal termination), sets the
DE bit of Status Register 1 to "1", and terminates
the Write Data command.
Write Data
After the Write Data command has been issued,
the FDC loads the head (if it is in the unloaded
state), waits the specified head load time if
unloaded (defined in the Specify command), and
begins reading ID fields. When the sector address
read from the diskette matches the sector address
specified in the command, the FDC reads the data
from the host via the FIFO and writes it to the
sector's data field.
The Write Data command operates in much the
same manner as the Read Data command. The
following items are the same. Please refer to the
Read Data Command for details:
•
•
•
•
•
Transfer Capacity
EN (End of Cylinder) bit
ND (No Data) bit
After writing data into the current sector, the FDC
computes the CRC value and writes it into the
CRC field at the end of the sector transfer. The
Sector Number stored in "R" is incremented by
one, and the FDC continues writing to the next
data field. The FDC continues this "Multi-Sector
Write Operation". Upon receipt of a terminal count
signal or if a FIFO over/under run occurs while a
data field is being written, then the remainder of
the data field is filled with zeros.
Head Load, Unload Time Interval
ID information when the host terminates the
command
•
Definition of DTL when N = 0 and when N does
not = 0
The FDC reads the ID field of each sector and
checks the CRC bytes. If it detects a CRC error in
47
command. By setting the EC bit to "1", an implicit
TC will be issued to the FDC. This implicit TC will
occur when the SC value has decremented to 0
(an SC value of 0 will verify 256 sectors). This
command can also be terminated by setting the
EC bit to "0" and the EOT value equal to the final
sector to be checked. If EC is set to "0", DTL/SC
should be programmed to 0FFH. Refer to Table
26 and Table 27 for information concerning the
values of MT and EC versus SC and EOT value.
Write Deleted Data
This command is almost the same as the Write
Data command except that a Deleted Data
Address Mark is written at the beginning of the
Data Field instead of the normal Data Address
Mark. This command is typically used to mark a
bad sector containing an error on the floppy disk.
Verify
Definitions:
The Verify command is used to verify the data
stored on a disk. This command acts exactly like
a Read Data command except that no data is
transferred to the host. Data is read from the disk
and CRC is computed and checked against the
previously-stored value.
# Sectors Per Side = Number of formatted sectors
per each side of the disk.
# Sectors Remaining = Number of formatted
sectors left which can be read, including side 1 of
the disk if MT is set to "1".
Because data is not transferred to the host, TC
(pin 25) cannot be used to terminate this
Table 25 - Verify Command Result Phase Table
SC/EOT VALUE TERMINATION RESULT
MT
EC
0
0
SC = DTL
Success Termination
Result Phase Valid
EOT ≤ # Sectors Per Side
SC = DTL
0
0
0
1
1
1
1
0
1
1
0
0
1
1
Unsuccessful Termination
Result Phase Invalid
Successful Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
Successful Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
Successful Termination
Result Phase Valid
EOT > # Sectors Per Side
SC ≤ # Sectors Remaining AND
EOT ≤ # Sectors Per Side
SC > # Sectors Remaining OR
EOT > # Sectors Per Side
SC = DTL
EOT ≤ # Sectors Per Side
SC = DTL
EOT > # Sectors Per Side
SC ≤ # Sectors Remaining AND
EOT ≤ # Sectors Per Side
SC > # Sectors Remaining OR
EOT > # Sectors Per Side
Unsuccessful Termination
Result Phase Invalid
NOTE: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on
Side 0, verifying will continue on Side 1 of the disk.
48
After formatting each sector, the host must send
new values for C, H, R and N to the FDC for the
next sector on the track. The R value (sector
number) is the only value that must be changed by
the host after each sector is formatted. This
allows the disk to be formatted with nonsequential
sector addresses (interleaving). This incrementing
and formatting continues for the whole track until
the FDC encounters a pulse on the IDX pin again
and it terminates the command.
Format A Track
The Format command allows an entire track to be
formatted. After a pulse from the IDX pin is
detected, the FDC starts writing data on the disk
including gaps, address marks, ID fields, and data
fields per the IBM System 34 or 3740 format (MFM
or FM respectively). The particular values that will
be written to the gap and data field are controlled
by the values programmed into N, SC, GPL, and D
which are specified by the host during the
command phase. The data field of the sector is
filled with the data byte specified by D. The ID
field for each sector is supplied by the host; that is,
four data bytes per sector are needed by the FDC
for C, H, R, and N (cylinder, head, sector number
and sector size respectively).
Table 28 contains typical values for gap fields
which are dependent upon the size of the sector
and the number of sectors on each track. Actual
values can vary due to drive electronics.
FORMAT FIELDS
SYSTEM 34 (DOUBLE DENSITY) FORMAT
DATA
GAP4a SYNC
IAM
GAP1 SYNC IDAM
C
Y
L
H
D
S
E
C
N
O
C
R
C
GAP2 SYNC
AM
C
R
C
80x
4E
12x
00
50x
4E
12x
00
22x
4E
12x
00
DATA
DATA
DATA
GAP3 GAP 4b
GAP3 GAP 4b
GAP3 GAP 4b
3x FC
C2
3x FE
A1
3x FB
A1 F8
SYSTEM 3740 (SINGLE DENSITY) FORMAT
DATA
GAP4a SYNC
IAM
FC
GAP1 SYNC IDAM
C
Y
L
H
D
S
E
C
N
O
C
R
C
GAP2 SYNC
AM
C
R
C
40x
FF
6x
00
26x
FF
6x
00
11x
FF
6x
00
FE
FB or
F8
PERPENDICULAR FORMAT
DATA
AM
GAP4a SYNC
IAM
GAP1 SYNC IDAM
C
Y
L
H
D
S
E
C
N
O
C
R
C
GAP2 SYNC
C
R
C
80x
4E
12x
00
50x
4E
12x
00
41x
4E
12x
00
3x FC
C2
3x FE
A1
3x FB
A1 F8
49
Table 26 - Typical Values for Formatting
FORMAT SECTOR SIZE
N
SC
GPL1
GPL2
128
128
512
00
00
02
03
04
05
...
12
10
08
04
02
01
07
10
18
46
C8
C8
09
19
30
87
FF
FF
FM
1024
2048
4096
...
5.25"
Drives
256
256
01
01
02
03
04
05
...
12
10
09
04
02
01
0A
20
2A
80
C8
C8
0C
32
50
F0
FF
FF
512*
1024
2048
4096
...
MFM
128
256
512
0
1
2
0F
09
05
07
0F
1B
1B
2A
3A
FM
3.5"
Drives
256
512
1
2
3
0F
09
05
0E
1B
35
36
54
74
MFM
1024
GPL1 = suggested GPL values in Read and Write commands to avoid splice point
between data field and ID field of contiguous sections.
GPL2 = suggested GPL value in Format A Track command.
*PC/AT values (typical)
NOTE: All values except sector size are in hex.
50
must be issued after the Recalibrate command to
effectively terminate it and to provide verification of
the head position (PCN). During the command
phase of the recalibrate operation, the FDC is in
the BUSY state, but during the execution phase it
is in a NON-BUSY state. At this time, another
Recalibrate command may be issued, and in this
manner parallel Recalibrate operations may be
done on up to four drives at once.
CONTROL COMMANDS
Control commands differ from the other
commands in that no data transfer takes place.
Three commands generate an interrupt when
complete: Read ID, Recalibrate, and Seek. The
other control commands do not generate an
interrupt.
Read ID
Upon power up, the software must issue a
Recalibrate command to properly initialize all
drives and the controller.
The Read ID command is used to find the present
position of the recording heads. The FDC stores
the values from the first ID field it is able to read
into its registers. If the FDC does not find an ID
address mark on the diskette after the second
occurrence of a pulse on the nINDEX pin, it then
sets the IC code in Status Register 0 to "01"
(abnormal termination), sets the MA bit in Status
Register 1 to "1", and terminates the command.
Seek
The read/write head within the drive is moved from
track to track under the control of the Seek
command. The FDC compares the PCN, which is
the current head position, with the NCN and
performs the following operation if there is a
difference:
The following commands will generate an interrupt
upon completion. They do not return any result
bytes. It is highly recommended that control
commands be followed by the Sense Interrupt
Status command. Otherwise, valuable interrupt
status information will be lost.
PCN < NCN: Direction signal to drive set to
"1" (step in) and issues step pulses.
PCN > NCN: Direction signal to drive set to
"0" (step out) and issues step pulses.
The rate at which step pulses are issued is
controlled by SRT (Stepping Rate Time) in the
Specify command. After each step pulse is
issued, NCN is compared against PCN, and when
NCN = PCN the SE bit in Status Register 0 is set
to "1" and the command is terminated.
Recalibrate
This command causes the read/write head within
the FDC to retract to the track 0 position. The
FDC clears the contents of the PCN counter and
checks the status of the nTR0 pin from the FDD.
As long as the nTR0 pin is low, the DIR pin
remains 0 and step pulses are issued. When the
nTR0 pin goes high, the SE bit in Status
Register 0 is set to "1" and the command is
terminated. If the nTR0 pin is still low after 79
step pulses have been issued, the FDC sets the
SE and the EC bits of Status Register 0 to "1" and
terminates the command. Disks capable of
handling more than 80 tracks per side may require
more than one Recalibrate command to return the
head back to physical Track 0.
During the command phase of the seek or
recalibrate operation, the FDC is in the BUSY
state, but during the execution phase it is in the
NON-BUSY state. At this time, another Seek or
Recalibrate command may be issued, and in this
manner, parallel seek operations may be done on
up to four drives at once. Note that if implied seek
is not enabled, the read and write commands
should be preceded by:
1) Seek command - Step to the proper track
2) Sense Interrupt Status command - Terminate
the Seek command
The Recalibrate command does not have a result
3) Read ID - Verify head is on proper track
phase.
The Sense Interrupt Status command
51
4) Issue Read/Write command.
The Seek, Relative Seek, and Recalibrate
commands have no result phase. The Sense
Interrupt Status command must be issued
immediately after these commands to terminate
them and to provide verification of the head
position (PCN). The H (Head Address) bit in ST0
will always return a "0". If a Sense Interrupt Status
is not issued, the drive will continue to be BUSY
and may affect the operation of the next
command.
The Seek command does not have a result
phase. Therefore, it is highly recommended that
the Sense Interrupt Status command be issued
after the Seek command to terminate it and to
provide verification of the head position (PCN).
The H bit (Head Address) in ST0 will always
return to a "0". When exiting POWERDOWN
mode, the FDC clears the PCN value and the
status information to zero. Prior to issuing the
POWERDOWN
command,
it
is
highly
Sense Drive Status
recommended that the user service all pending
interrupts through the Sense Interrupt Status
command.
Sense Drive Status obtains drive status
information. It has not execution phase and goes
directly to the result phase from the command
phase. Status Register 3 contains the drive status
information.
Sense Interrupt Status
An interrupt signal on IRQ pin is generated by the
FDC for one of the following reasons:
1.Upon entering the Result Phase of:
a. Read Data command
Specify
The Specify command sets the initial values for
each of the three internal times. The HUT (Head
Unload Time) defines the time from the end of the
execution phase of one of the read/write
commands to the head unload state. The SRT
(Step Rate Time) defines the time interval between
adjacent step pulses. Note that the spacing
between the first and second step pulses may be
shorter than the remaining step pulses. The HLT
(Head Load Time) defines the time between when
the Head Load signal goes high and the read/write
operation starts. The values change with the
data rate speed selection and are documented in
Table 28. The values are the same for MFM and
FM.
b. Read A Track command
c. Read ID command
d. Read Deleted Data command
e. Write Data command
f. Format A Track command
g. Write Deleted Data command
h. Verify command
2. End of Seek, Relative Seek, or Recalibrate
command
3. FDC requires a data transfer during the
execution phase in the non-DMA mode
The Sense Interrupt Status command resets the
interrupt signal and, via the IC code and SE bit of
Status Register 0, identifies the cause of the
interrupt.
Table 27 - Interrupt Identification
SE
IC
INTERRUPT DUE TO
Polling
0
11
1
00
Normal termination of Seek
or Recalibrate command
Abnormal termination of
Seek or Recalibrate
command
1
01
52
Table 28 - Drive Control Delays (ms)
HUT
SRT
2M
1M
500K 300K 250K
2M
1M
500K 300K 250K
0
1
..
E
F
64
128
256
426
26.7
..
512
4
8
7.5
..
16
15
..
26.7
32
30
..
4
8
16
32
3.75
..
25
..
..
..
..
..
56
60
112
120
224
240
373
400
448
480
0.5
0.25
1
2
3.33
1.67
4
0.5
1
2
HLT
2M
1M
500K
300K
250K
00
01
02
..
64
0.5
1
128
256
426
3.3
6.7
..
512
1
2
4
2
4
8
..
..
..
.
7F
7F
63
63.5
126
127
252
254
420
423
504
508
The choice of DMA or non-DMA operations is
made by the ND bit. When this bit is "1", the non-
DMA mode is selected, and when ND is "0", the
DMA mode is selected. In DMA mode, data
transfers are signalled by the FDRQ pin. Non-
DMA mode uses the RQM bit and the FINT pin to
signal data transfers.
executing a read or write command. Defaults to
no implied seek.
EFIFO - A "1" disables the FIFO (default). This
means data transfers are asked for on a byte-by-
byte basis. Defaults to "1", FIFO disabled. The
threshold defaults to "1".
POLL - Disable polling of the drives. Defaults to
"0", polling enabled. When enabled, a single
interrupt is generated after a reset. No polling is
performed while the drive head is loaded and the
head unload delay has not expired.
Configure
The Configure command is issued to select the
special features of the FDC.
A Configure
command need not be issued if the default values
of the FDC meet the system requirements.
FIFOTHR - The FIFO threshold in the execution
phase of read or write commands. This is
programmable from 1 to 16 bytes. Defaults to one
byte. A "00" selects one byte; "0F" selects 16
bytes.
Configure Default Values:
EIS - No Implied Seeks
EFIFO - FIFO Disabled
POLL - Polling Enabled
FIFOTHR - FIFO Threshold Set to 1 Byte
PRETRK - Pre-Compensation Set to Track 0
PRETRK
-
Pre-Compensation Start Track
Number. Programmable from track 0 to 255.
Defaults to track 0. A "00" selects track 0; "FF"
selects track 255.
EIS - Enable Implied Seek. When set to "1", the
FDC will perform
a Seek operation before
53
increment the register). If the head was on track
40 (d), the maximum track that the FDC could
position the head on using Relative Seek will be
295 (D), the initial track + 255 (D). The maximum
count that the head can be moved with a single
Relative Seek command is 255 (D).
Version
The Version command checks to see if the
controller is an enhanced type or the older type
(765A). A value of 90 H is returned as the result
byte.
The internal register, PCN, will overflow as the
cylinder number crosses track 255 and will contain
39 (D). The resulting PCN value is thus (RCN +
PCN) mod 256. Functionally, the FDC starts
counting from 0 again as the track number goes
above 255 (D). It is the user's responsibility to
compensate FDC functions (precompensation
track number) when accessing tracks greater than
255. The FDC does not keep track that it is
working in an "extended track area" (greater than
255). Any command issued will use the current
PCN value except for the Recalibrate command,
which only looks for the TRACK0 signal.
Recalibrate will return an error if the head is farther
than 79 due to its limitation of issuing a maximum
of 80 step pulses. The user simply needs to issue
Relative Seek
The command is coded the same as for Seek,
except for the MSB of the first byte and the DIR
bit.
DIR
Head Step Direction Control
DIR
ACTION
0
Step Head Out
1
Step Head In
RCN Relative Cylinder Number that determines
how many tracks to step the head in or out
from the current track number.
a second Recalibrate command.
The Seek
The Relative Seek command differs from the Seek
command in that it steps the head the absolute
number of tracks specified in the command
instead of making a comparison against an
internal register. The Seek command is good for
drives that support a maximum of 256 tracks.
Relative Seeks cannot be overlapped with other
Relative Seeks. Only one Relative Seek can be
command and implied seeks will function correctly
within the 44 (D) track (299-255) area of the
"extended track area". It is the user's responsibility
not to issue a new track position that will exceed
the maximum track that is present in the extended
area. To return to the standard floppy range (0-
255) of tracks, a Relative Seek should be issued to
cross the track 255 boundary.
active at
a time. Relative Seeks may be
overlapped with Seeks and Recalibrates. Bit 4 of
Status Register 0 (EC) will be set if Relative Seek
attempts to step outward beyond Track 0.
A Relative Seek can be used instead of the normal
Seek, but the host is required to calculate the
difference between the current head location and
the new (target) head location. This may require
the host to issue a Read ID command to ensure
that the head is physically on the track that
As an example, assume that a floppy drive has
300 useable tracks. The host needs to read track
300 and the head is on any track (0-255). If a
Seek command is issued, the head will stop at
track 255. If a Relative Seek command is issued,
the FDC will move the head the specified number
of tracks, regardless of the internal cylinder
software assumes it to be.
Different FDC
commands will return different cylinder results
which may be difficult to keep track of with
software without the Read ID command.
Perpendicular Mode
position
register
(but
will
The Perpendicular Mode command should be
issued prior to executing Read/Write/Format
commands that access
a
disk drive with
With this
perpendicular recording capability.
54
command, the length of the Gap2 field and VCO
enable timing can be altered to accommodate the
unique requirements of these drives. Table 31
describes the effects of the WGATE and GAP bits
for the Perpendicular Mode command. Upon a
reset, the FDC will default to the conventional
mode (WGATE = 0, GAP = 0).
approximately 24 bytes from the start of the Gap2
field. But, when the controller operates in the 1
Mbps perpendicular mode (WGATE = 1, GAP =
1), VCOEN goes active after 43 bytes to
accommodate the increased Gap2 field size. For
both cases, and approximate two-byte cushion is
maintained from the beginning of the sync field for
the purposes of avoiding write splices in the
presence of motor speed variation.
Selection of the 500 Kbps and
1
Mbps
perpendicular modes is independent of the actual
data rate selected in the Data Rate Select
Register. The user must ensure that these two
data rates remain consistent.
For the Write Data case, the FDC activates Write
Gate at the beginning of the sync field under the
conventional mode. The controller then writes a
new sync field, data address mark, data field, and
CRC as shown in Figure 4. With the pre-erase
head of the perpendicular drive, the write head
must be activated in the Gap2 field to insure a
proper write of the new sync field. For the 1 Mbps
perpendicular mode (WGATE = 1, GAP = 1), 38
bytes will be written in the Gap2 space. Since the
bit density is proportional to the data rate, 19 bytes
will be written in the Gap2 field for the 500 Kbps
perpendicular mode (WGATE = 1, GAP =0).
The Gap2 and VCO timing requirements for
perpendicular recording type drives are dictated by
the design of the read/write head. In the design of
this head, a pre-erase head precedes the normal
read/write head by a distance of 200 micrometers.
This works out to about 38 bytes at a 1 Mbps
recording density. Whenever the write head is
enabled by the Write Gate signal, the pre-erase
head is also activated at the same time. Thus,
when the write head is initially turned on, flux
transitions recorded on the media for the first 38
bytes will not be preconditioned with the pre-erase
head since it has not yet been activated. To
It should be noted that none of the alterations in
Gap2 size, VCO timing, or Write Gate timing affect
normal program flow. The information provided
here is just for background purposes and is not
accommodate
this
head
activation
and
deactivation time, the Gap2 field is expanded to a
length of 41 bytes. The format field shown on
page 61 illustrates the change in the Gap2 field
size for the perpendicular format.
needed for normal operation.
Once the
Perpendicular Mode command is invoked, FDC
software behavior from the user standpoint is
unchanged.
On the read back by the FDC, the controller must
begin synchronization at the beginning of the sync
field. For the conventional mode, the internal PLL
The perpendicular mode command is enhanced to
allow specific drives to be designated
Perpendicular
recording
drives.
This
VCO
is
enabled
(VCOEN)
enhancement allows data transfers between
Conventional and Perpendicular drives without
having to issue Perpendicular mode commands
between the accesses of the different drive types,
nor having to change write pre-compensation
values.
55
When both GAP and WGATE bits of the
PERPENDICULAR MODE COMMAND are both
programmed to "0" (Conventional mode), then D0,
D1, D2, D3, and D4 can be programmed
independently to "1" for that drive to be set
automatically to Perpendicular mode. In this mode
the following set of conditions also apply:
Note: Bits D0-D3 can only be overwritten when
OW is programmed as a "1". If either
GAP or WGATE is a "1" then D0-D3 are
ignored.
Software and hardware resets have the following
effect on the PERPENDICULAR MODE
COMMAND:
1. The GAP2 written to a perpendicular drive
during a write operation will depend upon the
programmed data rate.
1. "Software" resets (via the DOR or DSR
registers) will only clear GAP and WGATE bits
to "0". D0-D3 are unaffected and retain their
previous value.
2. The write pre-compensation given to
perpendicular mode drive wil be 0ns.
a
3. For D0-D3 programmed to "0" for conventional
mode drives any data written will be at the
currently programmed write pre-compensation.
2. "Hardware" resets will clear all bits ( GAP,
WGATE and D0-D3) to "0", i.e all conventional
mode.
Table 29 - Effects of WGATE and GAP Bits
LENGTH OF
GAP2 FORMAT
FIELD
PORTION OF GAP 2
WRITTEN BY WRITE
DATA OPERATION
WGATE GAP
MODE
0
0
0
1
Conventional
Perpendicular
(500 Kbps)
22 Bytes
22 Bytes
0 Bytes
19 Bytes
1
1
0
1
Reserved
22 Bytes
41 Bytes
0 Bytes
(Conventional)
Perpendicular
(1 Mbps)
38 Bytes
56
LOCK
ENHANCED DUMPREG
In order to protect systems with long DMA
latencies against older application software that
can disable the FIFO the LOCK Command has
been added. This command should only be used
by the FDC routines, and application software
should refrain from using it. If an application calls
for the FIFO to be disabled then the CONFIGURE
command should be used.
The DUMPREG command is designed to support
system run-time diagnostics and application
software
development
and
debug.
To
accommodate the LOCK command and the
enhanced PERPENDICULAR MODE command
the eighth byte of the DUMPREG command has
been modified to contain the additional data from
these two commands.
The LOCK command defines whether the EFIFO,
FIFOTHR, and PRETRK parameters of the
CONFIGURE command can be RESET by the
DOR and DSR registers. When the LOCK bit is
set to logic "1" all subsequent "software RESETS
by the DOR and DSR registers will not change the
previously set parameters to their default values.
All "hardware" RESET from the RESET pin will set
the LOCK bit to logic "0" and return the EFIFO,
FIFOTHR, and PRETRK to their default values.
A status byte is returned immediately after issuing
a a LOCK command. This byte reflects the value
of the LOCK bit set by the command byte.
COMPATIBILITY
The FDC37C78 was designed with software
compatibility in mind. It is a fully backwards-
compatible solution with the older generation
765A/B disk controllers.
The FDC also
implements on-board registers for compatibility
with PC/AT and PC/XT floppy disk controller
subsystems. After a hardware reset of the FDC, all
registers, functions and enhancements default to a
PC/AT compatible operating mode.
57
AUTO POWER MANAGEMENT
Power management capabilities are provided for
Disabling the auto powerdown mode cancels the
timer and holds the FDC37C78 out of auto
powerdown.
the floppy disk. Two types of power management
are provided; direct powerdown and auto
powerdown.
DSR From Powerdown
Direct powerdown is controlled by the powerdown
bit in the configuration registers. Auto Powerdown
can be enabled by setting the Auto Powerdown
Enable bit in the configluation registers.
If DSR powerdown is used when the part is in auto
powerdown, the DSR powerdown will override the
auto powerdown. However, when the part is
awakened from DSR powerdown, the auto
powerdown will once again become effective.
FDC Power Management
Direct power management is controlled by bit 3 of
Configuration Register 0(CR0). Refer to CR0 bit
3 for more information.
Wake Up From Auto Powerdown
If the part enters the powerdown state through the
auto powerdown mode, then the part can be
awakened by reset or by appropriate access to
certain registers.
Auto Power Management is enabled by CR7 bit 7.
When set, this bit allows FDC to enter powerdown
when all of the following conditions have been met:
If a hardware or software reset is used then the
part will go through the normal reset sequence. If
the access is through the selected registers, then
the FDC37C78 resumes operation as though it
was never in powerdown. Besides activating the
RESET pin or one of the software reset bits in the
DOR or DSR, the following register accesses will
wake up the part:
1. The motor enable pins of register DOR are
inactive (zero).
2. The part must be idle; MSR=80H and INT = 0
(INT may be high even if MSR = 80H due to
polling interrupts).
3. The internal head unload timer must have
expired.
1. Enabling any one of the motor enable bits in
the DOR register (reading the DOR does not
awaken the part).
4. The Auto powerdown timer (10msec) must
have timed out.
2. A read from the MSR register.
An internal timer is initiated as soon as the auto
powerdown command is enabled. The part is
then powered down when all the conditions are
met. During the countdown of the powerdown
timer, any operation of read MSR or read/write
data (FIFO) will reinitiate the timer.
3. A read or write to the Data register.
58
Once awake, the FDC37C78 will reinitiate the
auto powerdown timer for 10 ms. The part will
powerdown again when all the powerdown
conditions are satisfied.
Pin Behavior
The FDC37C78 is specifically designed for
portable PC systems in which power conservation
is a primary concern. This makes the behavior of
the pins during powerdown very important.
Register Behavior
Table 30 reiterates the AT registers available. It
also shows the type of access permitted. In order
to maintain software transparency, access to all
the registers must be maintained. As Table 30
shows, two sets of registers are distinguished
based on whether their access results in the part
remaining in powerdown state or exiting it.
The pins of the FDC37C78 can be divided into
two major categories: system interface and floppy
disk drive interface. The floppy disk drive pins are
disabled so that no power will be drawn through
the part as a result of any voltage applied to the
pin within the part's power supply range. Most of
the system interface pins are left active to monitor
system accesses that may wake up the part.
Access to all other registers is possible without
awakening the part. These registers can be
accessed during powerdown without changing the
status of the part. A read from these registers will
reflect the true status as shown in the register
description in the FDC description. A write to the
part will result in the part retaining the data and
subsequently reflecting it when the part awakens.
Accessing the part during powerdown may cause
an increase in the power consumption by the
part. The part will revert back to its low power
mode when the access has been completed.
System Interface Pins
Table 31 gives the state of the system interface
pins in the powerdown state. Pins unaffected by
the powerdown are labeled "Unchanged". Input
pins are "Disabled" to prevent them from causing
currents internal to the FDC37C78 when they have
indeterminate input values.
59
Table 30 - PC/AT Available Registers
Available Registers
Base + Address
PC-AT
Access Permitted
Access to these registers DOES NOT wake up the part
00H
----
R
01H
02H
03H
04H
06H
07H
07H
----
DOR (1)
---
DSR (1)
---
DIR
CCR
R
R/W
---
W
---
R
W
Access to these registers wakes up the part
04H
05H
MSR
Data
R
R/W
Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable
bits or doing a software reset (via DOR or DSR reset bits) will wake up the part
Table 31 - State of System Pins in Auto Powerdown
System Pins
State in Auto Powerdown
Input Pins
IOR
IOW
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
A[0:9]
D[0:7]
RESET
IDENT
DACK
TC
Output Pins
IRQ
DB[0:7]
FDRQ
Unchanged (low)
Unchanged
Unchanged (low)
60
FDD Interface Pins
used
for
local
logic
control
or
part
All pins in the FDD interface which can be
connected directly to the floppy disk drive itself are
programming are unaffected. Table 32 depicts the
state of the floppy disk drive interface pins in the
powerdown state.
either DISABLED or TRISTATED.
Pins
Table 32 - State of Floppy Disk Drive Interface Pins in Powerdown
FDD Pins
State in Auto Powerdown
Input Pins
RDATA
WP
TRK0
INDX
DRV2
DSKCHG
Input
Input
Input
Input
Input
Input
Output Pins
MOTEN[0:3]
DS[0:3]
DIR
Tristated
Tristated
Active
STEP
Active
WRDATA
WE
HDSEL
DENSEL
DRATE[0:1]
Tristated
Tristated
Active
Active
Active
61
CONFIGURATION
The configuration of the chip is programmable
Enter Configuration Mode
through
software
selectable
configuration
registers.
To enter the configuration mode, two writes in
succession to port +0 with 55H data are required.
If a write to another address or port occurs
between these two writes, the chip does not enter
CONFIGURATION REGISTER ADDRESS
The Configuration Registers are located at
address offset +0 and +1 with nCS active.
the configuration mode.
It is strongly
recommended that interrupts be disabled for the
duration of these two writes.
CONFIGURATION REGISTERS
Configuration Mode
The configuration registers are used to select
programmable options of the chip. After power up,
the chip is in the default mode. The default modes
are identified in the Configuration Mode Register
The chip contains configuration registers CR00-
CR1F. These registers are accessed by first
writing the number (0-1FH) of the desired register
to port +0 and then writing or reading the
configuration register through port +1.
Description.
To program the configuration
registers, the following sequence must be
followed:
Exit Configuration Mode
1.
2.
3.
Enter Configuration Mode.
Configure the Configuration Registers.
Exit Configuration Mode.
The configuration mode is exited by writing an
AAH to port +0.
Programming Example
The following is an example of a configuration
program in Intel 8086 assembly language and
assumes that the base address is set to 3F0H.
62
;-----------------------------.
; ENTER CONFIGURATION MODE
;-----------------------------'
|
MOV
MOV
CLI
OUT
OUT
STI
DX,3F0H
AX,055H
;
; disable interrupts
DX,AL
DX,AL
; enable interrupts
;-----------------------------.
; CONFIGURE REGISTERS CR0-CRx |
;-----------------------------'
MOV
MOV
OUT
MOV
MOV
OUT
;
MOV
MOV
OUT
MOV
MOV
OUT
;
DX,3F0H
AL,00H
DX,AL ; Point to CR0
DX,3F1H
AL,3FH
DX,AL ; Update CR0
DX,3F0H
AL,01H
DX,AL ; Point to CR1
DX,3F1H
AL,9FH
DX,AL ; Update CR1
;
; Repeat for all CRx registers
;
;-----------------------------.
; EXIT CONFIGURATION MODE
;-----------------------------'
|
MOV
MOV
OUT
DX,3F0H
AX,0AAH
DX,AL
63
Table 33 - Configuration Registers
Default
28H
DB7
DB6
DB5
OSC
DB4
DB3
DB2
PDEN
DB1
DB0
CR00
CR01
CR02
CR03
Valid
Reserved
Reserved
FDC PWR
Reserved
Reserved
Reserved
Reserved
Reserved
90H
Lock CRx
Reserved
Reserved
Reserved
Reserved
MFM
Reserved
00H
Reserved
70H
IDENT
EXTx4
DRVDEN 1
Reserved
Enhanced
Reserved
FDC Mode 2
00H
00H
FFH
00H
00H
00H
00H
00H
00H
78H
00H
00H
00H
00H
00H
CR04
CR05
CR06
CR07
CR08
CR09
CR0A
CR0B
CR0C
CR0D
CR0E
CR0F
CR10
CR11
Reserved
DEN SEL
Reserved
DRV 0X1
DMA Mode
Reserved
Floppy Drive D
Floppy Drive C
Auto Power Management
Reserved Reserved
Floppy Drive B
Media ID Polarity
Reserved Reserved
Reserved
Reserved
Floppy Drive A
Floppy Boot Drive
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FDD3-DRTx
FDD2-DRTx
FDD1-DRTx
FDD0-DRTx
Reserved
Device ID/ 78H
Device Revision/00
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
CR12-
CR1E
Reserved
00H
CR1F
FDD3-DTx
FDD2-DTx
FDD1-DTx
FDD0-DTx
before the configuration
registers
can be
Configuration Register Description
accessed and is used to select which of the
Configuration Registers are to be accessed at port
+1.
The configuration registers consist of the
Configuration Select Register (CSR) and
Configuration Registers CR00
- CR1F. The
configuration select register is written to by writing
to port +0. The Configuration Registers CR00;
CR1F are accessed by reading or writing to port
+1.
Configuration Registers CR00 -CR1F
These registers are set to their default values at
power up and are not affected by RESET (except
where explicitly defined that a hardware reset
causes that bit to be reset to default). They are
accessed at port +1. Refer to the following
descriptions for the function of each configuration
register.
Configuration Select Register (CSR)
This register can only be accessed when the
chip is in the Configuration Mode. This register,
located at port +0, must be initialized upon
entering the Configuration Mode
64
CR00
This register can only be accessed when the chip is in the Configuration Mode and after the CSR has
been initialized to 00H. The default value of this register after power up is 28H.
Table 34 - CR00
BIT NO.
BIT NAME
Reserved
PDEN
DESCRIPTION
0:1
2
Read only. Read as 0
Power Down and Idle enable.
0 nDS1pin=nDS1, nMTR1pin=nMTR1
1 nDS1pin=Power Down, nMTR1pin=Idle
3
FDC Power
A high level on this bit, supplies power to the FDC (default). A low
level on this bit puts the FDC in low power mode.
4, 6
5
Reserved
OSC
Read only. A read returns bits 4 and 6 as a 0.
Oscillator Control.
0 = Oscillator OFF
1 = Oscillator ON (default)
7
Valid
A high level on this software controlled bit can be used to indicate
that a valid configuration cycle has occurred. The control software
must take care to set this bit at the appropriate times. Set to zero
after power up. This bit has no effect on any other hardware in the
chip.
CR01
This register can only be accessed in the Configuration Mode and after the CSR has been
initialized to 01H. The default value of this register after power up is 90H.
Table 35 - CR01
BIT NO.
0,1,2,3
BIT NAME
Reserved
DESCRIPTION
Read Only. A read returns a 0.
4
5,6
7
Reserved
Reserved
Lock CRx
Read Only. A read returns a 1.
Read Only. A read returns a 0.
A high level on this bit enables the reading and writing of CRxx
registers (Default). A low level on this bit disables the reading and
writing of all CRxx registers. Once set to 0, this bit can only be set
to 1 by a hard reset or power-up reset.
65
CR02
This register can only be accessed in the Configuration Mode and after the CSR has been initialized
to 02H. The default value of this register after power up is 00H.
Table 36 - CR02
BIT NO.
BIT NAME
Reserved
DESCRIPTION
0:7
Read Only. A read returns a 0.
CR03
This register can only be accessed in the Configuration Mode and the CSR has been initialized
to 03H. The default value after power up is 70H.
Table 37 - CR03
BIT NO.
BIT NAME
DESCRIPTION
0
1
Reserved
Reserved - Read as zero
Enhanced
Floppy Mode
2
Bit 1
Floppy Mode - Refer to the description of the TAPE
DRIVE REGISTER (TDR) for more information on these
modes.
0
1
NORMAL Floppy Mode (Default)
Enhanced Floppy Mode 2 (OS2)
2
3
4
Reserved
Reserved
DRVDEN1
Reserved - Read as zero
Reserved - Read as zero
0
1
DRVDEN 1 output as per DRVDEN table
DRVDEN 1 pin is tri-state (default)
5
6
MFM
IDENT is used in conjunction with MFM to define the interface mode of
operation.
IDENT
IDENT
MFM
MODE
1
1
0
0
1
0
1
0
AT Mode (Default)
Reserved
Reserved
Reserved
7
Reserved
Reserved - Read as zero
CR04
This register can only be accessed in the Configuration Mode and the CSR has been initialized
to 04H. The default value after power up is 00H.
Table 38 - CR04
BIT NO.
BIT NAME
Reserved
DESCRIPTION
0:7
Reserved - Read as zero
66
CR05
This register can only be accessed in the Configuration Mode and the CSR has been initialized
to 05H. The default value after power up is 00H.
Table 39 - CR05- Floppy Disk Extended Setup Register
BIT NO.
BIT NAME
Reserved
DESCRIPTION
0,1
2
Read Only. A read returns a 0.
FDC DMA Mode 0=(default) Burst mode is enabled for the FDC FIFO execution
phase data transfers. 1=Non-Burst mode enabled. The FDRQ and
FIRQ pins are strobed once for each byte transferred while the FIFO
is enabled.
4,3
DenSel
Bit 4
Bit 3
Densel output
0
0
1
1
0
1
0
1
Normal (Default)
Reserved
1
0
5
6
7
Swap Drv 0,1
EXTx4
A high level on this bit, swaps drives and motor sel 0 and 1 of the
FDC. A low level on this bit does not (Default).
External 4 drive support: 0=Internal 2 drive decoder (default).
1=External 4 drive decoder (External 2 to 4 decoder required).
Reserved
Read Only. A read of this bit returns a 0
CR06
This register can only be accessed in the Configuration Mode and after the CSR has been initialized
to 06H. The default value of this register after power up is FFH. This register holds the floppy
disk drive types for up to four floppy disk drives.
CR07
This register can only be accessed in the Configuration Mode and after the CSR has been initialized
to 07H. The default value of this register after power up is 00H. This register holds the value for the auto
power management, polarity of the media ID bits and floppy boot drive information.
67
Table 40 - CR07
BIT NO.
BIT NAME
DESCRIPTION
0,1
Floppy Boot
This bit is used to define the boot floppy.
0 = Drive A (default)
1 = Drive B
Media ID0
Polarity
0 = Non-invert
2
3
1 = Invert
Media ID1
0 = Non-invert
1 = Invert
Read as 0.
Polarity
Reserved
Floppy Disk
Enable
4:6
7
This bit controls the AUTOPOWER DOWN feature of the Floppy
Disk. The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
CR08
This register can only be accessed in the Configuration Mode and after the CSR has been initialized to
08H. The default value of this register after power up is 00H. This register is read only.
CR09
This register can only be accessed in the Configuration Mode and after the CSR has been initialized to
09H. The default value of this register after power up is 00H. This register is read only.
CR0A
This register can only be accessed in the Configuration Mode and after the CSR has been initialized to
0AH. The default value of this register after power up is 00H. This register is read only.
CR0B
This register can only be ac1cessed in the Configuration Mode and after the CSR has been initialized
to 0BH. The default value of this register after power up is 00H. This register indicates the data rate
table used for each drive. Refer to CR1F for Drive Type register.
Table 41 - CR0B
FDD3
FDD2
FDD1
FDD0
D7
D6
D5
D4
D3
D2
D1
D0
DRT1
DRT0
DRT1
DRT0
DRT1
DRT0
DRT1
DRT0
CR0C
This register can only be accessed in the Configuration Mode and after the CSR has been initialized to
0CH. The default value of this register after power up is 00H. This register is reserved.
68
CR0D
This register can only be accessed in the Configuration Mode and after the CSR has been initialized to
0DH. This register is read only. This is the Device ID. The default value of this register after power up is
78H.
CR0E
This register can only be accessed in the Configuration Mode and after the CSR has been initialized to
0EH. This register is read only. The default value of this register after power up is 00H. This is used to
identify the chip revision level.
CR0F
This register can only be accessed in the Configuration Mode and after the CSR has
been initialized to 0FH. The default value of this register after power up is 00H. This is a test register and
must be left as 00H.
Table 42 - CR0F
BIT NO.
BIT NAME
DESCRIPTION
0:7
Reserved
Reserved For Test
CR10
This register can only be accessed in the Configuration Mode and after the CSR has been initialized
to 10H. The default value of this register after power up is 00H. This is a test register and must be left as
00H.
Table 43 - CR10
BIT NO.
BIT NAME
DESCRIPTION
0:7
Reserved
Reserved For Test
CR11
This register can only be accessed in the Configuration Mode and after the CSR has
been initialized to 11H. The default value of this register after power up is 00H. This is a test register and
must be left as 00H.
Table 44 - CR11
BIT NO.
BIT NAME
DESCRIPTION
0:7
Reserved
Reserved For Test
CR12-CR1E
These registers are reserved. The default value of these registers after power up is 00H.
69
CR1F
This register can only be accessed in the Configuration Mode and after the CSR has been initialized
to 1FH. The default value of this register after power up is 00H. This register indicates the Drive Type
used for each drive. Refer to CR0B for Data Rate Table register.
FDD3
FDD2
FDD1
FDD0
D7
D6
D5
D4
D3
D2
D1
D0
DT0
DT1
DT0
DT1
DT0
DT1
DT0
DT1
DTx = Drive Type select
DT0 DT1
DRVDEN0
DRVDEN1
(Note)
Drive Type
(Note)
0
0
DENSEL
DRATE0
4/2/1 MB 3.5"
2/1 MB 5.25" FDDS
2/1.6/1 MB 3.5" (3-MODE)
0
1
1
1
0
1
DRATE1
nDENSEL
DRATE0
DRATE0
DRATE0
DRATE1
Note:
DENSEL, DRATE1 and DRATE0 map onto two output pins DRVDEN0 and DRVDEN1.
70
OPERATIONAL DESCRIPTION
MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range..............................................................................................0oC to +70oC
Storage Temperature Range .............................................................................................. -55o to +150oC
Lead Temperature Range (soldering, 10 seconds).........................................................................+325oC
Positive Voltage on any pin, with respect to Ground.................................................................... VIO+0.3V
Negative Voltage on any pin, with respect to Ground ........................................................................ -0.3V
Maximum VIO ....................................................................................................................................... +7V
Maximum VCC ........................................................................................................................................VIO
*Stresses above those listed above could cause permanent damage to the device. This is a stress
rating only and functional operation of the device at any other condition above those indicated in the
operation sections of this specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the
Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit
voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients
on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp
circuit be used.
DC ELECTRICAL CHARACTERISTICS (TA = 0°C - 70°C, Vcc = +3.3 V ± 10%)
PARAMETER
SYMBOL MIN
TYP
MAX UNITS
COMMENTS
I Type Input Buffer
VILI
0.8
0.8
V
V
TTL Levels
Low Input Level
VIHI
2.0
2.2
High Input Level
IS Type Input Buffer
VILIS
VIHIS
VHYS
V
V
Schmitt Trigger
Schmitt Trigger
Low Input Level
High Input Level
250
mV
Schmitt Trigger Hysteresis
ICLK Input Buffer
VILCK
VIHCK
0.4
V
V
Low Input Level
2.2
High Input Level
Input Leakage
IIL
-10
-10
+10
+10
V
IN = 0
µA
µA
Low Input Leakage
High Input Leakage
IIH
VIN = VIO
71
PARAMETER
SYMBOL MIN
TYP
MAX UNITS
COMMENTS
I/O12 Type Buffer
VOL
0.5
V
V
I
I
OL = 12 mA
OH = -6 mA
IN = 0 to VIO (Note 1)
Low Output Level
High Output Level
VOH
IOL
2.4
-10
+10
0.5
V
Output Leakage
µA
O12 Type Buffer
VOL
VOH
IOL
V
V
I
I
OL = 12 mA
OH = -6 mA
Low Output Level
High Output Level
2.4
-10
+10
0.5
VIN = 0 to VIO (Note 1)
Output Leakage
µA
OD20 Type Buffer
VOL
V
I
OL = 20 mA
Low Output Level
IOH
ICC
-10
+10
VOH = 0 to VIO (Note 2)
Output Leakage
Supply Current Active
µA
TBD
mA All outputs open.
Supply Current Standby
ICSBY
TBD
mA (Note 3)
Note 1: All output leakages are measured with the current pins in high impedance.
Note 2: Output leakage is measured with the low driving output off.
Note 3: Defined by the device configuration.
DC ELECTRICAL CHARACTERISTICS (TA = 0°C - 70°C, Vcc = +5 V ± 10%)
PARAMETER
SYMBOL MIN
TYP
MAX UNITS
COMMENTS
I Type Input Buffer
VILI
0.8
0.8
V
V
TTL Levels
Low Input Level
VIHI
2.0
2.2
High Input Level
IS Type Input Buffer
VILIS
VIHIS
VHYS
V
V
Schmitt Trigger
Schmitt Trigger
Low Input Level
High Input Level
250
mV
Schmitt Trigger Hysteresis
72
PARAMETER
ICLK Input Buffer
SYMBOL MIN
TYP
MAX UNITS
COMMENTS
VILCK
0.4
V
V
Low Input Level
VIHCK
3.0
High Input Level
Input Leakage
IIL
-10
-10
+10
+10
V
IN = 0
IN = VIO
µA
µA
Low Input Leakage
IIH
V
High Input Leakage
I/O12 Type Buffer
VOL
VOH
IOL
0.5
V
V
I
I
OL = 24 mA
OH = -12mA
Low Output Level
High Output Level
2.4
-10
+10
0.5
VIN = 0 to VIO (Note 1)
Output Leakage
µA
O12 Type Buffer
VOL
VOH
IOL
V
V
I
I
OL = 24 mA
OH = -12 mA
Low Output Level
High Output Level
2.4
-10
+10
0.5
VIN = 0 to VIO (Note 1)
Output Leakage
µA
OD20 Type Buffer
VOL
V
I
OL = 48 mA
Low Output Level
IOH
ICC
-10
+10
VOH = 0 to VIO (Note 2)
Output Leakage
Supply Current Active
µA
TBD
mA All outputs open.
Supply Current Standby
ICSBY
TBD
mA (Note 3)
Note 1: All output leakages are measured with the current pins in high impedance.
Note 2: Output leakage is measured with the low driving output off.
Note 3: Defined by the device configuration.
CAPACITANCE TA = 25°C; fc = 1MHz; VCC = 3.3V, 5V
LIMITS
PARAMETER
Clock Input Capacitance
Input Capacitance
SYMBOL
CIN
UNIT
pF
pF
TEST CONDITION
All pins except pin
under test tied to
MIN
TYP
MAX
20
10
CIN
73
AC ground
Output Capacitance
COUT
20
pF
74
TIMING DIAGRAMS
t3
nCS
t1
t2
nIOR
t4
t5
DATA
(D0-D7)
DATA VALID
BUSY
IRQ
t6
Parameter
min
typ
max
units
t1
40
150
10
ns
nCS Set Up to nIOR Low
nIOR Width
t2
t3
ns
ns
nCS Hold from nIOR High
Data Access Time from nIOR Low
t4
t5
t6
100
60
ns
ns
ns
10
Data to Float Delay from nIOR High
Read Strobe to Clear IRQ
40
55
FIGURE 3 - MICROPROCESSOR READ TIMING
75
t3
nCS
t2
t1
t4
nIOW
t5
DATA
(D0-D7)
DATA VALID
t6
IRQ
Parameter
min
typ
max
units
t1
40
ns
nCS Set Up to nIOW Low
nIOW Width
t2
t3
150
10
ns
ns
nCS Hold from nIOW High
Data Set Up Time to nIOW High
40
t4
t5
ns
ns
10
Data Hold Time from nIOW High
Write Strobe to Clear IRQ
40
55
t6
ns
FIGURE 4 - MICROPROCESSOR WRITE TIMING
76
t15
nCS
t16
t3
t2
DRQ,
t1
t4
nDACK
t12
t14
t11
t6
t5
nIOR
or
t8
nIOW
t10
t9
t7
DATA
DATA VALID
(DO-D7)
t13
TC
Parameter
nDACK Delay Time from DRQ High
DRQ Reset Delay from nIOR or nIOW
DRQ Reset Delay from nDACK Low
nDACK Width
min
typ
max
units
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
t8
t9
100
100
150
0
0
nIOR Delay from DRQ High
nIOW Delay from DRQ High
Data Access Time from nIOR Low
Data Set Up Time to nIOW High
Data to Float Delay from nIOR High
100
60
40
10
10
5
10
60
40
10
t10 Data Hold Time from nIOW High
nDACK Set Up to nIOW/nIOR Low
nDACK Hold After nIOW/nIOR High
t13 TC Pulse Width
t14 nCS Set Up to nIOR/nIOW
t15 nCS Hold from nDACK
t16 TC Active to DRQ Inactive
t11
t12
100
FIGURE 5 - DMA TIMING
77
t1
t2
t2
X1
t4
nRESET
Name
Description
min
typ
max
Units
ns
Clock CycleTime for 24MHZ
40
43.33
t1
t2
Clock High Time/Low Time for
14.318MHZ
ns
14
Clock Rise Time/Fall Time
5
ns
us
(not shown)
nRESET Low Time
t6
1.5
NOTE 1:
The nRESET low time is dependent upon the processor clock. The
nRESET must be active for a minimum of 24 x16MHz clock cycles.
FIGURE 6 - CLOCK TIMING
78
t3
nDIR
t4
t1
t2
nSTEP
nDS0-1
nINDEX
nRDATA
t5
t6
t7
t8
nWDATA
nIOW
t9
t9
nDS0-1,
nMTR0-1
Parameter
min
typ
max
units
t1
t2
t3
t4
t5
t6
t7
t8
t9
nDIR Set Up to nSTEP Low
nSTEP Active Time Low
nDIR Hold Time After nSTEP
nSTEP Cycle Time
nDS0-1 Hold Time from nSTEP Low
nINDEX Pulse Width
nRDATA Active Time Low
nWDATA Write Data Width Low
nDS0-1, MTR0-1 from End of nIOW
4
24
96
132
20
2
40
.5
25
X*
X*
X*
X*
X*
X*
ns
Y*
ns
*X specifies one MCLK period and Y specifies one WCLK period.
MCLK = Controller Clock to FDC (See Table 6).
WCLK = 2 x Data Rate (See Table 6).
FIGURE 7 - DISK DRIVE TIMING
79
FIGURE 8 – 48 PIN TQFP PACKAGE DIMENSIONS
MIN
~
NOMINAL
MAX
1.6
REMARK
A
A1
A2
D
D/2
D1
E
E/2
E1
H
~
0.10
1.40
9.00
4.50
7.00
9.00
4.50
7.00
~
Overall Package Height
0.05
1.35
8.80
4.40
6.90
8.80
4.40
6.90
0.09
0.45
~
0.15
1.45
9.20
4.60
7.10
9.10
4.60
7.10
0.20
0.75
~
Standoff
Body Thickness
X Span
1/2 X Span Measure from Centerline
X body Size
Y Span
1/2 Y Span Measure from Centerline
Y body Size
Lead Frame Thickness
Lead Foot Length from Centerline
Lead Length
L
L1
e
0.60
1.00
0.50 Basic
~
Lead Pitch
Lead Foot Angle
Lead Width
0o
0.17
0.08
0.08
7o
0.27
~
θ
W
R1
R2
~
~
Lead Shoulder Radius
Lead Foot Radius
~
0.20
80
MIN
~
~
NOMINAL
MAX
0.0762
0.08
REMARK
Coplanarity (Assemblers)
Coplanarity (Test House)
ccc
ccc
~
~
Note 1:Controlling Unit: millimeter
Note 2:Tolerance on the position of the leads is ± 0.04 mm maximum.
Note 3:Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold
protrusion is 0.25 mm.
Note 4:Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.78-
1.08 mm.
Note 5:Details of pin 1 identifier are optional but must be located within the zone indicated.
81
FDC37C78 ERRATA SHEET
PAGE
SECTION/FIGURE/ENTRY
CORRECTION
DATE REVISED
80
FIGURE 8/Table
See Italicized Text
06/07/99
80 Arkay Drive
Hauppauge, NY 11788
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FAX (631) 273-3123
Copyright © SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications.
Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been
checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to
specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest
specifications before placing your product order. The provision of this information does not convey to the purchaser of the described
semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are
expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of
Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or
errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are
available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other
application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses
without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer.
Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s
website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names
and company names are the trademarks of their respective holders.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
A PARTICULAR PURPOSE, TITLE, AND AGAINST
INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE
OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR
CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF
THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT
LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE
FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
FDC37C78 Rev. 03/27/2000
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