FDC37C93XAPM_技术文档

FDC37C93xAPM

ADVANCE INFORMATION

Plug and Play Compatible Ultra I/O™ Controller

with Soft Power Management

FEATURES

-

Four DMA Options

Licensed CMOS 765B Floppy Disk

Controller

·

5 Volt Operation

ISA Plug-and-Play Standard (Version 1.0a)

Compatible Register Set

Soft Power Management, SMI Support

ACPI/Legacy Support

-

Advanced Digital Data Separator

Software and Register Compatible with

SMSC's Proprietary 82077AA

Compatible Core

Sophisticated Power Control Circuitry

(PCC) Including Multiple Powerdown

Modes for Reduced Power Consumption

Game Port Select Logic

·

-

SCI/SMI Support

Power Management Timer

Power Button Override Event

Either Edge Triggered Interrupts

ACCESS.bus Support

8042 Keyboard Controller

2K Program ROM

-

·

-

Supports Two Floppy Drives Directly

24mA AT Bus Drivers

Low Power CMOS Design

-

256 Bytes Data RAM

Asynchronous Access to Two Data

Registers and One Status Register

Supports Interrupt and Polling Access

8 Bit Timer/Counter

Port 92 Support

Fast Gate A20 and Hardware Keyboard

Reset

·

Licensed CMOS 765B Floppy Disk

Controller Core

-

Supports Vertical Recording Format

16 Byte Data FIFO

100% IBM® Compatibility

Detects All Overrun and Underrun

Conditions

48mA Drivers and Schmitt Trigger Inputs

DMA Enable Logic

·

Real Time Clock

-

MC146818 and DS1287 Compatible

256 Bytes of Battery Backed CMOS in

Two Banks of 128 Bytes

128 Bytes of CMOS RAM Lockable in

4x32 Byte Blocks

Data Rate and Drive Control Registers

Enhanced Digital Data Separator

Low Cost Implementation

·

-

No Filter Components Required

2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,

250 Kbps Data Rates

-

12 and 24 Hour Time Format

Binary and BCD Format

1 mA Standby Current (typ)

Intelligent Auto Power Management

2.88MB Super I/O Floppy Disk Controller

Relocatable to 480 Different Addresses

13 IRQ Options

-

Programmable Precompensation Modes

·

Serial Ports

Relocatable to 480 Different Addresses

-

TABLE OF CONTENTS

FEATURES ........................................................................................................................................1

GENERAL DESCRIPTION..................................................................................................................4

PIN CONFIGURATION.......................................................................................................................5

DESCRIPTION OF PIN FUNCTIONS...........................................................................................6

FUNCTIONAL DESCRIPTION..........................................................................................................15

SUPER I/O REGISTERS ...........................................................................................................15

HOST PROCESSOR INTERFACE.............................................................................................15

FLOPPY DISK CONTROLLER...................................................................................................16

FDC INTERNAL REGISTERS....................................................................................................16

INSTRUCTION SET .........................................................................................................................44

SERIAL PORT (UART).....................................................................................................................70

INFRARED INTERFACE...................................................................................................................85

PARALLEL PORT.............................................................................................................................86

IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES..............................................88

EXTENDED CAPABILITIES PARALLEL PORT ..........................................................................95

AUTO POWER MANAGEMENT .....................................................................................................111

INTEGRATED DRIVE ELECTRONICS INTERFACE .......................................................................116

HOST FILE REGISTERS.........................................................................................................116

TASK FILE REGISTERS..........................................................................................................116

IDE OUTPUT ENABLES..........................................................................................................117

BIOS BUFFER.........................................................................................................................118

GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION ...............................................................121

EITHER EDGE TRIGGERED INTERRUPTS............................................................................135

8042 KEYBOARD CONTROLLER AND REAL TIME CLOCK FUNCTIONAL DESCRIPTION...........136

SOFT POWER MANAGEMENT......................................................................................................161

SYSTEM MANAGEMENT INTERRUPT (SMI).................................................................................165

ACCESS.BUS ................................................................................................................................166

ACPI FEATURES ...........................................................................................................................172

CONFIGURATION...................................................................................................................188

OPERATIONAL DESCRIPTION......................................................................................................238

POWER SUPPLY OPERATIONAL MODES.............................................................................242

TIMING DIAGRAMS ................................................................................................................243

ECP PARALLEL PORT TIMING......................................................................................................270

80 Arkay Drive

Hauppauge, NY. 11788

(516) 435-6000

FAX (516) 273-3123

2

-

13 IRQ Options

-

Four DMA Options

Standard Mode

Two High Speed NS16C550 Compatible

UARTs with Send/Receive 16 Byte

FIFOs

-

IBM PC/XT, PC/AT, and PS/2Ô

Compatible Bidirectional ParallelPort

-

Programmable Baud Rate Generator

Modem Control Circuitry Including 230K

and 460K Baud

-

Enhanced Mode

-

Enhanced Parallel Port (EPP)

Compatible - EPP 1.7 and EPP 1.9

(IEEE 1284 Compliant)

-

IrDA, HP-SIR, ASK-IR Support

·

IDE Interface

High Speed Mode

-

Relocatable to 480 Different Addresses

13 IRQ Options (IRQ Steering through

Chip)

-

Microsoft and Hewlett Packard

Extended Capabilities Port (ECP)

Compatible (IEEE 1284 Compliant)

-

Two Channel/Four Drive Support

On-Chip Decode and Select Logic

Compatible with IBM PC/XT® and

PC/AT® Embedded Hard Disk Drives

Serial EEPROM Interface

Multi-ModeÔ Parallel Port with ChiProtectÔ

Relocatable to 480 Different Addresses

13 IRQ Options

-

Incorporates ChiProtectÔ Circuitry for

Protection Against Damage Due to

Printer Power-On

12 mA Output Drivers

·

ISA Host Interface

16 Bit Address Qualification

-

160 Pin QFP Package

*Note:

The “X” in the Ultra I/O part number is a designator that changes

depending upon the particular BIOS used inside the specific chip.

“2” denotes AMI Keyboard BIOS/”5” denotes Phoenix Keyboard

BIOS.

3

GENERAL DESCRIPTION

The FDC37C93xAPM incorporates a keyboard

These features include support of both legacy

and ACPI power management models through

the selection of SMI or SCI. It implements a 24-

bit power management timer, power button

override event (4 second button hold to turn off

the system) and either edge triggered interrupts.

interface, real-time clock, SMSC's true CMOS

765B floppy disk controller, advanced digital

data separator, 16 byte data FIFO, two 16C550

compatible UARTs, one Multi-Mode parallel port

which includes ChiProtect circuitry plus EPP

and ECP support, IDE interface, on-chip 24 mA

AT bus drivers, game port chip select and two

floppy direct drive support, as well as

ACCESS.bus, soft power management and SMI

support. The true CMOS 765B core provides

100% compatibility with IBM PC/XT and PC/AT

architectures in addition to providing data

overflow and underflow protection. The SMSC

advanced digital data separator incorporates

SMSC's patented data separator technology,

allowing for ease of testing and use. Both on-

chip UARTs are compatible with the NS16C550.

The parallel port, the IDE interface, and the

game port select logic are compatible with IBM

PC/AT architecture, as well as EPP and ECP.

The FDC37C93xAPM incorporates sophisticated

The FDC37C93xAPM provides support for the

ISA Plug-and-Play Standard (Version 1.0a) and

provides for the recommended functionality to

support Windows '95.

configuration registers,

Through internal

each of the

FDC37C93xAPM's logical device's I/O address,

DMA channel and IRQ channel may be

programmed.

There are 480 I/O address

location options, 13 IRQ options, and three DMA

channel options for each logical device.

The FDC37C93xAPM does not require any

external filter components and is, therefore,

easy to use and offers lower system cost and

reduced board area. The FDC37C93xAPM is

software and register compatible with SMSC's

proprietary 82077AA core.

power control circuitry (PCC).

The PCC

supports multiple low power down modes.

IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark

of International Business Machines Corporation

SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode

are trademarks of Standard Microsystems Corporation

The FDC37C93xAPM provides features for

compliance with the “Advanced Configuration

and Power Interface Specification” (ACPI).

4

PIN CONFIGURATION

GND

DRVDEN0

DRVDEN1

nMTR0

nDS1

nDS0

nMTR1

GND

nDIR

nSTEP

nWDATA

nWGATE

nHDSEL

nINDEX

nTRK0

nWRTPRT

nRDATA

nDSKCHG

MEDIA_ID1

mEDIA_ID0

VCC

CLOCKI

nIDE1_OE

nHDCS0

1

2

3

4

5

6

7

8

nROMDIR

nROMCS

RD7

RD6

RD5

RD4

RD3

RD2

RD1

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

RD0

GP25

GP24

GP23

GP22

GP21

GP20

GP17

GP16

GP15

VCC

GP14

GP13

GP12

GP11

GP10

GND

MCLK

MDAT

KCLK

KDAT

IOCHRDY

TC

DRQ3

nDACK3

DRQ2

nDACK2

DRQ1

nDACK1

DRQ0

nDACK0

FDC37C93xAPM

160 Pin QFP

nHDCS1

IDE1_IRQ

nHDCS2/SA13

nHDCS3/SA14

IDE2_IRQ/SA15

nIOROP

nIOWOP

VTR

nPOWER ON

BUTTON_IN

HCLK

16CLK

CLK01

CLK02

CLK03

82

81

GND

5

DESCRIPTION OF PIN FUNCTIONS

BUFFER

TYPE

PIN NO.

NAME

SYMBOL

PROCESSOR/HOST INTERFACE

72:79

41:52

53

System Data Bus

SD[0:7]

I/O24

System Address Bus

SA[0:11]

nCS

I

Chip Select/SA12 (Active Low)(Note 1, 4)

Address Enable (DMA master has bus control)

I/O Channel Ready

I

70

AEN

90

IOCHRDY

RESET_DRV

OD24

IS

80

Reset Drive

67:61,

59:54

Interrupt Requests [1,3:12,14,15]

(Polarity control for IRQ8)

IRQ[1,3:12,

14,15]

024/OD24

(Note 0)

82,84,

86,88

DMA Requests

DRQ[0:3]

O24

81,83,

85,87

DMA Acknowledge

nDACK[0:3]

I

89

68

69

35

36

22

37

38

39

Terminal Count

TC

I

I/O Read

nIOR

I

I/O Write

nIOW

HCLK

16CLK

CLOCKI

CLKO1

CLKO2

CLKO3

I

High Speed Clock Out 24/48 MHz

16 MHz Out

O20

O8SR

ICLK

O16SR

O8SR

14.318 MHz Clock Input

14.318 MHz Clock Output 1

14.318 MHz Clock Output 2

14.318 MHz Clock Output 3

POWER PINS

21, 60,

101, 125,

139

+5V Supply Voltage

VCC

32

Trickle Voltage Input

VTR

1, 8, 40, Ground

71, 95,

GND

123, 130

FDD INTERFACE

17

Read Disk Data

nRDATA

IS

6

DESCRIPTION OF PIN FUNCTIONS

NAME

BUFFER

TYPE

PIN NO.

12

SYMBOL

Write Gate

nWGATE

nWDATA

nHDSEL

nDIR

OD48

IS

11

Write Disk Data

Head Select (1 = side 0)

Step Direction (1 = out)

Step Pulse

13

9

10

nSTEP

18

Disk Change

nDSKCHG

nDS[1:0]

nMTR[1:0]

nWPROT

nTR0

5,6

7,4

16

Drive Select Lines

Motor On Lines

Write Protected

Track 0

OD48

IS

15

IS

14

Index Pulse Input

Drive Density Select [1:0]

nINDEX

IS

3,2

DRVDEN

[1:0]

OD48

19,20

Media ID inputs. In floppy enhanced mode 2 these MID[1:0]

inputs are the media ID [1:0] inputs. (Note 4)

IS

SERIAL PORT 1 INTERFACE

145

146

148

149

150

147

152

151

Receive Serial Data 1

Transmit Serial Data 1

Request to Send 1

Clear to Send 1

RXD1

TXD1

I

O4

nRTS1

nCTS1

nDTR1

nDSR1

nDCD1

nRI1

O4

I

Data Terminal Ready 1

Data Set Ready 1

O4

I

Data Carrier Detect 1

Ring Indicator 1

SERIAL PORT 2 INTERFACE

155

156

158

159

160

157

Receive Serial Data 2 (Note 4)

Transmit Serial Data 2 (Note 4)

Request to Send 2 (Note 4)

Clear to Send 2 (Note 4)

RXD2

I

TXD2

O4

I

nRTS2

nCTS2

nDTR2

nDSR2

Data Terminal Ready 2 (Note 4)

Data Set Ready 2 (Note 4)

O4

I

7

DESCRIPTION OF PIN FUNCTIONS

NAME

BUFFER

TYPE

PIN NO.

154

SYMBOL

nDCD2

Data Carrier Detect 2 (Note 4)

I

153

Ring Indicator 2 (Note 4)

nRI2

IDE1 INTERFACE

23

24

25

30

31

26

IDE1 Enable (Note 4)

nIDE1_OE

nHDCS0

nHDCS1

nIOROP

nIOWOP

IDE1_IRQ

O4

O24

I

IDE1 Chip Select 0 (Note 4)

IDE1 Chip Select 1 (Note 4)

IOR Output (Note 4)

IOW Output (Note 4)

IDE1 Interrupt Request (Note 4)

IDE2 INTERFACE

27

28

29

IDE2 Chip Select 2/SA13 (Note 3, 4)

IDE2 Chip Select 3/SA14 (Note 3, 4)

IDE2 Interrupt Request/SA15 (Note 4)

nHDCS2

nHDCS3

IDE2_IRQ

I/O24

I

PARALLEL PORT INTERFACE

138:131 Parallel Port Data Bus

PD[0:7]

nSLCTIN

nINIT

I/O24

140

141

143

144

128

129

127

126

142

Printer Select

OD24/O24

Initiate Output

Auto Line Feed

Strobe Signal

OD24/O24

nALF

OD24/O24

nSTB

OD24/O24

Busy Signal

BUSY

nACK

PE

I

Acknowledge Handshake

Paper End

Printer Selected

Error at Printer

SLCT

nERROR

REAL-TIME CLOCK

KEYBOARD/MOUSE

122

124

121

32 Khz Crystal Input

32 Khz Crystal Output

Battery Voltage

XTAL1

XTAL2

Vbat

ICLK2

OCLK2

91

Keyboard Data

KDAT

I/OD16P

8

DESCRIPTION OF PIN FUNCTIONS

NAME

BUFFER

TYPE

PIN NO.

92

SYMBOL

KCLK

Keyboard Clock

Mouse Data

I/OD16P

93

MDAT

MCLK

94

Mouse Clock

SOFT POWER MANAGEMENT INTERFACE

33

34

Power On (Note 4)

nPowerOn

Button_In

I/O24

Button Input (Note 4)

GPI/O; IRQ In (Note 4)

GENERAL PURPOSE I/O

96

97

GP10

GP11

GP12

GP13

GP14

GP15

GP16

GP17

GP20

I/O4

I/O24

I/O4

I/O8

I/O4

GPI/O; IRQ In/IRQ 13 (Note 4)

98

GPI/O; WD Timer Output/IRRX (Note 4)

GPI/O; Power Led Output/IRTX (Note 4)

GPI/O; GP Address Decode (Note 4)

GPI/O; GP Write Strobe (Note 4)

99

100

102

103

104

105

106

107

108

109

110

GPI/O; Joy Read Strobe/JOYCS (Note 4)

GPI/O; Joy Write Strobe (Note 4)

GPI/O; IDE2 Output Enable/8042 P20 (Note 4)

GPI/O; Serial EEPROM Data In/AB_DATA (Note 4) GP21

GPI/O; Serial EEPROM Data Out/AB_CLK (Note 4) GP22

GPI/O; Serial EEPROM Clock (Note 4)

GPI/O; Serial EEPROM Enable (Note 4)

GPI/O; 8042 P21 (Note 4)

GP23

GP24

GP25

BIOS BUFFERS

111:118 ROM Bus (I/O to the SD Bus) (Note 4)

RD[0:7]

I/O4

119

120

ROM Chip Select (only used for ROM) (Note 4)

nROMCS

I

ROM Output Enable (DIR) (only used for ROM) (Note 4) nROMDIR

Note 0:

The interrupt request is output on one of the IRQx signals as 024 buffer type. If EPP or

ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts.

In this case, the buffer type is OD24. Refer to the configuration section for more

information.

Note 1:

nCS -This pin is the active low chip select; it must be low for all chip accesses. For 12 bit

addressing, SA0:SA11, this input should be tied to GND. For 16 bit address qualification,

9

address bits SA12:SA15 can be "ORed" together and applied to this pin. If IDE2 is not

used, SA12 can be connected to nCS, pin 27 to SA13, pin 28 to SA14 and pin 29 to SA15.

nYY - The "n" as the first letter of a signal name indicates an "Active Low" signal

nHDCS2 and nHDCS3 require a pull-up to ensure a logic high at power-up when used for

IDE2 until the Active Bit is set to 1.

Note 2:

Note 3:

Note 4:

See Table on the following page for Multifunction Pins with GPI/O and Other Alternate

Functions.

10

Description of Multifunction Pins with GPI/O and Other Alternate Functions

No.

19

Original

Function

MEDIA_ID1

Alternate

Buffer

Type

I/O8

Index

Register GPI/O

Function 1 Function 2 Function 3

Default

float

GPI/O

-

GP4

GP40

GP41

GP42

GP43

GP44

GP45

GP46

20

23

24

25

26

30

MEDIA_ID0

nIDE1_OE

nHDCS0

-

I/O8

I/O4

float

high

float

-

I/O24

I/O8

nHDCS1

-

IDE1_IRQ

nIOROP

Power LED

Output

WDT

I/O24

31

33

nIOWOP

GPI/O

nSMI

-

I/O24

float

GP4

GP5

GP47

GP51

nPowerOn

-

active low

open

collector

output

input

34

Button_In

RD0

GPI/O

-

I/O24

I/O4

GP5

GP6

GP50

GP60

1,4

111

Power LED

Output

RD0

1,4

112

113

114

115

116

117

118

119

120

153

RD1

RD2

GPI/O

WDT

-

I/O4

I/O8

RD0

GP6

GP5

GP7

GP61

GP62

GP63

GP64

GP65

GP66

GP67

GP53

GP54

GP70

1,4

8042 - P12

8042 - P13

8042 - P14

8042 - P15

8042 - P16

8042 - P17

-

RD0

1,4

RD3

RD0

1,4

RD4

RD0

1,4

RD5

RD0

1,4

RD6

RD0

1,4

RD7

RD0

nROMCS

nROMOE

nRI2

nROMCS ¹

input ²

-

input ²

154

155

nDCD2

RXD2

GPI/O

-

I/O8

GP7

GP71

GP72

2,4

156

157

TXD2

GPI/O

-

I/O8

input

GP7

GP73

GP74

input, ²

nDSR2

2,4

158

159

160

nRTS2

nCTS2

nDTR2

GPI/O

-

I/O8

input

GP7

GP75

GP76

GP77

(2)

input

2,4

input

11

No.

27

Original

Function

nHDCS2

Alternate

Buffer

Type

I/O24

Index

Register GPI/O

Function 1 Function 2 Function 3

Default

float

SA13

SA14

SA15

-

28

29

53

96

97

98

nHDCS3

IDE2_IRQ

nCS/SA 12

GPI/O

-

I/O24

I

float

-

I

input

-

IRQ in

-

IRQ13

-

I/O4

GP1

GP10

GP11

GP12

GPI/O

WDT

Timer

GPI/O

Output/

IRRX

Power LED

Output/

IRTX

99

GPI/O

-

I/O24

I/O4

input

GP1

GP13

GP14

GP

100

Address

Decode

GP Write

Strobe

Joy Read

Strobe

Joy Write

Strobe

IDE2

102

103

104

105

GPI/O

-

I/O4

input

GP1

GP2

GP15

GP16

GP17

GP20

JOYCS

-

8042 P20

Output

Enable

Serial

EEPROM

Data In

106

107

GPI/O

AB_DATA

AB_CLK

-

I/O8

/OD8

(EN1)

I/O8

/OD8

(EN1)

I/O4

input

GP2

GP21

GP22

Serial

EEPROM

Data Out

Serial

EEPROM

Clock

Serial

EEPROM

Enable

108

109

110

GPI/O

-

input

GP2

GP23

GP24

GP25

I/O4

8042 P21

Note 1: At power-up, RD0-RD7, nROMCS and nROMOE function as the XD Bus. To use

RD0-RD7 for functions other than the XD Bus, nROMCS must stay high until

those pins are finished being reprogrammed.

Note 2: These pins are input (high-z) until programmed for second serial port.

Note 3: This is the trickle voltage input pin for the FDC37C93xAPM.

Note 4: These pins cannot be programmed as open drain pins in their original function.

Note:

No pins in their original function can be programmed as inverted input or inverted output.

12

BUFFER TYPE DESCRIPTIONS

BUFFER TYPE

I

DESCRIPTION

Input, TTL compatible.

IS

Input with Schmitt trigger.

I/OD16P

I/O24

I/O4

Input/Output, 16mA sink, 90uA pull-up.

Input/Output, 24mA sink, 12mA source.

Input/Output, 4mA sink, 2mA source.

Output, 4mA sink, 2mA source.

Output, 8mA sink, 4mA source with Slew Rate Limiting.

Output, 16mA sink, 8mA source with Slew Rate Limiting.

Output, 20mA sink, 10mA source.

Output, 24mA sink, 12mA source.

Output, Open Drain, 24mA sink.

Output, Open Drain, 48mA sink.

Clock Input

O4

O8SR

O16SR

O20

O24

OD24

OD48

ICLK

ICLK2

OCLK2

Clock Input

Clock Output

13

nGPA

nGPCS*

nSMI* IRQ13*

nROMDIR

nROMCS

RD[0:7]

nGPWR*

BIOS

BUFFER

nPowerOn

Button_In

SOFT

POWER

MANAGEMENT

SMI

ACPI/SCI

DECODER

MANAGEMENT

PD0-7

VTR

MULTI-MODE

PARALLEL

PORT/FDC

MUX

BUSY, SLCT, PE,

nERROR, nACK

DATA BUS

AB_DATA*

AB_CLK*

nSTB, nSLCTIN,

nINIT, nALF

ACCESS.bus

GP1[0:7]*

GP2[0:5]*

GENERAL

PURPOSE

I/O

ADDRESS BUS

DATAIN*

SERIAL

EEPROM

DATAOUT*

GP[4[0:7]*, GP5[0:1,3:4]*,

GP6[0:7]*, GP7[0:7]*

CLK*, ENABLE*

TXD1, nCTS1, nRTS1

CONFIGURATION

REGISTERS

16C550

COMPATIBLE

SERIAL

RXD1

nIOR

nIOW

PORT 1

nDSR1, nDCD1, nRI1, nDTR1

CONTROL BUS

AEN

SA[0:12] (nCS)

SA[13-15]

IRRX*, IRTX*

WDATA

16C550

COMPATIBLE

SERIAL

PORT 2 WITH

INFRARED

TXD2(IRTX), nCTS2, nRTS2

RXD2(IRRX)

WCLOCK

HOST

CPU

SMSC

PROPRIETARY

82077

nDSR2, nDCD2, nRI2, nDTR2

SD[O:7]

DIGITAL

DATA

SEPARATOR

WITH WRITE

PRECOM-

INTERFACE

nHDCS2,3

IDE2_IRQ

COMPATIBLE

DRQ[0:3]

IDE2

OPTIONAL

VERTICAL

FLOPPYDISK

CONTROLLER

CORE

nDACK[0:3]

PENSATION

IDE1_IRQ

nIDE1_OE

nIOWOP

nIOROP

IDE

RCLOCK

RDATA

TC

IRQ[1,3-12,14,15]

RESET_DRV

INTERFACE

nHDCS0, nHDCS1

CLOCK

GEN

KCLK

KDATA

8042

RTC

IOCHRDY

MCLK

MDATA

DENSEL

nINDEX

nTRK0

nDS0,1

nDIR

nMTR0,1

P20*, P21*

P12*, P13*, P14*,P15*, P16*, P17*

nWDATA nRDATA

nDSKCHG

nWRPRT

nWGATE

nSTEP DRVDEN0

XTAL1,2

VBAT

DRVDEN1

nHDSEL

ICLOCK

(14.318)

MID0, MID1

HCLK

CLKO[1:3]

(14.318)

Vcc

Vss

16CLK

*Multi-Function I/O Pin - Optional

FDC37C93xAPM BLOCK DIAGRAM

14

FUNCTIONAL DESCRIPTION

HOST PROCESSOR INTERFACE

SUPER I/O REGISTERS

The host processor communicates with the

FDC37C93xAPM through a series of read/write

registers. The port addresses for these registers

are shown in Table 1. Register access is

accomplished through programmed I/O or DMA

transfers. All registers are 8 bits wide except

the IDE data register at port 1F0H which is 16

bits wide. All host interface output buffers are

capable of sinking a minimum of 12 mA.

The address map, shown below in Table 1,

shows the addresses of the different blocks of

the Super I/O immediately after power up. The

base addresses of the FDC, IDE, serial and

parallel ports, Bank 2 of the RTC registers,

auxiliary I/O and ACCESS.bus can be moved

via the configuration registers. Some addresses

are used to access more than one register.

Table 1 - Super I/O Block Addresses

LOGICAL

DEVICE

ADDRESS

Base+(0-5) and +(7)

Base+(0-7)

BLOCK NAME

NOTES

Floppy Disk

0

4

5

3

Serial Port Com 1

Serial Port Com 2

Base+(0-7)

IR Support

Parallel Port

SPP

Base+(0-3)

Base+(0-7)

EPP

Base+(0-3), +(400-402)

Base+(0-7), +(400-402)

ECP

ECP+EPP+SPP

Base1+(0-7), Base2+(0)

IDE 1

IDE 2

RTC

1

2

6

70, 71

Base2+(0,1)

60, 64

KYBD

7

8

Base1+(0)

Base2+(0)

Aux. I/O

GPR

GPW

Base+(0-3)

ACCESS.bus

ACPI

9

Base1+(0-11)

Base2+(0-7)

A

Note: Refer to the configuration register descriptions for setting the base address

15

FLOPPY DISK CONTROLLER

FDC INTERNAL REGISTERS

The Floppy Disk Controller (FDC) provides the

interface between a host microprocessor and

the floppy disk drives. The FDC integrates the

functions of the Formatter/Controller, Digital

Data Separator, Write Precompensation and

Data Rate Selection logic for an IBM XT/AT

compatible FDC. The true CMOS 765B core

guarantees 100% IBM PC XT/AT compatibility

in addition to providing data overflow and

underflow protection.

The Floppy Disk Controller contains eight

internal registers which facilitate the interfacing

between the host microprocessor and the disk

drive. Table 2 shows the addresses required to

access these registers. Registers other than the

ones shown are not supported. The rest of the

description assumes that the primary addresses

have been selected.

The FDC is compatible to the 82077AA using

SMSC's proprietary floppy disk controller core.

Table 2 - Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

SECONDARY

PRIMARY

ADDRESS

R/W

REGISTER

3F0

3F1

3F2

3F3

3F4

3F5

3F6

3F7

370

371

372

373

374

375

376

377

R

R/W

R

Status Register A (SRA)

Status Register B (SRB)

Digital Output Register (DOR)

Tape Drive Register (TSR)

Main Status Register (MSR)

Data Rate Select Register (DSR)

Data (FIFO)

Reserved

Digital Input Register (DIR)

Configuration Control Register (CCR)

W

R/W

R

W

16

interface pins in PS/2 and Model 30 modes. The

SRA can be accessed at any time when in PS/2

mode. In the PC/AT mode the data bus pins

D0-D7 are held in a high impedance state for a

read of address 3F0.

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state

of the FINTR

and

several

disk

PS/2 Mode

7

6

5

4

3

2

1

0

INT

nDRV2 STEP nTRK0 HDSEL nINDX nWP

DIR

PENDING

RESET

COND.

0

N/A N/A N/A N/A

0

BIT 0 DIRECTION

BIT 4 nTRACK 0

Active high status indicating the direction of

head movement. A logic "1" indicates inward

direction; a logic "0" indicates outward direction.

Active low status of the TRK0 disk interface

input.

BIT 5 STEP

BIT 1 nWRITE PROTECT

Active high status of the STEP output disk

interface output pin.

Active low status of the WRITE PROTECT disk

interface input. A logic "0" indicates that the disk

is write protected.

BIT 6 nDRV2

Active low status of the DRV2 disk interface

input pin, indicating that a second drive has

been installed.

BIT 2 nINDEX

Active low status of the INDEX disk interface

input.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy

Disk Interrupt output.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface

input. A logic "1" selects side 1 and a logic "0"

selects side 0.

17

PS/2 Model 30 Mode

7

6

5

4

3

2

1

0

INT

PENDING

DRQ STEP TRK0 nHDSEL INDX

F/F

WP

nDIR

RESET

COND.

0

N/A

1

N/A

1

BIT 0 nDIRECTION

BIT 4 TRACK 0

Active low status indicating the direction of head

movement. logic "0" indicates inward

Active high status of the TRK0 disk interface

input.

A

direction; a logic "1" indicates outward direction.

BIT 5 STEP

BIT 1 WRITE PROTECT

Active high status of the latched STEP disk

interface output pin. This bit is latched with the

STEP output going active, and is cleared with a

read from the DIR register, or with a hardware

or software reset.

Active high status of the WRITE PROTECT disk

interface input. A logic "1" indicates that the disk

is write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface

input.

BIT 6 DMA REQUEST

Active high status of the DRQ output pin.

BIT 3 nHEAD SELECT

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy

Disk Interrupt output.

Active low status of the HDSEL disk interface

input. A logic "0" selects side 1 and a logic "1"

selects side 0.

18

Model 30 modes. The SRB can be accessed at

any time when in PS/2 mode. In the PC/AT

mode the data bus pins D0 - D7 are held in a

high impedance state for a read of address 3F1.

STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state

of several disk interface pins in PS/2 and

PS/2 Mode

7

1

6

1

5

4

3

2

1

0

DRIVE WDATA RDATA WGATE MOT

SEL0 TOGGLE TOGGLE

MOT

EN0

EN1

RESET

COND.

1

0

BIT 0 MOTOR ENABLE 0

BIT 4 WRITE DATA TOGGLE

Active high status of the MTR0 disk interface

output pin. This bit is low after a hardware reset

and unaffected by a software reset.

Every inactive edge of the WDATA input causes

this bit to change state.

BIT 5 DRIVE SELECT 0

BIT 1 MOTOR ENABLE 1

Reflects the status of the Drive Select 0 bit of

the DOR (address 3F2 bit 0). This bit is cleared

after a hardware reset and it is unaffected by a

software reset.

Active high status of the MTR1 disk interface

output pin. This bit is low after a hardware reset

and unaffected by a software reset.

BIT 2 WRITE GATE

BIT 6 RESERVED

Active high status of the WGATE disk interface

output.

Always read as a logic "1".

BIT 7 RESERVED

BIT 3 READ DATA TOGGLE

Always read as a logic "1".

Every inactive edge of the RDATA input causes

this bit to change state.

19

PS/2 Model 30 Mode

7

6

5

4

3

2

1

0

nDRV2 nDS1 nDS0 WDATA RDATA WGATE nDS3 nDS2

F/F

RESET

COND.

N/A

1

0

1

BIT 0 nDRIVE SELECT 2

BIT 4 WRITE DATA

Active low status of the DS2 disk interface

output.

Active high status of the latched WDATA output

signal. This bit is latched by the inactive going

edge of WDATA and is cleared by the read of

the DIR register. This bit is not gated with

WGATE.

BIT 1 nDRIVE SELECT 3

Active low status of the DS3 disk interface

output.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface

output.

BIT 2 WRITE GATE

Active high status of the latched WGATE output

signal. This bit is latched by the active going

edge of WGATE and is cleared by the read of

the DIR register.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface

output.

BIT 3 READ DATA

Active high status of the latched RDATA output

signal. This bit is latched by the inactive going

edge of RDATA and is cleared by the read of the

DIR register.

BIT 7 nDRV2

Active low status of the DRV2 disk interface

input.

20

DIGITAL OUTPUT REGISTER (DOR)

also contains the enable for the DMA logic and a

software reset bit. The contents of the DOR are

unaffected by a software reset. The DOR can

be written to at any time.

Address 3F2 READ/WRITE

The DOR controls the drive select and motor

enables of the disk interface outputs. It

7

6

5

4

3

2

1

0

MOT

EN3

MOT

EN2

MOT

EN1

MOT DMAEN nRESE DRIVE DRIVE

EN0

T

SEL1

SEL0

RESET

COND.

0

BIT 0 and 1 DRIVE SELECT

BIT 4 MOTOR ENABLE 0

These two bits are binary encoded for the four drive

selects DS0 -DS3, thereby allowing only one drive to

be selected at one time.

This bit controls the MTR0 disk interface output. A

logic "1" in this bit will cause the output pin to go

active.

BIT 2 nRESET

BIT 5 MOTOR ENABLE 1

A logic "0" written to this bit resets the floppy disk

controller. This reset will remain active until a logic

"1" is written to this bit. This software reset does not

affect the DSR and CCR registers, nor does it affect

the other bits of the DOR register. The minimum

reset duration required is 100ns, therefore toggling

this bit by consecutive writes to this register is a valid

method of issuing a software reset.

This bit controls the MTR1 disk interface output. A

logic "1" in this bit will cause the output pin to go

active.

BIT 6 MOTOR ENABLE 2

This bit controls the MTR2 disk interface output. A

logic "1" in this bit will cause the output pin to go

active.

BIT 3 DMAEN

BIT 7 MOTOR ENABLE 3

PC/AT and Model 30 Mode:

This bit controls the MTR3 disk interface output. A

logic "1" in this bit causes the output to go active.

Writing this bit to logic "1" will enable the DRQ,

nDACK, TC and FINTR outputs. When this bit is a a

logic "0" it disables the nDACK and TC inputs and

Table 3 - Drive Activation Values

holds the DRQ and FINTR outputs in

a high

impedance state. This bit is a logic "0" after a reset

and in these modes.

DRIVE

DOR VALUE

0

1

2

3

1CH

2DH

4EH

8FH

PS/2 Mode: In this mode the DRQ, nDACK, TC and

FINTR pins are always enabled. During a reset, the

DRQ, nDACK, TC, and FINTR pins will remain

enabled, but this bit will be cleared to a logic "0".

21

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

Table 4 - Tape Select Bits

This register is included for 82077 software

compatability. The robust digital data separator

used in the FDC does not require its

characteristics modified for tape support. The

contents of this register are not used internal to

DRIVE

SELECTED

TAPE SEL1

TAPE SEL2

0

1

0

1

0

1

None

1

2

3

the device.

The TDR is unaffected by a

Bits 2-7 are tri-stated when

software reset.

read in this mode.

Table 5 - Internal 2 Drive Decode - Normal

DRIVE SELECT

MOTOR ON OUTPUTS

(ACTIVE LOW)

DIGITAL OUTPUT REGISTER

OUTPUTS (ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0

nDS1

nDS0

nMTR1

nBIT 5

nMTR0

nBIT 4

X

1

X

1

X

1

X

0

1

X

0

1

0

1

X

1

0

1

0

1

X

0

X

0

Table 6 - Internal 2 Drive Decode - Drives 0 and 1 Swapped

DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS

(ACTIVE LOW) (ACTIVE LOW)

nDS1 nDS0

DIGITAL OUTPUT REGISTER

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0

nMTR1

nMTR0

nBIT 5

X

1

X

1

X

1

X

0

1

X

0

1

0

1

X

0

1

0

1

nBIT 4

X

0

X

0

22

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a

high impedance.

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

REG 3F3 Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state tape sel1 tape sel0

Enhanced Floppy Mode 2 (OS2)

Register 3F3 for Enhanced Floppy Mode 2 operation.

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

REG 3F3

Media

ID1

Media

ID0

Drive Type ID

Floppy Boot Drive

tape sel1 tape sel0

For this mode, MEDIA_ID[1:0] pins are gated

into bits 6 and 7 of the 3F3 register. These two

bits are not affected by a hard or soft reset.

Note: L0-CRF1-B5

=

Logical Device 0,

Configuration Register F1, Bit 5

BIT 7 MEDIA ID 1 READ ONLY (Pin 19) (See

Table 7)

BIT 3 and 2 FLOPPY BOOT DRIVE - These

bits reflect the value of L0-CRF1. Bit 3 = L0-

CRF1-B7. Bit 2 = L0-CRF1-B6.

BIT 6 MEDIA ID 0 READ ONLY (Pin 20) (See

Table 8)

BIT

1 AND 0 - TAPE DRIVE SELECT

(READ/WRITE). Same as in Normal and

Enhanced Floppy Mode. 1.

BIT 5 and 4 DRIVE TYPE ID - These bits

reflect two of the bits of L0-CRF1. Which

two bits these are depends on the last drive

selected in the Digital Output Register (3F2).

(See Table 9)

Table 7 - Media ID1

MEDIA ID1

Table 8 - Media ID0

MEDIA ID0

INPUT

BIT 7

INPUT

Pin 20

BIT 6

Pin 19

L0-CRF1-B5 L0-CRF1-B5

CRF1-B4

= 0

CRF1-B4

= 1

= 0

= 1

0

1

0

1

0

1

0

1

0

1

0

23

Table 9 - Drive Type ID

DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID

Bit 1

Bit 0

Bit 5

Bit 4

0

1

0

1

0

1

L0-CRF2 - B1

L0-CRF2 - B3

L0-CRF2 - B5

L0-CRF2 - B7

L0-CRF2 - B0

L0-CRF2 - B2

L0-CRF2 - B4

L0-CRF2 - B6

Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

24

30 and Microchannel applications.

Other

DATA RATE SELECT REGISTER (DSR)

applications can set the data rate in the DSR.

The data rate of the floppy controller is the most

recent write of either the DSR or CCR. The DSR

is unaffected by a software reset. A hardware

reset will set the DSR to 02H, which

corresponds to the default precompensation

setting and 250 Kbps.

Address 3F4 WRITE ONLY

This register is write only. It is used to program

the data rate, amount of write precompensation,

power down status, and software reset. The

data

rate

is

programmed

using

the

Configuration Control Register (CCR) not the

DSR,

for

PC/AT and PS/2 Model

7

6

5

0

4

3

2

1

0

S/W POWER

RESET DOWN

PRE-

PRE- DRATE DRATE

COMP2 COMP1 COMP0 SEL1

SEL0

RESET

COND.

0

1

0

separator circuits will be turned off.

The

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy

controller. See Table 11 for the settings

corresponding to the individual data rates. The

data rate select bits are unaffected by a

software reset, and are set to 250 Kbps after a

hardware reset.

controller will come out of manual low power

mode after a software reset or access to the

Data Register or Main Status Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the

DOR RESET (DOR bit 2) except that this bit is

self clearing.

BIT 2 - 4 PRECOMPENSATION SELECT

These three bits select the value of write

precompensation that will be applied to the

WDATA output signal. Table 10 shows the

precompensation values for the combination of

these bits settings. Track 0 is the default

starting track number to start precompensation.

this starting track number can be changed by

the configure command.

Table 10 - Precompensation Delays

PRECOMP

432

PRECOMPENSATION

DELAY (nsec)

<2Mbps

2Mbps*

111

001

010

011

100

101

110

000

0.00

41.67

83.34

125.00

166.67

208.33

250.00

Default

0

20.8

41.7

62.5

83.3

104.2

125

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy

controller into manual low power mode. The

Default

Default: See Table 12

floppy

controller

clock

and data

*2Mbps data rate is only available if V_CC= 5V.

25

Table 11 - Data Rates

DATA RATE DATA RATE

DRIVE RATE

DRATE(1)

DENSEL

DRT1

DRT0

SEL1 SEL0

MFM

FM

1

0

1

0

1

0

1

0

1Meg

500

---

1

0

1

0

1

0

1

0

250

150

125

300

250

0

1

0

1

0

1

0

1Meg

500

---

1

0

1

0

1

0

1

0

250

125

500

250

1

0

1

0

1

0

1

0

1Meg

500

---

250

---

1

0

1

0

1

0

1

0

2Meg

250

125

Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format

01 = 3-Mode Drive

10 = 2 Meg Tape

Note 1:

The DRATE and DENSEL values are mapped onto the DRVDEN pins.

Table 12 - DRVDEN Mapping

DT1

DT0

DRVDEN1 (1)

DRVDEN0 (1)

DRIVE TYPE

0

DRATE0

DENSEL

4/2/1 MB 3.5"

2/1 MB 5.25" FDDS

2/1.6/1 MB 3.5" (3-MODE)

1

0

1

0

1

DRATE0

DRATE1

nDENSEL

DRATE0

PS/2

26

Table 13 - Default Precompensation Delays

PRECOMPENSATION

DATA RATE

DELAYS

2 Mbps*

1 Mbps

500 Kbps

300 Kbps

250 Kbps

20.8 ns

41.67 ns

125 ns

*The 2Mbps data rate is only available if V_CC= 5V.

27

read at any time. The MSR indicates when the

disk controller is ready to receive data via the

Data Register. It should be read before each

byte transferring to or from the data register

except in DMA mode. No delay is required

when reading the MSR after a data transfer.

MAIN STATUS REGISTER

Address 3F4 READ ONLY

The Main Status Register is a read-only register

and indicates the status of the disk controller.

The

Main

Status

Register

can be

7

6

5

4

3

2

1

0

RQM

DIO

NON

DMA

CMD

BUSY

DRV3

BUSY

DRV2

BUSY

DRV1

BUSY

DRV0

BUSY

BIT 0-3 DRVx BUSY

BIT 5 NON-DMA

These bits are set to “1”s when a drive is in the

seek portion of a command, including implied

and overlapped seeks and recalibrates.

This mode is selected in the SPECIFY

command and will be set to a “1” during the

execution phase of a command. This is for

polled data transfers and helps differentiate

between the data transfer phase and the reading

of result bytes.

BIT 4 COMMAND BUSY

This bit is set to a “1” when a command is in

progress. This bit will go active after the

command byte has been accepted and goes

inactive at the end of the results phase. If there

is no result phase (Seek, Recalibrate

commands), this bit is returned to a “0” after the

last command byte.

BIT 6 DIO

Indicates the direction of a data transfer once a

RQM is set. A “1” indicates a read and a “0”

indicates a write is required.

BIT 7 RQM

Indicates that the host can transfer data if set to

a “1”. No access is permitted if set to a “0”.

28

DATA REGISTER (FIFO)

FIFO. The data is based upon the following

formula:

Address 3F5 READ/WRITE

All command parameter information, disk data

and result status are transferred between the

host processor and the floppy disk controller

through the Data Register.

Threshold # x

1

x 8 - 1.5 ms = DELAY

DATA RATE

At the start of a command, the FIFO action is

always disabled and command parameters

must be sent based upon the RQM and DIO bit

settings. As the command execution phase is

entered, the FIFO is cleared of any data to

ensure that invalid data is not transferred.

Data transfers are governed by the RQM and

DIO bits in the Main Status Register.

The Data Register defaults to FIFO disabled

mode after any form of reset. This maintains

PC/AT hardware compatibility.

The default

An overrun or underrun will terminate the

current command and the transfer of data. Disk

writes will complete the current sector by

generating a 00 pattern and valid CRC. Reads

require the host to remove the remaining data

so that the result phase may be entered.

values can be changed through the Configure

command (enable full FIFO operation with

threshold control). The advantage of the FIFO

is that it allows the system a larger DMA

latency without causing a disk error. Table 14

gives several examples of the delays with a

Table 14 - FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING

AT 2 Mbps* DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 4 ms - 1.5 ms = 2.5 ms

2 x 4 ms - 1.5 ms = 6.5 ms

8 x 4 ms - 1.5 ms = 30.5 ms

15 x 4 ms - 1.5 ms = 58.5 ms

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING

AT 1 Mbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 8 ms - 1.5 ms = 6.5 ms

2 x 8 ms - 1.5 ms = 14.5 ms

8 x 8 ms - 1.5 ms = 62.5 ms

15 x 8 ms - 1.5 ms = 118.5 ms

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING

AT 500 Kbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 16 ms - 1.5 ms = 14.5 ms

2 x 16 ms - 1.5 ms = 30.5 ms

8 x 16 ms - 1.5 ms = 126.5 ms

15 x 16 ms - 1.5 ms = 238.5 ms

*The 2 Mbps data rate is only available if V_CC= 5V.

29

DIGITAL INPUT REGISTER (DIR)

Address 3F7 READ ONLY

This register is read-only in all modes.

PC/AT Mode

7

6

5

4

3

2

1

0

DSK

CHG

RESET

COND.

N/A

BIT 0 - 6 UNDEFINED

BIT 7 DSKCHG

The data bus outputs D0-6 will remain in a high

impedance state during a read of this register.

This bit monitors the pin of the same name and

reflects the opposite value seen on the disk

cable.

PS/2 Mode

7

6

1

5

1

4

1

3

1

2

1

0

DSK

CHG

DRATE DRATE nHIGH

SEL1

SEL0 nDENS

RESET

COND.

N/A

1

software reset and are set to 250 Kbps after a

hardware reset.

BIT 0 nHIGH DENS

This bit is low whenever the 500 Kbps or 1 Mbps

data rates are selected, and high when 250

Kbps and 300 Kbps are selected.

BIT 3 - 6 UNDEFINED

Always read as a logic "1"

BIT 1 and 2 DATA RATE SELECT

These bits control the data rate of the floppy

BIT 7 DSKCHG

controller.

corresponding to the individual data rates. The

data rate select bits are unaffected by

See Table 11 for the settings

This bit monitors the pin of the same name and

reflects the opposite value seen on the disk

cable.

a

30

Model 30 Mode

7

DSK

CHG

6

0

5

0

4

0

3

2

1

0

DMAEN NOPREC DRATE DRATE

SEL1

SEL0

RESET

COND.

N/A

0

1

0

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy

controller. See Table 11 for the settings

BIT 3 DMAEN

This bit reflects the value of DMAEN bit set in

the DOR register bit 3.

corresponding to the individual data rates. The

data rate select bits are unaffected by a

software reset, and are set to 250 Kbps after a

hardware reset.

BIT 4 - 6 UNDEFINED

Always read as a logic "0"

BIT 7 DSKCHG

This bit monitors the pin of the same name and

reflects the opposite value seen on the pin.

BIT 2 NOPREC

This bit reflects the value of NOPREC bit set in

the CCR register.

31

CONFIGURATION CONTROL REGISTER (CCR)

Address 3F7 WRITE ONLY

PC/AT and PS/2 Modes

7

6

5

4

3

2

1

0

DRATE DRATE

SEL1

SEL0

RESET

COND.

N/A

1

0

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy

controller. See Table 11 for the appropriate

values.

BIT 2 - 7 RESERVED

Should be set to a logical "0"

PS/2 Model 30 Mode

7

6

5

4

3

2

1

0

NOPREC DRATE DRATE

SEL1

SEL0

RESET

COND.

N/A

1

0

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy

controller. See Table 11 for the appropriate

values.

BIT 3 - 7 RESERVED

Should be set to a logical "0"

Table 12 shows the state of the DENSEL pin.

The DENSEL pin is set high after a hardware

reset and is unaffected by the DOR and the

DSR resets.

BIT 2 NO PRECOMPENSATION

This bit can be set by software, but it has no

functionality. It can be read by bit 2 of the DSR

when in Model 30 register mode. Unaffected by

software reset.

32

STATUS REGISTER ENCODING

During the Result Phase of certain commands, the Data Register contains data bytes that give the

status of the command just executed.

Table 15 - Status Register 0

BIT NO.

SYMBOL

IC

NAME

DESCRIPTION

7,6

Interrupt

Code

00 - Normal termination of command. The specified

command was properly executed and completed

without error.

01 - Abnormal termination of command. Command

execution was started, but was not successfully

completed.

10 - Invalid command. The requested command

could not be executed.

11 - Abnormal termination caused by Polling.

5

4

SE

EC

Seek End

The FDC completed a Seek, Relative Seek or

Recalibrate command (used during a Sense Interrupt

Command).

Equipment

Check

The TRK0 pin failed to become a "1" after:

1. 80 step pulses in the Recalibrate command.

2. The Relative Seek command caused the FDC to

step outward beyond Track 0.

3

2

Unused. This bit is always "0".

The current head address.

H

Head

Address

1,0

DS1,0

Drive Select

The current selected drive.

33

Table 16 - Status Register 1

NAME

End of

BIT NO.

SYMBOL

EN

DESCRIPTION

7

The FDC tried to access a sector beyond the final

sector of the track (255D). Will be set if TC is not

issued after Read or Write Data command.

Cylinder

6

5

Unused. This bit is always "0".

DE

OR

Data Error

The FDC detected a CRC error in either the ID field or

the data field of a sector.

4

Overrun/

Underrun

Becomes set if the FDC does not receive CPU or DMA

service within the required time interval, resulting in

data overrun or underrun.

3

2

Unused. This bit is always "0".

ND

No Data

Any one of the following:

1. Read Data, Read Deleted Data command - the

FDC did not find the specified sector.

2. Read ID command - the FDC cannot read the ID

field without an error.

3. Read A Track command - the FDC cannot find

the proper sector sequence.

1

0

NW

MA

Not Writable WP pin became a "1" while the FDC is executing a

Write Data, Write Deleted Data, or Format A Track

command.

Missing

Any one of the following:

Address Mark 1. The FDC did not detect an ID address mark at the

specified track after encountering the index pulse

from the IDX pin twice.

2. The FDC cannot detect a data address mark or a

deleted data address mark on the specified track.

34

Table 17 - Status Register 2

NAME

BIT NO.

SYMBOL

DESCRIPTION

Unused. This bit is always "0".

Control Mark Any one of the following:

1. Read Data command - the FDC encountered a

7

6

CM

deleted data address mark.

2. Read Deleted Data command

encountered a data address mark.

-

the FDC

5

4

DD

Data Error in The FDC detected a CRC error in the data field.

Data Field

WC

Wrong

The track address from the sector ID field is different

from the track address maintained inside the FDC.

Cylinder

3

2

1

Unused. This bit is always "0".

BC

Bad Cylinder The track address from the sector ID field is different

from the track address maintained inside the FDC and

is equal to FF hex, which indicates a bad track with a

hard error according to the IBM soft-sectored format.

0

MD

Missing Data The FDC cannot detect a data address mark or a

Address Mark deleted data address mark.

35

Table 18- Status Register 3

NAME

BIT NO.

SYMBOL

DESCRIPTION

Unused. This bit is always "0".

7

6

WP

Write

Indicates the status of the WP pin.

Protected

5

4

3

2

Unused. This bit is always "1".

T0

Track 0

Indicates the status of the TRK0 pin.

Unused. This bit is always "1".

HD

Head

Indicates the status of the HDSEL pin.

Address

1,0

DS1,0

Drive Select

Indicates the status of the DS1, DS0 pins.

RESET

DOR Reset vs. DSR Reset (Software Reset)

There are three sources of system reset on the

FDC: the RESET pin of the FDC, a reset

generated via a bit in the DOR, and a reset

generated via a bit in the DSR. At power on, a

Power On Reset initializes the FDC. All resets

take the FDC out of the powerdown state.

These two resets are functionally the same.

Both will reset the FDC core, which affects drive

status information and the FIFO circuits. The

DSR reset clears itself automatically while the

DOR reset requires the host to manually clear it.

DOR reset has precedence over the DSR reset.

The DOR reset is set automatically upon a pin

reset. The user must manually clear this reset

bit in the DOR to exit the reset state.

All operations are terminated upon a RESET,

and the FDC enters an idle state. A reset while

a disk write is in progress will corrupt the data

and CRC.

MODES OF OPERATION

On exiting the reset state, various internal

registers are cleared, including the Configure

command information, and the FDC waits for a

new command. Drive polling will start unless

disabled by a new Configure command.

The FDC has three modes of operation, PC/AT

mode, PS/2 mode and Model 30 mode. These

are determined by the state of the IDENT and

MFM bits 6 and 5 respectively of CRxx.

PC/AT mode - (IDENT high, MFM a "don't

care")

RESET Pin (Hardware Reset)

The PC/AT register set is enabled, the DMA

enable bit of the DOR becomes valid (FINTR

and DRQ can be hi Z), and TC and DENSEL

The RESET pin is a global reset and clears all

registers except those programmed by the

Specify command.

The DOR reset bit is

become active high signals.

enabled and must be cleared by the host to exit

the reset state.

36

Burst mode is enabled via Bit[1] of CRF0 in

Logical Device 0. Setting Bit[1]=0 enables burst

mode; the default is Bit[1]=1, for non-burst

mode.

PS/2 mode - (IDENT low, MFM high)

This mode supports the PS/2 models 50/60/80

configuration and register set. The DMA bit of

the DOR becomes a "don't care" (FINTR and

DRQ are always valid), TC and DENSEL

become active low.

CONTROLLER PHASES

For simplicity, command handling in the FDC

can be divided into three phases: Command,

Execution, and Result. Each phase is described

in the following sections.

Model 30 mode - (IDENT low, MFM low)

This mode supports PS/2 Model 30

configuration and register set. The DMA enable

bit of ther DOR becomes valid (FINTR and DRQ

can be hi Z), TC is active high and DENSEL is

active low.

Command Phase

After a reset, the FDC enters the command

phase and is ready to accept a command from

the host. For each of the commands, a defined

set of command code bytes and parameter

bytes has to be written to the FDC before the

command phase is complete. (Please refer to

Table 19 for the command set descriptions.)

These bytes of data must be transferred in the

order prescribed.

DMA TRANSFERS

DMA transfers are enabled with the Specify

command and are initiated by the FDC by

activating the FDRQ pin during a data transfer

command. The FIFO is enabled directly by

asserting nDACK and addresses need not be

valid.

Note that if the DMA controller (i.e. 8237A) is

programmed to function in verify mode, a

pseudo read is performed by the FDC based

only on nDACK. This mode is only available

when the FDC has been configured into byte

mode (FIFO disabled) and is programmed to do

a read. With the FIFO enabled, the FDC can

perform the above operation by using the new

Verify command; no DMA operation is needed.

Before writing to the FDC, the host must

examine the RQM and DIO bits of the Main

Status Register. RQM and DIO must be equal

to "1" and "0" respectively before command

bytes may be written. RQM is set false by the

FDC after each write cycle until the received

byte is processed. The FDC asserts RQM again

to request each parameter byte of the command

unless an illegal command condition is

detected.

After the last parameter byte is

The FDC37C93xAPM supports two DMA

transfer modes for the FDC: Single Transfer and

received, RQM remains "0" and the FDC

automatically enters the next phase as defined

by the command definition.

Burst Transfer.

In the case of the single

transfer, the DMA Req goes active at the start of

the DMA cycle, and the DMA Req is deasserted

after the nDACK. In the case of the burst

transfer, the Req is held active until the last

transfer (independent of nDACK). See timing

diagrams for more information.

The FIFO is disabled during the command

phase to provide for the proper handling of the

"Invalid Command" condition.

37

full sector have been placed in the FIFO. The

FINT pin can be used for interrupt-driven

systems, and RQM can be used for polled

systems. The host must respond to the request

by reading data from the FIFO. This process is

repeated until the last byte is transferred out of

the FIFO. The FDC will deactivate the FINT pin

and RQM bit when the FIFO becomes empty.

Execution Phase

All data transfers to or from the FDC occur

during the execution phase, which can proceed

in DMA or non-DMA mode as indicated in the

Specify command.

After a reset, the FIFO is disabled. Each data

byte is transferred by an FINT or FDRQ

depending on the DMA mode. The Configure

command can enable the FIFO and set the

FIFO threshold value.

Non-DMA Mode - Transfers from the Host to the

FIFO

The FINT pin and RQM bit in the Main Status

Register are activated upon entering the

execution phase of data transfer commands.

The host must respond to the request by writing

data into the FIFO. The FINT pin and RQM bit

remain true until the FIFO becomes full. They

are set true again when the FIFO has

<threshold> bytes remaining in the FIFO. The

FINT pin will also be deactivated if TC and

nDACK both go inactive. The FDC enters the

result phase after the last byte is taken by the

FDC from the FIFO (i.e. FIFO empty condition).

The following paragraphs detail the operation of

the FIFO flow control. In these descriptions,

<threshold> is defined as the number of bytes

available to the FDC when service is requested

from the host and ranges from 1 to 16. The

parameter FIFOTHR, which the user programs,

is one less and ranges from 0 to 15.

A low threshold value (i.e. 2) results in longer

periods of time between service requests, but

requires faster servicing of the request for both

read and write cases. The host reads (writes)

from (to) the FIFO until empty (full), then the

transfer request goes inactive. The host must

be very responsive to the service request. This

is the desired case for use with a "fast" system.

DMA Mode - Transfers from the FIFO to the

Host

The FDC activates the DDRQ pin when the

FIFO contains (16 - <threshold>) bytes, or the

last byte of a full sector transfer has been

placed in the FIFO. The DMA controller must

respond to the request by reading data from the

FIFO. The FDC will deactivate the DDRQ pin

when the FIFO becomes empty. FDRQ goes

inactive after nDACK goes active for the last

byte of a data transfer (or on the active edge of

nIOR, on the last byte, if no edge is present on

nDACK). A data underrun may occur if FDRQ

is not removed in time to prevent an unwanted

cycle.

A high value of threshold (i.e. 12) is used with a

"sluggish" system by affording a long latency

period after a service request, but results in

more frequent service requests.

Non-DMA Mode - Transfers from the FIFO to

the Host

The FINT pin and RQM bits in the Main Status

Register are activated when the FIFO contains

(16-<threshold>) bytes or the last bytes of a

38

DMA Mode - Transfers from the Host to the

FIFO

complete the sector as if a hardware TC was

received. The only difference between these

implicit functions and TC is that they return

The FDC activates the FDRQ pin when entering

the execution phase of the data transfer

commands. The DMA controller must respond

by activating the nDACK and nIOW pins and

placing data in the FIFO. FDRQ remains active

until the FIFO becomes full. FDRQ is again set

true when the FIFO has <threshold> bytes

remaining in the FIFO. The FDC will also

deactivate the FDRQ pin when TC becomes true

(qualified by nDACK), indicating that no more

data is required. FDRQ goes inactive after

nDACK goes active for the last byte of a data

transfer (or on the active edge of nIOW of the

last byte, if no edge is present on nDACK). A

data overrun may occur if FDRQ is not removed

in time to prevent an unwanted cycle.

"abnormal termination" result status.

status indications can be ignored if they were

expected.

Such

Note that when the host is sending data to the

FIFO of the FDC, the internal sector count will

be complete when the FDC reads the last byte

from its side of the FIFO. There may be a delay

in the removal of the transfer request signal of

up to the time taken for the FDC to read the last

16 bytes from the FIFO. The host must tolerate

this delay.

Result Phase

The generation of FINT determines the

beginning of the result phase. For each of the

commands, a defined set of result bytes has to

be read from the FDC before the result phase is

complete. These bytes of data must be read out

for another command to start.

Data Transfer Termination

The FDC supports terminal count explicitly

through the TC pin and implicitly through the

underrun/overrun and end-of-track (EOT)

functions. For full sector transfers, the EOT

parameter can define the last sector to be

transferred in a single or multi-sector transfer.

RQM and DIO must both equal "1" before the

result bytes may be read. After all the result

bytes have been read, the RQM and DIO bits

switch to "1" and "0" respectively and the CB bit

is cleared, indicating that the FDC is ready to

accept the next command.

If the last sector to be transferred is a partial

sector, the host can stop transferring the data in

mid-sector, and the FDC will continue to

39

COMMAND SET/DESCRIPTIONS

interrupt is issued. The user sends a Sense

Interrupt Status command which returns an

invalid command error. Refer to Table 19 for

explanations of the various symbols used. Table

20 lists the required parameters and the results

associated with each command that the FDC is

capable of performing.

Commands can be written whenever the FDC is

in the command phase. Each command has a

unique set of needed parameters and status

results. The FDC checks to see that the first

byte is a valid command and, if valid, proceeds

with the command. If it is invalid, an

Table 19 - Description of Command Symbols

NAME DESCRIPTION

Cylinder Address The currently selected address; 0 to 255.

Data Pattern The pattern to be written in each sector data field during

SYMBOL

C

D

formatting.

D0, D1, D2, Drive Select 0-3

D3

Designates which drives are perpendicular drives on the

Perpendicular Mode Command. A "1" indicates a perpendicular

drive.

DIR

Direction Control If this bit is 0, then the head will step out from the spindle during a

relative seek. If set to a 1, the head will step in toward the spindle.

DS1

DS0

DRIVE

DS0, DS1

Disk Drive Select

0

1

0

1

0

1

drive 0

drive 1

drive 2

drive 3

DTL

Special Sector

Size

By setting N to zero (00), DTL may be used to control the number

of bytes transferred in disk read/write commands. The sector size

(N = 0) is set to 128. If the actual sector (on the diskette) is larger

than DTL, the remainder of the actual sector is read but is not

passed to the host during read commands; during write

commands, the remainder of the actual sector is written with all

zero bytes. The CRC check code is calculated with the actual

sector. When N is not zero, DTL has no meaning and should be

set to FF HEX.

EC

Enable Count

Enable FIFO

When this bit is "1" the "DTL" parameter of the Verify command

becomes SC (number of sectors per track).

EFIFO

EIS

This active low bit when a 0, enables the FIFO. A "1" disables the

FIFO (default).

Enable Implied

Seek

When set, a seek operation will be performed before executing any

read or write command that requires the C parameter in the

command phase. A "0" disables the implied seek.

40

Table 19 - Description of Command Symbols

NAME DESCRIPTION

SYMBOL

EOT

End of Track

The final sector number of the current track.

GAP

GPL

Alters Gap 2 length when using Perpendicular Mode.

Gap Length

The Gap 3 size. (Gap 3 is the space between sectors excluding

the VCO synchronization field).

H/HDS

HLT

Head Address

Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector

ID field.

Head Load Time The time interval that FDC waits after loading the head and before

initializing a read or write operation. Refer to the Specify

command for actual delays.

HUT

Head Unload

Time

The time interval from the end of the execution phase (of a read or

write command) until the head is unloaded. Refer to the Specify

command for actual delays.

LOCK

Lock defines whether EFIFO, FIFOTHR and PRETRK parameters

of the CONFIGURE COMMAND can be reset to their default

values by a "Software Reset" (reset caused by writing to the

appropriate bits of either tha DSR or DOR).

MFM

MT

MFM/FM Mode

Selector

A “1” selects the double density (MFM) mode. A “0” selects single

density (FM) mode.

Multi-Track

Selector

When set, this flag selects the multi-track operating mode. In this

mode, the FDC treats a complete cylinder under head 0 and 1 as

a single track. The FDC operates as this expanded track started

at the first sector under head 0 and ended at the last sector under

head 1. With this flag set, a multitrack read or write operation will

automatically continue to the first sector under head 1 when the

FDC finishes operating on the last sector under head 0.

41

Table 19 - Description of Command Symbols

NAME DESCRIPTION

SYMBOL

N

Sector Size Code This specifies the number of bytes in a sector. If this parameter is

"00", then the sector size is 128 bytes. The number of bytes

transferred is determined by the DTL parameter. Otherwise the

sector size is (2 raised to the "N'th" power) times 128. All values

up to "07" hex are allowable. "07"h would equal a sector size of

16k. It is the user's responsibility to not select combinations that

are not possible with the drive.

N

SECTOR SIZE

128 bytes

00

01

02

03

256 bytes

512 bytes

1024 bytes

NCN

ND

New Cylinder

Number

The desired cylinder number.

Non-DMA Mode

Flag

When set to “1”, indicates that the FDC is to operate in the non-

DMA mode. In this mode, the host is interrupted for each data

transfer. When set to “0”, the FDC operates in DMA mode,

interfacing to a DMA controller by means of the DRQ and nDACK

signals.

OW

Overwrite

The bits D0-D3 of the Perpendicular Mode Command can only be

modified if OW is set to “1”. OW is defined in the Lock command.

PCN

Present Cylinder The current position of the head at the completion of Sense

Number

Interrupt Status command.

POLL

PRETRK

Polling Disable

When set, the internal polling routine is disabled. When clear,

polling is enabled.

Precompensation Programmable from track 00 to FFH.

Start Track

Number

R

Sector Address

The sector number to be read or written. In multi-sector transfers,

this parameter specifies the sector number of the first sector to be

read or written.

RCN

Relative Cylinder Relative cylinder offset from present cylinder as used by the

Number Relative Seek command.

42

Table 19 - Description of Command Symbols

DESCRIPTION

SYMBOL

SC

NAME

Number of

The number of sectors per track to be initialized by the Format

Sectors Per Track command. The number of sectors per track to be verified during a

Verify command when EC is set.

SK

Skip Flag

When set to “1”, sectors containing a deleted data address mark

will automatically be skipped during the execution of Read Data. If

Read Deleted is executed, only sectors with a deleted address

mark will be accessed. When set to "0", the sector is read or

written the same as the read and write commands.

SRT

Step Rate Interval The time interval between step pulses issued by the FDC

Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms

at the 1 Mbps data rate. Refer to the SPECIFY command for

actual delays.

ST0

Status 0

Status 1

Status 2

Status 3

Write Gate

Registers within the FDC which store status information after a

command has been executed. This status information is available

to the host during the result phase after command execution.

ST1

ST2

ST3

WGATE

Alters timing of WE to allow for pre-erase loads in perpendicular

drives.

43

INSTRUCTION SET

Table 20 - Instruction Set

READ DATA

DATA BUS

REMARKS

PHASE

R/W D7

D6

D5 D4 D3 D2 D1 D0

Command

W

MT MFM SK

0

1

0

Command Codes

0

HDS DS1 DS0

--------C --------

Sector ID information prior to

Command execution.

W

--------H --------

--------R --------

--------N --------

-------EOT -------

-------GPL -------

-------DTL -------

Execution

Result

Data transfer between the

FDD and system.

R

-------ST0 -------

Status information after

Command execution.

R

-------ST1 -------

-------ST2 -------

--------C --------

Sector ID information after

Command execution.

R

--------H --------

--------R --------

--------N --------

44

READ DELETED DATA

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5 D4 D3 D2 D1 D0

Command

W

MT MFM SK

0

1

0

1

0

Command Codes

0

HDS DS1 DS0

--------C --------

Sector ID information prior to

Command execution.

W

--------H --------

--------R --------

--------N --------

-------EOT -------

-------GPL -------

-------DTL -------

Execution

Result

Data transfer between the

FDD and system.

R

-------ST0 -------

Status information after

Command execution.

R

-------ST1 -------

-------ST2 -------

--------C --------

Sector ID information after

Command execution.

R

--------H --------

--------R --------

--------N --------

45

WRITE DATA

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5 D4 D3 D2 D1 D0

Command

W

MT MFM

0

1

0

1

Command Codes

0

HDS DS1 DS0

--------C --------

Sector ID information prior to

Command execution.

W

--------H --------

--------R --------

--------N --------

-------EOT -------

-------GPL -------

-------DTL -------

Execution

Result

Data transfer between the

FDD and system.

R

-------ST0 -------

Status information after

Command execution.

R

-------ST1 -------

-------ST2 -------

--------C --------

Sector ID information after

Command execution.

R

--------H --------

--------R --------

--------N --------

46

WRITE DELETED DATA

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5 D4 D3

D2

D1

D0

Command

W

MT MFM

0

1

0

1

Command Codes

0

HDS DS1 DS0

--------C --------

Sector ID information

prior to Command

execution.

W

--------H --------

--------R --------

--------N --------

-------EOT -------

-------GPL -------

-------DTL -------

Execution

Result

Data transfer between

the FDD and system.

R

-------ST0 -------

-------ST1 -------

-------ST2 -------

--------C --------

--------H --------

--------R --------

--------N --------

Status information after

Command execution.

Sector ID information

after Command

execution.

47

READ A TRACK

DATA BUS

PHASE

R/W

REMARKS

D7

0

D6

MFM

0

D5 D4 D3

D2

D1

D0

Command

W

0

1

0

Command Codes

0

HDS DS1 DS0

--------C --------

Sector ID information

prior to Command

execution.

W

--------H --------

--------R --------

--------N --------

-------EOT -------

-------GPL -------

-------DTL -------

Execution

Result

Data transfer between

the FDD and system.

FDC reads all of

cylinders' contents from

index hole to EOT.

R

-------ST0 -------

-------ST1 -------

-------ST2 -------

--------C --------

--------H --------

--------R --------

--------N --------

Status information after

Command execution.

Sector ID information

after Command

execution.

48

VERIFY

DATA BUS

PHASE

R/W

D7

D6

D5 D4 D3

D2

D1

D0

REMARKS

Command

W

MT MFM SK

1

0

1

0

Command Codes

EC

0

HDS DS1 DS0

--------C --------

Sector ID information

prior to Command

execution.

W

--------H --------

--------R --------

--------N --------

-------EOT -------

-------GPL -------

------DTL/SC ------

Execution

Result

No data transfer takes

place.

R

-------ST0 -------

-------ST1 -------

-------ST2 -------

--------C --------

--------H --------

--------R --------

Status information after

Command execution.

R

Sector ID information

after Command

execution.

R

--------N --------

VERSION

DATA BUS

PHASE

R/W

REMARKS

D7

0

D6

0

D5 D4 D3

D2

0

D1

0

D0

0

Command

Result

W

R

0

1

0

Command Code

1

0

Enhanced Controller

49

FORMAT A TRACK

DATA BUS

PHASE

R/W

REMARKS

D7

0

D6

MFM

0

D5 D4 D3

D2

D1

D0

Command

W

0

1

0

1

0

1

Command Codes

0

HDS DS1 DS0

--------N --------

--------SC --------

-------GPL -------

--------D --------

Bytes/Sector

Sectors/Cylinder

Gap 3

Filler Byte

Execution for

Each Sector

Repeat:

W

--------C --------

Input Sector

Parameters

W

--------H --------

--------R --------

--------N --------

FDC formats an entire

cylinder

Result

R

-------ST0 -------

Status information after

Command execution

R

-------ST1 -------

-------ST2 -------

------Undefined ------

50

RECALIBRATE

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3 D2

D1

D0

Command

W

0

1

0

1

Command Codes

DS1 DS0

Execution

Head retracted to Track 0

Interrupt.

SENSE INTERRUPT STATUS

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3 D2 D1 D0

Command

Result

W

R

0

1

0

Command Codes

-------ST0 -------

Status information at the end

of each seek operation.

R

-------PCN -------

SPECIFY

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3 D2 D1 D0

Command

W

0

1

Command Codes

---SRT ---

---HUT ---

------HLT ------

ND

51

SENSE DRIVE STATUS

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3

D2

D1

D0

Command

W

R

0

1

0

Command Codes

HDS DS1 DS0

Result

-------ST3 -------

Status information about

FDD

SEEK

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3

D2

D1

D0

Command

W

0

1

0

1

Command Codes

HDS DS1 DS0

-------NCN -------

Execution

Head positioned over

proper cylinder on

diskette.

CONFIGURE

DATA BUS

PHASE

R/W

REMARKS

Configure

Information

D7 D6

D5

D4

D3

D2

D1

D0

Command

W

0

1

0

1

W

0

EIS EFIFO POLL

---FIFOTHR ---

Execution

---------PRETRK ---------

52

RELATIVE SEEK

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3

D2

D1

D0

Command

W

1

0

DIR

0

1

0

1

HDS DS1 DS0

-------RCN -------

DUMPREG

DATA BUS

PHASE

R/W

REMARKS

D7

D6

D5

D4

D3 D2

D1

D0

Command

W

0

1

0

*Note:

Registers

placed in

FIFO

Execution

Result

R

------PCN-Drive 0 -------

------PCN-Drive 1 -------

------PCN-Drive 2 -------

------PCN-Drive 3 -------

----SRT ----

-------HLT -------

-------SC/EOT -------

D3 D2 D1 D0

EIS EFIFO POLL

---HUT ---

ND

LOCK

0

GAP WGATE

--FIFOTHR --

--------PRETRK --------

53

READ ID

DATA BUS

PHASE

R/W

REMARKS

Commands

D7

0

D6

MFM

0

D5 D4 D3

D2

D1

D0

Command

W

0

1

0

1

0

HDS DS1 DS0

Execution

Result

The first correct ID

information on the

Cylinder is stored in

Data Register

--------ST0 --------

--------ST1 --------

Status information after

Command execution.

R

--------ST2 --------

--------C --------

--------H --------

--------R --------

--------N --------

Disk status after the

Command has

completed

54

PERPENDICULAR MODE

DATA BUS

PHASE

R/W

REMARKS

D7

0

D6 D5 D4 D3 D2

D1

D0

Command

W

0

1

0

1

0

Command Codes

OW

D3 D2 D1 D0

GAP WGATE

INVALID CODES

DATA BUS

PHASE

R/W

REMARKS

D7 D6 D5 D4 D3 D2 D1 D0

Command

W

-----Invalid Codes -----

Invalid Command Codes

(NoOp - FDC goes into

Standby State)

Result

R

-------ST0 -------

ST0 = 80H

LOCK

DATA BUS

PHASE

R/W

REMARKS

D7

LOCK

0

D6 D5

D4

1

D3 D2 D1 D0

Command

Result

W

R

0

1

0

Command Codes

LOCK

SC is returned if the last command that was issued was the Format command. EOT is returned if the

last command was a Read or Write.

NOTE: These bits are used internally only. They are not reflected in the Drive Select pins. It is the

user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).

55

CRC bytes, and at the end of the sector,

terminate the Read Data Command.

DATA TRANSFER COMMANDS

All of the Read Data, Write Data and Verify type

commands use the same parameter bytes and

return the same results information, the only

difference being the coding of bits 0-4 in the first

byte.

N determines the number of bytes per sector

(see Table 21 below). If N is set to zero, the

sector size is set to 128. The DTL value

determines the number of bytes to be

transferred. If DTL is less than 128, the FDC

transfers the specified number of bytes to the

host. For reads, it continues to read the entire

128-byte sector and checks for CRC errors. For

writes, it completes the 128-byte sector by filling

in zeros. If N is not set to 00 Hex, DTL should

be set to FF Hex and has no impact on the

number of bytes transferred.

An implied seek will be executed if the feature

was enabled by the Configure command. This

seek is completely transparent to the user. The

Drive Busy bit for the drive will go active in the

Main Status Register during the seek portion of

the command. If the seek portion fails, it is

reflected in the results status normally returned

for

a

Read/Write Data command. Status

Register 0 (ST0) would contain the error code

and C would contain the cylinder on which the

seek failed.

Table 21 - Sector Sizes

N

SECTOR SIZE

00

01

02

03

..

128 bytes

256 bytes

512 bytes

1024 bytes

...

Read Data

A set of nine (9) bytes is required to place the

FDC in the Read Data Mode. After the Read

Data command has been issued, the FDC loads

the head (if it is in the unloaded state), waits the

specified head settling time (defined in the

Specify command), and begins reading ID

Address Marks and ID fields. When the sector

address read off the diskette matches with the

sector address specified in the command, the

FDC reads the sector's data field and transfers

the data to the FIFO.

07

16 Kbytes

The amount of data which can be handled with

a single command to the FDC depends upon

MT (multi-track) and N (number of bytes/sector).

The Multi-Track function (MT) allows the FDC to

read data from both sides of the diskette. For a

particular cylinder, data will be transferred

starting at Sector 1, Side 0 and completing the

last sector of the same track at Side 1.

After completion of the read operation from the

current sector, the sector address is

incremented by one and the data from the next

logical sector is read and output via the FIFO.

This continuous read function is called "Multi-

Sector Read Operation". Upon receipt of TC, or

an implied TC (FIFO overrun/underrun), the

FDC stops sending data but will continue to

read data from the current sector, check the

If the host terminates a read or write operation

in the FDC, the ID information in the result

phase is dependent upon the state of the MT bit

and EOT byte. Refer to Table 22.

56

At the completion of the Read Data command,

the head is not unloaded until after the Head

Unload Time Interval (specified in the Specify

command) has elapsed. If the host issues

another command before the head unloads,

then the head settling time may be saved

between subsequent reads.

the Read Data Command.

After reading the ID and Data Fields in each

sector, the FDC checks the CRC bytes. If a

CRC error occurs in the ID or data field, the

FDC sets the IC code in Status Register 0 to

"01" indicating abnormal termination, sets the

DE bit flag in Status Register 1 to "1", sets the

DD bit in Status Register 2 to "1" if CRC is

incorrect in the ID field, and terminates the Read

Data Command. Table 23 describes the effect

of the SK bit on the Read Data command

execution and results. Except where noted in

Table 23, the C or R value of the sector address

is automatically incremented (see Table 25).

If the FDC detects a pulse on the nINDEX pin

twice without finding the specified sector

(meaning that the diskette's index hole passes

through index detect logic in the drive twice), the

FDC sets the IC code in Status Register 0 to

"01" indicating abnormal termination, sets the

ND bit in Status Register 1 to "1" indicating a

sector

not

found,

and

terminates

Table 22 - Effects of MT and N Bits

FINAL SECTOR READ

FROM DISK

26 at side 0 or 1

26 at side 1

15 at side 0 or 1

15 at side 1

MAXIMUM TRANSFER

CAPACITY

MT

N

0

1

0

1

0

1

2

3

256 x 26 = 6,656

256 x 52 = 13,312

512 x 15 = 7,680

512 x 30 = 15,360

1024 x 8 = 8,192

1024 x 16 = 16,384

8 at side 0 or 1

16 at side 1

Table 23 - Skip Bit vs Read Data Command

DATA ADDRESS

MARK TYPE

ENCOUNTERED

SK BIT

VALUE

RESULTS

SECTOR CM BIT OF DESCRIPTION OF

READ?

ST2 SET?

RESULTS

0

Normal Data

Deleted Data

Yes

No

Normal termination.

Yes

Address not incremented.

Next sector not searched for.

Normal termination.

1

Normal Data

Deleted Data

Yes

No

Normal termination. Sector

not read ("skipped").

Yes

57

Table 24 describes the effect of the SK bit on

the Read Deleted Data command execution

and results.

Read Deleted Data

This command is the same as the Read Data

command, only it operates on sectors that

contain a Deleted Data Address Mark at the

beginning of a Data Field.

Except where noted in Table 24, the C or R

value of the sector address is automatically

incremented (see Table 25).

Table 24 - Skip Bit vs. Read Deleted Data Command

DATA ADDRESS

MARK TYPE

ENCOUNTERED

SK BIT

VALUE

RESULTS

SECTOR CM BIT OF

DESCRIPTION

OF RESULTS

READ?

ST2 SET?

0

Normal Data

Yes

Address not

incremented.

Next sector not

searched for.

Normal

0

1

Deleted Data

Normal Data

Yes

No

termination.

Normal

Yes

termination.

Sector not read

("skipped").

Normal

1

Deleted Data

Yes

No

termination.

command and sets the ND flag of Status

Register 1 to a "1" if there is no comparison.

Multi-track or skip operations are not allowed

with this command. The MT and SK bits (bits

D7 and D5 of the first command byte

respectively) should always be set to "0".

Read A Track

This command is similar to the Read Data

command except that the entire data field is

read continuously from each of the sectors of

a track. Immediately after encountering a

pulse on the nINDEX pin, the FDC starts to

read all data fields on the track as continuous

blocks of data without regard to logical sector

numbers. If the FDC finds an error in the ID or

DATA CRC check bytes, it continues to read

data from the track and sets the appropriate

error bits at the end of the command. The

FDC compares the ID information read from

each sector with the specified value in the

This command terminates when the EOT

specified number of sectors has not been

read. If the FDC does not find an ID Address

Mark on the diskette after the second

occurrence of a pulse on the IDX pin, then it

sets the IC code in Status Register 0 to "01"

(abnormal termination), sets the MA bit in

Status Register 1 to "1", and terminates the

command.

58

Table 25 - Result Phase Table

FINAL SECTOR

ID INFORMATION AT RESULT PHASE

MT

HEAD

TRANSFERRED TO

HOST

C

H

R

N

0

Less than EOT

Equal to EOT

Less than EOT

Equal to EOT

Less than EOT

Equal to EOT

Less than EOT

Equal to EOT

NC

LSB

NC

LSB

R + 1

01

NC

C + 1

NC

1

0

1

R + 1

01

C + 1

NC

1

R + 1

01

NC

R + 1

01

C + 1

NC: No Change, the same value as the one at the beginning of command execution.

LSB: Least Significant Bit, the LSB of H is complemented.

sector and checks the CRC bytes. If it detects

a CRC error in one of the ID fields, it sets the

IC code in Status Register 0 to "01" (abnormal

termination), sets the DE bit of Status Register 1

to "1", and terminates the Write Data command.

Write Data

After the Write Data command has been issued,

the FDC loads the head (if it is in the unloaded

state), waits the specified head load time if

unloaded (defined in the Specify command),

and begins reading ID fields. When the sector

address read from the diskette matches the

sector address specified in the command, the

FDC reads the data from the host via the FIFO

and writes it to the sector's data field.

The Write Data command operates in much the

same manner as the Read Data command. The

following items are the same. Please refer to the

Read Data Command for details:

·

Transfer Capacity

EN (End of Cylinder) bit

ND (No Data) bit

Head Load, Unload Time Interval

ID information when the host terminates the

command

After writing data into the current sector, the

FDC computes the CRC value and writes it into

the CRC field at the end of the sector transfer.

The Sector Number stored in "R" is incremented

by one, and the FDC continues writing to the

next data field. The FDC continues this "Multi-

Sector Write Operation". Upon receipt of a

terminal count signal or if a FIFO over/under run

occurs while a data field is being written, then

the remainder of the data field is filled with

·

Definition of DTL when N = 0 and when N

does not = 0

Write Deleted Data

This command is almost the same as the Write

Data command except that a Deleted Data

Address Mark is written at the beginning of the

Data Field instead of the normal Data Address

Mark. This command is typically used to mark

zeros.

The FDC reads the ID field of each

59

a bad sector containing an error on the floppy

disk.

decremented to 0 (an SC value of 0 will verify

256 sectors). This command can also be

terminated by setting the EC bit to "0" and the

EOT value equal to the final sector to be

checked. If EC is set to "0", DTL/SC should be

programmed to 0FFH. Refer to Table 25 and

Table 26 for information concerning the values

of MT and EC versus SC and EOT value.

Verify

The Verify command is used to verify the data

stored on a disk. This command acts exactly

like a Read Data command except that no data

is transferred to the host. Data is read from the

disk and CRC is computed and checked against

the previously-stored value.

Definitions:

# Sectors Per Side = Number of formatted

sectors per each side of the disk.

Because data is not transferred to the host, TC

(pin 89) cannot be used to terminate this

command. By setting the EC bit to "1", an

implicit TC will be issued to the FDC. This

implicit TC will occur when the SC value has

# Sectors Remaining = Number of formatted

sectors left which can be read, including side 1

of the disk if MT is set to "1".

Table 26 - Verify Command Result Phase Table

MT

EC

SC/EOT VALUE

TERMINATION RESULT

0

SC = DTL

EOT £ # Sectors Per Side

Success Termination

Result Phase Valid

0

1

SC = DTL

EOT > # Sectors Per Side

Unsuccessful Termination

Result Phase Invalid

Successful Termination

Result Phase Valid

SC £ # Sectors Remaining AND

EOT £ # Sectors Per Side

0

1

0

1

SC > # Sectors Remaining OR

EOT > # Sectors Per Side

Unsuccessful Termination

Result Phase Invalid

SC = DTL

EOT £ # Sectors Per Side

Successful Termination

Result Phase Valid

SC = DTL

EOT > # Sectors Per Side

Unsuccessful Termination

Result Phase Invalid

Successful Termination

Result Phase Valid

SC £ # Sectors Remaining AND

EOT £ # Sectors Per Side

1

SC > # Sectors Remaining OR

EOT > # Sectors Per Side

Unsuccessful Termination

Result Phase Invalid

Note: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors

on Side 0, verifying will continue on Side 1 of the disk.

60

After formatting each sector, the host must send

new values for C, H, R and N to the FDC for the

next sector on the track. The R value (sector

number) is the only value that must be changed

by the host after each sector is formatted. This

allows the disk to be formatted with

nonsequential sector addresses (interleaving).

This incrementing and formatting continues for

the whole track until the FDC encounters a pulse

on the IDX pin again and it terminates the

command.

Format A Track

The Format command allows an entire track to

be formatted. After a pulse from the IDX pin is

detected, the FDC starts writing data on the disk

including gaps, address marks, ID fields, and

data fields per the IBM System 34 or 3740

format (MFM or FM respectively). The particular

values that will be written to the gap and data

field are controlled by the values programmed

into N, SC, GPL, and D which are specified by

the host during the command phase. The data

field of the sector is filled with the data byte

specified by D. The ID field for each sector is

supplied by the host; that is, four data bytes per

sector are needed by the FDC for C, H, R, and

N (cylinder, head, sector number and sector size

respectively).

Table 27 contains typical values for gap fields

which are dependent upon the size of the sector

and the number of sectors on each track.

Actual values can vary due to drive electronics.

FORMAT FIELDS

SYSTEM 34 (DOUBLE DENSITY) FORMAT

DATA

GAP4a SYNC

IAM

GAP1 SYNC IDAM

C

Y

L

H

D

S

E

C

N

O

C

R

C

GAP2 SYNC

AM

C

R

C

80x

4E

12x

00

50x

4E

12x

00

22x

4E

12x

00

DATA

GAP3 GAP 4b

3x FC

C2

3x FE

A1

3x FB

A1 F8

SYSTEM 3740 (SINGLE DENSITY) FORMAT

DATA

AM

GAP4a SYNC

IAM

FC

GAP1 SYNC IDAM

C

Y

L

H

D

S

E

C

N

O

C

R

C

GAP2 SYNC

C

R

C

40x

FF

6x

00

26x

FF

6x

00

11x

FF

6x

00

FE

FB or

F8

PERPENDICULAR FORMAT

DATA

AM

GAP4a SYNC

IAM

GAP1 SYNC IDAM

C

Y

L

H

D

S

E

C

N

O

C

R

C

GAP2 SYNC

C

R

C

80x

4E

12x

00

50x

4E

12x

00

41x

4E

12x

00

3x FC

C2

3x FE

A1

3x FB

A1 F8

61

Table 27 - Typical Values for Formatting

FORMAT SECTOR SIZE

N

SC

GPL1

GPL2

128

512

1024

2048

4096

...

00

02

03

04

05

...

12

10

08

04

02

01

07

10

18

46

C8

09

19

30

87

FF

FM

5.25"

Drives

256

01

02

03

04

05

...

12

10

09

04

02

01

0A

20

2A

80

C8

0C

32

50

F0

FF

512*

1024

2048

4096

...

MFM

128

256

512

0

1

2

0F

09

05

07

0F

1B

2A

3A

FM

3.5"

Drives

256

512**

1024

1

2

3

0F

09

05

0E

1B

35

36

54

74

MFM

GPL1 = suggested GPL values in Read and Write commands to avoid splice point

between data field and ID field of contiguous sections.

GPL2 = suggested GPL value in Format A Track command.

*PC/AT values (typical)

**PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives.

NOTE: All values except sector size are in hex.

62

Disks capable of handling more than 80 tracks

per side may require more than one Recalibrate

command to return the head back to physical

Track 0.

CONTROL COMMANDS

Control commands differ from the other

commands in that no data transfer takes place.

Three commands generate an interrupt when

complete: Read ID, Recalibrate, and Seek. The

other control commands do not generate an

interrupt.

The Recalibrate command does not have a

result phase.

The Sense Interrupt Status

command must be issued after the Recalibrate

command to effectively terminate it and to

provide verification of the head position (PCN).

During the command phase of the recalibrate

operation, the FDC is in the BUSY state, but

during the execution phase it is in a NON-BUSY

Read ID

The Read ID command is used to find the

present position of the recording heads. The

FDC stores the values from the first ID field it is

able to read into its registers. If the FDC does

not find an ID address mark on the diskette after

the second occurrence of a pulse on the

nINDEX pin, it then sets the IC code in Status

Register 0 to "01" (abnormal termination), sets

the MA bit in Status Register 1 to "1", and

terminates the command.

state.

At this time, another Recalibrate

command may be issued, and in this manner

parallel Recalibrate operations may be done on

up to four drives at once.

Upon power up, the software must issue a

Recalibrate command to properly initialize all

drives and the controller.

Seek

The following commands will generate an

interrupt upon completion. They do not return

any result bytes. It is highly recommended that

control commands be followed by the Sense

Interrupt Status command. Otherwise, valuable

interrupt status information will be lost.

The read/write head within the drive is moved

from track to track under the control of the Seek

command. The FDC compares the PCN, which

is the current head position, with the NCN and

performs the following operation if there is a

difference:

Recalibrate

PCN < NCN: Direction signal to drive set

to "1" (step in) and issues

step pulses.

PCN > NCN: Direction signal to drive set

to "0" (step out) and issues

step pulses.

This command causes the read/write head

within the FDC to retract to the track 0 position.

The FDC clears the contents of the PCN counter

and checks the status of the nTR0 pin from the

FDD. As long as the nTR0 pin is low, the DIR

pin remains 0 and step pulses are issued.

When the nTR0 pin goes high, the SE bit in

Status Register 0 is set to "1" and the command

is terminated. If the nTR0 pin is still low after 79

step pulses have been issued, the FDC sets the

SE and the EC bits of Status Register 0 to "1"

and terminates the command.

The rate at which step pulses are issued is

controlled by SRT (Stepping Rate Time) in the

Specify command. After each step pulse is

issued, NCN is compared against PCN, and

when NCN = PCN the SE bit in Status Register

0 is set to "1" and the command is terminated.

63

During the command phase of the seek or

recalibrate operation, the FDC is in the BUSY

state, but during the execution phase it is in the

NON-BUSY state. At this time, another Seek or

Recalibrate command may be issued, and in

this manner, parallel seek operations may be

done on up to four drives at once.

b. Read A Track command

c. Read ID command

d. Read Deleted Data command

e. Write Data command

f. Format A Track command

g. Write Deleted Data command

h. Verify command

Note that if implied seek is not enabled, the read

and write commands should be preceded by:

2. End of Seek, Relative Seek, or Recalibrate

command

1) Seek command - Step to the proper track

2) Sense Interrupt Status command

Terminate the Seek command

3. FDC requires a data transfer during the

execution phase in the non-DMA mode

-

3) Read ID - Verify head is on proper track

4) Issue Read/Write command.

The Sense Interrupt Status command resets the

interrupt signal and, via the IC code and SE bit

of Status Register 0, identifies the cause of the

interrupt.

The Seek command does not have a result

phase. Therefore, it is highly recommended that

the Sense Interrupt Status command be issued

after the Seek command to terminate it and to

provide verification of the head position (PCN).

The H bit (Head Address) in ST0 will always

return to a "0". When exiting POWERDOWN

mode, the FDC clears the PCN value and the

status information to zero. Prior to issuing the

POWERDOWN command, it is highly

recommended that the user service all pending

interrupts through the Sense Interrupt Status

command.

Table 28 - Interrupt Identification

SE

IC

INTERRUPT DUE TO

0

1

11

00

Polling

Normal termination of Seek

or Recalibrate command

Abnormal termination of

Seek or Recalibrate

command

1

01

The Seek, Relative Seek, and Recalibrate

commands have no result phase. The Sense

Interrupt Status command must be issued

immediately after these commands to terminate

them and to provide verification of the head

position (PCN). The H (Head Address) bit in

ST0 will always return a "0". If a Sense Interrupt

Status is not issued, the drive will continue to be

BUSY and may affect the operation of the next

command.

Sense Interrupt Status

An interrupt signal on FINT pin is generated by

the FDC for one of the following reasons:

1. Upon entering the Result Phase of:

a. Read Data command

64

from the end of the execution phase of one of

the read/write commands to the head unload

state. The SRT (Step Rate Time) defines the

time interval between adjacent step pulses. Note

that the spacing between the first and second

step pulses may be shorter than the remaining

Sense Drive Status

Sense Drive Status obtains drive status

information. It has no execution phase and

goes directly to the result phase from the

command phase. Status Register 3 contains

the drive status information.

step pulses.

The HLT (Head Load Time)

defines the time between when the Head Load

signal goes high and the read/write operation

starts. The values change with the data rate

speedselection and are documented in Table 29.

The values are the same for MFM and FM.

Specify

The Specify command sets the initial values for

each of the three internal times. The HUT

(Head Unload Time) defines the time

Table 29 - Drive Control Delays (ms)

HUT

SRT

2M

1M

500K 300K 250K

2M

1M

500K 300K 250K

0

1

..

E

F

64

4

..

56

60

128

8

..

112

120

256

16

..

224

240

426

26.7

..

373

400

512

32

..

448

480

4

3.75

..

0.5

0.25

8

7.5

..

1

0.5

16

15

..

2

1

26.7

25

..

3.33

1.67

32

30

..

4

2

HLT

500K

2M

1M

300K

250K

00

01

02

..

64

0.5

1

128

1

2

256

2

4

426

3.3

6.7

..

512

4

8

..

.

7F

63

63.5

126

127

252

254

420

423

504

508

The choice of DMA or non-DMA operations is

made by the ND bit. When this bit is "1", the

non-DMA mode is selected, and when ND is "0",

the DMA mode is selected. In DMA mode, data

transfers are signalled by the FDRQ pin. Non-

DMA mode uses the RQM bit and the FINT pin

to signal data transfers.

Configure

The Configure command is issued to select the

special features of the FDC. A Configure

command need not be issued if the default

values of the FDC meet the system

requirements.

65

Configure Default Values:

Relative Seek

EIS - No Implied Seeks

EFIFO - FIFO Disabled

POLL - Polling Enabled

The command is coded the same as for Seek,

except for the MSB of the first byte and the DIR

bit.

FIFOTHR - FIFO Threshold Set to 1 Byte

PRETRK - Pre-Compensation Set to Track 0

DIR

Head Step Direction Control

EIS - Enable Implied Seek. When set to "1", the

FDC will perform a Seek operation before

executing a read or write command. Defaults to

no implied seek.

DIR

ACTION

0

1

Step Head Out

Step Head In

EFIFO - A "1" disables the FIFO (default). This

means data transfers are asked for on a byte-

by-byte basis. Defaults to "1", FIFO disabled.

The threshold defaults to "1".

RCN Relative

Cylinder

Number

that

determines how many tracks to step the

head in or out from the current track

number.

POLL - Disable polling of the drives. Defaults to

"0", polling enabled. When enabled, a single

interrupt is generated after a reset. No polling is

performed while the drive head is loaded and

the head unload delay has not expired.

The Relative Seek command differs from the

Seek command in that it steps the head the

absolute number of tracks specified in the

command instead of making a comparison

against an internal register.

The Seek

FIFOTHR - The FIFO threshold in the execution

phase of read or write commands. This is

programmable from 1 to 16 bytes. Defaults to

one byte. A "00" selects one byte; "0F" selects

16 bytes.

command is good for drives that support a

maximum of 256 tracks. Relative Seeks cannot

be overlapped with other Relative Seeks. Only

one Relative Seek can be active at a time.

Relative Seeks may be overlapped with Seeks

and Recalibrates. Bit 4 of Status Register 0

(EC) will be set if Relative Seek attempts to step

outward beyond Track 0.

PRETRK

-

Pre-Compensation Start Track

Number. Programmable from track 0 to 255.

Defaults to track 0. A "00" selects track 0; "FF"

selects track 255.

As an example, assume that a floppy drive has

300 useable tracks. The host needs to read

track 300 and the head is on any track (0-255).

If a Seek command is issued, the head will stop

at track 255. If a Relative Seek command is

issued, the FDC will move the head the

specified number of tracks, regardless of the

internal cylinder position register (but will

increment the register). If the head was on track

40 (d), the maximum track that the FDC could

position the head on using Relative Seek will be

295 (D), the initial track + 255 (D). The

maximum count that the head can be moved

Version

The Version command checks to see if the

controller is an enhanced type or the older type

(765A). A value of 90 H is returned as the result

byte.

66

with a single Relative Seek command is 255

(D).

to keep track of with software without the Read

ID command.

The internal register, PCN, will overflow as the

cylinder number crosses track 255 and will

contain 39 (D). The resulting PCN value is thus

(RCN + PCN) mod 256. Functionally, the FDC

starts counting from 0 again as the track

number goes above 255 (D). It is the user's

responsibility to compensate FDC functions

Perpendicular Mode

The Perpendicular Mode command should be

issued prior to executing Read/Write/Format

commands that access

a disk drive with

perpendicular recording capability. With this

command, the length of the Gap2 field and VCO

enable timing can be altered to accommodate

the unique requirements of these drives. Table

30 describes the effects of the WGATE and

GAP bits for the Perpendicular Mode command.

Upon a reset, the FDC will default to the

conventional mode (WGATE = 0, GAP = 0).

(precompensation

track

number)

when

accessing tracks greater than 255. The FDC

does not keep track that it is working in an

"extended track area" (greater than 255). Any

command issued will use the current PCN value

except for the Recalibrate command, which only

looks for the TRACK0 signal. Recalibrate will

return an error if the head is farther than 79 due

to its limitation of issuing a maximum of 80 step

pulses. The user simply needs to issue a

Selection of the 500 Kbps and

1 Mbps

perpendicular modes is independent of the

actual data rate selected in the Data Rate Select

Register. The user must ensure that these two

data rates remain consistent.

second Recalibrate command.

The Seek

command and implied seeks will function

correctly within the 44 (D) track (299-255) area

of the "extended track area". It is the user's

responsibility not to issue a new track position

that will exceed the maximum track that is

present in the extended area.

The Gap2 and VCO timing requirements for

perpendicular recording type drives are dictated

by the design of the read/write head. In the

design of this head, a pre-erase head precedes

the normal read/write head by a distance of 200

micrometers. This works out to about 38 bytes

at a 1 Mbps recording density. Whenever the

write head is enabled by the Write Gate signal,

the pre-erase head is also activated at the same

time. Thus, when the write head is initially

turned on, flux transitions recorded on the media

for the first 38 bytes will not be preconditioned

with the pre-erase head since it has not yet been

activated. To accommodate this head activation

and deactivation time, the Gap2 field is

expanded to a length of 41 bytes. The format

field shown on Page 61 illustrates the change in

the Gap2 field size for the perpendicular format.

To return to the standard floppy range (0-255) of

tracks, a Relative Seek should be issued to

cross the track 255 boundary.

A Relative Seek can be used instead of the

normal Seek, but the host is required to

calculate the difference between the current

head location and the new (target) head

location. This may require the host to issue a

Read ID command to ensure that the head is

physically on the track that software assumes it

to be. Different FDC commands will return

different cylinder results which may be difficult

67

On the read back by the FDC, the controller

must begin synchronization at the beginning of

the sync field. For the conventional mode, the

internal PLL VCO is enabled (VCOEN)

approximately 24 bytes from the start of the

Gap2 field. But, when the controller operates in

the 1 Mbps perpendicular mode (WGATE = 1,

GAP = 1), VCOEN goes active after 43 bytes to

accommodate the increased Gap2 field size.

For both cases, and approximate two-byte

cushion is maintained from the beginning of the

sync field for the purposes of avoiding write

splices in the presence of motor speed variation.

enhancement allows data transfers between

Conventional and Perpendicular drives without

having to issue Perpendicular mode commands

between the accesses of the different drive

types, nor having to change write pre-

compensation values.

When both GAP and WGATE bits of the

PERPENDICULAR MODE COMMAND are both

programmed to "0" (Conventional mode), then

D0, D1, D2, D3, and D4 can be programmed

independently to "1" for that drive to be set

automatically to Perpendicular mode. In this

mode the following set of conditions also apply:

For the Write Data case, the FDC activates

Write Gate at the beginning of the sync field

under the conventional mode. The controller

then writes a new sync field, data address mark,

data field, and CRC as shown on page 62. With

the pre-erase head of the perpendicular drive,

the write head must be activated in the Gap2

field to insure a proper write of the new sync

field. For the 1 Mbps perpendicular mode

(WGATE = 1, GAP = 1), 38 bytes will be written

in the Gap2 space. Since the bit density is

proportional to the data rate, 19 bytes will be

written in the Gap2 field for the 500 Kbps

perpendicular mode (WGATE = 1, GAP =0).

1. The GAP2 written to a perpendicular drive

during a write operation will depend upon the

programmed data rate.

2. The write pre-compensation given to a

perpendicular mode drive will be 0ns.

3. For D0-D3 programmed to "0" for

conventional mode drives any data written

will be at the currently programmed write

pre-compensation.

Note: Bits D0-D3 can only be overwritten when

OW is programmed as a "1".If either

GAP or WGATE is a "1" then D0-D3 are

ignored.

It should be noted that none of the alterations in

Gap2 size, VCO timing, or Write Gate timing

affect normal program flow. The information

provided here is just for background purposes

and is not needed for normal operation. Once

the Perpendicular Mode command is invoked,

FDC software behavior from the user standpoint

is unchanged.

Software and hardware resets have the

following effect on the PERPENDICULAR

MODE COMMAND:

1. "Software" resets (via the DOR or DSR

registers) will only clear GAP and WGATE

bits to "0". D0-D3 are unaffected and retain

their previous value.

The perpendicular mode command is enhanced

to allow specific drives to be designated

2. "Hardware" resets will clear all bits (GAP,

WGATE and D0-D3) to "0", i.e all

conventional mode.

Perpendicular

recording

drives. This

68

Table 30 - Effects of WGATE and GAP Bits

PORTION OF

GAP 2

LENGTH OF

WRITTEN BY

GAP2 FORMAT WRITE DATA

WGATE GAP

MODE

FIELD

OPERATION

0

1

Conventional

Perpendicular

(500 Kbps)

Reserved

(Conventional)

Perpendicular

(1 Mbps)

22 Bytes

0 Bytes

19 Bytes

1

0

1

22 Bytes

41 Bytes

0 Bytes

38 Bytes

LOCK

ENHANCED DUMPREG

In order to protect systems with long DMA

latencies against older application software that

can disable the FIFO, the LOCK Command has

been added. This command should only be

used by the FDC routines, and application

software should refrain from using it. If an

application calls for the FIFO to be disabled

then the CONFIGURE command should be

used.

The DUMPREG command is designed to

support system run-time diagnostics and

application software development and debug.

To accommodate the LOCK command and the

enhanced PERPENDICULAR MODE command

the eighth byte of the DUMPREG command has

been modified to contain the additional data

from these two commands.

COMPATIBILITY

The LOCK command defines whether the

EFIFO, FIFOTHR, and PRETRK parameters of

the CONFIGURE command can be RESET by

the DOR and DSR registers. When the LOCK

bit is set to logic "1" all subsequent "software

RESETS by the DOR and DSR registers will not

change the previously set parameters to their

default values. All "hardware" RESET from the

RESET pin will set the LOCK bit to logic "0" and

return the EFIFO, FIFOTHR, and PRETRK to

their default values. A status byte is returned

immediately after issuing a a LOCK command.

This byte reflects the value of the LOCK bit set

by the command byte.

The FDC37C93xAPM was designed with

software compatibility in mind. It is a fully

backwards-compatible solution with the older

generation 765A/B disk controllers. The FDC

also implements on-board registers for

compatibility with the PS/2, as well as PC/AT

and PC/XT, floppy disk controller subsystems.

After a hardware reset of the FDC, all registers,

functions and enhancements default to a PC/AT,

PS/2 or PS/2 Model 30 compatible operating

mode, depending on how the IDENT and MFM

bits are configured by the system BIOS.

69

SERIAL PORT (UART)

The FDC37C93xAPM incorporates two full

function UARTs. They are compatible with the

NS16450, the 16450 ACE registers and the

by programming OUT2 of that UART to a logic

"1". OUT2 being a logic "0" disables that

UART's interrupt.

The second UART also

NS16550A.

parallel conversion on received characters and

parallel-to-serial conversion on transmit

The UARTS perform serial-to-

supports IrDA, HP-SIR and ASK-IR infrared

modes of operation.

characters. The data rates are independently

programmable from 460.8K baud down to 50

baud. The character options are programmable

for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky

or no parity; and prioritized interrupts. The

UARTs each contain a programmable baud rate

generator that is capable of dividing the input

clock or crystal by a number from 1 to 65535.

The UARTs are also capable of supporting the

MIDI data rate. Refer to the Configuration

Registers for information on disabling, power

down and changing the base address of the

UARTs. The interrupt from a UART is enabled

Note: The UARTs may be configured to share

an interrupt. Refer to the Configuration section

for more information.

REGISTER DESCRIPTION

Addressing of the accessible registers of the

Serial Port is shown below.

The base

addresses of the serial ports are defined by the

configuration registers (see Configuration

section). The Serial Port registers are located at

sequentially increasing addresses above these

base addresses. The FDC37C93xAPM contains

two serial ports, each of which contain a register

set as described below.

Table 31 - Addressing the Serial Port

DLAB*

A2

0

1

0

A1

0

1

0

1

0

A0

0

1

0

1

0

1

0

1

0

1

REGISTER NAME

Receive Buffer (read)

0

Transmit Buffer (write)

0

Interrupt Enable (read/write)

Interrupt Identification (read)

FIFO Control (write)

X

1

Line Control (read/write)

Modem Control (read/write)

Line Status (read/write)

Modem Status (read/write)

Scratchpad (read/write)

Divisor LSB (read/write)

Divisor MSB (read/write)

1

*Note: DLAB is Bit 7 of the Line Control Register

70

The following section describes the operation of

the registers.

BIT 0

This bit enables the Received Data Available

Interrupt (and timeout interrupts in the FIFO

mode) when set to logic "1".

RECEIVE BUFFER REGISTER (RB)

Address Offset = 0H, DLAB = 0, READ ONLY

BIT 1

This register holds the received incoming data

byte. Bit 0 is the least significant bit, which is

transmitted and received first. Received data is

double buffered; this uses an additional shift

register to receive the serial data stream and

convert it to a parallel 8 bit word which is

transferred to the Receive Buffer register. The

shift register is not accessible.

This bit enables the Transmitter Holding

Register Empty Interrupt when set to logic "1".

BIT 2

This bit enables the Received Line Status

Interrupt when set to logic "1". The error

sources causing the interrupt are Overrun,

Parity, Framing and Break. The Line Status

Register must be read to determine the source.

TRANSMIT BUFFER REGISTER (TB)

Address Offset = 0H, DLAB = 0, WRITE ONLY

BIT 3

This bit enables the MODEM Status Interrupt

when set to logic "1". This is caused when one

of the Modem Status Register bits changes

state.

This register contains the data byte to be

transmitted.

The transmit buffer is double

buffered, utilizing an additional shift register (not

accessible) to convert the 8 bit data word to a

serial format. This shift register is loaded from

the Transmit Buffer when the transmission of

the previous byte is complete.

BIT 4 - 7

These bits are always logic "0".

FIFO CONTROL REGISTER (FCR)

Address Offset = 2H, DLAB = X, WRITE

INTERRUPT ENABLE REGISTER (IER)

Address Offset = 1H, DLAB = 0, READ/WRITE

This is a write only register at the same location

as the IIR. This register is used to enable and

clear the FIFOs, set the RCVR FIFO trigger

level. Note: DMA is not supported.

The lower four bits of this register control the

enables of the five interrupt sources of the Serial

Port interrupt. It is possible to totally disable the

interrupt system by resetting bits 0 through 3 of

this register. Similarly, setting the appropriate

bits of this register to a high, selected interrupts

can be enabled. Disabling the interrupt system

inhibits the Interrupt Identification Register and

disables any Serial Port interrupt out of the

FDC37C93xAPM. All other system functions

operate in their normal manner, including the

Line Status and MODEM Status Registers. The

contents of the Interrupt Enable Register are

described below.

BIT 0

Setting this bit to a logic "1" enables both the

XMIT and RCVR FIFOs. Clearing this bit to a

logic "0" disables both the XMIT and RCVR

FIFOs and clears all bytes from both FIFOs.

When changing from FIFO Mode to non-FIFO

(16450) mode, data is automatically cleared

from the FIFOs. This bit must be a 1 when

other bits in this register are written to or they

will not be properly programmed.

71

1. Receiver Line Status (highest priority)

2. Received Data Ready

3. Transmitter Holding Register Empty

4. MODEM Status (lowest priority)

BIT 1

Setting this bit to a logic "1" clears all bytes in

the RCVR FIFO and resets its counter logic to 0.

The shift register is not cleared. This bit is self-

clearing.

Information indicating that a prioritized interrupt

is pending and the source of that interrupt is

stored in the Interrupt Identification Register

(refer to Interrupt Control Table). When the CPU

accesses the IIR, the Serial Port freezes all

interrupts and indicates the highest priority

pending interrupt to the CPU. During this CPU

access, even if the Serial Port records new

interrupts, the current indication does not

change until access is completed. The contents

of the IIR are described below.

BIT 2

Setting this bit to a logic "1" clears all bytes in

the XMIT FIFO and resets its counter logic to 0.

The shift register is not cleared. This bit is self-

clearing.

BIT 3

Writting to this bit has no effect on the operation

of the UART. The RXRDY and TXRDY pins are

not available on this chip.

BIT 0

BIT 4 and 5

This bit can be used in either a hardwired

prioritized or polled environment to indicate

whether an interrupt is pending. When bit 0 is a

logic "0", an interrupt is pending and the

contents of the IIR may be used as a pointer to

the appropriate internal service routine. When

bit 0 is a logic "1", no interrupt is pending.

Reserved

BIT 6 and 7

These bits are used to set the trigger level for

the RCVR FIFO interrupt.

INTERRUPT IDENTIFICATION REGISTER

(IIR)

Address Offset = 2H, DLAB = X, READ

BIT 1 and 2

These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated by

the Interrupt Control Table.

RCVR FIFO

Bit 6 TRIGGER LEVEL (BYTES)

Bit 7

0

BIT 3

0

1

0

1

In non-FIFO mode, this bit is a logic "0". In

FIFO mode this bit is set along with bit 2 when a

timeout interrupt is pending.

0

1

4

8

14

BIT 4 and 5

These bits of the IIR are always logic "0".

By accessing this register, the host CPU can

determine the highest priority interrupt and its

source. Four levels of priority interrupt exist.

They are in descending order of priority:

BIT 6 and 7

These two bits are set when the FIFO

CONTROL Register bit 0 equals 1.

72

Table 32 - Interrupt Control Table

FIFO

INTERRUPT

MODE IDENTIFICATION

ONLY

REGISTER

INTERRUPT SET AND RESET FUNCTIONS

BIT

3

BIT

1

BIT PRIORITY

INTERRUPT

TYPE

INTERRUPT

SOURCE

INTERRUPT

RESET CONTROL

2

0

1

0

1

0

LEVEL

0

1

-

None

-

Highest

Receiver Line

Status

Overrun Error,

Parity Error,

Reading the Line

Status Register

Framing Error or

Break Interrupt

0

1

0

Second

Received Data

Available

Receiver Data

Available

Read Receiver

Buffer or the FIFO

drops below the

trigger level.

Character

Timeout

Indication

No Characters

Have Been

Removed From

or Input to the

RCVR FIFO

Reading the

Receiver Buffer

Register

during the last 4

Char times and

there is at least 1

char in it during

this time

0

1

0

Third

Transmitter

Reading the IIR

Holding Register Holding Register Register (if Source

Empty

of Interrupt) or

Writing the

Transmitter Holding

Register

Fourth

MODEM Status

Clear to Send or Reading the

Data Set Ready MODEM Status

or Ring Indicator Register

or Data Carrier

Detect

73

LINE CONTROL REGISTER (LCR)

BIT 3

Parity Enable bit. When bit 3 is a logic "1", a

parity bit is generated (transmit data) or

checked (receive data) between the last data

word bit and the first stop bit of the serial data.

(The parity bit is used to generate an even or

odd number of 1s when the data word bits and

the parity bit are summed).

Address Offset = 3H, DLAB = 0, READ/WRITE

This register contains the format information of

the serial line. The bit definitions are:

BIT 0 and 1

These two bits specify the number of bits in

each transmitted or received serial character.

The encoding of bits 0 and 1 is as follows:

BIT 4

Even Parity Select bit. When bit 3 is a logic "1"

and bit 4 is a logic "0", an odd number of logic

"1"'s is transmitted or checked in the data word

bits and the parity bit. When bit 3 is a logic "1"

and bit 4 is a logic "1" an even number of bits is

transmitted and checked.

BIT 1 BIT 0 WORD LENGTH

0

1

0

1

0

1

5 Bits

6 Bits

7 Bits

8 Bits

BIT 5

Stick Parity bit. When bit 3 is a logic "1" and bit

5 is a logic "1", the parity bit is transmitted and

then detected by the receiver in the opposite

state indicated by bit 4.

The Start, Stop and Parity bits are not included

in the word length.

BIT 6

BIT 2

Set Break Control bit. When bit 6 is a logic "1",

the transmit data output (TXD) is forced to the

Spacing or logic "0" state and remains there

(until reset by a low level bit 6) regardless of

other transmitter activity. This feature enables

This bit specifies the number of stop bits in each

transmitted or received serial character. The

following table summarizes the information.

NUMBER OF

the Serial Port to alert

communications system.

a terminal in a

BIT 2 WORD LENGTH

STOP BITS

0

1

--

1

1.5

2

BIT 7

5 bits

6 bits

7 bits

8 bits

Divisor Latch Access bit (DLAB). It must be set

high (logic "1") to access the Divisor Latches of

the Baud Rate Generator during read or write

operations. It must be set low (logic "0") to

access the Receiver Buffer Register, the

Transmitter Holding Register, or the Interrupt

Enable Register.

2

Note: The receiver will ignore all stop bits

beyond the first, regardless of the number used

in transmitting.

MODEM CONTROL REGISTER (MCR)

Address Offset

READ/WRITE

=

4H, DLAB

=

X,

74

This 8 bit register controls the interface with the

MODEM or data set (or device emulating a

MODEM). The contents of the MODEM control

register are described below.

5. The four MODEM Control outputs (nDTR,

nRTS, OUT1 and OUT2) are internally

connected to the four MODEM Control

inputs (nDSR, nCTS, RI, DCD).

6. The Modem Control output pins are forced

inactive high.

BIT 0

7. Data that is transmitted is immediately

received.

This bit controls the Data Terminal Ready

(nDTR) output. When bit 0 is set to a logic "1",

the nDTR output is forced to a logic "0". When

bit 0 is a logic "0", the nDTR output is forced to

a logic "1".

This feature allows the processor to verify the

transmit and receive data paths of the Serial

Port. In the diagnostic mode, the receiver and

the transmitter interrupts are fully operational.

The MODEM Control Interrupts are also

operational but the interrupts' sources are now

the lower four bits of the MODEM Control

Register instead of the MODEM Control inputs.

The interrupts are still controlled by the Interrupt

Enable Register.

BIT 1

This bit controls the Request To Send (nRTS)

output. Bit 1 affects the nRTS output in a

manner identical to that described above for bit

0.

BIT 2

This bit controls the Output 1 (OUT1) bit. This

bit does not have an output pin and can only be

read or written by the CPU.

BIT 5 - 7

These bits are permanently set to logic “0”.

LINE STATUS REGISTER (LSR)

BIT 3

Address Offset

READ/WRITE

=

5H, DLAB

=

X,

Output 2 (OUT2). This bit is used to enable an

UART interrupt. When OUT2 is a logic "0", the

serial port interrupt output is forced to a high

impedance state - disabled. When OUT2 is a

logic "1", the serial port interrupt outputs are

enabled.

BIT 0

Data Ready (DR). It is set to a logic "1"

whenever a complete incoming character has

been received and transferred into the Receiver

Buffer Register or the FIFO. Bit 0 is reset to a

logic "0" by reading all of the data in the Receive

Buffer Register or the FIFO.

BIT 4

This bit provides the loopback feature for

diagnostic testing of the Serial Port. When bit 4

is set to logic "1", the following occur:

BIT 1

1. The TXD is set to the Marking State (logic

"1").

Overrun Error (OE). Bit 1 indicates that data in

the Receiver Buffer Register was not read before

the next character was transferred into the

register, thereby destroying the previous

character. In FIFO mode, an overrunn error will

occur only when the FIFO is full and the next

character has been completely received in the

shift register, the character in the shift register is

overwritten but not transferred to the FIFO. The

OE indicator is set to a logic "1" immediately

2. The receiver Serial Input (RXD) is

disconnected.

3. The output of the Transmitter Shift

Register is "looped back" into the Receiver

Shift Register input.

4. All MODEM Control inputs (nCTS, nDSR,

nRI and nDCD) are disconnected.

75

upon detection of an overrun condition, and

reset whenever the Line Status Register is read.

Restarting after a break is received, requires the

serial data (RXD) to be logic "1" for at least 1/2

bit time.

BIT 2

Note: Bits 1 through 4 are the error conditions

that produce a Receiver Line Status Interrupt

whenever any of the corresponding conditions

are detected and the interrupt is enabled.

Parity Error (PE). Bit 2 indicates that the

received data character does not have the

correct even or odd parity, as selected by the

even parity select bit. The PE is set to a logic

"1" upon detection of a parity error and is

reset to a logic "0" whenever the Line Status

Register is read. In the FIFO mode this error is

associated with the particular character in the

FIFO it applies to. This error is indicated when

the associated character is at the top of the

FIFO.

BIT 5

Transmitter Holding Register Empty (THRE). Bit

5 indicates that the Serial Port is ready to accept

a new character for transmission. In addition,

this bit causes the Serial Port to issue an

interrupt when the Transmitter Holding Register

interrupt enable is set high. The THRE bit is set

to a logic "1" when a character is transferred

from the Transmitter Holding Register into the

Transmitter Shift Register. The bit is reset to

logic "0" whenever the CPU loads the

Transmitter Holding Register. In the FIFO mode

this bit is set when the XMIT FIFO is empty, it is

cleared when at least one byte is written to the

XMIT FIFO. Bit 5 is a read- only bit.

BIT 3

Framing Error (FE). Bit 3 indicates that the

received character did not have a valid stop bit.

Bit 3 is set to a logic "1" whenever the stop bit

following the last data bit or parity bit is detected

as a zero bit (Spacing level). The FE is reset to

a logic "0" whenever the Line Status Register is

read. In the FIFO mode this error is associated

with the particular character in the FIFO it

applies to. This error is indicated when the

associated character is at the top of the FIFO.

The Serial Port will try to resynchronize after a

framing error. To do this, it assumes that the

framing error was due to the next start bit, so it

samples this 'start' bit twice and then takes in

the 'data'.

BIT 6

Transmitter Empty (TEMT). Bit 6 is set to a

logic "1" whenever the Transmitter Holding

Register (THR) and Transmitter Shift Register

(TSR) are both empty. It is reset to logic "0"

whenever either the THR or TSR contains a data

character. Bit 6 is a read only bit. In the FIFO

mode this bit is set whenever the THR and TSR

are both empty.

BIT 4

Break Interrupt (BI). Bit 4 is set to a logic "1"

whenever the received data input is held in the

Spacing state (logic "0") for longer than a full

word transmission time (that is, the total time of

the start bit + data bits + parity bits + stop bits).

The BI is reset after the CPU reads the contents

of the Line Status Register. In the FIFO mode

this error is associated with the particular

character in the FIFO it applies to. This error is

indicated when the associated character is at

the top of the FIFO. When break occurs only

one zero character is loaded into the FIFO.

BIT 7

This bit is permanently set to logic "0" in the 450

mode. In the FIFO mode, this bit is set to a

logic "1" when there is at least one parity error,

framing error or break indication in the FIFO.

This bit is cleared when the LSR is read if there

are no subsequent errors in the FIFO.

76

MODEM STATUS REGISTER (MSR)

BIT 5

This bit is the complement of the Data Set

Ready (nDSR) input. If bit 4 of the MCR is set

to logic "1", this bit is equivalent to DTR in the

MCR.

Address Offset

READ/WRITE

=

6H, DLAB

=

X,

This 8 bit register provides the current state of

the control lines from the MODEM (or peripheral

BIT 6

device).

In addition to this current state

This bit is the complement of the Ring Indicator

(nRI) input. If bit 4 of the MCR is set to logic

"1", this bit is equivalent to OUT1 in the MCR.

information, four bits of the MODEM Status

Register (MSR) provide change information.

These bits are set to logic "1" whenever a

control input from the MODEM changes state.

They are reset to logic "0" whenever the

MODEM Status Register is read.

BIT 7

This bit is the complement of the Data Carrier

Detect (nDCD) input. If bit 4 of the MCR is set

to logic "1", this bit is equivalent to OUT2 in the

MCR.

BIT 0

Delta Clear To Send (DCTS). Bit 0 indicates

that the nCTS input to the chip has changed

state since the last time the MSR was read.

SCRATCHPAD REGISTER (SCR)

Address Offset =7H, DLAB =X, READ/WRITE

BIT 1

Delta Data Set Ready (DDSR). Bit 1 indicates

that the nDSR input has changed state since the

last time the MSR was read.

This 8 bit read/write register has no effect on the

operation of the Serial Port. It is intended as a

scratchpad register to be used by the

programmer to hold data temporarily.

BIT 2

Trailing Edge of Ring Indicator (TERI). Bit 2

indicates that the nRI input has changed from

logic "0" to logic "1".

PROGRAMMABLE BAUD RATE GENERATOR

(AND DIVISOR LATCHES DLH, DLL)

The Serial Port contains a programmable Baud

Rate Generator that is capable of taking any

clock input (DC to 3 MHz) and dividing it by any

divisor from 1 to 65535. This output frequency

of the Baud Rate Generator is 16x the Baud

rate. Two 8 bit latches store the divisor in 16 bit

binary format. These Divisor Latches must be

loaded during initialization in order to insure

desired operation of the Baud Rate Generator.

Upon loading either of the Divisor Latches, a 16

bit Baud counter is immediately loaded. This

prevents long counts on initial load. If a 0 is

loaded into the BRG registers the output divides

the clock by the number 3. If a 1 is loaded the

output is the inverse of the input oscillator. If a

two is loaded the output is a divide by 2 signal

with a 50% duty cycle. If a 3 or greater is

loaded the output is low for 2 bits and high for

BIT 3

Delta Data Carrier Detect (DDCD).

indicates that the nDCD input to the chip has

changed state.

Bit 3

NOTE: Whenever bit 0, 1, 2, or 3 is set to a

logic "1",

generated.

a

MODEM Status Interrupt is

BIT 4

This bit is the complement of the Clear To Send

(nCTS) input. If bit 4 of the MCR is set to logic

"1", this bit is equivalent to nRTS in the MCR.

77

the remainder of the count. The input clock to

the BRG is a 1.8462 MHz clock.

was longer than four continuous character

times ago. (If two stop bits are

programmed, the second one is included in

this time delay.)

The most recent CPU read of the FIFO was

longer than 4 continuous character times

ago.

Table 33 shows the baud rates possible with a

1.8462 MHz crystal.

-

Effect Of The Reset on Register File

This will cause a maximum character received

to interrupt issued delay of 160 msec at

300BAUD with a 12 bit character.

The Reset Function Table (Table 34) details the

effect of the Reset input on each of the registers

of the Serial Port.

B. Character times are calculated by using the

RCLK input for a clock signal (this makes

the delay proportional to the baud rate).

FIFO INTERRUPT MODE OPERATION

When the RCVR FIFO and receiver interrupts

are enabled (FCR bit 0 = "1", IER bit 0 = "1"),

RCVR interrupts occur as follows:

C. When a timeout interrupt has occurred it is

cleared and the timer reset when the CPU

reads one character from the RCVR FIFO.

A. The receive data available interrupt will be

issued when the FIFO has reached its

programmed trigger level; it is cleared as

soon as the FIFO drops below its

programmed trigger level.

D. When a timeout interrupt has not occurred

the timeout timer is reset after a new

character is received or after the CPU reads

the RCVR FIFO.

B. The IIR receive data available indication also

occurs when the FIFO trigger level is

reached. It is cleared when the FIFO drops

below the trigger level.

When the XMIT FIFO and transmitter interrupts

are enabled (FCR bit 0 = "1", IER bit 1 = "1"),

XMIT interrupts occur as follows:

A. The transmitter holding register interrupt

(02H) occurs when the XMIT FIFO is empty;

it is cleared as soon as the transmitter

holding register is written to (1 of 16

characters may be written to the XMIT FIFO

while servicing this interrupt) or the IIR is

read.

C. The receiver line status interrupt (IIR=06H),

has higher priority than the received data

available (IIR=04H) interrupt.

D. The data ready bit (LSR bit 0) is set as soon

as a character is transferred from the shift

register to the RCVR FIFO. It is reset when

the FIFO is empty.

B. The transmitter FIFO empty indications will

be delayed 1 character time minus the last

stop bit time whenever the following occurs:

THRE=1 and there have not been at least

two bytes at the same time in the transmitter

FIFO since the last THRE=1. The transmitter

interrupt after changing FCR0 will be

immediate, if it is enabled.

When RCVR FIFO and receiver interrupts are

enabled, RCVR FIFO timeout interrupts occur

as follows:

A. A FIFO timeout interrupt occurs if all the

following conditions exist:

-

at least one character is in the FIFO

The most recent serial character received

78

Character timeout and RCVR FIFO trigger level

interrupts have the same priority as the current

received data available interrupt; XMIT FIFO

empty has the same priority as the current

transmitter holding register empty interrupt.

-

Bit 0=1 as long as there is one byte in the

RCVR FIFO.

Bits 1 to 4 specify which error(s) have

occurred. Character error status is handled

the same way as when in the interrupt

mode, the IIR is not affected since EIR bit

2=0.

FIFO POLLED MODE OPERATION

-

Bit 5 indicates when the XMIT FIFO is

empty.

Bit 6 indicates that both the XMIT FIFO and

shift register are empty.

Bit 7 indicates whether there are any errors

in the RCVR FIFO.

With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or

3 or all to “0” puts the UART in the FIFO Polled

Mode of operation. Since the RCVR and

XMITTER are controlled separately, either one

or both can be in the polled mode of operation.

There is no trigger level reached or timeout

condition indicated in the FIFO Polled Mode,

however, the RCVR and XMIT FIFOs are still

fully capable of holding characters.

In this mode, the user's program will check

RCVR and XMITTER status via the LSR. LSR

definitions for the FIFO Polled Mode are as

follows:

79

Table 33 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432 MHz Clock

for 115.2k ; Using 3.6864 MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k

DESIRED

DIVISOR USED TO

PERCENT ERROR DIFFERENCE

CRxx:

BAUD RATE

GENERATE 16X CLOCK

BETWEEN DESIRED AND ACTUAL*

BIT 7 OR 6

50

75

2304

1536

1047

857

768

384

192

96

0.001

X

1

-

110

-

134.5

150

0.004

-

300

-

600

-

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

57600

115200

230400

460800

-

64

-

58

0.005

48

-

32

-

24

16

-

12

-

6

-

3

0.030

0.16

2

1

32770

32769

1

*Note: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.

80

Table 34 - Reset Function Table

RESET CONTROL

REGISTER/SIGNAL

Interrupt Enable Register

Interrupt Identification Reg.

FIFO Control

RESET STATE

RESET

All bits low

RESET

Bit 0 is high; Bits 1 - 7 low

RESET

All bits low

Line Control Reg.

RESET

All bits low

MODEM Control Reg.

Line Status Reg.

RESET

All bits low

RESET

All bits low except 5, 6 high

MODEM Status Reg.

TXD1, TXD2

RESET

Bits 0 - 3 low; Bits 4 - 7 input

RESET

High

INTRPT (RCVR errs)

RESET/Read LSR

Low

INTRPT (RCVR Data Ready) RESET/Read RBR

Low

INTRPT (THRE)

OUT2B

RESET/ReadIIR/Write THR

Low

RESET

High

RTSB

High

DTRB

High

OUT1B

High

RCVR FIFO

RESET/

All Bits Low

FCR1*FCR0/_FCR0

XMIT FIFO

RESET/

All Bits Low

FCR1*FCR0/_FCR0

81

Table 35 - Register Summary for an Individual UART Channel

REGISTER

ADDRESS*

REGISTER NAME

SYMBOL

BIT 0

BIT 1

ADDR = 0

DLAB = 0

Receive Buffer Register (Read Only)

RBR

Data Bit 0

(Note 1)

Data Bit 1

ADDR = 0

DLAB = 0

Transmitter Holding Register (Write

Only)

THR

IER

Data Bit 0

Data Bit 1

ADDR = 1

DLAB = 0

Interrupt Enable Register

Enable

Received

Data

Available

Interrupt

(ERDAI)

Enable

Transmitter

Holding Register

Empty Interrupt

(ETHREI)

ADDR = 2

Interrupt Ident. Register (Read Only)

IIR

"0" if

Interrupt ID Bit

Interrupt

Pending

ADDR = 2

ADDR = 3

FIFO Control Register (Write Only)

Line Control Register

FCR

LCR

FIFO

Enable

RCVR FIFO

Reset

Word

Length

Select Bit 0

(WLS0)

Word Length

Select Bit 1

(WLS1)

ADDR = 4

MODEM Control Register

MCR

Data

Request to Send

(RTS)

Terminal

Ready

(DTR)

Data Ready

(DR)

ADDR = 5

ADDR = 6

Line Status Register

LSR

Overrun Error

(OE)

Delta Clear

to Send

(DCTS)

MODEM Status Register

MSR

Delta Data Set

Ready (DDSR)

ADDR = 7

Scratch Register (Note 4)

Divisor Latch (LS)

SCR

DDL

Bit 0

Bit 1

ADDR = 0

DLAB = 1

ADDR = 1

DLAB = 1

Divisor Latch (MS)

DLM

Bit 8

Bit 9

*DLAB is Bit 7 of the Line Control Register (ADDR = 3).

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift

register is empty.

82

Table 35 - Register Summary for an Individual UART Channel (continued)

BIT 2

Data Bit 2

BIT 3

Data Bit 3

BIT 4

Data Bit 4

0

BIT 5

Data Bit 5

0

BIT 6

Data Bit 6

0

BIT 7

Data Bit 7

0

Enable

Receiver Line

Status

Enable

MODEM

Status

Interrupt

(ELSI)

Interrupt

(EMSI)

FIFOs

Enabled

(Note 5)

Interrupt ID

Bit

Interrupt ID

Bit (Note 5)

0

FIFOs

Enabled

(Note 5)

XMIT FIFO

Reset

DMA Mode

Select

(Note 6)

Reserved

Stick Parity

RCVR Trigger RCVR Trigger

LSB

MSB

Divisor Latch

Access Bit

(DLAB)

Number of

Stop Bits

(STB)

Parity Enable Even Parity

(PEN)

Set Break

Select (EPS)

OUT1

OUT2

Loop

0

(Note 3)

Parity Error

(PE)

Framing Error Break

(FE)

Transmitter

Interrupt (BI) Holding

Transmitter

Empty

(TEMT)

Error in

RCVR FIFO

(Note 5)

Register

(THRE)

(Note 2)

Trailing Edge Delta Data

Clear to Send Data Set

Ring Indicator Data Carrier

Ring Indicator Carrier Detect (CTS)

Ready (DSR) (RI)

Detect (DCD)

(TERI)

(DDCD)

Bit 2

Bit 3

Bit 4

Bit 12

Bit 5

Bit 13

Bit 6

Bit 14

Bit 7

Bit 15

Bit 2

Bit 3

Bit 10

Bit 11

Note 3: This bit no longer has a pin associated with it.

Note 4: When operating in the XT mode, this register is not available.

Note 5: These bits are always zero in the non-FIFO mode.

Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.

83

NOTES ON SERIAL PORT OPERATION

FIFO MODE OPERATION:

interrupt delay will remain active until at

least two bytes have the Tx FIFO empties

after this condition, the Tx been loaded into

the FIFO, concurrently. When interrupt will

be activated without a one character delay.

GENERAL

The RCVR FIFO will hold up to 16 bytes

regardless of which trigger level is selected.

Rx support functions and operation are quite

different from those described for the

transmitter. The Rx FIFO receives data until the

number of bytes in the FIFO equals the selected

TX AND RX FIFO OPERATION

interrupt trigger level.

At that time if Rx

The Tx portion of the UART transmits data

through TXD as soon as the CPU loads a byte

into the Tx FIFO. The UART will prevent

loads to the Tx FIFO if it currently holds 16

characters. Loading to the Tx FIFO will again

be enabled as soon as the next character is

transferred to the Tx shift register. These

capabilities account for the largely autonomous

operation of the Tx.

interrupts are enabled, the UART will issue an

interrupt to the CPU. The Rx FIFO will continue

to store bytes until it holds 16 of them. It will

not accept any more data when it is full. Any

more data entering the Rx shift register will set

the Overrun Error flag. Normally, the FIFO

depth and the programmable trigger levels will

give the CPU ample time to empty the Rx FIFO

before an overrun occurs.

The UART starts the above operations typically

with a Tx interrupt. The chip issues a Tx

interrupt whenever the Tx FIFO is empty and the

Tx interrupt is enabled, except in the following

instance. Assume that the Tx FIFO is empty

and the CPU starts to load it. When the first

byte enters the FIFO the Tx FIFO empty

interrupt will transition from active to inactive.

Depending on the execution speed of the service

routine software, the UART may be able to

transfer this byte from the FIFO to the shift

register before the CPU loads another byte. If

this happens, the Tx FIFO will be empty again

and typically the UART's interrupt line would

transition to the active state. This could cause a

system with an interrupt control unit to record a

Tx FIFO empty condition, even though the CPU

is currently servicing that interrupt. Therefore,

after the first byte has been loaded into the

FIFO the UART will wait one serial character

transmission time before issuing a new Tx

FIFO empty interrupt. This one character Tx

One side-effect of having a Rx FIFO is that the

selected interrupt trigger level may be above the

data level in the FIFO. This could occur when

data at the end of the block contains fewer bytes

than the trigger level. No interrupt would be

issued to the CPU and the data would remain in

the UART. To prevent the software from

having to check for this situation the chip

incorporates a timeout interrupt.

The timeout interrupt is activated when there is

a least one byte in the Rx FIFO, and neither the

CPU nor the Rx shift register has accessed the

Rx FIFO within 4 character times of the last

byte. The timeout interrupt is cleared or reset

when the CPU reads the Rx FIFO or another

character enters it.

These FIFO-related features allow optimization

of CPU/UART transactions and are especially

useful given the higer baud rate capability (256

kbaud).

84

INFRARED INTERFACE

The infrared interface provides

wireless communications port using infrared as

transmission medium. Two IR

implementations have been provided for the

second UART in this chip (logical device 5),

IrDA and Amplitude Shift Keyed IR. The IR

transmission can use the standard UART2 TX

and RX pins or optional IRTX2 and IRRX2 pins.

These can be selected through the configuration

registers.

a

two-way

500 kHz waveform for the duration of the serial

bit time. A “1” is signaled by sending no

transmission the bit time. Please refer to the

AC timing for the parameters of the ASK-IR

waveform.

a

If the Half Duplex option is chosen, there is a

time-out when the direction of the transmission

is changed. This time-out starts at the last bit

transferred during a transmission and blocks the

receiver input until the timeout expires. If the

transmit buffer is loaded with more data before

the time-out expires, the timer is restarted after

the new byte is transmitted. If data is loaded

into the transmit buffer while a character is

being received, the transmission will not start

until the time-out expires after the last receive

bit has been received. If the start bit of another

character is received during this time-out, the

timer is restarted after the new character is

received. The IR half duplex time-out is

programmable via CRF2 in Logical Device 5.

This register allows the time-out to be

programmed to any value between 0 and

10msec in 100usec increments.

IrDA allows serial communication at baud rates

up to 115K Baud. Each word is sent serially

beginning with a “0” value start bit. A “0” is

signaled by sending a single IR pulse at the

beginning of the serial bit time. A “1” is signaled

by sending no IR pulse during the bit time.

Please refer to the AC timing for the parameters

of these pulses and the IrDA waveform.

The Amplitude Shift Keyed IR allows serial

communication at baud rates up to 19.2K Baud.

Each word is sent serially beginning with a “0”

value start bit. A zero is signaled by sending a

85

PARALLEL PORT

The parallel port also incorporates SMSC's

The FDC37C93xAPM incorporates an IBM

XT/AT compatible parallel port. This supports

the optional PS/2 type bi-directional parallel port

(SPP), the Enhanced Parallel Port (EPP) and

the Extended Capabilities Port (ECP) parallel

ChiProtect circuitry, which prevents possible

damage to the parallel port due to printer power-

up.

The functionality of the parallel port is achieved

through the use of eight addressable ports,

with their associated registers and control

gating. The control and data port are read/write

by the CPU, the status port is read/write in the

EPP mode. The address map of the parallel

port is shown below:

port modes.

Refer to the Configuration

Registers for information on disabling, power

down, changing the base address of the parallel

port, and selecting the mode of operation.

The FDC37C93xAPM also provides a mode for

support of the floppy disk controller on the

parallel port.

DATA PORT

BASE ADDRESS + 00H

BASE ADDRESS + 01H

BASE ADDRESS + 02H

BASE ADDRESS + 03H

EPP DATA PORT 0

EPP DATA PORT 1

EPP DATA PORT 2

EPP DATA PORT 3

BASE ADDRESS + 04H

BASE ADDRESS + 05H

BASE ADDRESS + 06H

BASE ADDRESS + 07H

STATUS PORT

CONTROL PORT

EPP ADDR PORT

The bit map of these registers is:

D0

PD0

D1

PD1

0

D2

PD2

0

D3

D4

D5

PD5

PE

D6

D7

Note

DATA PORT

PD3

PD4

SLCT

PD6

PD7

1

STATUS

PORT

TMOUT

nERR

nACK nBUSY

CONTROL

PORT

STROBE AUTOFD nINIT

SLC

PD3

IRQE

PD4

PCD

PD5

0

1

EPP ADDR

PORT

PD0

PD1

PD2

PD6

AD7

PD7

2,3

EPP DATA

PORT 0

EPP DATA

PORT 1

EPP DATA

PORT 2

EPP DATA

PORT 3

Note 1: These registers are available in all modes.

Note 2: These registers are only available in EPP mode.

Note 3 : For EPP mode, IOCHRDY must be connected to the ISA bus.

86

Table 36 - Parallel Port Connector

HOST

CONNECTOR

PIN NUMBER

STANDARD

nStrobe

EPP

ECP

1

nWrite

PData<0:7>

Intr

nStrobe

2-9

10

11

12

PData<0:7>

nAck

PData<0:7>

nAck

Busy

nWait

Busy, PeriphAck(3)

PE

(NU)

PError,

nAckReverse(3)

13

14

Select

(NU)

Select

nAutofd

nDatastb

nAutoFd,

HostAck(3)

15

16

17

nError

nInit

(NU)

nFault(1)

nPeriphRequest(3)

(NU)

nInit(1)

nReverseRqst(3)

nSelectin

nAddrstrb

nSelectIn(1,3)

(1) = Compatible Mode

(3) = High Speed Mode

Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers,

refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14,

July 14, 1993. This document is available from Microsoft.

87

BIT 3 nERR - nERROR

IBM XT/AT COMPATIBLE, BI-

DIRECTIONAL AND EPP MODES

The level on the nERROR input is read by the

CPU as bit 3 of the Printer Status Register. A

logic “0” means an error has been detected; a

logic “1” means no error has been detected.

DATA PORT

ADDRESS OFFSET = 00H

BIT 4 SLCT - PRINTER SELECTED STATUS

The level on the SLCT input is read by the CPU

as bit 4 of the Printer Status Register. A logic

“1” means the printer is on line; a logic “0”

means it is not selected.

The Data Port is located at an offset of '00H'

from the base address. The data register is

cleared at initialization by RESET. During a

WRITE operation, the Data Register latches the

contents of the data bus with the rising edge of

the nIOW input. The contents of this register

are buffered (non inverting) and output onto the

PD0-PD7 ports. During a READ operation in

SPP mode, PD0-PD7 ports are buffered (not

latched) and output to the host CPU.

BIT 5 PE - PAPER END

The level on the PE input is read by the CPU as

bit 5 of the Printer Status Register. A logic “1”

indicates a paper end; a logic “0” indicates the

presence of paper.

STATUS PORT

ADDRESS OFFSET = 01H

BIT 6 nACK - nACKNOWLEDGE

The level on the nACK input is read by the CPU

as bit 6 of the Printer Status Register. A logic

“0” means that the printer has received a

character and can now accept another. A logic

“1” means that it is still processing the last

character or has not received the data.

The Status Port is located at an offset of '01H'

from the base address. The contents of this

register are latched for the duration of an nIOR

read cycle. The bits of the Status Port are

defined as follows:

BIT 7 nBUSY - nBUSY

BIT 0 TMOUT - TIME OUT

The complement of the level on the BUSY input

is read by the CPU as bit 7 of the Printer Status

Register. A logic “0” in this bit means that the

printer is busy and cannot accept a new

character. A logic “1” means that it is ready to

accept the next character.

This bit is valid in EPP mode only and indicates

that a 10 msec time out has occured on the EPP

bus. A logic “0” means that no time out error

has occured; a logic “1” means that a time out

error has been detected. This bit is cleared by a

RESET. Writing a “1” to this bit clears the time

out status bit. On a write, this bit is self clearing

and does not require a write of a “0”. Writing a

“0” to this bit has no effect.

CONTROL PORT

ADDRESS OFFSET = 02H

The Control Port is located at an offset of '02H'

from the base address. The Control Register is

initialized by the RESET input, bits 0 to 5 only

being affected; bits 6 and 7 are hard wired low.

BIT 1 and 2 - are not implemented as register

bits, during a read of the Printer Status Register

these bits are a low level.

88

BIT 0 STROBE - STROBE

EPP ADDRESS PORT

This bit is inverted and output onto the

nSTROBE output.

ADDRESS OFFSET = 03H

The EPP Address Port is located at an offset of

'03H' from the base address. The address

register is cleared at initialization by RESET.

During a WRITE operation, the contents of DB0-

DB7 are buffered (non inverting) and output onto

the PD0-PD7 ports, the leading edge of nIOW

causes an EPP ADDRESS WRITE cycle to be

performed, the trailing edge of IOW latches the

data for the duration of the EPP write cycle.

During a READ operation, PD0-PD7 ports are

read, the leading edge of IOR causes an EPP

ADDRESS READ cycle to be performed and the

data output to the host CPU, the deassertion of

ADDRSTB latches the PData for the duration of

the IOR cycle. This register is only available in

EPP mode.

BIT 1 AUTOFD - AUTOFEED

This bit is inverted and output onto the

nAUTOFD output. A logic 1 causes the printer

to generate a line feed after each line is printed.

A logic “0” means no autofeed.

BIT 2 nINIT - nINITIATE OUTPUT

This bit is output onto the nINIT output without

inversion.

BIT 3 SLCTIN - PRINTER SELECT INPUT

This bit is inverted and output onto the nSLCTIN

output. A logic 1 on this bit selects the printer; a

logic 0 means the printer is not selected.

BIT 4 IRQE - INTERRUPT REQUEST ENABLE

The interrupt request enable bit when set to a

high level may be used to enable interrupt

requests from the Parallel Port to the CPU. An

interrupt request is generated on the IRQ port by

a positive going nACK input. When the IRQE

bit is programmed low the IRQ is disabled.

EPP DATA PORT 0

ADDRESS OFFSET = 04H

The EPP Data Port 0 is located at an offset of

'04H' from the base address. The data register

is cleared at initialization by RESET. During a

WRITE operation, the contents of DB0-DB7 are

buffered (non-inverting) and output onto the PD0

- PD7 ports, the leading edge of nIOW causes

an EPP DATA WRITE cycle to be performed,

the trailing edge of IOW latches the data for the

duration of the EPP write cycle. During a READ

operation, PD0-PD7 ports are read, the leading

edge of IOR causes an EPP READ cycle to be

performed and the data output to the host CPU,

the deassertion of DATASTB latches the PData

for the duration of the IOR cycle. This register

is only available in EPP mode.

BIT

5

PCD

-

PARALLEL CONTROL

DIRECTION

Parallel Control Direction is not valid in printer

mode. In printer mode, the direction is always

out regardless of the state of this bit. In bi-

directional, EPP or ECP mode, a logic “0”

means that the printer port is in output mode

(write); a logic 1 means that the printer port is in

input mode (read).

Bits 6 and 7 during a read are a low level, and

cannot be written.

89

deasserted (after command). If a time-out

occurs, the current EPP cycle is aborted and the

time-out condition is indicated in Status bit 0.

EPP DATA PORT 1

ADDRESS OFFSET = 05H

The EPP Data Port 1 is located at an offset of

'05H' from the base address. Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

EPP DATA PORT 2

During an EPP cycle, if STROBE is active, it

overrides the EPP write signal forcing the PDx

bus to always be in a write mode and the

nWRITE signal to always be asserted.

ADDRESS OFFSET = 06H

Software Constraints

The EPP Data Port 2 is located at an offset of

'06H' from the base address. Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

Before an EPP cycle is executed, the software

must ensure that the control register bit PCD is

a logic "0" (ie a 04H or 05H should be written to

the Control port). If the user leaves PCD as a

logic "1", and attempts to perform an EPP write,

the chip is unable to perform the write (because

PCD is a logic "1") and will appear to perform an

EPP read on the parallel bus; no error is

indicated.

EPP DATA PORT 3

ADDRESS OFFSET = 07H

The EPP Data Port 3 is located at an offset of

'07H' from the base address. Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

EPP 1.9 Write

The timing for a write operation (address or

data) is shown in timing diagram EPP Write

Data or Address cycle. IOCHRDY is driven

active low at the start of each EPP write and is

released when it has been determined that the

write cycle can complete. The write cycle can

complete under the following circumstances:

EPP 1.9 OPERATION

When the EPP mode is selected in the

configuration register, the standard and bi-

directional modes are also available. If no EPP

Read, Write or Address cycle is currently

executing, then the PDx bus is in the standard or

bi-directional mode, and all output signals

(STROBE, AUTOFD, INIT) are as set by the

SPP Control Port and direction is controlled by

PCD of the Control port.

1. If the EPP bus is not ready (nWAIT is active

low) when nDATASTB or nADDRSTB goes

active then the write can complete when

nWAIT goes inactive high.

In EPP mode, the system timing is closely

coupled to the EPP timing. For this reason, a

watchdog timer is required to prevent system

lockup. The timer indicates if more than 10

msec have elapsed from the start of the EPP

cycle (nIOR or nIOW asserted) to nWAIT being

2. If the EPP bus is ready (nWAIT is inactive

high) then the chip must wait for it to go

active low before changing the state of

nDATASTB, nWRITE or nADDRSTB. The

write can complete once nWAIT is

determined inactive.

90

Write Sequence of Operation

1. If the EPP bus is not ready (nWAIT is active

low) when nDATASTB goes active then the

read can complete when nWAIT goes

inactive high.

1. The host selects an EPP register, places

data on the SData bus and drives nIOW

active.

2. The chip drives IOCHRDY inactive (low).

3. If WAIT is not asserted, the chip must wait

until WAIT is asserted.

2. If the EPP bus is ready (nWAIT is inactive

high) then the chip must wait for it to go

active low before changing the state of

WRITE or before nDATASTB goes active.

The read can complete once nWAIT is

determined inactive.

4. The chip places address or data on PData

bus, clears PDIR, and asserts nWRITE.

5. Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus contains valid

information, and the WRITE signal is valid.

6. Peripheral deasserts nWAIT, indicating that

any setup requirements have been satisfied

and the chip may begin the termination

phase of the cycle.

7. a) The chip deasserts nDATASTB or

nADDRSTRB, this marks the beginning

of the termination phase. If it has not

already done so, the peripheral should

latch the information byte now.

Read Sequence of Operation

1. The host selects an EPP register and drives

nIOR active.

2. The chip drives IOCHRDY inactive (low).

3. If WAIT is not asserted, the chip must wait

until WAIT is asserted.

4. The chip tri-states the PData bus and

deasserts nWRITE.

5. Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus is tri-stated, PDIR

is set and the nWRITE signal is valid.

6. Peripheral drives PData bus valid.

7. Peripheral deasserts nWAIT, indicating that

PData is valid and the chip may begin the

termination phase of the cycle.

8. a) The chip latches the data from the

PData bus for the SData bus and

deasserts nDATASTB or nADDRSTRB.

This marks the beginning of the

termination phase.

b) The chip latches the data from the

SData bus for the PData bus and

asserts (releases) IOCHRDY allowing

the host to complete the write cycle.

8. Peripheral asserts nWAIT, indicating to the

host that any hold time requirements have

been satisfied and acknowledging the

termination of the cycle.

9. Chip may modify nWRITE and nPDATA in

preparation for the next cycle.

b) The chip drives the valid data onto the

SData bus and asserts (releases)

IOCHRDY allowing the host to

complete the read cycle.

EPP 1.9 Read

The timing for a read operation (data) is shown

in timing diagram EPP Read Data cycle.

IOCHRDY is driven active low at the start of

each EPP read and is released when it has been

determined that the read cycle can complete.

The read cycle can complete under the following

circumstances:

9. Peripheral tri-states the PData bus and

asserts nWAIT, indicating to the host that

the PData bus is tri-stated.

10. Chip may modify nWRITE, PDIR and

nPDATA in preparation for the next cycle.

91

Write Sequence of Operation

EPP 1.7 OPERATION

1. The host sets PDIR bit in the control

When the EPP 1.7 mode is selected in the

configuration register, the standard and bi-

directional modes are also available. If no EPP

Read, Write or Address cycle is currently

executing, then the PDx bus is in the standard or

bi-directional mode, and all output signals

(STROBE, AUTOFD, INIT) are as set by the

SPP Control Port and direction is controlled by

PCD of the Control port.

register to a logic "0".

nWRITE.

This asserts

2. The host selects an EPP register, places

data on the SData bus and drives nIOW

active.

3. The chip places address or data on PData

bus.

4. Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus contains valid

information, and the WRITE signal is valid.

5. If nWAIT is asserted, IOCHRDY is

deasserted until the peripheral deasserts

nWAIT or a time-out occurs.

6. When the host deasserts nIOW the chip

deasserts nDATASTB or nADDRSTRB and

latches the data from the SData bus for the

PData bus.

In EPP mode, the system timing is closely

coupled to the EPP timing. For this reason, a

watchdog timer is required to prevent system

lockup. The timer indicates if more than 10

msec have elapsed from the start of the EPP

cycle (nIOR or nIOW asserted) to the end of the

cycle nIOR or nIOW deasserted). If a time-out

occurs, the current EPP cycle is aborted and the

time-out condition is indicated in Status bit 0.

7. Chip may modify nWRITE, PDIR and

nPDATA in preparation of the next cycle.

Software Constraints

EPP 1.7 Read

Before an EPP cycle is executed, the software

must ensure that the control register bits D0, D1

and D3 are set to zero. Also, bit D5 (PCD) is a

logic "0" for an EPP write or a logic "1" for and

EPP read.

The timing for a read operation (data) is shown

in timing diagram EPP 1.7 Read Data cycle.

IOCHRDY is driven active low when nWAIT is

active low during the EPP cycle. This can be

used to extend the cycle time. The read cycle

can complete when nWAIT is inactive high.

EPP 1.7 Write

Read Sequence of Operation

The timing for a write operation (address or

data) is shown in timing diagram EPP 1.7 Write

Data or Address cycle. IOCHRDY is driven

active low when nWAIT is active low during the

EPP cycle. This can be used to extend the cycle

1. The host sets PDIR bit in the control

register to a logic "1". This deasserts

nWRITE and tri-states the PData bus.

2. The host selects an EPP register and drives

nIOR active.

time.

The write cycle can complete when

nWAIT is inactive high.

3. Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus is tri-stated, PDIR

is set and the nWRITE signal is valid.

4. If nWAIT is asserted, IOCHRDY is

deasserted until the peripheral deasserts

nWAIT or a time-out occurs.

5. The Peripheral drives PData bus valid.

92

6. The Peripheral deasserts nWAIT, indicating

that PData is valid and the chip may begin

the termination phase of the cycle.

8. Peripheral tri-states the PData bus.

9. Chip may modify nWRITE, PDIR and

nPDATA in preparation of the next cycle.

7. When the host deasserts nIOR the chip

deasserts nDATASTB or nADDRSTRB.

93

Table 37 - EPP Pin Descriptions

EPP

SIGNAL

EPP NAME

nWrite

TYPE

EPP DESCRIPTION

This signal is active low. It denotes a write operation.

nWRITE

PD<0:7>

INTR

O

Address/Data

Interrupt

I/O

I

Bi-directional EPP byte wide address and data bus.

This signal is active high and positive edge triggered. (Pass

through with no inversion, Same as SPP.)

WAIT

nWait

I

This signal is active low. It is driven inactive as a positive

acknowledgement from the device that the transfer of data

is completed. It is driven active as an indication that the

device is ready for the next transfer.

DATASTB nData Strobe

RESET nReset

O

This signal is active low. It is used to denote data read or

write operation.

This signal is active low.

When driven active, the EPP

device is reset to its initial operational mode.

ADDRSTB nAddress

Strobe

This signal is active low. It is used to denote address read

or write operation.

PE

Paper End

I

Same as SPP mode.

SLCT

Printer

Selected

Status

nERR

PDIR

Error

I

Same as SPP mode.

Parallel Port

Direction

O

This output shows the direction of the data transfer on the

parallel port bus. A low means an output/write condition and

a high means an input/read condition. This signal is

normally a low (output/write) unless PCD of the control

register is set or if an EPP read cycle is in progress.

Note 1: SPP and EPP can use one common register.

Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP

cycle. For correct EPP read cycles, PCD is required to be a low.

94

reverse: Peripheral to Host communication

EXTENDED CAPABILITIES PARALLEL PORT

Pword:

A port word; equal in size to

the

width of the ISA interface. For this

implementation, PWord is always 8

bits.

A high level.

A low level.

ECP provides a number of advantages, some of

which are listed below. The individual features

are explained in greater detail in the remainder

of this section.

1

0

·

High performance half-duplex forward and

reverse channel

Interlocked handshake, for fast reliable

transfer

Optional single byte RLE compression for

improved throughput (64:1)

Channel addressing for low-cost peripherals

Maintains link and data layer separation

Permits the use of active output drivers

Permits the use of adaptive signal timing

Peer-to-peer capability

These terms may be considered synonymous:

·

PeriphClk, nAck

HostAck, nAutoFd

PeriphAck, Busy

nPeriphRequest, nFault

nReverseRequest, nInit

nAckReverse, PError

Xflag, Select

ECPMode, nSelectln

HostClk, nStrobe

·

Vocabulary

Reference Document:

The following terms are used in this document:

IEEE 1284 Extended Capabilities Port Protocol

and ISA Interface Standard, Rev 1.14, July 14,

assert:

When a signal asserts it transitions

to a "true" state, when a signal

deasserts it transitions to a "false"

state.

1993.

This document is available from

Microsoft.

The bit map of the Extended Parallel Port

registers is shown in the table on the following

page.

forward: Host to Peripheral communication.

95

D7

PD7

D6

D5

D4

D3

D2

D1

D0

Note

data

PD6

PD5

PD4

PD3

PD2

PD1

PD0

ecpAFifo

dsr

Addr/RLE

nBusy

0

Address or RLE field

2

1

2

nAck

0

PError

Select

nFault

ackIntEn SelectIn

Parallel Port Data FIFO

ECP Data FIFO

0

dcr

Direction

nInit

autofd

strobe

cFifo

ecpDFifo

tFifo

Test FIFO

cnfgA

cnfgB

ecr

0

1

0

compress

intrValue

MODE

Parallel Port IRQ

nErrIntrEn dmaEn

Parallel Port DMA

serviceIntr full

empty

Note 1: These registers are available in all modes.

Note 2: All FIFOs use one common 16 byte FIFO.

Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration

Registers.

It does not do any "protocol" negotiation, rather

it provides an automatic high burst-bandwidth

channel that supports DMA for ECP in both the

forward and reverse directions.

ISA IMPLEMENTATION STANDARD

This specification describes the standard ISA

interface to the Extended Capabilities Port

(ECP). All ISA devices supporting ECP must

meet the requirements contained in this section

or the port will not be supported by Microsoft.

For a description of the ECP Protocol, please

refer to the IEEE 1284 Extended Capabilities

Port Protocol and ISA Interface Standard, Rev.

1.14, July 14, 1993. This document is available

from Microsoft.

Small FIFOs are employed in both forward and

reverse directions to smooth data flow and

improve the maximum bandwidth requirement.

The size of the FIFO is 16 bytes deep. The port

supports an automatic handshake for the

standard parallel port to improve compatibility

mode transfer speed.

The port also supports run length encoded

(RLE) decompression (required) in hardware.

Compression is accomplished by counting

identical bytes and transmitting an RLE byte

that indicates how many times the next byte is

to be repeated. Decompression simply

intercepts the RLE byte and repeats the

following byte the specified number of times.

Hardware support for compression is optional.

Description

The port is software and hardware compatible

with existing parallel ports so that it may be

used as a standard LPT port if ECP is not

required. The port is designed to be simple and

requires a small number of gates to implement.

96

Table 38 - ECP Pin Descriptions

DESCRIPTION

NAME

nStrobe

TYPE

O

During write operations nStrobe registers data or address into the slave

on the asserting edge (handshakes with Busy).

PData 7:0

nAck

I/O

I

Contains address or data or RLE data.

Indicates valid data driven by the peripheral when asserted. This signal

handshakes with nAutoFd in reverse.

PeriphAck (Busy)

I

This signal deasserts to indicate that the peripheral can accept data.

This signal handshakes with nStrobe in the forward direction. In the

reverse direction this signal indicates whether the data lines contain

ECP command information or data. The peripheral uses this signal to

flow control in the forward direction. It is an "interlocked" handshake

with nStrobe. PeriphAck also provides command information in the

reverse direction.

PError

Used to acknowledge a change in the direction the transfer (asserted =

(nAckReverse)

forward).

nReverseRequest.

The peripheral drives this signal low to acknowledge

It is an "interlocked" handshake with

nReverseRequest. The host relies upon nAckReverse to determine

when it is permitted to drive the data bus.

Select

I

Indicates printer on line.

nAutoFd

O

Requests a byte of data from the peripheral when asserted,

(HostAck)

handshaking with nAck in the reverse direction. In the forward direction

this signal indicates whether the data lines contain ECP address or

data. The host drives this signal to flow control in the reverse direction.

It is an "interlocked" handshake with nAck. HostAck also provides

command information in the forward phase.

nFault

(nPeriphRequest)

I

Generates an error interrupt when asserted. This signal provides a

mechanism for peer-to-peer communication. This signal is valid only in

the forward direction. During ECP Mode the peripheral is permitted

(but not required) to drive this pin low to request a reverse transfer. The

request is merely a "hint" to the host; the host has ultimate control over

the transfer direction. This signal would be typically used to generate

an interrupt to the host CPU.

nInit

O

Sets the transfer direction (asserted = reverse, deasserted = forward).

This pin is driven low to place the channel in the reverse direction. The

peripheral is only allowed to drive the bi-directional data bus while in

ECP Mode and HostAck is low and nSelectIn is high.

nSelectIn

Always deasserted in ECP mode.

97

to avoid conflict with standard ISA devices. The

port is equivalent to a generic parallel port

interface and may be operated in that mode.

The port registers vary depending on the mode

field in the ecr. The table below lists these

dependencies. Operation of the devices in

modes other that those specified is undefined.

Register Definitions

The register definitions are based on the

standard IBM addresses for LPT. All of the

standard printer ports are supported.

additional registers attach to an upper bit

decode of the standard LPT port definition

The

Table 39 - ECP Register Definitions

ADDRESS (Note 1) ECP MODES

NAME

FUNCTION

Data Register

data

+000h R/W

+001h R/W

+002h R/W

+400h R/W

+400h R

000-001

011

All

ecpAFifo

dsr

ECP FIFO (Address)

Status Register

dcr

All

Control Register

cFifo

ecpDFifo

tFifo

010

011

110

111

All

Parallel Port Data FIFO

ECP FIFO (DATA)

Test FIFO

cnfgA

cnfgB

ecr

Configuration Register A

Configuration Register B

Extended Control Register

+401h R/W

+402h R/W

Note 1: These addresses are added to the parallel port base address as selected by configuration

register or jumpers.

Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.

Table 40 - Mode Descriptions

MODE

000

001

010

011

100

101

110

111

DESCRIPTION*

SPP mode

PS/2 Parallel Port mde

Parallel Port Data FIFO mode

ECP Parallel Port mode

EPP mode (If this option is enabled in the configuration registers)

(Reserved)

Test mode

Configuration mode

*Refer to ECR Register Description

98

DATA and ecpAFifo PORT

ADDRESS OFFSET = 00H

BIT 4 Select

The level on the Select input is read by the CPU

as bit 4 of the Device Status Register.

Modes 000 and 001 (Data Port)

BIT 5 PError

The Data Port is located at an offset of '00H'

from the base address. The data register is

cleared at initialization by RESET. During a

WRITE operation, the Data Register latches the

contents of the data bus on the rising edge of

the nIOW input. The contents of this register

are buffered (non inverting) and output onto the

PD0-PD7 ports. During a READ operation,

PD0-PD7 ports are read and output to the host

CPU.

The level on the PError input is read by the CPU

as bit 5 of the Device Status Register. Printer

Status Register.

BIT 6 nAck

The level on the nAck input is read by the CPU

as bit 6 of the Device Status Register.

BIT 7 nBusy

The complement of the level on the BUSY input

is read by the CPU as bit 7 of the Device Status

Register.

Mode 011 (ECP FIFO - Address/RLE)

A data byte written to this address is placed in

the FIFO and tagged as an ECP Address/RLE.

The hardware at the ECP port transmits this

byte to the peripheral automatically. The

operation of this register is ony defined for the

forward direction (direction is 0). Refer to the

ECP Parallel Port Forward Timing Diagram,

located in the Timing Diagrams section of this

data sheet.

DEVICE CONTROL REGISTER (dcr)

ADDRESS OFFSET = 02H

The Control Register is located at an offset of

'02H' from the base address. The Control

Register is initialized to zero by the RESET

input, bits 0 to 5 only being affected; bits 6 and

7 are hard wired low.

BIT 0 STROBE - STROBE

This bit is inverted and output onto the

nSTROBE output.

DEVICE STATUS REGISTER (dsr)

ADDRESS OFFSET = 01H

The Status Port is located at an offset of '01H'

BIT 1 AUTOFD - AUTOFEED

from the base address.

Bits 0-2 are not

This bit is inverted and output onto the

nAUTOFD output. A logic 1 causes the printer

to generate a line feed after each line is printed.

A logic 0 means no autofeed.

implemented as register bits, during a read of

the Printer Status Register these bits are a low

level. The bits of the Status Port are defined as

follows:

BIT 2 nINIT - nINITIATE OUTPUT

This bit is output onto the nINIT output without

inversion.

BIT 3 nFault

The level on the nFault input is read by the CPU

as bit 3 of the Device Status Register.

BIT 3 SELECTIN

This bit is inverted and output onto the nSLCTIN

output. A logic 1 on this bit selects the printer; a

logic 0 means the printer is not selected.

99

Data bytes from the peripheral are read under

automatic hardware handshake from ECP into

this FIFO when the direction bit is 1. Reads or

DMAs from the FIFO will return bytes of ECP

data to the system.

BIT 4 ackIntEn - INTERRUPT REQUEST

ENABLE

The interrupt request enable bit when set to a

high level may be used to enable interrupt

requests from the Parallel Port to the CPU due

to a low to high transition on the nACK input.

Refer to the description of the interrupt under

Operation, Interrupts.

tFifo (Test FIFO Mode)

ADDRESS OFFSET = 400H

Mode = 110

BIT 5 DIRECTION

Data bytes may be read, written or DMAed to or

from the system to this FIFO in any direction.

If mode=000 or mode=010, this bit has no effect

and the direction is always out regardless of the

state of this bit. In all other modes, Direction is

valid and a logic 0 means that the printer port is

in output mode (write); a logic 1 means that the

printer port is in input mode (read).

Data in the tFIFO will not be transmitted to the

parallel port lines using a hardware protocol

handshake. However, data in the tFIFO may be

displayed on the parallel port data lines.

The tFIFO will not stall when overwritten or

underrun. If an attempt is made to write data to

a full tFIFO, the new data is not accepted into

the tFIFO. If an attempt is made to read data

from an empty tFIFO, the last data byte is re-

read again. The full and empty bits must

always keep track of the correct FIFO state. The

tFIFO will transfer data at the maximum ISA

rate so that software may generate performance

metrics.

BITS 6 and 7 during a read are a low level, and

cannot be written.

cFifo (Parallel Port Data FIFO)

ADDRESS OFFSET = 400h

Mode = 010

Bytes written or DMAed from the system to this

FIFO are transmitted by a hardware handshake

to the peripheral using the standard parallel port

protocol.

Transfers to the FIFO are byte

The FIFO size and interrupt threshold can be

determined by writing bytes to the FIFO and

checking the full and serviceIntr bits.

aligned. This mode is only defined for the

forward direction.

ecpDFifo (ECP Data FIFO)

ADDRESS OFFSET = 400H

Mode = 011

The writeIntrThreshold can be determined by

starting with a full tFIFO, setting the direction bit

to 0 and emptying it a byte at a time until

serviceIntr is set. This may generate a spurious

interrupt, but will indicate that the threshold has

been reached.

Bytes written or DMAed from the system to this

FIFO, when the direction bit is 0, are transmitted

by a hardware handshake to the peripheral

using the ECP parallel port protocol. Transfers

to the FIFO are byte aligned.

The readIntrThreshold can be determined by

setting the direction bit to 1 and filling the empty

tFIFO a byte at a time until serviceIntr is set.

This may generate a spurious interrupt, but will

indicate that the threshold has been reached.

100

Data bytes are always read from the head of

tFIFO regardless of the value of the direction bit.

For example if 44h, 33h, 22h are written to the

FIFO, then reading the tFIFO will return 44h,

33h, 22h in the same order as was written.

BITS 7 - 5

These bits are Read/Write and select the Mode.

BIT 4 nErrIntrEn

Read/Write (Valid only in ECP Mode)

1: Disables the interrupt generated on the

asserting edge of nFault.

0: Enables an interrupt pulse on the high to

low edge of nFault. Note that an interrupt

will be generated if nFault is asserted

(interrupting) and this bit is written from a

“1” to a “0”. This prevents interrupts from

being lost in the time between the read of

the ecr and the write of the ecr.

cnfgA (Configuration Register A)

ADDRESS OFFSET = 400H

Mode = 111

This register is a read-only register. When read,

10H is returned. This indicates to the system

that this is an 8-bit implementation. (PWord = 1

byte)

BIT 3 dmaEn

Read/Write

1: Enables DMA (DMA starts when serviceIntr

is 0).

cnfgB (Configuration Register B)

ADDRESS OFFSET = 401H

Mode = 111

0: Disables DMA unconditionally.

BIT 7 compress

This bit is read only. During a read it is a low

level. This means that this chip does not

support hardware RLE compression. It does

support hardware de-compression!

BIT 2 serviceIntr

Read/Write

1: Disables DMA and all of the service

interrupts.

0: Enables one of the following three cases of

interrupts. Once one of the three service

interrupts has occurred serviceIntr bit shall

be set to a “1” by hardware. It must be reset

to “0” to re-enable the interrupts. Writing

this bit to a “1” will not cause an interrupt.

case dmaEn=1:

BIT 6 intrValue

Returns the value on the ISA IRQ line to

determine possible conflicts.

BITS 3 - 0 Parallel Port IRQ

Refer to Table 41B.

During DMA (this bit is set to a “1” when

terminal count is reached).

case dmaEn=0 direction=0:

BITS 2 - 0 Parallel Port DMA

Refer to Table 41C.

This bit shall be set to 1 whenever there are

writeIntrThreshold or more bytes free in the

FIFO.

ecr (Extended Control Register)

ADDRESS OFFSET = 402H

Mode = all

case dmaEn=0 direction=1:

This bit shall be set to 1 whenever there are

readIntrThreshold or more valid bytes to be

read from the FIFO.

This register controls the extended ECP parallel

port functions.

101

BIT 1 full

BIT 0 empty

Read only

1: The FIFO cannot accept another byte or the

FIFO is completely full.

1: The FIFO is completely empty.

0: The FIFO contains at least one byte of data.

0: The FIFO has at least one free byte.

102

Table 41A - Extended Control Register

MODE

R/W

000: Standard Parallel Port Mode. In this mode the FIFO is reset and common collector drivers

are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction

bit will not tri-state the output drivers in this mode.

001: PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the

data lines and reading the data register returns the value on the data lines and not the

value in the data register. All drivers have active pull-ups (push-pull).

010: Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to

the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol.

Note that this mode is only useful when direction is 0. All drivers have active pull-ups

(push-pull).

011: ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the

ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted

automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1)

bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All

drivers have active pull-ups (push-pull).

100: Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in

configuration register L3-CRF0. All drivers have active pull-ups (push-pull).

101: Reserved

110: Test Mode. In this mode the FIFO may be written and read, but the data will not be

transmitted on the parallel port. All drivers have active pull-ups (push-pull).

111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and

0x401. All drivers have active pull-ups (push-pull).

Table 41B

CONFIG REG B

Table 41C

CONFIG REG B

IRQ SELECTED

BITS 5:3

BITS 2:0

DMA SELECTED

15

110

101

100

011

010

001

111

000

3

011

010

001

000

14

2

1

11

10

All Others

9

7

5

All Others

103

After negotiation, it is necessary to initialize

some of the port bits. The following are required:

OPERATION

Mode Switching/Software Control

·

Set Direction = 0, enabling the drivers.

Set strobe = 0, causing the nStrobe signal

to default to the deasserted state.

Set autoFd = 0, causing the nAutoFd

signal to default to the deasserted state.

Set mode = 011 (ECP Mode)

Software will execute P1284 negotiation and all

operation prior to a data transfer phase under

programmed I/O control (mode 000 or 001).

Hardware provides an automatic control line

handshake, moving data between the FIFO and

the ECP port only in the data transfer phase

(modes 011 or 010).

·

ECP address/RLE bytes or data bytes may be

sent automatically by writing the ecpAFifo or

ecpDFifo respectively.

Setting the mode to 011 or 010 will cause the

hardware to initiate data transfer.

Note that all FIFO data transfers are byte wide

and byte aligned. Address/RLE transfers are

byte-wide and only allowed in the forward

direction.

If the port is in mode 000 or 001 it may switch to

any other mode. If the port is not in mode 000

or 001 it can only be switched into mode 000 or

001. The direction can only be changed in

mode 001.

The host may switch directions by first switching

to mode = 001, negotiating for the forward or

Once in an extended forward mode the software

should wait for the FIFO to be empty before

switching back to mode 000 or 001. In this case

all control signals will be deasserted before the

mode switch. In an ecp reverse mode the

software waits for all the data to be read from

the FIFO before changing back to mode 000 or

001. Since the automatic hardware ecp reverse

handshake only cares about the state of the

FIFO it may have acquired extra data which will

be discarded. It may in fact be in the middle of a

transfer when the mode is changed back to 000

or 001. In this case the port will deassert

nAutoFd independent of the state of the transfer.

The design shall not cause glitches on the

handshake signals if the software meets the

constraints above.

reverse channel, setting

direction to 1 or 0,

then setting mode = 011. When direction is 1

the hardware shall handshake for each ECP

read data byte and attempt to fill the FIFO.

Bytes may then be read from the ecpDFifo as

long as it is not empty.

ECP transfers may also be accomplished (albeit

slowly) by handshaking individual bytes under

program control in mode = 001, or 000.

Termination from ECP Mode

Termination from ECP Mode is similar to the

termination from Nibble/Byte Modes. The host is

permitted to terminate from ECP Mode only in

specific well-defined states. The termination can

only be executed while the bus is in the forward

direction. To terminate while the channel is in

the reverse direction, it must first be transitioned

into the forward direction.

ECP Operation

Prior to ECP operation the Host must negotiate

on the parallel port to determine if the peripheral

supports the ECP protocol. This is a somewhat

complex negotiation carried out under program

control in mode 000.

104

is not supported. To transfer compressed data

in ECP mode, the compression count is written

to the ecpAFifo and the data byte is written to

the ecpDFifo.

Command/Data

ECP Mode supports two advanced features to

improve the effectiveness of the protocol for

some

applications.

The

features

are

Compression is accomplished by counting

identical bytes and transmitting an RLE byte

that indicates how many times the next byte is

to be repeated. Decompression simply

intercepts the RLE byte and repeats the

following byte the specified number of times.

When a run-length count is received from a

peripheral, the subsequent data byte is

replicated the specified number of times. A

run-length count of zero specifies that only one

byte of data is represented by the next data

implemented by allowing the transfer of normal

8-bit data or 8-bit commands.

When in the forward direction, normal data is

transferred when HostAck is high and an 8-bit

command is transferred when HostAck is low.

The most significant bit of the command

indicates whether it is a run-length count (for

compression) or a channel address.

byte, whereas a run-length

count

of 127

When in the reverse direction, normal data is

transferred when PeriphAck is high and an 8-bit

command is transferred when PeriphAck is low.

The most significant bit of the command is

always zero. Reverse channel addresses are

seldom used and may not be supported in

hardware.

indicates that the next byte should be expanded

to 128 bytes. To prevent data expansion,

however, run-length counts of zero should be

avoided.

Pin Definition

The drivers for nStrobe, nAutoFd, nInit and

nSelectIn are open-collector in mode 000 and

are push-pull in all other modes.

Table 42

Forward Channel Commands (HostAck Low)

Reverse Channel Commands (PeripAck Low)

D7

D[6:0]

ISA Connections

0

Run-Length Count (0-127)

(mode 0011 0X00 only)

The interface can never stall causing the host to

hang. The width of data transfers is strictly

controlled on an I/O address basis per this

specification. All FIFO-DMA transfers are byte

wide, byte aligned and end on a byte boundary.

(The PWord value can be obtained by reading

Configuration Register A, cnfgA, described in

the next section.) Single byte wide transfers

are always possible with standard or PS/2 mode

using program control of the control signals.

1

Channel Address (0-127)

Data Compression

The ECP port supports run length encoded

(RLE) decompression in hardware and can

transfer compressed data to a peripheral. Run

length encoded (RLE) compression in hardware

105

readIntrThreshold or more

bytes in the FIFO. Also, an

interrupt is generated when

Interrupts

The interrupts are enabled by serviceIntr in the

ecr register.

serviceIntr is cleared to

whenever there

0

are

readIntrThreshold or more

bytes in the FIFO.

serviceIntr = 1 Disables the DMA and all of the

service interrupts.

3. When nErrIntrEn is 0 and nFault transitions

from high to low or when nErrIntrEn is set

from 1 to 0 and nFault is asserted.

serviceIntr = 0 Enables the selected interrupt

condition. If the interrupting

condition is valid, then the

interrupt

is

generated

4. When ackIntEn is 1 and the nAck signal

transitions from a low to a high.

immediately when this bit is

changed from a 1 to a 0. This

can occur during Programmed

I/O if the number of bytes

removed or added from/to the

FIFO does not cross the

threshold.

FIFO Operation

The FIFO threshold is set in the chip

configuration registers. All data transfers to or

from the parallel port can proceed in DMA or

Programmed I/O (non-DMA) mode as indicated

by the selected mode. The FIFO is used by

selecting the Parallel Port FIFO mode or ECP

Parallel Port Mode. (FIFO test mode will be

addressed separately.) After a reset, the FIFO

is disabled. Each data byte is transferred by a

Programmed I/O cycle or PDRQ depending on

the selection of DMA or Programmed I/O mode.

The interrupt generated is ISA friendly in that it

must pulse the interrupt line low, allowing for

interrupt sharing.

After a brief pulse low

following the interrupt event, the interrupt line is

tri-stated so that other interrupts may assert.

An interrupt is generated when:

1. For DMA transfers: When serviceIntr is 0,

dmaEn is 1 and the DMA TC is received.

The following paragraphs detail the operation of

the FIFO flow control. In these descriptions,

2. For Programmed I/O:

<threshold> ranges from

1

to 16.

The

a.

When serviceIntr is 0, dmaEn is 0,

direction is and there are

writeIntrThreshold or more free bytes in

the FIFO. Also, an interrupt is

generated when serviceIntr is cleared

to whenever there are

parameter FIFOTHR, which the user programs,

is one less and ranges from 0 to 15.

0

A low threshold value (i.e. 2) results in longer

periods of time between service requests, but

requires faster servicing of the request for both

read and write cases. The host must be very

responsive to the service request. This is the

0

writeIntrThreshold or more free bytes in

the FIFO.

b.

(1) When serviceIntr is 0, dmaEn is

0, direction is 1 and there are

desired case for use with a "fast" system.

A

high value of threshold (i.e. 12) is used with a

"sluggish" system by affording a long latency

period after a service request, but results in

more frequent service requests.

106

DMA TRANSFERS

DMA Mode - Transfers from the FIFO to the

Host

DMA transfers are always to or from the

ecpDFifo, tFifo or CFifo. DMA utilizes the

standard PC DMA services. To use the DMA

transfers, the host first sets up the direction and

state as in the programmed I/O case. Then it

programs the DMA controller in the host with the

desired count and memory address. Lastly it

sets dmaEn to 1 and serviceIntr to 0. The ECP

requests DMA transfers from the host by

activating the PDRQ pin. The DMA will empty

or fill the FIFO using the appropriate direction

and mode. When the terminal count in the DMA

controller is reached, an interrupt is generated

and serviceIntr is asserted, disabling DMA. In

order to prevent possible blocking of refresh

requests dReq shall not be asserted for more

than 32 DMA cycles in a row. The FIFO is

enabled directly by asserting nPDACK and

addresses need not be valid. PINTR is

generated when a TC is received. PDRQ must

not be asserted for more than 32 DMA cycles in

a row. After the 32nd cycle, PDRQ must be

kept unasserted until nPDACK is deasserted for

a minimum of 350nsec. (Note: The only way to

properly terminate DMA transfers is with a TC.)

(Note: In the reverse mode, the peripheral may

not continue to fill the FIFO if it runs out of data

to transfer, even if the chip continues to request

more data from the peripheral.)

The ECP activates the PDRQ pin whenever

there is data in the FIFO. The DMA controller

must respond to the request by reading data

from the FIFO. The ECP will deactivate the

PDRQ pin when the FIFO becomes empty or

when the TC becomes true (qualified by

nPDACK), indicating that no more data is

required. PDRQ goes inactive after nPDACK

goes active for the last byte of a data transfer

(or on the active edge of nIOR, on the last byte,

if no edge is present on nPDACK). If PDRQ

goes inactive due to the FIFO going empty, then

PDRQ is active again as soon as there is one

byte in the FIFO. If PDRQ goes inactive due to

the TC, then PDRQ is active again when there

is one byte in the FIFO, and serviceIntr has

been re-enabled. (Note: A data underrun may

occur if PDRQ is not removed in time to prevent

an unwanted cycle.)

DMA may be disabled in the middle of a transfer

by first disabling the host DMA controller. Then

setting serviceIntr to 1, followed by setting

dmaEn to 0, and waiting for the FIFO to

become empty or full. Restarting the DMA is

accomplished by enabling DMA in the host,

setting dmaEn to 1, followed by setting

serviceIntr to 0.

Programmed I/O Mode or Non-DMA Mode

The ECP or parallel port FIFOs may also be

operated using interrupt driven programmed I/O.

Software can determine the writeIntrThreshold,

readIntrThreshold, and FIFO depth by accessing

the FIFO in Test Mode.

Programmed I/O transfers are to the ecpDFifo

at 400H and ecpAFifo at 000H or from the

ecpDFifo located at 400H, or to/from the tFifo at

400H. To use the programmed I/O transfers,

the host first sets up the direction and state, sets

dmaEn to 0 and serviceIntr to 0.

107

The ECP requests programmed I/O transfers

from the host by activating the PINTR pin. The

programmed I/O will empty or fill the FIFO using

the appropriate direction and mode.

the FIFO. If at this time the FIFO is full, it can

be completely emptied in single burst,

otherwise a minimum of (16-<threshold>) bytes

may be read from the FIFO in a single burst.

a

Note: A threshold of 16 is equivalent to a

threshold of 15. These two cases are treated

the same.

Programmed I/O - Transfers from the Host to

the FIFO

In the forward direction an interrupt occurs when

serviceIntr is 0 and there are writeIntrThreshold

or more bytes free in the FIFO. At this time if

the FIFO is empty it can be filled with a single

burst before the empty bit needs to be re-read.

Programmed I/O - Transfers from the FIFO to

the Host

In the reverse direction an interrupt occurs when

serviceIntr is 0 and readIntrThreshold bytes

are available in the FIFO. If at this time the

FIFO is full it can be emptied completely in a

single burst, otherwise readIntrThreshold bytes

may be read from the FIFO in a single burst.

Otherwise

it

may

be

filled

with

writeIntrThreshold bytes.

writeIntrThreshold = (16-<threshold>) free

bytes in FIFO

readIntrThreshold

=

(16-<threshold>)

data bytes in FIFO

An interrupt is generated when serviceIntr is 0

and the number of bytes in the FIFO is less than

or equal to <threshold>. (If the threshold = 12,

then the interrupt is set whenever there are 12 or

less bytes of data in the FIFO.) The PINT pin

can be used for interrupt-driven systems. The

host must respond to the request by writing data

to the FIFO. If at this time the FIFO is empty, it

can be completely filled in a single burst,

otherwise a minimum of (16-<threshold>) bytes

may be written to the FIFO in a single burst.

This process is repeated until the last byte is

transferred into the FIFO.

An interrupt is generated when serviceIntr is 0

and the number of bytes in the FIFO is greater

than or equal to (16-<threshold>). (If the

threshold

= 12, then the interrupt is set

whenever there are 4-16 bytes in the FIFO). The

PINT pin can be used for interrupt-driven

systems. The host must respond to the request

by reading data from the FIFO. This process is

repeated until the last byte is transferred out of

108

PARALLEL PORT FLOPPY DISK CONTROLLER

The following parallel port pins are read as

In this mode, the Floppy Disk Control signals

are available on the parallel port pins. When

this mode is selected, the parallel port is not

available. There are two modes of operation,

PPFD1 and PPFD2. These modes can be

selected in the Parallel Port Mode Register, as

defined in the Parallel Port Mode Register,

Logical Device 3, at 0xF1. PPFD1 has only

drive 1 on the parallel port pins; PPFD2 has

drive 0 and 1 on the parallel port pins.

follows by a read of the parallel port register:

1. Data Register (read) = last Data Register

(write)

2. Control Register read as "cable not

connected" STROBE, AUTOFD and SLC =

0 and nINIT =1

3. Status Register reads: nBUSY = 0, PE = 0,

SLCT = 0, nACK = 1, nERR = 1.

The following FDC pins are all in the high

impedence state when the PPFDC is actually

selected by the drive select register:

When the PPFDC is selected the following pins

are set as follows:

1. nPDACK: high-Z

2. PDRQ: not ECP = high-Z, ECP & dmaEn =

0, ECP & not dmaEn = high-Z

3. PINTR: not active, this is hi-Z or Low

depending on settings.

1. nWDATA, DENSEL, nHDSEL, nWGATE,

nDIR, nSTEP, nDS1, nDS0, nMTR0,

nMTR1.

2. If PPFDx is selected, then the parallel port

can not be used as a parallel port until

"Normal" mode is selected.

Note:

nPDACK, PDRQ and PINTR refer to

the nDACK, DRQ and IRQ chosen

for the parallel port.

The FDC signals are muxed onto the Parallel

Port pins as shown in Table 43.

109

Table 43 - FDC Parallel Port Pins

CONNECTOR

PIN #

CHIP PIN #

SPP MODE

FDC MODE

PIN DIRECTION

1

2

144

138

137

136

135

134

133

132

131

129

128

127

126

143

142

141

140

nSTB

PD0

I/O

I

(nDS0)

nINDEX

nTRK0

I/(O) (Note1)

I

3

PD1

I

4

PD2

nWP

I

5

PD3

nRDATA

nDSKCHG

nMEDIA_ID0

(nMTR0)

MEDIA_ID1

nDS1

I

6

PD4

I

7

PD5

I

8

PD6

I/(O) (Note1)

9

PD7

I

10

11

12

13

14

15

16

17

nACK

BUSY

PE

O

I

nMTR1

I

nWDATA

nWGATE

DRVDEN0

nHDSEL

nDIR

SLCT

nALF

nERROR

nINIT

nSLCTIN

I

I/O

I

I/O

nSTEP

Note 1: These pins are outputs in mode PPFD2, inputs in mode PPFD1.

110

AUTO POWER MANAGEMENT

Power management capabilities are provided for

DSR From Powerdown

the following logical devices: floppy disk, UART

1, UART 2 and the parallel port. For each

logical device, two types of power management

are provided; direct powerdown and auto

powerdown.

If DSR powerdown is used when the part is in

auto powerdown, the DSR powerdown will

override the auto powerdown. However, when

the part is awakened from DSR powerdown, the

auto powerdown will once again become

effective.

FDC Power Management

Direct power management is controlled by

CR22. Refer to CR22 for more information.

Wake Up From Auto Powerdown

If the part enters the powerdown state through

the auto powerdown mode, then the part can be

awakened by reset or by appropriate access to

certain registers.

Auto Power Management is enabled by CR23-

B0. When set, this bit allows FDC to enter

powerdown when all of the following conditions

have been met:

If a hardware or software reset is used then the

part will go through the normal reset sequence.

If the access is through the selected registers,

then the FDC resumes operation as though it

was never in powerdown. Besides activating the

RESET pin or one of the software reset bits in

the DOR or DSR, the following register

accesses will wake up the part:

1. The motor enable pins of register 3F2H are

inactive (zero).

2. The part must be idle; MSR=80H and INT =

0 (INT may be high even if MSR = 80H due

to polling interrupts).

3. The head unload timer must have expired.

4. The auto powerdown timer (10msec) must

have timed out.

1. Enabling any one of the motor enable bits

in the DOR register (reading the DOR does

not awaken the part).

2. A read from the MSR register.

3. A read or write to the data register.

An internal timer is initiated as soon as the auto

powerdown command is enabled. The part is

then powered down when all the conditions are

met.

Disabling the auto powerdown mode cancels the

timer and holds the FDC block out of auto

powerdown.

Once awake, the FDC will reinitiate the auto

powerdown timer for 10 ms. The part will

powerdown again when all the powerdown

conditions are satisfied.

111

Register Behavior

Pin Behavior

Table 44 reiterates the AT and PS/2 (including

Model 30) configuration registers available. It

also shows the type of access permitted. In

order to maintain software transparency, access

to all the registers must be maintained. As Table

44 shows, two sets of registers are distinguished

based on whether their access results in the part

remaining in powerdown state or exiting it.

The FDC37C93xAPM is specifically designed for

portable PC systems in which power

conservation is a primary concern. This makes

the behavior of the pins during powerdown very

important.

The pins of the FDC37C93xAPM can be divided

into two major categories: system interface and

floppy disk drive interface. The floppy disk drive

pins are disabled so that no power will be drawn

through the part as a result of any voltage

applied to the pin within the part's power supply

range. Most of the system interface pins are left

active to monitor system accesses that may

wake up the part.

Access to all other registers is possible without

awakening the part. These registers can be

accessed during powerdown without changing

the status of the part. A read from these

registers will reflect the true status as shown in

the register description in the FDC description.

A write to the part will result in the part retaining

the data and subsequently reflecting it when the

System Interface Pins

part awakens.

Accessing the part during

powerdown may cause an increase in the power

consumption by the part. The part will revert

back to its low power mode when the access

has been completed.

Table 45 gives the state of the system interface

pins in the powerdown state. Pins unaffected by

the powerdown are labeled "Unchanged". Input

pins are "Disabled" to prevent them from

causing

currents

internal

to

the

FDC37C93xAPM when they have indeterminate

input values.

112

Table 44 - PC/AT and PS/2 Available Registers

Available Registers

Base + Address

Access to these registers DOES NOT wake up the part

PC-AT

PS/2 (Model 30) Access Permitted

00H

01H

02H

03H

04H

06H

07H

----

SRA

SRB

R

DOR (1)

---

DOR (1)

---

R/W

---

W

DSR (1)

---

DSR (1)

---

R

DIR

CCR

W

Access to these registers wakes up the part

04H

05H

MSR

Data

MSR

Data

R

R/W

Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the

motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part.

Table 45 - State of System Pins in Auto Powerdown

SYSTEM PINS

STATE IN AUTO POWERDOWN

Input Pins

IOR

IOW

Unchanged

A[0:9]

D[0:7]

RESET

IDENT

DACKx

TC

Unchanged

Output Pins

Unchanged (low)

Unchanged

IRQx

DB[0:7]

DRQx

Unchanged (low)

113

FDD Interface Pins

Pins used for local logic control or part

programming are unaffected. Table 46 depicts

the state of the floppy disk drive interface pins in

the powerdown state.

All pins in the FDD interface which can be

connected directly to the floppy disk drive itself

are either DISABLED or TRISTATED.

Table 46 - State of Floppy Disk Drive Interface Pins in Powerdown

FDD PINS

STATE IN AUTO POWERDOWN

Input Pins

Input

RDATA

WP

Input

TRK0

Input

INDX

Input

DRV2

DSKCHG

Input

Output Pins

Tristated

Active

MOTEN[0:3]

DS[0:3]

DIR

STEP

Active

WRDATA

WE

Tristated

Active

HDSEL

DENSEL

DRATE[0:1]

Active

114

UART Power Management

Parallel Port

Direct power management is controlled by

CR22. Refer to CR22 for more information.

Direct power management is controlled by

CR22. Refer to CR22 for more information.

Auto Power Management is enabled by CR23-

B4 and B5. When set, these bits allow the

following auto power management operations:

Auto power management is enabled by CR23-

B3. When set, this bit allows the ECP or EPP

logical parallel port blocks to be placed into

powerdown when not being used.

1. The transmitter enters auto powerdown

when the transmit buffer and shift register

are empty.

The EPP logic is in powerdown under any of the

following conditions:

2. The receiver enters powerdown when the

following conditions are all met:

1. EPP is not enabled in the configuration

registers.

A. Receive FIFO is empty

B. The receiver is waiting for a start bit.

2. EPP is not selected through ecr while in

ECP mode.

Note: While in powerdown the Ring Indicator

interrupt is still valid and transitions when the

RI input changes.

The ECP logic is in powerdown under any of the

following conditions:

1. ECP is not enabled in the configuration

registers.

Exit Auto Powerdown

2

SPP, PS/2 Parallel port or EPP mode is

selected through ecr while in ECP mode.

The transmitter exits powerdown on a write to

the XMIT buffer.

The receiver exits auto

powerdown when RXDx changes state.

Exit Auto Powerdown

The parallel port logic can change powerdown

modes when the ECP mode is changed through

the ecr register or when the parallel port mode is

changed through the configuration registers.

115

INTEGRATED DRIVE ELECTRONICS INTERFACE

The FDC37C93xAPM contains two IDE the AT Task File, and the Miscellaneous AT

interfaces. This enables hard disks with

embedded controllers (AT or IDE) to be

Register.

interfaced to the host processor.

The IDE

ADDRESS 1F0H-1F7H; 170H-177H

interface performs the address decoding for the

IDE interface, generates the buffer enables for

external buffers and provides internal buffers for

the low byte IDE data transfers. For more

information, refer to the IDE pin descriptions

These AT registers contain the Task File

Registers. These registers communicate data,

command, and status information with the AT

host, and are addressed when nHCS0 or nHCS2

is low.

and the ATA specification.

The following

example uses IDE1 base1=1F0H, base2=3F6H

and IDE2 base1=170H, base2 =376H.

ADDRESS 3F6H/376H;

These AT registers may be used by the BIOS for

drive control. They are accessed by the AT

interface when nHCS1 or nHCS3 is active low.

HOST FILE REGISTERS

The Host File Registers are accessed by the AT

Host.

There are two groups of registers,

HOST PROCESSOR REGISTER ADDRESS MAP (AT MODE)

PRIMARY

1F0H

SECONDARY

170H

|

TASK FILE REGISTERS

MISC AT REGISTERS

1F7H

3F6H

177H

376H

and EATA specifications. These are available

from:

TASK FILE REGISTERS

Task File Registers may be accessed by the

host AT when pin nHDCS0 is active (low). The

Data Register (1F0H) is 16 bits wide; the

remaining task file registers are 8 bits wide. The

Global Engineering

2805 McGaw Street

Irvine, CA 92714

(800) 854-7179 or

(714) 261-1455

task file registers are

ATA

and EATA

compatible. Please refer to the ATA

116

IDE OUTPUT ENABLES

Two IDE output Enables are available. The IDE output enables treat all IDE transfers as 16 bit

transfers.

nIDE1_OE

IDE1 (1)

nIDE2_OE

IDE2 (2)

Option 1

Option 2

IDE1&IDE2 (3)

(Not used)

Note 1:

Note 2:

Note 3:

The low and high byte transfers for IDE1 goes through external buffers controlled by

IDE1_OE. (Refer to Option 1)

The low and high byte transfers for IDE2 goes through external buffers controlled by

IDE2_OE. (Refer to Option 1)

The low and high byte transfers of IDE1 and IDE2 go through one set of external buffers

controlled by IDE1. (Refer to Option 2)

configured to support IDE drives, can be

programmed as general purpose address

decoders. Refer to the Configuration Register

Section, Logical Device 1, CRF0 and CRF1.

HDCS0 and HDCS1 of IDE1 as General

Purpose Address Decoders

HDCS0 and HDCS1 of IDE1, initially

117

BIOS BUFFER

The FDC37C93xAPM contains one 245 type

This function allows data transmission from the

RD bus to the SD bus or from the SD bus to the

buffer that can be used for a BIOS Buffer. If the

BIOS buffer is not used, then nROMCS and

nROMDIR must be tied high so as not to

interfere with the boot ROM.

RD bus.

The direction of the transfer is

controlled by nROMDIR. The enable input,

nROMCS, can be used to disable the transfer

and isolate the buses.

nROMCS

nROMDIR

L

H

X

RD[0:7] data to SD[0:7] bus

SD[0:7] data to RD[0:7]

Isolation

H

SD[15:8]

IDE Channel 1

FDC37C93xAPM

SD[7:0]

IDE1_OE

B1

BIOS

Option 1

IDE2_OE

IDE Channel 2

FIGURE 2 - IDE OUTPUT ENABLE OPTION 1

118

SD[15:8]

IDE Channel 1

FDC37C93xAPM

SD[7:0]

IDE1_OE

B1

BIOS

Option 2

IDE2_OE

NC

IDE Channel 2

FIGURE 3 - IDE OUTPUT ENABLE OPTION 2

119

floats - cannot use as a bus. Any pin can be

programmed as an alternate function.

RD Bus Functionality

The following four cases described below

illustrate the use of the RD Bus.

Case 4: nROMCS and nROMOE as alternate

function. Same as Case 3.

Case 1: nROMCS and nROMOE as original

function. The RD bus can be used as the RD

bus or one or more RD pins can be

8042 Functions

programmed as alternate function.

These

The second alternate function for pins 113-118

are the 8042 functions P12-P17. These are

implemented as in a true 8042 part. Reference

the 8042 specification for all timing. A port

signal of 0 drives the output to 0. A port signal

of 1 causes the port enable signal to drive the

output to 1 within 20-30nsec. After several (#

TBD) clocks, the port enable goes away and the

internal 90µA pull-up maintains the output signal

as 1.

alternate functions behave as follows: if in RD to

SD mode, any value on RDx will appear on SDx;

if in SD to RD mode, SDx will not appear on

RDx, RDx gets the alternate function value.

Note: In this case, nROMCS=0, nROMOE=1.

Case 2: nROMOE as alternate function

(nROMOE internally tied to ground). In this

case, the RD bus is a unidirectional bus (read

only) controlled by nROMCS. If nROMCS = 0,

the values on RD0-7 appear on SD0-7. If

nROMCS = 1, the RD bus is disabled and

nothing appears on the SD bus. Note: any RD

bus pin can be programmed as an alternate

function, however, if nROMCS=0, then anything

on the RD bus will appear on the SD bus.

In 8042 mode, the pins can be programmed as

open drain. When programmed in open drain

mode, the port enables do not come into play. If

the port signal is 0 the output will be 0. If the

port signal is 1, the output tristates: an external

pull-up can pull the pin high, and the pin can be

shared i.e., P12 and nSMI can be externally tied

together. In 8042 mode, the pins cannot be

programmed as input nor inverted through the

GP configuration registers.

Case 3: nROMCS as alternate function

(nROMCS internally tied to VDD). The RD bus

120

GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION

The FDC37C93xAPM provides a set of flexible

General Purpose I/O Ports

Input/Output control functions to the system

designer through a set of General Purpose I/O

pins (GPI/O). These GPI/O pins may perform

simple I/O or may be individually configured to

provide a predefined alternate function. Power-

on reset configures all GPI/O pins as simple

non-inverting inputs.

The FDC37C93xAPM has 14 dedicated,

independently-programmable general purpose

I/O ports (GPI/O).

Each GPI/O port is

represented as a bit in one of two GPI/O 8-bit

registers, GP1 or GP2. Only 6 bits of GP2 are

implemented. Each GPI/O port and its alternate

function is listed in Table 47A.

Table 47A - General Purpose I/O Port Assignments

Alternate Alternate Alternate

Function 1 Function 2

Number

96

Original

Function

GP10

Register

Assignment

GP1, bit 0

Function 3

Interrupt Steering*

WD Timer Output

Power LED

-

97

98

GP11

GP12

GP13

GP14

IRQ 13

IRRX Input

IRTX Output

-

GP1, bit 1

GP1, bit 2

GP1, bit 3

GP1, bit 4

99

100

GP Address

Decoder

102

103

104

GP15

GP16

GP17

GP Write Strobe

-

GP1, bit 5

GP1, bit 6

GP1, bit 7

Joystick RD Strobe Joystick Chip Sel

Joystick WR

Strobe

-

105

106

GP20

GP21

IDE2 Buffer Enable

8042 P20

AB_DATA

-

GP2, bit 0

GP2, bit 1

Serial EEPROM

Data In *

107

108

109

110

GP22

GP23

GP24

GP25

Serial EEPROM

Data Out

AB_CLK

-

GP2, bit 2

GP2, bit 3

GP2, bit 4

GP2, bit 5

Serial EEPROM

Clock

-

Serial EEPROM

Enable

8042 P21

Note 1: 8042 P21 is normally used for Gate A20

Note 2: 8042 P20 is normally used for the Keyboard Reset Output

* These are input-type alternate functions; all other GPI/O pins contain output-type alternate

functions.

121

The FDC37C93xAPM also has 28 GPI/O ports

that are the first alternate functions of pins

with other default functions. These pins are

listed in Table 47B below.

Table 47B - Multifunction GPI/O Pins

GPI/O

NUMBER

19

ORIGINAL

FUNCTION

MEDIA_ID1

ALTERNATE

FUNCTION 1

GP40

ALTERNATE ALTERNATE

FUNCTION 2 FUNCTION 3 ASSIGNMENT

REGISTER

-

GP4, bit 0

GP4, bit 1

GP4, bit 2

GP4, bit 3

GP4, bit 4

GP4, bit 5

GP4, bit 6

20

23

24

25

26

30

MEDIA_ID0

nIDE1_OE

nHDCS0

GP41

GP42

GP43

GP44

GP45

GP46

-

nHDCS1

-

IDE1_IRQ

nIOROP

Power LED

Output

WDT

31

33

nIOWOP

nPowerOn

Button_In

RD0 (1) (3)

GP47

GP51

GP50

GP60

nSMI

-

GP4, bit 7

GP5, bit 1

GP5, bit 0

GP6, bit 0

-

34

Power LED

Output

111

112

113

114

115

116

117

118

119

120

153

154

155

156

RD1 (1) (3)

RD2 (1) (3)

RD3 (1) (3)

RD4 (1) (3)

RD5 (1) (3)

RD6 (1) (3)

RD7 (1) (3)

nROMCS (1)

nROMOE (1)

nRI2 (2)

GP61

GP62

GP63

GP64

GP65

GP66

GP67

GP53

GP54

GP70

GP71

GP72

GP73

WDT

-

GP6, bit 1

GP6, bit 2

GP6, bit 3

GP6, bit 4

GP6, bit 5

GP6, bit 6

GP6, bit 7

GP5, bit 3

GP5, bit 4

GP7, bit 0

GP7, bit 1

GP7, bit 2

GP7, bit 3

8042 - P12

8042 - P13

8042 - P14

8042 - P15

8042 - P16

8042 - P17

-

nDCD2 (2)

RXD2 (2)

TXD2 (2) (3)

122

GPI/O

NUMBER

157

ORIGINAL

FUNCTION

nDSR2 (2)

ALTERNATE

FUNCTION 1

GP74

ALTERNATE ALTERNATE

FUNCTION 2 FUNCTION 3 ASSIGNMENT

REGISTER

-

GP7, bit 4

158

nRTS2 (2)

(3)

GP75

-

GP7, bit 5

159

160

nCTS2 (2)

GP76

GP77

-

GP7, bit 6

GP7, bit 7

nDTR2 (2)

(3)

Note 1: At power-up, RD0-RD7, nROMCS and nROMOE function as the XD Bus. To use RD0-

RD7 for functions other than the XD Bus, nROMCS must stay high until those pins are

finished being reprogrammed.

Note 2: These pins are input (high-z) until programmed for second serial port.

Note 3: These pins cannot be programmed as open drain pins in their original function.

Note 4: No pins in their original function can be programmed as inverted input or inverted output.

GPI/O registers GP1 through GP7 as well as the

Soft Power and SMI Enable and Status

Registers can be accessed by the host when the

chip is in the normal run mode if CR03 Bit[7]=1.

The host uses an Index and Data register to

access these registers. The Power on default

Index and Data registers are 0xEA and 0xEB

respectively. In configuration mode the Index

address may be programmed to reside on

addresses 0xE0, 0xE2, 0xE4 or 0xEA. The Data

address is automatically set to the Index

address + 1. Upon exiting the configuration

mode the new Index and Data registers are used

to access registers GP1 through GP7 and Soft

Power and SMI Enable and Status Registers.

To access the GP1 register when in normal

(run) mode, the host should perform an IOW of

0x01 to the Index register (at 0xEX) to select

GP1 and then read or write the Data register (at

Index+1) to access the GP1 register. To access

GP2 the host should perform an IOW of 0x02 to

the Index register and then access GP2 through

the Data register. GP4-7 and the Soft Power

and SMI Registers are acessed similarly.

Additionally the host can access the

WDT_CTRL (Watch Dog Timer Control)

Configuration Register while in the normal (run)

mode by writing an 0x03 to the index register.

The GP registers can also be accessed by the

host when in configuration mode through CRF6-

FB of Logical Device 8.

123

Table 48A - Index and Data Register

REGISTER

Index

ADDRESS

NORMAL (RUN) MODE

0xE0, E2, E4, EA

Index address + 1

0x01-0x0F

Data

Access to GP1, GP2,

Watchdog Timer Control,

GP4, GP5, GP6, GP7, Soft

Power and SMI Enable and

Status Registers (see

Table 48B)

Table 48B - Index and Data Register Normal (Run) Mode

INDEX

NORMAL (RUN) MODE

Access to GP1 (L8 - CRF6)

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

Access to GP2 (L8 - CRF7)

Access to Watchdog Timer Control (L8 - CRF4)

Access to GP4 (L8 - CRF8)

Access to GP5 (L8 - CRF9)

Access to GP6 (L8 - CRFA)

Access to GP7 (L8 - CRFB)

Access to Soft Power Enable Register 1 (L8-CRB0)

Access to Soft Power Enable Register 2 (L8-CRB1)

Access to Soft Power Status Register 1 (L8-CRB2)

Access to Soft Power Status Register 2 (L8-CRB3)

Access to SMI Enable Register 1 (L8-CRB4)

Access to SMI Enable Register 2 (L8-CRB5)

Access to SMI Status Register 1 (L8-CRB6)

Access to SMI Status Register 2 (L8-CRB7)

Note 1: These registers can also be accessed through the configuration registers at L8 -

CRxx shown in the table above.

124

GPI/O ports contain alternate functions which

are either output-type or input-type. The GPI/O

port structure

in the following two figures. Note: the input pin

buffer is always enabled.

for each type is illustrated

GPI/O

Configuration

Register bit-1

(Polarity)

Configuration

Register bit-0

(Input/Output)

SD-bit

D-TYPE

nIOW

GPI/O

0

Transparent

0

1

nIOR

1

GPI/O

Register

Bit-n

GPI/O

GPIO

Configuration

Register bit-3

(Alt Function)

Configuration

Register bit-2

(Int En)

Alternate

Input

Function

To GP Interrupt

FIGURE 4 - GPI/O HAVING AN INPUT-TYPE ALTERNATE FUNCTION [GP10, GP11, GP12, GP21]

125

GPIO

GPI/O

Configuration

Register bit-3

(Alt Function)

Configuration

Register bit-1

(Polarity)

Configuration

Register bit-0

(Input/Output)

Alternate

Output

Function

1

0

SD-bit

nIOW

D-TYPE

GPI/O

0

1

Transparent

0

nIOR

1

GPI/O

Register

Bit-n

GPI/O

Configuration

Register bit-2

(Int En)

To GP Interrupt

FIGURE 5 - GPI/O HAVING AN OUTPUT-TYPE ALTERNATE FUNCTION [GP12 - GP17, GP20,

GP22 - GP25]

126

In addition, the GPI/O port may be optionally

programmed to steer its signal to a Combined

General Purpose Interrupt request output pin on

the FDC37C93xAPM. The interrupt channel for

the Combined Interrupt is selected by the

GP_INT Configuration Register defined in the

FDC37C93xAPM System Configuration Section.

The Combined Interrupt is the "ORed" function

of the interrupt enabled GPI/O ports and will

represent a standard ISA interrupt (edge high).

General Purpose I/O Configuration Registers

Assigned to each GPI/O port is an 8-bit GPI/O

Configuration Register which is used to

independently program each I/O port. The

GPI/O Configuration Registers are only

accessible when the FDC37C93xAPM is in the

Configuration Mode; more information can be

found in the Configuration section of this

specification.

Each GPI/O port may be programmed as either

a simple inverting or non-inverting input or

output port, or as an alternate function port. The

least-significant four bits of each GPI/O

Configuration Register define the operation of

the respective GPI/O port. The basic GPI/O

operations are outlined in Table 49.

When programmed as an input steered onto

the General Purpose Combined Interrupt (GP

IRQ), the Interrupt Circuitry contains

a

selectable debounce/digital filter circuit in

order that switches or push-buttons may be

directly connected to the chip. This filter will

reject signals with pulse widths of 1ms or less.

Table 49 - GPI/O Configuration Register Bits [3:0]

POLARITY

ALT FUNC

BIT 3

BIT 1

0=

INT EN

BIT 2

I/O

BIT 0

0=

DISABLE

1=SELECT

NO INVERT

1=INVERT

GPI/O PORT

OPERATION

0=DISABLE

1=ENABLE

1=INPUT

0=OUTPUT

0

1

0

1

0

1

0

1

0

simple non-inverting output

simple non-inverting input

simple inverting output

simple inverting input

non-inverting output steered back to GP

IRQ

0

1

0

1

0

1

0

1

0

non-inverting input steered to GP IRQ

inverting output steered back to GP IRQ

inverting input steered to GP IRQ

Alternate Function Output-type:

Alternate non-inverted output.

Alternate Function Input-type:

Alternate function not valid, GPI/O pin

acts as a simple non-inverting output.

127

Table 49 - GPI/O Configuration Register Bits [3:0]

POLARITY

ALT FUNC

BIT 3

BIT 1

0=

INT EN

BIT 2

I/O

BIT 0

0=

DISABLE

1=SELECT

NO INVERT

1=INVERT

GPI/O PORT

OPERATION

0=DISABLE

1=ENABLE

1=INPUT

0=OUTPUT

1

0

1

0

Alternate Function Output-type:

Alternate function not valid, GPI/O pin

acts as a simple non-inverting input.

Alternate Function Input-type:

Alternate non-inverting input.

1

0

Alternate Function Output-type:

Alternate output function with inverted

sense

Alternate Function Input-type:

Alternate function not valid, GPI/O pin

acts as a simple inverting output.

1

0

1

0

1

0

1

Alternate Function Output-type:

Alternate output function not valid,

GPI/O pin acts as a simple inverting

input.

Alternate Function Input-type:

Inverting input to alternate input

function.

Alternate Function Output-type:

Alternate output function with non

inverted sense steered to GP IRQ

Alternate Function Input-type:

Alternate function not valid, GPI/O pin

acts as a simple non-inverting output

steered to GP IRQ

Alternate Function Output-Type:

Alternate output function not valid,

GPI/O pin acts as a simple non-inverting

input steered to GP IRQ.

Alternate Function Input-type:

Non-inverting input to alternate input

function also steered to the GP IRQ.

128

Table 49 - GPI/O Configuration Register Bits [3:0]

POLARITY

ALT FUNC

BIT 3

BIT 1

0=

INT EN

BIT 2

I/O

BIT 0

0=

DISABLE

1=SELECT

NO INVERT

1=INVERT

GPI/O PORT

OPERATION

0=DISABLE

1=ENABLE

1=INPUT

0=OUTPUT

1

0

Alternate Function Output-type:

Alternate output function with inverted

sense steered to GP IRQ

Alternate Function Input-

type:Alternate function not valid, GPI/O

pin acts as a simple inverting output

steered to GP IRQ.

1

Alternate Function Output-type:

Alternate output function not valid,

GPI/O pin acts as a simple inverting

input steered to GP IRQ.

Alternate Function Input-type:

Inverting input to alternate input function

also steered to the GP IRQ.

The alternate function of GP10 and GP11 allows

these GPI/O port pins to be mapped to their own

configuration registers is used to select the

active interrupt channel for each of these ports

as shown in the Configuration section of this

specification.

independent interrupt channels.

nibble of the GP10 and

The upper

GP11 GPI/O

129

effect. When a GPI/O port is programmed as

an output, the logic value written into the GPI/O

register is either output to or inverted to the

GPI/O pin; when read the result will reflect the

contents of the GPI/O register bit. This is

summarized in Table 50.

Reading and Writing GPI/O Ports

When a GPI/O port is programmed as an input,

reading it through the GPI/O register latches

either the inverted or non-inverted logic value

present at the GPI/O pin; writing it has no

Table 50 - GPI/O Read/Write Behavior

GPI/O INPUT PORT

HOST OPERATION

GPI/O OUTPUT PORT

Bit Value In GP Register

Bit Placed In GP Register

Read

Write

Latched Value of GPI/O Pin

No Effect

WATCH DOG TIMER/POWER LED CONTROL

Configuration Registers is set "and" bit 6 of the

BASIC FUNCTIONS

IR Options Register is set.

The FDC37C93xAPM contains a Watch Dog

Timer (WDT) and also has the capability to

directly drive the system's Power-on LED.

Pins 30 (nIOROP/GP46) and 111 (RD0/GP60)

can also be configured for Power LED.

The Watch Dog Time-Out status bit

(WDT_CTRL bit 0) is mapped to GP12 when the

alternate function bit of the GP12 Configuration

Register is set "and" bit 6 of the IR Options

Register = 0. In addition, the Watch Dog Time-

out status bit may be mapped to an interrupt

through the WDT_CFG Configuration Register.

WATCH DOG TIMER

The

FDC37C93xAPM's

WDT

has

a

programmable time-out ranging from one to 255

minutes with one minute resolution, or one to

255 seconds with one second resolution. The

units of the WDT timeout value are selected via

bit 7 of the GPA_GPW_EN register (located at

0xF1 of Logical Device 8). The WDT time-out

Pins 30 (nIOROP/GP46) and 112 (RD1/GP61)

can also be configured for WDT.

value

is

set

through

the

WDT_VAL

Configuration register. Setting the WDT_VAL

register to 0x00 disables the WDT function (this

is its power on default). Setting the WDT_VAL

to any other non-zero value will cause the WDT

to reload and begin counting down from the

value loaded. When the WDT count value

reaches zero the counter stops and sets the

Watchdog time-out status bit in the WDT_CTRL

Configuration Register. Note: Regardless of the

current state of the WDT, the WDT time-out

status bit can be directly set or cleared by the

Host CPU.

GP13 may be configured as a high current LED

driver to drive the power LED.

This is

accomplished by setting the alternate function

bit of the GP13 Configuration Register "and"

clearing bit 6 of the IR Options Register.

The infared signals, IRRX and IRTX, are

mapped to GP12 and GP13 when the alternate

function bit of the GP12 and GP13

130

There are three system events which can reset

the WDT; these are a keyboard interrupt, a

mouse interrupt, or I/O reads/writes to address

0x201 (the internal or an external joystick Port).

The effect on the WDT for each of these system

events may be individually enabled or disabled

through bits in the WDT_CFG Configuration

Register. When a system event is enabled

through the WDT_CFG register, the occurence

of that event will cause the WDT to reload the

value stored in WDT_VAL and reset the WDT

time-out status bit if set. If all three system

events are disabled, the WDT will inevitably

time out.

The host may force a Watch Dog time-out to

occur by writing a "1" to bit 2 of the WDT_CTRL

(Force WD Time-out) Configuration Register.

Writing a "1" to this bit forces the WDT count

value to zero and sets bit 0 of the WDT_CTRL

(Watch Dog Status). Bit 2 of the WDT_CTRL is

self-clearing.

POWER LED TOGGLE

Setting bit 1 of the WDT_CTRL Configuration

Register will cause the power LED output driver

to toggle at 1 Hertz with a 50 percent duty cycle.

When this bit is cleared the power LED output

will drive continuously unless it has been

configured to toggle on Watch Dog time-out

conditions. Setting bit 3 of the WDT_CFG

configuration register will cause the Power LED

output driver to toggle at 1 Hertz with a 50

percent duty cycle whenever the WDT time-out

status bit is set. The truth table below clarifies

the conditions for which the Power LED will

toggle.

The Watch Dog Timer may be configured to

generate an interrupt on the rising edge of the

time-out status bit.

mapped to an interrupt channel through the

WDT_CFG Configuration Register. When

The WDT interrupt is

mapped to an interrupt the interrupt request pin

reflects the value of the WDT time-out status bit.

When the polarity bit is 0, GP12 reflect the value

of the Watch Dog Time-out status bit, however

when the polarity bit is 1, GP12 reflects the

inverted value of the Watch Dog time-out status

bit. This is also true for the other two pins used

for WDT, nIOROP (GP46) and RD1 (GP61).

When the polarity bit is 0, the power LED output

asserts or drives low. If the polarity bit is 1 then

the power LED output asserts or drives high.

Table 51 - LED Toggle Truth Table

WDT_CFG BIT 3

POWER LED

WDT_CTRL BIT 1

WDT_CTRL BIT 0

POWER LED TOGGLE

TOGGLE ON WDT

POWER LED STATE

Toggle

WDT T/O STATUS BIT

1

0

X

0

1

X

0

1

Continuous

Toggle

131

Table 52 - Watchdog Timer/Power LED Configuration Registers

CONFIG REG.

WDT_VAL

BIT FIELD

Bits[7:0]

DESCRIPTION

Binary coded time-out value, 0x00 disables the WDT.

Joystick enable

WDT_CFG

Bit[0]

Bit[1]

Keyboard enable

Bit[2]

Mouse enable

Bit[3]

Power LED toggle on WDT time-out

Bits[7:4]

WDT interrupt mapping,

0000b = diables irq mapping

WDT_CTRL

Bit[0]

WDT time-out status bit

Bit[1]

Power LED toggle

Bit[2]

Force Timeout, self-clearing

P20 Force Timeout Enable

Reserved, set to zero

Bit[3]

Bit[4]

Bit[5,6,7]

Stop_Cnt, Restart_Cnt, SPOFF: used for Soft power mgt

GENERAL PURPOSE ADDRESS DECODER

GENERAL PURPOSE WRITE

General Purpose I/O pin GP15 may be

configured as a General Purpose Write pin. The

General Purpose Write provides an output

decoded from the 12-bit address stored in a

two-byte Base I/O Address Register (Logical

Device 8 Configuration Registers 0x62, 0x63)

qualified with IOW and AEN. This General

Purpose output is normally active low, however

the polarity may be altered through the polarity

bit in its GPI/O Configuration Register.

General Purpose I/O pin GP14 may be

configured as a General Purpose Address

Decode Pin. The General Purpose Address

Decoder provides an output decoded from bits

A11-A1 of the 12-bit address stored in a two-

byte Base I/O Address Register (Logical Device

8 Configuration Registers 0x60, 0x61) qualified

with AEN. Thus, the decoder provides a two

address decode where A0=X. This General

Purpose output is normally active low, however

the polarity may be altered through the polarity

bit in its GPI/O Configuration Register.

The GPA_GPW_EN Configuration Register

contains two bits which allow the General

Purpose Address Decode and Write functions to

be independently enabled or disabled.

The pins nHDCS0 and nHDCS1 can also be

used as general purpose address decoders. See

Configuration section, Logical Device 1, for

more information.

JOYSTICK CONTROL

The base I/O address of the Joystick (Game)

Port is fixed at address 0x201.

132

GP16 JOYSTICK FUNCTION

SERIAL EEPROM INTERFACE

The FDC37C93xAPM may be configured to

generate either a Joystick Chip Select or a

Joystick Read Strobe on GP16. The polarity is

programmable through a bit in the GP16

confiugration register. When configured as a

Joystick Chip Select the output is simply a

decode of the address = 0x201 qualified by AEN

active. When configured as a Joystick Read

Strobe the output is a decode of the address =

0x201 qualified by IOR and AEN both active.

The Joystick Chip Select or Read Strobe is

normally active low, however its polarity is

programmable through a bit in the GP20

configuration register.

Four of the FDC37C93xAPM's general purpose

I/O pins may be configured to provide a four

wire direct interface to a family of industry

standard serial EEPROMs.

For proper

operation the polarity bits of these four pins

must be set to 0 (non-inverting). The interface

is depicted below and will allow connection to

either a 93C06 (256-bit), a 93C46 (1K-bit), a

93C56 (2K-bit), or a 93C66 (4K-bit) device.

GP21 <---- Serial EEPROM Data In

GP22 ----> Serial EEPROM Data Out

GP23 ----> Serial EEPROM Clock

GP24 ----> Serial EEPROM Enable

Reset out is an internal signal from the keyboard

controller (Port 20). The FDC37C93xAPM may

be configured to drive this signal onto GP20 by

programming its GPI/O configuration register.

GP17 JOYSTICK FUNCTION

The FDC37C93xAPM may be configured to

generate a Joystick Write Strobe on GP17.

When configured as a Joystick Write Strobe the

output is a decode of the address = 0x201

qualified by IOW and AEN both active.

Access to the serial EEPROM is only available

when the FDC37C93xAPM is in the

configuration mode. A set of six configuration

registers, located in Logical Device 6 (RTC) is

used to fully access and configure the serial

EEPROM. The registers are defined as follows:

The Joystick Write Strobe is normally active

low, however, its polarity is programmable

through a bit in the GP20 configuration register.

Serial EEPROM Mode Register, 0xF1

IDE2 BUFFER ENABLE/RESET OUT

The FDC37C93xAPM may be configured to

provide an nIDE2_OE buffer enable signal on

pin GP20. The IDE2 Mode Register (0xF0 of

BIT 3 and 0

These are the lock bits which once set deny

access to the serial EEPROM's first 128 bytes in

32 byte blocks. Bit 0 locks the first block, bit 1

the second block, bit 2 the third block and bit 3

the fourth block of 32 bytes. Once these lock

bits are set they cannot be reset in any way

other than by a Hard reset or a power-on reset.

Logical Device 2) contains

a

bit which

determines whether nIDE1_OE or nIDE2_OE is

active for IDE2 transfers. If GP20 is selected

as a General Purpose I/O pin, IDE2 I/O

accesses must be configured to activate

nIDE1_OE for IDE2 transfers if a secondary

hard drive interface is present.

BIT 4

This selects the type of EEPROM connected to

the FDC37C93xAPM. If cleared the device must

be either a 93C06 or 93C46 and if set the device

must be either an 93C56 or 93C66. This bit

must be properly set before attempting to

access the serial EEPROM.

The polarity of nIDE2_OE, which is normally

active low, is programmable through a bit in the

GP20 configuration register.

133

When = (0,0) bit 1 is cleared on the second

write of the Write EEPROM Data register

indicating that two bytes have been accepted

and that the serial device interface is busy

writing the word to the EEPROM.

BIT 7 - 5

Reserved, set to zero.

Serial EEPROM Pointer Register, 0xF2

BIT 7 - 0

BIT 6 - 2

Use this register to set the Serial EEPROM's

Reserved, set to “0”

pointer.

The value in this register always

reflects the current EEPROM pointer address.

The Serial Device Pointer increments after each

pair of reads from the Resource Data register or

after each pair of writes to the Program

Resource Data register.

BIT 7

This bit is cleared to configure the EEPROM

interface for Read operations. Clearing this bit

enables the serial EEPROM prefetch when the

Serial EEPROM Pointer Register is updated

(written or auto-incremented).

Write EEPROM Data Register, 0xF3

This bit is set to configure the EEPROM

interface for Write operations. Setting this bit

disables the serial EEPROM prefetch when the

Serial EEPROM Pointer Register is updated

(written or auto-incremented).

BIT 7 - 0

This register allows the host to write data into

the serial EEPROM.

supports serial EEPROMS

The FDC37C93xAPM

with x16

configurations. Two bytes must be written to

this register in order to generate an EEPROM

write cycle. The LSB leads the MSB. The first

write to this register resets bit 0 of the Write

Status register. The second write resets bit 1 of

the Write Status register and generates a write

cycle to the serial EEPROM. The Write Status

register must be polled before performing a pair

of writes to this register.

Read EEPROM Data Register, 0xF5

BIT 7 - 0

This register allows the host to read data from

the serial EEPROM. Data is not valid in this

register until bit 0 of the Read Status Register is

set. Since the EEPROM is a 16-bit device this

register presents the LSB followed by the MSB

for each pair of register reads. Immediately after

the MSB is read bit-0 of the Read Status

Register will be cleared, then the Serial

EEPROM Pointer Register will be auto-

incremented, then the next word of EEPROM

data will be fetched, followed by the Read

Status Register, bit 0 being set.

Write Status Register, 0xF4

BIT 1 and 0

When = (1,1)Indicates that the Write EEPROM

Data register is ready to accept a pair of bytes.

When = (1,0) bit 0 is cleared on the first write of

the Write EEPROM Data register. This status

indicates that the serial device controller has

received one byte (LSB) and is waiting for the

second byte (MSB).

Read Status Register, 0xF6

Bit[0]

When set, indicates that data in the Read

EEPROM Data register is valid. This bit is

cleared when EEPROM Data is read until the

next byte is valid. Reading the Read EEPROM

Data register when bit 0 is clear will have no

detremental effects; the data will simply be

invalid.

134

pin. In addition, if this function is selected, then

the bits that control in/out, polarity and open

collector/push-pull will have no effect on the

function of the pin. However, the polarity will

affect the value of the GP bit.

GATEA20

GATEA20 is an internal signal from the

Keyboard

FDC37C93xAPM may be configured to drive this

signal onto GP25 by programming its GPI/O

Configuration Register. See the 8042 Keyboard

Controller Section for more information.

controller

(Port

21).

The

An interrupt occurs if the status bit is set and the

interrupt is enabled. The status bits indicate

which of these interrupts transitioned. These

status bits are located in the MSC_STS register

(See ACPI section). These bits are cleared by a

writing a 1 to their respective bit locations

(writing a 0 has no effect). The status is valid

whether the interrupt is enabled or not and

whether or not the pin is selected for either edge

triggered interrupt.

EITHER EDGE TRIGGERED INTERRUPTS

Three GPIOs will allow an interrupt to be

generated on either a high-to-low or low-to-high

edge transition, instead of one or the other as

selected by the polarity bit. These GPIOs,

GP42, GP23, GP24, pins 23, 108, 109,

respectively, can be used to detect system

changes.

Note: These additional interrupts will go through

the same selectable debounce/digital filter

circuit as any interrupt that is steered onto one

of the GP group interrupts.

Note: These pins are enabled as interrupts by

selecting the “Either Edge Triggered Interrupt

Input

x Enable” function through bits[4:3].

These interrupts function as follows: when an

edge comes in, an interrupt is generated and the

status bit is set. When the interrupt is serviced,

the status bit is cleared. When the next edge

comes in, an interrupt is generated and the

status bit is set. Again, when the interrupt is

serviced, the status bit is cleared. See Figure 6

below.

Selecting the “Either Edge Triggered Interrupt

Input x Enable” function for these GPI/O pins is

only applicable if the combined interrupt is

enabled (GP42 can be enabled onto either

GPINT1 or GPINT2; GP23 and GP24 can be

enabled onto GPINT1). Otherwise, selection of

this function will produce no function for the

GPI/O Pin

GP Interrupt

Cleared by a Write to the

Status Bit

FIGURE 6 - EITHER EDGE TRIGGERED INTERRUPT TIMING EXAMPLE

135

8042 KEYBOARD CONTROLLER AND REAL TIME CLOCK FUNCTIONAL

DESCRIPTION

The FDC37C93xAPM is a Ultra I/O, Real Time

Clock and Universal Keyboard Controller de-

signed for intelligent keyboard management in

desktop computer applications. The Ultra I/O

supports a floppy disk controller, two 16550-

type serial ports, one ECP/EPP parallel port and

two IDE drive interfaces with support for four

drives.

The Universal Keyboard Controller uses an

8042 microcontroller CPU core. This section

concentrates

enhancements to the 8042.

on

the

FDC37C93xAPM

For general

information about the 8042, refer to the "Hard-

ware Description of the 8042" in the 8-Bit

Embedded Controller Handbook.

P24

P25

P21

P20

KIRQ

MIRQ

GP25

GP20 (WD Timer)

8042A

LS05

P27

P10

KDAT

KCLK

MCLK

MDAT

P26

TST0

P23

TST1

P22

P11

FIGURE 6 - KEYBOARD AND MOUSE INTERFACE

KIRQ is the Keyboard IRQ

MIRQ is the Mouse IRQ

GP25 - Port 21 is GP25's alternate function output and can be used to create a GATEA20 signal from

the FDC37C93xAPM.

GP20 - This general purpose output can be configured as the 8042 Port 2.0 which is typically used to

create a "keyboard reset" signal. The 8042's P20 can be used to optionally reset the Watch Dog

Timer.

136

KEYBOARD AND RTC ISA INTERFACE

The FDC37C93xAPM ISA interface

functionally compatible with the 8042-style host

interface. It consists of the D0-7 data bus, the

nIOR, nIOW and the Status register,

Input Data register, and Output Data register.

Table 53 shows how the interface decodes the

control signals. In addition to the above signals,

the host interface includes keyboard and mouse

IRQs.

is

Table 53 - ISA I/O Address Map

Addresses 0x60, 0x64, 0x70 and 0x71 are qualified by AEN

ISA ADDRESS (NOTE 1)

0x70 (R/W)

BLOCK

RTC

FUNCTION

Address Register

Data Register

0x71 (R/W)

RTC

Bank 0 is at 70h. Bank 1 and 2 are relocatable via the RTC Mode Register and the Secondary Base

Address for RTC Bank 1 and 2 (CR62 and CR63). See Configuration section.

ISA ADDRESS

nIOW

nIOR

BLOCK

KDATA

KDCTL

FUNCTION*

Keyboard Data Write (C/D=0)

Keyboard Data Read

0x60

0

1

0

1

0

1

0

0x64

Keyboard Command Write (C/D=1)

Keyboard Status Read

Note*:

These registers consist of three separate 8 bit registers: Status, Data/Command Write

and Data Read.

Keyboard Data Write

Keyboard Command Write

This is an 8 bit write only register. When

written, the C/D status bit of the status register

is cleared to zero and the IBF bit is set.

This is an 8 bit write only register. When

written, the C/D status bit of the status register

is set to one and the IBF bit is set.

Keyboard Data Read

Keyboard Status Read

This is an 8 bit read only register. If enabled by

"ENABLE FLAGS", when read, the KIRQ output

is cleared and the OBF flag in the status register

is cleared. If not enabled, the KIRQ and/or

AUXOBF1 must be cleared in software.

This is an 8 bit read only register. Refer to the

description of the Status Register for more

information.

RTC Address Register

Writing to this register sets the CMOS address

that will be read or written.

137

RTC Data Register

CPU-to-Host Communication

A read of this register will read the contents of

the selected CMOS register. A write to this

register will write to the selected CMOS register.

The FDC37C93xAPM CPU can write to the Out-

put Data register via register DBB. A write

to this register automatically sets Bit 0 (OBF) in

the Status register. See Table 54.

Table 54 - Host Interface Flags

8042 INSTRUCTION

FLAG

OUT DBB

Set OBF, and, if enabled, the KIRQ output signal goes high

If "EN FLAGS” has not been executed, KIRQ

can be controlled by writing to P24. Writing a

Host-to-CPU Communication

“0” to P24 forces KIRQ low; a high forces KIRQ

high.

The host system can send both commands and

data to the Input Data register. The CPU

differentiates between commands and data by

reading the value of Bit 3 of the Status register.

When bit 3 is "1", the CPU interprets the register

contents as a command. When bit 3 is "0", the

CPU interprets the register contents as data.

During a host write operation, bit 3 is set to "1" if

SA2 = 1 or reset to "0" if SA2 = 0.

MIRQ

If "EN FLAGS" has been executed and P25 is

set to a “1”, IBF is inverted and gated onto

MIRQ. The MIRQ signal can be connected to

system

interrupt

to

signify

that

the

FDC37C93xAPM’s CPU has read the DBB

register.

KIRQ

If "EN FLAGS” has not been executed, MIRQ is

controlled by P25, Writing a “0” to P25 forces

MIRQ low; a high forces MIRQ high. (MIRQ is

normally selected as IRQ12 for mouse support.)

If "EN FLAGS" has been executed and P24 is

set to a one: the OBF flag is gated onto KIRQ.

The KIRQ signal can be connected to system

interrupt to signify that the FDC37C93xAPM’s

CPU has written to the output data register via

"OUT DBB,A". If P24 is set to a “0”, KIRQ is

forced low. On power-up, after a valid RST

pulse has been delivered to the device, KIRQ is

reset to 0. KIRQ will normally reflects the status

of writes "DBB". (KIRQ is normally selected as

IRQ1 for keyboard support.)

Gate A20

A general purpose P21 can be routed out to the

general purpose pin GP25 for use as

a

software-controlled Gate A20 or user-defined

output.

138

interrupt and the IBF interrupt is enabled, then

program execution resumes with a CALL to the

interrupt routine, otherwise the next instruction

is executed. If it is exited using RESET, then a

normal reset sequence is initiated and program

execution starts from program memory location

0.

EXTERNAL

INTERFACE

KEYBOARD

AND

MOUSE

Industry-standard PC/AT-compatible keyboards

employ a two-wire, bidirectional TTL interface

for data transmission. Several sources also

supply PS/2 mouse products that employ the

same type of interface. To facilitate system

expansion, the FDC37C93xAPM provides four

signal pins that may be used to implement this

interface directly for an external keyboard and

mouse.

Hard Powerdown Mode

This mode is entered by executing a STOP

instruction. The oscillator is stopped by

disabling the oscillator driver

either RESET is driven active or a data byte is

written to the DBBIN register by master

CPU, this mode will be exited (as above).

However, as the oscillator cell will require an

initialization time, either RESET must be held

active for sufficient time to allow the oscillator to

stabilise. Program execution will resume as

above.

cell. When

The FDC37C93xAPM has four high-drive, open-

drain output, bidirectional port pins that can be

used for external serial interfaces, such as ISA

external keyboard and PS/2-type mouse

interfaces. They are KCLK, KDAT, MCLK, and

MDAT. P26 is inverted and output as KCLK.

The KCLK pin is connected to TEST0. P27 is

inverted and output as KDAT. The KDAT pin is

connected to P10. P23 is inverted and output

as MCLK. The MCLK pin is connected to

TEST1. P22 is inverted and output as MDAT.

The MDAT pin is connected to P11. Note:

External pull-ups may be required.

a

INTERRUPTS

The FDC37C93xAPM provides the two 8042

interrupts, IBF and the Timer/Counter Overflow.

KEYBOARD POWER MANAGEMENT

MEMORY CONFIGURATIONS

The keyboard provides support for two power-

saving modes: soft powerdown mode and hard

powerdown mode. In soft powerdown mode,

the clock to the ALU is stopped but the

timer/counter and interrupts are still active. In

hard power down mode the clock to the 8042 is

The FDC37C93xAPM provides 2K of on-chip

ROM and 256 bytes of on-chip RAM.

REGISTER DEFINITIONS

Host I/F Data Register

stopped.

Efforts must be made to reduce

power wherever possible!

The Input Data register and Output Data register

are each 8 bits wide. A write to this 8 bit register

will load the Keyboard Data Read Buffer, set the

OBF flag and set the KIRQ output if enabled. A

read of this register will read the data from the

Keyboard Data or Command Write Buffer and

clear the IBF flag. Refer to the KIRQ and Status

register descriptions for more information.

Soft Powerdown Mode

This mode is entered by executing a HALT

instruction. The execution of program code is

halted until either RESET is driven active or a

data byte is written to the DBBIN register by a

master CPU. If this mode is exited using the

139

Host I/F Status Register

The Status register is 8 bits wide. Table 55 shows the contents of the Status register.

Table 55 - Status Register

D7

D6

D5

D4

D3

D2

D1

D0

UD

C/D

UD

IBF

OBF

Status Register

OBF

Output Buffer Full

This flag is set to

1

whenever the

This register is cleared on a reset. This register

is read-only for the Host and read/write by the

FDC37C93xAPM CPU.

FDC37C93xAPM CPU write to the output data

register (DBB). When the host system reads

the output data register, this bit is automatically

reset.

UD

Writeable by FDC37C93xAPM CPU. These bits

are user-definable.

EXTERNAL CLOCK SIGNAL

The FDC37C93xAPM’s X1K clock source is a 12

MHz clock generated from a 14.318 MHz clock.

The reset pulse must last for at least 24 16

C/D

Command Data

This bit specifies whether the input data register

contains data or a command (0 = data, 1 =

command). During a host data/command write

operation, this bit is set to "1" if SA2 = 1 or reset

to "0" if SA2 = 0.

MHz clock periods.

requirement applies to both internally - and

externally generated reset signals. In

The pulse-width

-

powerdown mode, the external clock signal on

X1K is not loaded by the chip.

IBF

The FDC37C93xAPM’s X1C clock source must

be from a crystal connected across X1C and

X2C. Due to the low current internal oscillator

circuit, this X1C can not be driven by an external

clock signal.

Input Buffer Full

This flag is set to 1 whenever the host system

writes data into the input data register. Setting

this flag activates the FDC37C93xAPM CPU's

nIBF (MIRQ) interrupt if enabled. When the

FDC37C93xAPM’s CPU reads the input data

register (DBB), this bit is automatically reset and

the interrupt is cleared. There is no output pin

associated with this internal signal.

DEFAULT RESET CONDITIONS

The FDC37C93xAPM has one source of reset,

an external reset via the RESET pin. Refer to

Table 56 for the effect of each type of reset on

the internal registers.

140

Table 56 - Resets

HARDWARE RESET (RESET)

DESCRIPTION

KCLK

Weak High

N/A

KDAT

MCLK

MDAT

Host I/F Data Reg

Host I/F Status Reg

RTCCNTRL

RTCADDR

RTCDATA

00H

80H

NC

NC: No Change N/A: Not Applicable

GATEA20 AND KEYBOARD RESET

Port 92 Fast GateA20 and Keyboard Reset

The FDC37C93xAPM provides several options

for GateA20 and Keyboard Reset: 8042

Software Generated GateA20 and KRESET,

Fast GateA20 and KRESET (via Hardware

Speed-up) and Port 92 Fast GateA20 and

KRESET.

Port 92 Register

This port can only be read or written if Port 92

has been enabled via bit 2 of the KRST_GA20

Register (Logical Device 7, 0xF0) set to 1.

This register is used to support the alternate

reset (nALT_RST) and alternate A20 (ALT_A20)

functions.

NAME

Location

PORT 92

92h

Default Value 24h

Attribute

Size

Read/Write

8 bits

141

Table 57 - Port 92 Register

FUNCTION

Reserved. Returns 00 when read.

BIT

7:6

5

Reserved. Returns a 1 when read.

4

Reserved. Returns a 0 when read.

3

Reserved. Returns a 0 when read.

2

Reserved. Returns a 1 when read.

1

ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to

be driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven

high.

0

Alternate System Reset. This read/write bit provides an alternate system reset

function. This function provides an alternate means to reset the system CPU to

effect a mode switch from Protected Virtual Address Mode to the Real Address

Mode. This provides a faster means of reset than is provided by the Keyboard

controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will

cause the nALT_RST signal to pulse acitive (low) for a minimum of 1 µs after a

delay of 500 ns. Before another nALT_RST pulse can be generated, this bit

must be written back to a 0.

Table 58 - nGATEA20

8042

System

P21

0

1

ALT_A20

nA20M

0

1

0

1

0

1

Bit 0 of Port 92, which generates the nALT_RST

signal, is used to reset the CPU under program

The diagram on the following page illustrates

the generation of the nALT_RST function. If

software control is selected, i.e., bit 0 of

KRST_GA20 is set to 0, the reset pulse is

generated by the 8042 upon writing an FE

command to register 64. If hardware speed-up

is selected, i.e., bit 0 of KRST_GA20 is set to 1,

the reset pulse is generated in hardware upon

writing an FE command to register 64.

control.

This signal is AND’ed together

externally with the reset signal (nKBDRST) from

the keyboard controller to provide a software

means of resetting the CPU. This provides a

faster means of reset than is provided by the

keyboard controller. Writing a 1 to bit 0 in the

Port 92 Register causes this signal to pulse low

for a minimum of 6µs after a delay of a

minimum of 14µs. Before another nALT_RST

pulse can be generated, bit 0 must be set to 0

either by a system reset of a write to Port 92.

Upon reset, this signal is driven inactive high (bit

0 in the Port 92 Register is set to 0).

In addition, if Port 92 is enabled, i.e., bit 2 of

KRST_GA20 is set to 1, then a pulse is also

generated by writing a 1 to bit 0 of the Port 92

Register and this pulse is ANDed with the

142

pulse generated above. This pulse is output on

pin KRESET and its polarity is controlled by the

GPI/O polarity configuration.

14us

6us

8042

P20

KRST

MUX

FE

Command

GPI/O Polarity

Config

Pulse

Gen

KRST_GA20

Bit 0

KRESET

KRST_GA20

P92

Bit 2

nALT_RST

Bit 0

Pulse

Gen

14us

Note: When Port 92 is disabled,

writes are ignored and reads

return undefined values.

6us

FIGURE 7 - KRESET GENERATION

Bit 1 of Port 92, the ALT_A20 signal, is used to

force nA20M to the CPU low for support of real

low. Writing a 1 to bit 1 of the Port 92 Register

forces ALT_A20 high. ALT_A20 high drives

nA20M to the CPU high, regardless of the state

of A20GATE from the keyboard controller. Upon

reset, this signal is driven low.

mode compatible software.

This signal is

externally OR’ed with the A20GATE signal from

the keyboard controller and CPURST to control

the nA20M input of the CPU. Writing a 0 to bit 1

of the Port 92 Register forces ALT_A20 low.

ALT_A20 low drives nA20M to the CPU low, if

A20GATE from the keyboard controller is also

The diagram on the following page illustrates

the logic for the generation of the Gate A20

signal.

143

GateA20 Logic

64&nAEN

KRST_GA20

Bit 1

A

nIOW

DD1

nIOW

DFF

DFE

8042

Address

A

KRST_GA20

Bit 0

CPURST

To KRESET Gen

GPI/O Polarity

Config

nAEN&60

A20GATE

nIOW

GA20

MUX

GateA20

DD1

After D1

D[1]

nIOW

KRST_GA20

Bit 1

nAEN&64

nIOW

D

KRST_GA20

Bit 2

nAEN&60

Trailing Edge Delay

ALT_A20

P92

Bit 1

Delay

VCC

Note: When Port 92 is disabled,

writes are ignored and reads

return undefined values.

A

nIOW

24MHz

Note: Use 64 and 60 or the alternate addresses

for command and data ports.

FIGURE 8 - GATEA20 GENERATION LOGIC

The timing for a D1 command write followed by

data write is shown on the following

page. This is the GATEA20 turn-on sequence

shown in the Table “GATE20 Command/Data

Sequence Examples”.

a

144

0ns

250ns

500ns

CLK

AEN

nAEN

64=I/O Addr

n64

nIOW

nA

DD1

nDD1

nCNTL

nIOW'

nIOW+n64

AfterD1

nAfterD1

60=I/O Addr

n60

nIOW+n60=B

nAfterD1+B

D[1]

GA20

FIGURE 9 - GATE A20 TURN-ON SEQUENCE TIMING

When writing to the command and data port

setup time is only required to be met when using

hardware speedup; the data must be valid a

minimum of 0 nsec from the leading edge of

the write and held throughout the entire write

cycle.

with hardware speedup, the IOW timing shown

in the figure titled “IOW Timing for Port 92” in

the Timing Diagrams Section is used. This

145

hardware speed-up feature. GATEA20 from the

chip is part of the control required to mask

address line A20 to emulate 8086 addressing.

FAST GATEA20 AND KEYBOARD RESET

GATEA20/KRESET Hardware Speed-Up

GATEA20 and KRESET is configured via a byte

at F0 in the keyboard configuration space,

Logical Device 7. The byte is defined below.

The FDC37C93xAPM contains on-chip logic

support for the GATEA20 and KRESET

Table 59 - GATEA20/KRESET

REG INDEX DESCRIPTION

0xF0

NAME

STATE

KRST_GA20

Bits[7:3] Reserved

C

Bit[2] Port 92 Select

= 0 Port 92 Disabled

= 1 Port 92 Enabled

Bit[1] GATEA20 Select

= 0 8042 Software Control

= 1 Hardware Speed-up

Bit[0] KRESET Select

= 0 8042 Software Control

= 1 Hardware Speed-up

When the chip receives a "D1" command

followed by data (via the host interface), the on-

chip hardware copies the value of data bit 1 in

the received data field to the GATEA20 host

latch. It also copies the value of D[0] to

KRESET latch. At no time during this host-

interface transaction will PCOBF or the IBF flag

(bit 1) in the Status register be activated; i.e.,

this host control of GATEA20 is transparent to

firmware, with no consequent degradation of

overall system performance. Table 60 details

the possible GATEA20 sequences and the chip

responses.

On VCC1 POR, GATEA20 and KRESET pins

will float.

GATEA20 comes from either the software

control or hardware speed-up and they are

mutually exclusive.

If Port 92 is enabled,

GATEA20 from one of these two are merged

along with Port 92. See Port 92 Section.

KRESET comes from either the software control

or hardware speed-up and they are mutually

exclusive. If Port 92 is enabled, KRESET from

one of these two are merged along with Port 92.

See Port 92 Section.

146

Table 60 - GATEA20 Command/Data Sequence Examples

IBF

SA2

R/W

D[0:7]

FLAG

GATEA20

COMMENTS

1

0

1

0

1

0

1

0

1

W

D1

D[1]=1

FF

D1

D[1]=0

FF

D1

D[1]=1

FF

D1

D[1]=0

FF

D1

XX**

FF

0

1

Q

1

Q

0

Q

1

Q

0

GATEA20 Turn-on Sequence

GATEA20 Turn-off Sequence

GATEA20 Turn-on Sequence(*)

GATEA20 Turn-off Sequence(*)

Invalid Sequence

Q

Notes:

"Q" indicates the bit remains set at the previous state.

*Not a standard sequence.

**XX = Anything except D1.

If multiple data bytes, set IBF and wait at state 0. Let the software know something unusual

happened.

For data bytes SA2=0, only D[1] is used; all other bits are don't care.

The polarity control bit for GPI/O controls the polarity of GATEA20.

Table 61 below details the possible KRESET sequences and the chip responses.

Table 61 - KRESET Command/Data Sequence Examples

IBF

SA2

R/W

D[0:7]

FLAG

COMMENTS

1

W

FE

0

Pulse KRESET

When an FE command is received, pulse

KRESET. KRESET is pulsed low for

The polarity control bit for GPI/O controls the

polarity of KRESET.

a

minimum of 6µs pulse width after a minimum of

a 14µs delay.

147

RTC Reset

REAL TIME CLOCK

The clock, calendar, or RAM functions are not

affected by the system reset (RESET_DRV

active). When the RESET_DRV pin is active

(i.e., system reset) and the battery voltage is

above 1 volt nominal, the following occurs:

The Real Time Clock is a complete time of day

clock with two alarms, calendar (up to the year

9999), a programmable periodic interrupt, and a

programmable square wave generator.

Features

1. Periodic Interrupt Enable (PIE) is cleared to

0.

2. Alarm Interrupt Enable (AIE) bit is cleared

to 0.

3. Update Ended Interrupt Enable (UIE) bit is

cleared to 0.

4. Update Ended Interrupt Flag (UF) bit is

cleared to 0.

5. Interrupt Request Status Flag (IRQF) bit is

cleared to 0.

6. Periodic Interrupt Flag (PIF) is cleared to 0.

7. The RTC and CMOS registers are not

accessable.

·

Counts seconds, minutes, and hours of the

day.

Counts days of the week, date, month, year

and century.

·

Time of Day Alarm

Time Of Century Wake-Up Alarm

Binary or BCD representation of time,

calendar and alarms.

·

Three interrupts

software maskable. (No daylight savings

time!)

-

each is separately

256 Bytes of CMOS RAM.

8. Alarm Interrupt Flag (AF) is cleared to 0.

9. nIRQ pin is in high impedance state.

Port Definition and Description

When RESET_DRV is active and the battery

voltage is below 1 volt nominal, the following

occurs:

OSC

Crystal Oscillator input. Maximum clock

frequency is 32.768 kHz.

1. Registers 00-0D are initialized to 00h.

2. Access to all registers from the host or

FDC37C93xAPM’s CPU (8042) are blocked.

148

RTC Interrupt

to a non-zero value. If IRQ 8 is selected then

the polarity of this IRQ output is

programmable through a bit in the OSC Global

Configuration Register.

8

The interrupt generated by the RTC is an active

high output. The RTC interrupt output remains

high as long as the status bit causing the

interrupt is present and the corresponding

interrupt-enable

bit

is

set.

Activating

INTERNAL REGISTERS

RESET_DRV or reading register C clears the

RTC interrupt.

Table 62A shows the address map of the RTC,

ten bytes of time, calendar, and alarm 1 data,

four control and status bytes and 114 bytes of

"CMOS" registers.

The RTC Interrupt is brought out by

programming the RTC Primary Interrupt Select

Table 62A - Real Time Clock Address Map, Bank 0

ADDRESS

REGISTER TYPE

REGISTER FUNCTION

Register 0: Seconds

0

1

R/W

R

Register 1: Seconds Alarm 1

Register 2: Minutes

2

3

Register 3: Minutes Alarm 1

Register 4: Hours

4

5

Register 5: Hours Alarm 1

Register 6: Day of Week

Register 7: Date of Month

Register 8: Month

6

7

8

9

Register 9: Year

A

Register A:

B

Register B: (Bit 0 is Read Only)

Register C:

C

D

E-7F

R

Register D:

R/W

Register E-7F: General Purpose

All 14 bytes are directly writable and readable by

the host with the following exceptions:

a. Registers C and D are read only

b. Bit 7 of Register A is read only

c. Bits 0 of Register B is read only

149

Table 62B shows Bank 1, the second bank of

CMOS registers which contains an additional

128 bytes of general purpose CMOS registers.

All 128 bytes are directly writeable and readable

by the host.

Table 62B - Real Time Clock Address Map, Bank 1

ADDRESS

REGISTER TYPE

REGISTER FUNCTION

0-7F

R/W

Register 0-7F: General Purpose

Table 62C shows the address map of Bank 2,

the third bank of CMOS registers, which contain

the registers for the century byte and the second

alarm function.

All 9 bytes are directly writable and readable by

the host.

Table 62C - Real Time Clock Address Map, Bank 2

ADDRESS

REGISTER TYPE

REGISTER FUNCTION

Register 0: Century Byte

40

41

42

43

44

45

46

47

48

R/W

Register 1: Seconds Alarm 2

Register 2: Minutes Alarm 2

Register 3: Hours Alarm 2

Register 4: Day of Week Alarm 2

Register 5: Date of Month Alarm 2

Register 6: Month Alarm 2

Register 7: Year Alarm 2

Register 8: Control Register 1

Note: One or two of the three banks of CMOS

Registers are selected via the RTC Mode

Register (Logical Device 6, 0xF0). Banks 1 and

2 are also relocatable via the RTC Mode

Register and the Secondary Base Address

(CR62 and CR63). See Configuration Section.

and seven alarm 2 bytes can also be in binary

or BCD as shown in Table 63B.

Before initializing the internal registers, the SET

bit in Register B should be set to a "1" to prevent

time/calendar updates from occurring. The

program initializes the ten locations in the binary

or BCD format as defined by the DM bit in

Register B. The SET bit may now be cleared to

allow updates.

Time Calendar and Alarm

The processor program obtains time and

calendar information by reading the appropriate

locations. The program may initialize the time,

calendar and alarm by writing to these locations.

The contents of the ten time, calendar and

alarm 1 bytes can be in binary or BCD as shown

in Table 63A. The contents of the century byte

The 12/24 bit in Register B establishes whether

the hour locations represent 1 to 12 or 0 to 23.

The 12/24 bit cannot be changed without

reinitializing the hour locations. When the 12

150

hour format is selected, the high order bit of the

hours byte represents PM when it is a "1".

The three alarm 1 bytes may be used in two

ways. First, when the program inserts an alarm

time in the appropriate hours, minutes and

seconds alarm locations, the alarm interrupt is

initiated at the specified time each day if the

alarm enable bit is high. The second usage is to

insert a "don't care" state in one or more of three

alarm bytes. The "don't care" code is any

hexadecimal byte from C0 to FF inclusive. That

is the two most significant bits of each byte,

when set to "1" create a "don't care" situation.

An alarm interrupt each hour is created with a

"don't care" code in the hours alarm location.

Similarly, an alarm is generated every minute

with "don't care" codes in the hours and minutes

alarm bytes. The "don't care" codes in all three

alarm bytes create an interrupt every second.

Once per second, the ten time, calendar and

alarm 1 bytes as well as the century byte and

seven alarm 2 bytes are switched to the update

logic to be advanced by one second and to

check for an alarm condition. If any of these

bytes are read at this time, the data outputs are

undefined. The update cycle time is shown in

Table 63. The update logic contains circuitry for

automatic end-of-month recognition as well as

automatic leap year compensation.

151

Table 63A - Time, Calendar and Alarm 1 Bytes

ADD

REGISTER FUNCTION

Register 0: Seconds

BCD RANGE

00-59

BINARY RANGE

00-3B

0

1

2

3

4

Register 1: Seconds Alarm

Register 2: Minutes

Register 3: Minutes Alarm

Register 4: Hours

00-59

00-3B

00-59

00-3B

00-59

00-3B

01-12 am

81-92 pm

00-23

01-0C

81-8C

00-17

(12 hour mode)

(24 hour mode)

5

Register 5: Hours Alarm

(12 hour mode)

01-12 am

81-92 pm

00-23

01-0C

81-8C

00-17

(24 hour mode)

6

7

8

9

Register 6: Day of Week

Register 7: Day of Month

Register 8: Month

01-07

01-31

01-1F

01-12

01-0C

00-63

Register 9: Year

00-99

Table 63B - Century Byte and Alarm 2 Bytes

DECIMAL

RANGE

0-99

ADDRESS

40h

REGISTER FUNCTION

Register 0: Century Byte

Register 1: Seconds Alarm 2

Register 2: Minutes Alarm 2

BCD RANGE BINARY RANGE

00-99

00-59

00-63

00-3B

41h

42h

0-59

00-59

00-3B

12-hr

mode

24-hr

mode

1-12

01-12 AM

81-92 PM

00-23

01-0C AM

81-8C PM

00-17

43h

Register 3: Hours Alarm 2

0-23

44h

45h

46h

47h

Register 4: Day of Week Alarm 2

Register 5: Date of Month Alarm 2

Register 6: Month Alarm 2

1-7

01-07

01-31

01-12

00-99

01-07

01-1F

01-0C

00-63

1-31

1-12

0-99

Register 7: Year Alarm 2

Alarm 2 Function

Alarm 2 can only be used as a wake-up alarm to

turn on power to the system when the system is

powered off. There are two bits used to control

alarm 2. The alarm 2 wake-up function is

enabled via the alarm 2 Enable bit, AL2_EN, in

the Soft Power Enable Register 2. The alarm 2

Remember Enable bit, AL2_REM_EN, in the

RTC Control Register 1, is used to power-up the

152

system upon return of power if the alarm 2 time

has passed during loss of power. These bits

function as follows:

code is set in the year, month, date, day and

hours alarm byte. An alarm is generated every

minute with “don’t care” codes in the year,

month, date, day, hours and minutes alarm

bytes. The “don’t care” codes in all seven alarm

bytes creates an interrupt every second. As a

final example, an alarm is generated every one

of a certain day of the week, i.e., every Friday,

by specifying the “don’t care” code in the year,

month and date of month bytes.

If VTR is present: AL2_EN controls whether or

not alarm 2 is enabled as a wake-up function. If

AL2_EN is set and VTR=5V, the nPowerOn pin

will go active (low) when the date/time is equal

to the alarm 2 date/time and the power supply

will turn on the machine.

If VTR is not present: AL2_REM_EN controls

whether or not Alarm 2 will power-up the system

upon the return of VTR, regardless of the value

of AL2_EN. If AL2_REM_EN is set and VTR=0

at the date/time that Alarm 2 is set for, the

nPowerOn pin will go active (low) as soon as

VTR comes back and the machine will power-

up.

Update Cycle

An update cycle is executed once per second if

the SET bit in Register B is clear and the

DV0-DV2 divider is not clear. The SET bit in the

"1" state permits the program to initialize the

time and calendar bytes by stopping an existing

update and preventing

occurring.

a

new one from

The seven alarm 2 bytes may be used in two

ways. First, when the alarm time is written in

the appropriate year, month, date, day, hours,

minutes, and seconds alarm locations, the

alarm interrupt is initiated at the specified time

on the day of the week, on the date of the

month, in the year if the Alarm 2 Enable bit is

high. The second usage is to insert a “don’t

care” state into one or more of the alarm bytes.

The “don’t care” code is any hexadecimal byte

from C0 to FF inclusive. That is, the two most

significant bits of each byte, when set to “1”

create a “don’t care” situation. An alarm is

generated each year if the year byte is set to a

“don’t care” condition. Similarly, an alarm is

generated every month with “don’t care” codes

in the year and month bytes. An alarm is

generated on every day of every month of every

year with “don’t care” codes in the year, month,

date of month and day of week bytes. An alarm

is generated each hour, every day of the month,

every month, every year when the “don’t care”

The primary function of the update cycle is to

increment the seconds byte, check for overflow,

increment the minutes byte when appropriate

and so forth through to the year of the century

byte. The update cycle also compares each

alarm byte with the corresponding time byte and

issues an alarm if a match or if a "don't care"

code is present.

The length of an update cycle is shown in Table

58. During the update cycle the time, calendar

and alarm bytes are not accessible by the

processor program. If the processor reads these

locations before the update cycle is complete

the output will be undefined. The UIP (update in

progress) status bit is set during the interval.

When the UIP bit goes high, the update cycle

will begin 244 us later. Therefore, if a low is read

on the UIP bit the user has at least 244ms before

time/calendar data will be changed.

153

Table 64 - Update Cycle Time

INPUT CLOCK

FREQUENCY

MINIMUM TIME

UPDATE CYCLE

UIP BIT

UPDATE CYCLE TIME

32.768 kHz

1

0

-

1948 ms

-

244 ms

CONTROL AND STATUS REGISTERS, BANK

0

times when Bank 0 is enabled, even during the

update cycle.

Bank 0 of the RTC has four registers which are

accessible to the processor program at all

REGISTER A (AH)

MSB

LSB

b7

b6

b5

b4

b3

b2

b1

b0

UIP

DV2

DV1

DV0

RS3

RS2

RS1

RS0

UIP

also used to reset the divider chain. When the

time/calendar is first initialized, the program

may start the divider chain at the precise time

stored in the registers. When the divider reset is

removed the first update begins one-half second

later. These three read/write bits are not affected

by RESET_DRV.

The update in progress bit is a status flag that

may be monitored by the program. When UIP is

a "1" the update cycle is in progress or will soon

begin. When UIP is a "0" the update cycle is not

in progress and will not be for at least 244us.

The time, calendar, and alarm information is

fully available to the program when the UIP bit is

zero. The UIP bit is a read only bit and is not

affected by RESET_DRV. Writing the SET bit in

Register B to a "1" inhibits any update cycle and

then clears the UIP status bit. The UIP bit is

only valid when the RTC is enabled. Refer to

Table 64.

RS3-0

The four rate selection bits select one of 15 taps

on the divider chain or disable the divider

output. The selected tap determines rate or

frequency of the periodic interrupt. The program

may enable or disable the interrupt with the PIE

bit in Register B. Table 66 lists the periodic

interrupt rates and equivalent output frequencies

that may be chosen with the RS0-RS3 bits.

These four bits are read/write bits which are not

affected by RESET_DRV.

DV2-0

Three bits are used to permit the program to

select various conditions of the 22 stage divider

chain. Table 65 shows the allowable

combinations. The divider selection bits are

154

Table 65 - Divider Selection Bits

REGISTER A BITS

OSCILLATOR

FREQUENCY

DV2

DV1

DV0

MODE

32.768 KHz

0

1

0

1

0

1

0

1

0

1

X

Oscillator Disabled

Normal Operate

Test

Reset Driver

Table 66 - Periodic Interrupt Rates

32.768 kHz TIME BASE

RATE SELECT

PERIOD RATE OF

INTERRUPT

FREQUENCY OF

INTERRUPT

RS3

0

RS2

0

RS1

0

RS0

0

0.0

0

1

3.90625 ms

7.8125 ms

122.070 us

244.141 us

488.281 us

976.562 us

1.953125 ms

3.90625 ms

7.8125 ms

15.625 ms

31.25 ms

62.5 ms

256 Hz

128 Hz

8.192 kHz

4.096 kHz

2.048 kHz

1.024 kHz

512 Hz

256 Hz

128 Hz

64 Hz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32 Hz

1

0

16 Hz

1

0

1

125 ms

8 Hz

1

0

250 ms

4 Hz

1

500 ms

2 Hz

155

REGISTER B (BH)

MSB

LSB

b0

b7

b6

PIE

b5

b4

b3

b2

b1

SET

AIE

UIE

RES

DM2

24/12

DSE

"0". The AIE bit is not affected by any internal

functions.

SET

When the SET bit is a "0", the update functions

normally by advancing the counts once per

second. When the SET bit is a "1", an update

cycle in progress is aborted and the program

may initialize the time and calendar bytes

without an update occurring in the middle of

initialization. SET is a read/write bit which is

not modified by RESET_DRV or any internal

functions.

UIE

The update-ended interrupt enable bit is a

read/write bit which enables the update-end flag

(UF) bit in Register C to assert IRQB. The

RESET_DRV port or the SET bit going high

clears the UIE bit.

RES

PIE

Reserved - read as “0”.

The periodic interrupt enable bit is a read/write

bit which allows the periodic-interrupt flag (PF)

bit in Register C to cause the IRQB port to be

driven low. The program writes a "1" to the PIE

bit in order to receive periodic interrupts at the

rate specified by the RS3-RS0 bits in Register

A. A zero in PIE blocks IRQB from being

initiated by a periodic interrupt, but the periodic

flag (PF) is still set at the periodic rate. PIE is

not modified by any internal function, but is

cleared to "0" by a RESET_DRV.

DM

The data mode bit indicates whether time and

calendar updates are to use binary or BCD

formats. The DM bit is written by the processor

program and may be read by the program,

but is not modified by any internal functions

or by RESET_DRV.

binary data, while a "0" in DM specifies BCD

data.

A

"1" in DM signifies

24/12

AIE

The 24/12 control bit establishes the format of

the hours byte as either the 24 hour mode if

set to a "1", or the 12 hour mode if cleared to

a "0". This is a read/write bit which is not

affected by RESET_DRV or any internal

function.

The alarm interrupt enable bit is a read/write bit,

which when set to a "1" permits the alarm flag

(AF) bit in Register C to assert IRQB. An

alarm interrupt occurs for each second that the

three time bytes equal the three alarm bytes

(including a "don't care" alarm code of binary

11XXXXXX). When the AIE bit is a "0", the AF

bit does not initiate an IRQB signal. The

DSE

The daylight savings enable bit is read only and

is always set to a "0" to indicate that the daylight

savings time option is not available.

RESET_DRV

port

clears

AIE

to

156

REGISTER C (CH) - READ ONLY REGISTER

MSB

LSB

b0

0

b7

b6

b5

b4

b3

0

b2

0

b1

0

IRQF

PF

AF

UF

IRQF

AF

The interrupt request flag is set to a "1" when

one or more of the following are true:

The alarm interrupt flag when set to a "1"

indicates that the current time has matched the

alarm time. A "1" in AF causes a "1" to appear in

IRQF and the IRQB port to go low when the AIE

bit is also a "1". A RESET_DRV or a read of

Register C clears the AF bit.

PF = PIE = 1

AF = AIE = 1

UF = UIE = 1

Any time the IRQF bit is a "1", the IRQB signal

is driven low. All flag bits are cleared after

Register C is read or by the RESET_DRV port.

UF

The update-ended interrupt flag bit is set after

each update cycle. When the UIE bit is also a

"1", the "1" in UF causes the IRQF bit to be set

and asserts IRQB. A RESET_DRV or a read of

Register C causes UF to be cleared.

PF

The periodic interrupt flag is a read-only bit

which is set to a "1" when a particular edge is

detected on the selected tap of the divider chain.

The RS3 -RS0 bits establish the periodic rate.

PF is set to a "1" independent of the state of

the PIE bit. PF being a "1" sets the IRQF bit

and initiates an IRQB signal when PIE is also a

"1". The PF bit is cleared by RESET_DRV or by

a read of Register C.

b3-0

The unused bits of Register C are read as zeros

and cannot be written.

157

REGISTER D (DH) READ ONLY REGISTER

MSB

LSB

b0

0

b7

b6

0

b5

0

b4

0

b3

0

b2

0

b1

0

VRT

The processor program selects which interrupts,

if any, it wishes to receive by writing a "1" to the

appropriate enable bits in Register B. A "0" in

an enable bit prohibits the IRQB port from being

asserted due to that interrupt cause. When an

interrupt event occurs a flag bit is set to a "1" in

Register C. Each of the three interrupt sources

have separate flag bits in Register C, which are

set independent of the state of the

corresponding enable bits in Register B. The

flag bits may be used with or without enabling

the corresponding enable bits. The flag bits in

Register C are cleared (record of the interrupt

event is erased) when Register C is read.

Double latching is included in Register C to

ensure the bits that are set are stable

throughout the read cycle. All bits which are

high when read by the program are cleared, and

new interrupts are held until after the read cycle.

If an interrupt flag is already set when the

interrupt becomes enabled, the IRQB port is

immediately activated, though the interrupt

initiating the event may have occurred much

earlier.

VRT

When a "1", this bit indicates that the contents

of the RTC are valid. A "0" appears in the VRT

bit when the battery voltage is low. The VRT bit

is read only bit which can only be set by a read

of Register D. Refer to Power Management for

the conditions when this bit is reset. The

processor program can set the VRT bit when the

time and calendar are initialized to indicate that

the time is valid.

b6:b0

The remaining bits of Register D are read as

zeros and cannot be written.

Register EH-FFH: General purpose

Registers Eh-FFH are general purpose CMOS

registers. These registers can be used by the

host or 8042 and are fully available during the

time update cycle.

registers are preserved by the battery power.

The contents of these

INTERRUPTS

When an interrupt flag bit is set and the

corresponding interrupt-enable bit is also set,

the IRQB port is driven low. IRQB is asserted as

long as at least one of the three interrupt

sources has its flag and enable bits both set.

The IRQF bit in Register C is a "1" whenever the

IRQB port is being driven low.

The RTC includes three separate fully-

automatic sources of interrupts to the processor.

The alarm interrupt may be programmed to

occur at rates from one-per-second to

one-a-day.

The periodic interrupt may be

selected for rates from half-a-second to 122.070

ms. The update ended interrupt may be used

to indicate to the program that an update cycle

is completed.

Each of these independent

interrupts are described in greater detail in

other sections.

158

Control Registers, Bank 2

CONTROL REGISTER 1

Default is 0; cleared upon Vbat POR. This

register is battery backed-up.

Bank 2 of the RTC has one control register.

D7

0

D6

0

D5

0

D4

0

D3

0

D2

VTR_POR

_EN

D1

0

D0

AL2_REM

_EN

Frequency Divider

AL2_REM_EN - One of the two control bits for

the Alarm wakeup function; it is the

2

The RTC has 22 binary divider stages following

the clock input. The output of the divider is a 1

Hz signal to the update-cycle logic. The divider

is controlled by the three divider bits (DV3-DV0)

in Register A. As shown in Table 65 the divider

control bits can select the operating mode or

be used to hold the divider chain reset which

allows precision setting of the time. When the

divider chain is changed from reset to the

operating mode, the first update cycle is

one-half second later. The divider control bits

are also used to facilitate testing of the RTC.

“remember” enable bit for the second alarm.

This bit, if set to 1, wil cause the system to

power-up upon return of power if the Alarm 2

time has passed during loss of power. It is only

applicable when VTR=0. This bit is independent

of the other control bit for the Alarm 2 wake-up

function, Al2_EN (bit 4 of the Soft Power Enable

Register 2) which controls Alarm 2 when

VTR=5V. See the Alarm 2 Function Section for

more information. The function of Bit 0 is

summarized as follows:

If AL2_REM_EN is set and VTR=0 at the

date/time that Alarm 2 is set for, the nPowerOn

pin will go active (low) and the machine will

power-up as soon as VTR comes back.

Periodic Interrupt Selection

The periodic interrupt allows the IRQB port to be

triggered from once every 500 ms to once every

122.07 ms. As Table 66 shows, the periodic

interrupt is selected with the RS0-RS3 bits in

Register A. The periodic interrupt is enabled

with the PIE bit in Register B.

VTR POR - The enable bit for VTR POR. If

VTR_POR_EN is set, the nPowerOn pin will go

active (low) and the machine will power-up as

soon as a VTR POR occurs.

159

1. The Divider Chain Controls (bits 6-4) are in

any mode but Normal Operation ("010").

2. The VRT bit is a "0".

3. When battery voltage is below 1 volt

nominal and RESET_DRV is a "1". This

will also initialize all registers 00-0D to a

"00".

Power Supply Operational Modes

Note: See the Operational Description Section

for the Power Supply Operational Modes.

Power Management

The RAMD signal controls all bus inputs to the

RTC and RAM (nIOW, nIOR, RESET_DRV).

When asserted, it disallows any modification of

the RTC and RAM data by the host or 8042.

RAMD is asserted whenever: V_CCis below 4.0

volts nominal.

To minimize power consumption, the oscillator

is not operational under the following conditions:

1. The Divider Chain Controls (bits 6-4) are in

Oscillator Disabled mode (000, or 001).

2. If VTR and V_CC=0 and the battery power is

removed and then re-applied (a new battery

is installed) the following occurs:

When the VTR voltage drops below the battery

voltage, the RTC switches to battery power.

When VTR rises above the battery voltage, the

RTC switches back to VTR power.

a. The oscillator is disabled immediately.

b. Initialize all registers 00-0D to a "00"

when V_CCis applied.

When the V_CCvoltage drops below 4.0 volts

nominal, all inputs are locked out so that the

internal registers cannot be modified by the

system. This lockout condition continues for 62

msec (min) to 125 msec (max) after the system

power has been restored. The 62 msec lockout

does not occur under the following conditions:

If the battery voltage is between 1 volt nominal

and 2.4 volt nominal when V_CCis applied:

1. Clear VRT bit to "0". Maintain all other RTC

bits in the state as before V_CCwas applied

V_CC

<4.0

>4.0

HYSTER

BATTERY

REGISTER ACCESS

1

0

1

x

N

Y

Hyster=1 implies that V_CC<4.0 volts +/-0.25V; Hyster=0 implies that V_CC>4.0

volts +/-0.25V.

160

SOFT POWER MANAGEMENT

The FDC37C93xAPM employs soft power

transition on the Button input or on any of the

enabled wakeup events (SPx) causes the

nPowerOn output to go active low which turns

on the main power supply. Even if the power

supply is completely lost (i.e., VTR is not

present) the power supply can still be turned on

upon the return of VTR by an alarm 2 event that

has already passed (if the alarm 2 remember bit

is enabled) or by a VTR power on reset (if the

VTR POR bit is enabled). These bits are

described in the RTC section.

management to allow the chip to enter low

power mode and to provide a variety of wakeup

events to power up the chip. This technique

allows for software control over powerdown and

wakeup events. In low power mode, the chip

runs off of the trickle voltage, VTR, which is 5

volts at 2mA maximum. In this mode, the chip

is ready to power up from either the power

button or from one of a number of wakeup

events including pressing a key, touching the

mouse or receiving data from one of the UARTs.

The alarm can also be set to power up the

system at a predetermined time to perform one

or more tasks.

The Button input can be used to turn off the

power supply after a debounce delay. The

power supply can also be turned off under

software control (via

a

write to register

The implementation of Soft Power Management

is illustrated in Figure 11. A high to low

WDT_CTRL with bit 7 set).

161

Soft Power Mangement

nBINT

Delay2

OFF_EN

nSPOFF1

Logic

OFF_DLY

Button

nSPOFF

L

VTR_POR_EN

VTR POR

Logic

AL2_REM_EN

Alarm 2

Button Input

ED; PG

ED; L

OFF_DLY

Delay1

SP1

VTR

EN1

Flip

Flop 1

nSPOFF1

nPowerOn

D

Q

CLR

Open Collector

Type output

SPx

ED; L

VBAT POR

ENx

Logic

nSPOFF1

Soft Power

Off nSPOFF1

Override

Timer

PWRBTNOR_STS

PWRBTNOR_EN

A transition on the Button input or on any enabled SPx inputs causes the nPowerOn output to go active low.

A low pulse on the Soft Power Off signal causes the nPowerOn bit to float.

ED;PG = Edge Detect, Pulse Generator

ED;L = Edge Detect and Latch

FIGURE 11 - SOFT POWER MANAGEMENT FUNCTIONAL DIAGRAM

Note 1: All soft power management functions run off of VTR. When VTR is present, it supplies power

to the RTC. When VTR is not present, Vbat supplies power to the RTC and Flip Flop 1.

Note 2: Flip Flop 1 is battery backed-up so that it returns the last valid state of the machine.

Note 3: A battery backed-up enable bit in the alarm control register can be set to force Flip Flop 1 in

the soft power management circuit to come up ‘on’ if an alarm occurred when VTR was not present.

This is gated into wakeup circuitry. Refer to the AL2_REM_EN Bit description in the RTC Control

Register section for more information.

162

This register contains the status for the wake-up

events. Note: The status bit gets set if the

wakeup event occurs, whether or not it is

enabled as a wakeup function by setting the

corresponding bit in Soft Power Enable Register

1. However, only the enabled wakeup functions

will turn on power to the system.

REGISTERS

The following registers can be accessed when in

configuration mode at Logical Device 8,

Registers B0-B3, B8 and F4, and when not in

configuration they can be accessed through the

Index and Data Register.

Soft Power Status Register 2

Soft Power Enable Registers

(Configuration Register B3, Logical Device 8)

This register contains additional status for the

wake-up events. Note: The status bit gets set if

the wakeup event occurs, whether or not it is

enabled as a wakeup function by setting the

corresponding bit in Soft Power Enable Register

2. However, only the enabled wakeup functions

will turn on power to the system.

Soft Power Enable Register 1

(Configuration Register B0, Logical Device 8)

This register contains the enable bits for the

wake-up function of the nPowerOn bit. When

enabled, these bits allow their corresponding

function to turn on power to the system.

Soft Power Enable Register 2

Soft Power Control Registers

(Configuration Register B1, Logical Device 8)

This register contains additional enable bits for

the wake-up function of the nPowerOn bit.

When enabled, these bits allow their

corresponding function to turn on power to the

system. It also contains OFF_EN: After power

up, this bit defaults to 1, i.e., enabled. This bit

allows the software to enable or disable the

button control of power off.

WDT_CTRL

(Configuration Register F4, Logical Device 8)

This register is used for soft power management

and watchdog timer control. Bits[7:5] are for soft

power management: SPOFF, Restart_Cnt,

Stop_Cnt.

Delay 2 Time Set Register

(Configuration Register B8, Logical Device 8)

This register is used to set Delay 2 to value from

500msec to 32sec. The default value is

500msec.

Soft Power Status Registers

Soft Power Status Register 1

(Configuration Register B2, Logical Device 8)

163

The power button has an override event as

required by the ACPI specification. If the user

presses the power button for more than four

seconds while the system is in the working

state, a hardware event is generated and the

system will transition to the off state. There are

status and enable bits associated with this

feature in the PM1_BLK registers. See the ACPI

section.

to turn off the system. The override status bit

alerts the system upon power-up that an

override event was used to power down the

system, and will be used to properly power-up

the system.

Figure 11 shows the soft power management

logic with the override timer path from the

button input. The override timer counts while

the button is held (in the present implementation

this would be when the button input is high) and

is cleared upon release of the button. It has a

0.5 second or faster resolution (run off of the

32kHz clock divided down) and the minimum

time for triggering the override power down is

four seconds, with a maximum of 4.5 seconds.

The timer output will pulse the clear on the Flip

Flop 1.

This override event utilizes power button logic to

determine that the power button (Button_In) has

been pressed for more that four seconds. The

override enable/disable bit, PWRBTNOR_EN,

allows this override function to be turned on/off.

If enabled, this override event will result in

setting

the

override

status

bit,

PWRBTNOR_STS (to be cleared by writing a 1

to its bit position - writing a 0 has no effect),

clearing the regular button status bit,

PWRBTN_STS, and generating an event to be

routed into the soft power management logic

Figure 12 illustrates the timing of the blanking

period relative to Button_In and nPowerOn for

the override event.

Button_In

nPowerOn

4+

sec

Release

4 sec

Blanking Period

4 sec

V

cc

FIGURE 12 - BLANKING PERIOD

164

SYSTEM MANAGEMENT INTERRUPT (SMI)

The FDC37C93xAPM implements a group nSMI

SMI Enable Registers

output pin. The System Management Interrupt

is a non-maskable interrupt with the highest

priority level used for transparent power

management. The nSMI group interrupt output

consists of the enabled interrupts from each of

the functional blocks in the chip. The interrupts

are enabled onto the group nSMI output via the

SMI Enable Registers 1 and 2. The nSMI output

is then enabled onto the group nSMI output pin

via bit[7] in the SMI Enable Register 2. The

logic equation for the nSMI output is as follows:

SMI Enable Register 1

(Configuration Register B4, Logical Device 8)

This register is used to enable the different

interrupt sources onto the group nSMI output.

SMI Enable Register 2

(Configuration Register B5, Logical Device 8)

This register is used to enable additional

interrupt sources onto the group nSMI output.

This register is also used to enable the group

nSMI output onto the nSMI GPI/O pin and the

routing of 8042 P12 internally to nSMI.

nSMI =

(EN_IDE1

(EN_PINT

and

IRQ_IDE1)

IRQ_PINT)

or

(EN_U2INT and IRQ_U2INT) or

(EN_U1INT and IRQ_U1INT) or

(EN_FINT

and

IRQ_FINT)

or

SMI Status Registers

(EN_GPINT2 and IRQ_GPINT2) or

(EN_GPINT1 and IRQ_GPINT1) or

SMI Status Register 1

(EN_WDT

(EN_MINT

(EN_KINT

(EN_IRINT

(EN_BINT

and

IRQ_WDT)

IRQ_MINT)

IRQ_KINT)

IRQ_IRINT)

iRQ_BINT)

or

(Configuration Register B6, Logical Device 8)

This register is used to read the status of the

SMI input events. Note: The status bit gets set

whether or not the interrupt is enabled onto the

group SMI output.

(EN_ABINT and IRQ_ABINT)

SMI Status Register 2

(Configuration Register B7, Logical Device 8)

This register is used to read the status of the

SMI input events. Note: The status bit gets set

whether or not the interrupt is enabled onto the

group SMI output.

REGISTERS

The following registers can be accessed when in

configuration mode at Logical Device 8,

Registers B4-B7 and when not in configuration

they can be accessed through the Index and

Data Register.

165

ACCESS.bus

The FDC37C93xAPM supports ACCESS.bus.

device driver interface, and several specific

device protocols.

ACCESS.bus is a serial communication protocol

between a computer host and its peripheral

devices. It provides a simple, uniform and

inexpensive way to connect peripheral devices

to a single computer port. A single ACCESS.bus

For a description of the ACCESS.bus protocol,

please refer to the ACCESS.bus Specifications

Version 2.2, February 1994, available from the

ACCESS.bus Industry Group.

on

a host can accommodate up to 125

peripheral devices.

The ACCESS.bus interface is based on the

PDC8584 controller. The registers are mapped

into the ISA I/O register space as set by the

configuration registers. The addresses for the

registers are shown in Table 67.

The ACCESS.bus protocol includes a physical

layer based on the I²C serial bus developed by

Philips, and several software layers.

The

software layers include the base protocol, the

Table 67 - ACCESS.bus Register Addresses

ADDRESS*

Base+0

Base+1

REGISTER

Control/Status

Own Address

Data

Base+2

Base+3

Clock

Note 1: Base I/O Range: [0x00:0x0FFC] on 4 byte boundaries

ACCESS.bus. Register

S1

contains

REGISTERS

ACCESS.bus status information required for bus

access and or monitoring.

The ACCESS.bus interface has four internal

register locations. Two of these, Own Address

Register S0 and Clock Register S2, are used for

initialization of the chip. Normally they are only

written once directly after resetting of the chip.

The other two registers, the Data Shift Register

S0 and the Control/Status Register S1 (which

functions as a double register), are used during

actual data transmission/reception. Register S0

performs all serial-to-parallel interfacing with the

ACCESS.bus Control/Status Register S1

The control/status register controls the

ACCESS.bus operation and provides status

information. This register has separate read and

write functions for all bit positions. The write-

only section provides register access control

and control over ACCESS.bus signals, while the

read-only section provides ACCESS.bus status

information.

166

Table 68 - ACCESS.BUS Control/Status Register S1:

Control

R/W

D7

W

D6

D5

D4

D3

D2

D1

W

D0

W

Bit Def

ES0

Reserved

ENI

STA

STO

ACK

Status

R/W

D7

R

D6

R

D5

R

D4

R

D3

R

D2

R

D1

R

D0

R

Bit Def

0

STS

BER

LRB

AAS

LAB

nBB

communication with serial shift register S0 is

enabled and the S1 bus status bits are made

available for reading. With ESO = 0, bits ENI,

STA, STO and ACK of S1 can be read for test

purposes.

Bit Definitions

Register S1 Control Section

The write-only section of S1 enables access to

registers S0, S0’, S1 and S2, and controls

ACCESS.bus operation.

BITS 5 and 4: Reserved

BIT 3: ENI

BIT 7: PIN

This bit enables the internal interrupt, nINT,

which is generated when the PIN bit is active

(logic “0”).

Pending Interrupt Not. When the PIN bit is

written with a logic 1, all status bits are reset to

logic 0, with the exception of PIN which is set to

1, and nBB which is not affected. This may

serve as a software reset function.

BITS 2 and 1: STA and STO

These bits control the generation of the

ACCESS.bus

START

condition

and

BIT 6: ESO

transmission of slave address and R/nW bit,

generation of repeated START condition, and

generation of the STOP condition (see Table 69)

Enable Serial Output. ESO enables or disables

the serial ACCESS.bus I/O. When ESO is high,

ACCESS.bus communication is enabled;

Table 69 - Instruction Table for Serial Bus Control

STA

1

STO

0

PRESENT MODE

FUNCTION

START

OPERATION

Transmit START+address, remain

MST/TRM if R/nW=0; go to MST/REC if

R/nW=1

SLV/REC

1

0

1

MST/TRM

MST/REC;

MST/TRM

MST

REPEAT START Same as for SLV/REC

STOP READ;

STOP WRITE

Transmit STOP go to SLV/REC mode;

Note 1

1

0

1

0

DATA CHAINING Send STOP, START and address after

last master frame without STOP sent;

Note 2

ANY

NOP

No operation; Note 3

167

Note 1: In master receiver mode, the last byte

must be terminated with ACK bit high (‘negative

acknowledge’)

also set to logic “1” (inactive) each time S0 is

written. In receiver mode, the PIN bit is

automatically set to logic “1” each time the data

register S0 is read.

Note 2: If both STA and STO are set high

simultaneously in master mode,

condition followed by a START condition +

address will be generated. This allows

‘chaining’ of transmissions without relinquishing

bus control.

a

STOP

After transmission or reception of one byte on

the ACCESS.bus (9 clock pulses, including

acknowledge) the PIN bit will be automatically

reset to logic “0” (active) indicating a complete

byte transmission/reception. When the PIN bit

is subsequently set to logic “1” (inactive), all

status bits will be reset to “0” on a BER (bus

error) condition.

Note 3: All other STA and STO mode

combinations not mentioned in Table 69 are

NOPs.

In polled applications, the PIN bit is tested to

determine when a serial transmission/reception

has been completed. When the ENI bit (bit 4 of

write-only section of register S1) is also set to

logic 1 the hardware interrupt is enabled. In this

case, the PI flag also triggers and internal

interrupt (active low) via the nINT output each

time PIN is reset to logic “0”.

BIT 0: ACK

This bit must be set normally to logic “1”. This

causes the ACCESS.bus to send an

acknowledge automatically after each byte (this

occurs during the ninth clock pulse) . The bit

must be reset (to logic 0) when the

ACCESS.bus controller is operating in

master/receiver mode and requires no further

data to be sent from the slave transmitter. This

When acting as a slave transmitter or slave

receiver, while PIN=“0”, the chip will suspend

ACCESS.bus transmission by holding the SCL

line low until the PIN bit is set to logic “1”

(inactive). This prevents further data from being

transmitted or received until the current data

byte in S0 has been read (when acting as slave

receiver) or the next data byte is written to S0

(when acting as slave transmitter).

causes

a

negative acknowledge on the

ACCESS.bus, which halts further transmission

from the slave device.

Register S1 Status Section

The read-only section of S1 enables access to

ACCESS.bus status information.

PIN bit summary:

BIT 7: PIN

(Pending Interrupt Not)

·

The PIN bit can be used in polled

applications to test when serial

This bit is a status flag which is used to

synchronize serial communication and is set to

logic “0” whenever the chip requires servicing.

The PIN bit is normally read in polled

applications to determine when an ACCESS.bus

byte transmission/reception is completed.

a

transmission has been completed. When

the ENI bit is also set, the PIN flag sets the

internal interrupt via the nINT output.

Setting the STA bit (start bit) will set

PIN=“1” (inactive).

In transmitter mode, after successful

transmission of one byte on the

ACCESS.bus the PIN bit will be

·

Each time a serial data transmission is initiated

(by setting the STA bit in the same register) the

PIN bit will be set to logic “1” automatically

(inactive). When acting as transmitter, PIN is

168

automatically reset to logic “0” (active)

indicating a complete byte transmission.

In transmitter mode, PIN is set to logic “1”

(inactive) each time register S0 is written.

In receiver mode, PIN is set to logic “0”

(inactive) on completion of each received

byte. Subsequently, the SCL line will be

held low until PIN is set to logic “1”.

In receiver mode, when register S0 is read,

PIN is set to logic “1” (inactive).

In slave receiver mode, an ACCESS.bus

STOP condition will set PIN=“0” (active).

PIN= “0” if a bus error (BER) occurs.

2. ADO; when AAS=“1” (Addressed as slave

condition) the ACCESS.bus controller has

been addressed as a slave. Under this

condition, this bit becomes the AD0 bit and

will be set to logic “1” if the slave address

received was the ‘general call’ (00h)

address, or logic “0” if it was the

·

ACCESS.bus

address.

controller’s

own

slave

·

BIT 2: AAS

Addressed As Slave bit.

Valid only when

PIN=“0”. When acting as slave receiver, this

flag is set when an incoming address over the

ACCESS.bus matches the value in own address

register S0’ (shifted by one bit) or if the

ACCESS.bus ‘general call’ address (00h) has

been received (‘general call’ is indicated when

AD0 status bit is also set to logic “1”).

BIT 6: Logic 0

BIT 5: STS

When in slave receiver mode, this flag is

asserted when an externally generated STOP

condition is detected (used only in slave receiver

mode).

BIT 1: LAB

Lost Arbitration Bit. This bit is set when, in

multi-master operation, arbitration is lost to

another master on the ACCESS.bus.

BIT 4: BER

Bus error;

a misplaced START or STOP

condition has been detected. Resets nBB (to

logic “1”; inactive), sets PIN= “0” (active).

Bit 0: nBB

Bus Busy bit.

This is a read-only flag indicating when the

ACCESS.bus is in use. A “0” indicates that the

bus is busy and access is not possible. This bit

is set/reset (logic “1”/logic “0”) by START/STOP

conditions.

BIT 3: LRB/AD0

Last Received Bit or Address 0 (general call) bit.

This status bit serves a dual function, and is

valid only while PIN= “0”.

1. LRB holds the value of the last received bit

over the ACCESS.bus while AAS=“0” (not

addressed as slave). Normally this will be

the value of the slave acknowledgment;

thus checking for slave acknowledgment is

done via testing of the LRB.

169

when this address is received (the value in S0 is

compared with the value in S0’). Note that the

S0 and S0’ registers are offset by one bit;

hence, programming the own address register

S0’ with a value of 55h will result in the value

AAh being recognized as the chip’s

ACCESS.bus slave address.

Own Address Register S0’

When the chip is addressed as slave, this

register must be loaded with the 7-bit

ACCESS.bus address to which the chip is to

respond. During initialization, the own address

register S0’ must be written to, regardless

whether it is later used. The Addressed As

Slave (AAS) bit in status register S1 is set

After reset, S0’ has default address 00h.

D7

R/W

D6

R/W

D5

R/W

D4

R/W

D3

R/W

D2

R/W

D1

R/W

D0

R/W

Reserved

Slave

Address

6

Slave

Address

5

Slave

Address

4

Slave

Address

3

Slave

Address

2

Slave

Address

1

Slave

Address

0

In receiver mode the ACCESS.bus data is

shifted into the shift register until the

acknowledge phase. Further reception of data

is inhibited (SCL held low) until the S0 data shift

register is read.

Data Shift Register S0

Register S0 acts as serial shift register and read

buffer interfacing to the ACCESS.bus. All read

and write operations to/from the ACCESS.bus

are done via this register. ACCESS.bus data is

always shifted in or out of shift register S0.

In the transmitter mode data is transmitted to

the ACCESS.bus as soon as it is written to the

S0 shift register if the serial I/O is enabled

(ESO=1).

D7

D6

D5

D4

D3

D2

D1

D0

R/W

170

Clock Register S2

ACCESS.bus block. This determines the SCL

clock frequency generated by the chip. The

selection is made via Bits[2:0] (see Table 70).

Register S2 controls the selection of the internal

chip

clock

D7

AB RST

frequency

used

for

the

D6

D5

R

D4

D3

D2

D1

R/W

D0

RESERVED

See Table 70

Default = 00 at hard reset and power on reset.

entire ACCESS.bus block. Not self-clearing,

must be written high and then written low.

BIT 7: AB_RST

ACCESS.bus Reset Bit. This bit resets the

Table 70 - Internal Clock Rates and ACCESS.bus Data Rates in the FDC37C93xAPM

ACCESS BUS

CLOCK

REGISTER D[2:0]

CLOCK

RATE

DATA

RATE

NOMINAL

HIGH

NOMINAL MINIMUM

LOW

HIGH

000

001

010

011

100

101

110

Off

12MHz

14.318 MHz

16MHz

24MHz

50kHz

60kHz

67kHz

100kHz

8ms

6.7ms

6ms

12ms

10.1ms

9ms

4ms

6ms

171

ADVANCED CONFIGURATION AND POWER INTERFACE

The FDC37C93xAPM supports the Advanced

Configuration and Power Interface (ACPI) as

described in this section.

The SCI enable and status registers are run-

time registers which have the same interrupt

event enable and status bits as the SMI

registers. The SCI registers are contained in the

MSC_BLK. Logical Device A will hold the

address pointers to the ACPI power

management register block, PM1_BLK, and the

Miscellaneous register block, MSC_BLK.

LEGACY/ACPI SELECT CAPABILITY

This capability consists of an SMI/SCI switch

which is required if the system supports both

legacy and ACPI power management models.

This is due to the fact that the system software

for legacy power management consists of the

SMI interrupt handler while for ACPI it consists

of the ACPI driver (SCI interrupt handler). This

support uses Logical Device A at 0x0A to hold

the address pointers to the ACPI power

management register block, PM1_BLK, and the

Miscellaneous register block, MSC_BLK. These

The SCI pin is the second alternate function

added to pin 97, with the resulting pin having the

multiple functions GP11/IRQIN/IRQ13. The

configuration register for this pin (0xE1) allows

polarity control and selection of open collector

for this interrupt. The nSMI output pin is the

second alternate function of pin 31 in the

FDC37C93xAPM.

are run-time registers.

Contained in the

The SCI interrupt can be routed to any of the

dedicated interrupt request pins, IRQ[1,3:15].

The SCI interrupt is active low open collector for

all of these IRQ pins. Note that the SCI

interrupt is the only one routed to IRQ13 and its

polarity and output type is selected through

configuration register 0xE1.

MSC_BLK are SCI enable and status registers

which will allow the SMI interrupt events to be

enabled as SCI interrupt events. Included in the

PM1_BLK is an enable bit to allow the SCI

group interrupt to be switched out to SCI

interrupt 13 (pin 97, IRQ13) or routed to one of

the dedicated interrupts.

GLOBAL STATUS AND BIOS STATUS

The software power management events (those

that generate an SMI in legacy mode and an

SCI in ACPI mode) are controlled by the

EN_SMI and SCI_EN bits. For legacy power

management, the EN_SMI bit is used; if set, it

routes the power management events to the

Figure 13 shows the process of generating an

interrupt from SMI to SCI and SCI to SMI. This

figure shows the bits involved in this process.

The GBL_EN, GBL_STS and GBL_RLS bits are

located in the PM1_BLK registers.

The

SMI interrupt logic.

For ACPI power

BIOS_RLS, BIOS_EN and BIOS_STS bits are

located in the MISC_BLK registers. These bits

are described below.

management, the SCI_EN bit is used; if set, it

routes the power management events to the SCI

interrupt logic.

The BIOS_RLS bit is used by the BIOS to raise

an event to the ACPI software. GBL_EN and

GBL_STS are the corresponding enable and

status bits used by ACPI software to control its

ability to receive SCI events. Setting BIOS_RLS

The SCI enable bit, SCI_EN, is located in the

PM1_CNTRL register, bit 0. This bit is used in

conjunction with EN_SMI, bit 7 of the SMI

enable register 2, to enable either SCI or SMI (or

both).

sets GBL_STS.

If GBL_EN is set and

BIOS_RLS is set an SCI is raised. BIOS_RLS is

172

set by writing “1” to its bit location; it is cleared

by writing a “1” to the GBL_STS bit. Writing a

“0” to BIOS_RLS has no effect. Writing a “0” to

GBL_STS has no effect.

status bits used by the BIOS to control its ability

to receive ACPI events. Setting GBL_RLS sets

BIOS_STS. If BIOS_EN is set and GBL_RLS

is set an SMI is raised. GBL_RLS is set by

writing a “1” to its bit location; it is cleared by

writing a “1” to the BIOS_STS bit. Writing a “0”

to GBL_RLS has no effect. Writing a “0” to

BIOS_STS has no effect.

The GBL_RLS bit is used by the ACPI software

to raise an event to the BIOS. BIOS_EN and

BIOS_STS are the corresponding enable and

SMI to SCI

Clears

GBL_STS

BIOS_RLS

GBL_EN

To SCI Logic

SCI to SMI

Clears

BIOS_STS

GBL_RLS

BIOS_EN

To SMI Logic

Enable bit. Software writing this bit HIGH or LOW will result in the bit

being read as HIGH or LOW.

SYMBOL

DEFINITION

Sticky Status Bit. This bit is set by a hardware signal assertion HIGH.

Cleared by software writing a one to its bit position.

Latched on trailing edge of write strobe.

FIGURE 13 - PROCESS OF GENERATING AN INTERRUPT FROM SMI TO SCI AND SCI TO SMI

173

Setting BM_CNTRL sets BM_STS. If BM_RLD

is set and BM_CNTRL is set, an SCI is raised.

BM_CNTRL is set by writing a 1 to its bit

location; it is cleared by writing a “1” to the

BM_STS bit. Writing a “0” to BM_CNTRL has no

effect. Writing a “0” to BM_STS has no effect.

Bus Master

The Bus Master event logic is shown in Figure

14. The BM_RLD and BM_STS bits are located

in the PM1_BLK and BM_CNTRL is located in

the MSC_BLK. These bits are described below.

C lears

B M _ S T S

B M _ C N T R L

B M _ R L D

S C I

FIGURE 14 - BUS MASTER SCI EVENT LOGIC

174

extend the number of bits in the timer, the power

management timer generates an SCI interrupt (if

enabled) when the last bit of the timer changes

from 0 to 1 or 1 to 0. The implementation also

includes a timer enable bit and a timer status

bit. Three additional registers are used to read

the timer value. Figure 15 shows the power

management timer functional diagram.

POWER MANAGEMENT TIMER

This is a 24-bit free running timer that is

required for ACPI compliance.

management timer provides an accurate time

function while the system is in the working state.

This feature is a 24-bit counter which runs off of

a 3.579545 MHz clock. To allow software to

The power

TMR_ON_OFF

TMR_STS

24-bit

Counter

TMR_PME

3.5795454MHz

24

TMR_EN

TMR_VAL

FIGURE 15 - POWER MANAGEMENT TIMER

This circuit has an enable/disable bit to turn the

timer on/off (TMR_ON_OFF, MSC_EN Register,

bit 1). The default of this bit is disabled (off). It

also has a status bit, TMR_STS (PM1_STS

register, bit 0), which is set when the timer

changes from 0 to 1 or 1 to 0 and is cleared by

writing a 1 to its bit location (writing a 0 has no

effect). In addition, it has a bit (TMR_EN,

PM1_EN register, bit 0) to enable the power

management event, TMR_PME, as an SCI

event. The default of this enable/disable bit is

disabled.

The three bytes used to read the 24 bit timer

value, TMR_VAL, are located in the PM1_TMR

register at bits 0-23. Note: Reading the lower

byte of the timer value latches the value in the

other 2 bytes. Reading any byte other than the

lower byte first won’t latch the other 2 bytes, and

the data read will be the previous latched data.

175

with events (which have an associated interrupt

status and enable bits, and sometimes an

associated control function) and control

features. The status registers illustrate what

defined function is requesting ACPI interrupt

services (SCI). Any status bit in the ACPI

specification has the following attributes:

POWER BUTTON OVERRIDE EVENT

The power button has an override event as

required for ACPI compliance. See the Soft

Power Management Section. If the user presses

the power button for more than four seconds

while the system is in the working state, a

hardware event is generated and the system will

transition to the off state. There are status and

enable bits associated with this feature in the

PM1_BLK registers.

A. Status bits are only set through some

defined “hardware event”.

B. Unless otherwise noted, Status bits are

cleared by writing a “HIGH” to that bit

position and upon VTR POR. Writing a “0”

has no effect.

RTC ALARM

C. Status bits only generate interrupts while

their associated bits in the enable register

are set.

D. Function bit positions in the status register

have the same bit position in the enable

register (there are exceptions to this rule;

special status bits have no enables).

The ACPI specification requires that the RTC

alarm generate a hardware wake-up event from

the sleeping state. The extended RTC alarm 2

event can be enabled as both an SMI and an

SCI event.

There is a bit in the SMI Enable Register 2 and

the SMI Status Register 2 to enable the RTC

alarm 2 event as an SMI interrupt and to read its

status. The status bit is set when the RTC

generates an alarm event and is cleared by

writing a “1” to this bit (writing a “0” has no

effect). When the RTC generates an alarm

event, the RTC_STS bit will be set. If the

RTC_EN bit is set, an RTC hardware power

Note that this implies that if the respective

enable bit is reset and the hardware event

occurs, the respective status bit is set, however

no interrupt is generated until the enable bit is

set. This allows software to test the state of the

event (by examining the status bit) without

necessarily generating an interrupt. There is a

special class of status bits that have no

respective enable bit; these are called out

specifically, and the respective enable bit in the

enable register is marked as reserved for these

special cases.

management event will be generated.

The

RTC_EN bit will be located at bit 6 of the SMI

Enable Register 2, Logical Device 8, 0xB5. The

RTC_STS bit will be located at bit 6 of the SMI

Status Register 2, Logical Device 8, 0xB7.

The enable registers allow the setting of the

status bit to generate an interrupt. As a general

rule, there is an enable bit in the enable register

for every status bit in the status register. The

control register provides special controls for the

associated event, or special control features that

are not associated with an interrupt event. The

ordering of a register block is the status

registers, followed by enable registers, followed

by control registers.

For SCI, the RTC_STS and RTC_EN bits are in

the PM1_STS and PM1_EN registers.

ACPI REGISTER BLOCK DESCRIPTION

The ACPI register model consists of a number

of fixed register blocks that perform designated

functions. A register block consists of a number

of registers that perform Status, Enable and

Control functions. The ACPI specification deals

176

Table 71A and 71B list the PM1 and

MSCregister blocks and the locations of the

registers contained in these blocks. All of these

new registers are to be powered by VTR. Table

71C shows the block size and range of base

addresses for each block.

Table 71A - PM1 Register Block

REGISTER

PM1_STS 1

PM1_STS 2

PM1_EN 1

SIZE

8

ADDRESS

<PM1_BLK>

<PM1_BLK>+1h

<PM1_BLK>+2h

<PM1_BLK>+3h

<PM1_BLK>+4h

<PM1_BLK>+5h

<PM1_BLK>+6h

<PM1_BLK>+7h

<PM1_BLK>+8h

<PM1_BLK>+9h

<PM1_BLK>+Ah

<PM1_BLK>+Bh

PM1_EN 2

PM1_CNTRL 1

PM1_CNTRL 2

Reserved

PM1_TMR 1

PM1_TMR 2

PM1_TMR 3

PM1_TMR 4

Table 71B - MSC Register Block

REGISTER

SIZE

ADDRESS

SCI_STS 1

SCI_STS 2

SCI_EN 1

SCI_EN 2

MSC_STS

Reserved

8

<MSC_BLK>

<MSC_BLK>+1h

<MSC_BLK>+2h

<MSC_BLK>+3h

<MSC_BLK>+4h

<MSC_BLK>+5h

<MSC_BLK>+6h

<MSC_BLK>+7h

MSC_EN

MSC_CNTRL

Table 71C - Register Block Attributes

BLOCK NAME

BLOCK SIZE

BASE ADDRESS RANGE

PM1_BLK

MSC_BLK

16

8

0-FFFF

177

Power Management 1 Register Block (PM1_BLK)

The registers in this block are powered by VTR.

Power Management 1 Status Register 1 (PM1_STS 1)

Register Location: <PM1_BLK> System I/O Space

Default Value:

Attribute:

Size:

00h on VTR POR

Read/Write (Note 0)

8 bits

Table 72 - Power Management 1 Status Register 1

BIT

NAME

DESCRIPTION

0

TMR_STS

This is the timer status bit. This bit gets set any time bit 23 of the 24

bit counter changes (whenever the MSB changes from low to high or

high to low). Note: bits are counted from 0 to 23. While TMR_EN

and TMR_STS are set a power management event is raised. Note:

This bit is only set by hardware and is reset by software writing a “1”

to this bit position and by VTR POR. Writing a “0” has no effect.

Reserved.

1-3

4

Reserved

BM_STS

This is the bus master status bit. Cleared by VTR POR, and writing

a “1” to this bit position (writing a “0” has no effect). Writing a “1” to

this bit also clears BM_CNTRL.

MSC_CNTRL register, sets this bit.

BM_CNTRL, bit 1 of the

5

GBL_STS

Reserved

The global status bit. This bit is set when BIOS_RLS is set. Setting

BIOS_RLS will also raise an SCI if GBL_EN is set. This bit is only

set by hardware and is reset by software writing a “1” to this bit

position and by VTR POR. Writing a “0” has no effect. Writing a “1”

to this bit also clears BIOS_RLS.

6-7

Reserved. These bits always return a value of “0”.

178

Power Management 1 Status Register 2 (PM1_STS 2)

Register Location: <PM1_BLK>+1h System I/O Space

Default Value:

Attribute:

Size:

00h on VTR POR

Read/Write (Note 0)

8 bits

Table 73 - Power Management 1 Status Register 2

BIT

0

NAME

PWRBTN_ST

DESCRIPTION

This bit is set when the Button_In signal is asserted. In the system

working state, while PWRBTN_EN and PWRBTN_STS are both set,

an SCI interrupt event is raised. In the sleeping state, while

PWRBTN_EN and PWRBTN_STS are both set a wake-up event is

generated (Note 2). This bit is only set, by hardware and is reset by

software writing a “1” to this bit position, by VTR POR. Writing a 0

has no effect. It is also reset as follows: If PWRBTNOR_EN is set,

and if the Button_In signal is held asserted for more than four

seconds, then this bit is cleared, the PWRBTNOR_STS bit is set

and the system will transition into the soft off state (nPowerOn

floats). Note: The implementation of the PWRBTN_STS and

PWRBTN_EN as described here which requires that PWRBTN_EN

be set for the button to generate a wake-up event is redundant

relative to our present implementation of Button_In where pressing

the button will always wake the machine (i.e., activate nPowerOn).

Reserved.

S

1

2

Reserved

RTC_STS

This bit is set when the RTC generates an alarm 2. Additionally if

the RTC_EN bit is set then the setting of the RTC_STS bit will

generate an SCI. (See Note)

3

PWRBTNOR_

STS

This bit is set when the power switch over-ride function is set: If

PWRBTNOR_EN is set, and if the Button_In signal is held asserted

for more than four seconds. Hardware is also required to reset the

PWRBTN_STS when issuing a power switch over-ride function.

(See Note)

4-6

7

Reserved

WAK_STS

Reserved. These bits always return a value of “0”.

This bit is set when the system is in the suspended state and an

enabled resume event occurs. This bit is set on the high-to-low

transition of nPowerOn. It is cleared by writing a 1 to its bit location

when nPowerOn is active. Upon setting this bit, the suspend/resume

state machine will transition the system to the on state. (See Note)

Note: This bit is only set by hardware and is reset by software writing a “1” to this bit position and by

VTR POR. Writing a “0” has no effect.

179

Power Management 1 Enable Register 1 (PM1_EN 1)

Register Location:

Default Value:

Attribute:

<PM1_BLK>+2 System I/O Space

00h on VTR POR

Read/Write (Note 0)

8 bits

Size:

Table 74 - Power Management 1 Enable Register 1

DESCRIPTION

BIT

0

NAME

TMR_EN

This is the timer interrupt enable bit. When this bit is set, then, an

SCI event is generated any time the TMR_STS bit is set. When this

bit is reset, then no interrupt is generated when the TMR_STS bit is

set.

1-4

5

Reserved

GBL_EN

Reserved. These bits always return a value of “0”.

The global enable bit. When both the GBL_EN and the GBL_STS

are set, an SCI is raised.

6-7

Reserved

Reserved.

Power Management 1 Enable Register 2 (PM1_EN 2)

Register Location:

Default Value:

Attribute:

<PM1_BLK>+3 System I/O Space

00h on VTR POR

Read/Write (Note 0)

8 bits

Size:

Table 75 - Power Management 1 Enable Register 2

NAME DESCRIPTION

BIT

0

PWRBTN_EN This bit is used to enable the assertion of the Button_In to generate

an SCI or wake-up event. The PWRBTN_STS bit is set any time the

Button_In signal is asserted. The enable bit does not have to be set

to enable the setting of the PWRBTN_STS bit by the assertion of the

Button_In signal.

1

2

Reserved

RTC_EN

Reserved.

This bit is used to enable the setting of the RTC_STS bit to generate

an SCI. The RTC_STS bit is set any time the RTC generates an

alarm 2.

3-7

Reserved

Reserved. These bits always return a value of “0”.

180

Power Management 1 Control Register 1 (PM1_CNTRL 1)

Register Location:

Default Value:

Attribute:

<PM1_BLK>+4 System I/O Space

00h on VTR POR

Read/Write (Note 0)

8 bits

Size:

Table 76 - Power Management 1 Control Register 1

NAME DESCRIPTION

BIT

0

SCI_EN

When this bit is set, then the SCI enabled power management events

will generate an SCI interrupt. When this bit is reset, power

management events will not generate an SCI interrupt.

When set, this bit allows the generation of a bus master request to

cause any processor in the “soft off” state (nPowerOn floats) to

transition to the working state (nPowerOn active). When this bit is

reset, the generation of a bus master request does not affect any

processor in the “soft off” state. If this bit is set and BM_CNTRL is

set, an SCI is raised.

The global release bit. This bit is used by the ACPI software to raise

an event to the BIOS software. BIOS software has corresponding

enable and status bits to control its ability to receive ACPI events.

Setting GBL_RLS sets BIOS_STS, and, if BIOS_EN is set, generates

an SMI. Cleared by writing a “1” to BIOS_STS (writing a “0” has no

effect).

1

2

BM_RLD

GBL_RLS

Reserved

3-7

Reserved. These bits always return a value of “0”.

Power Management 1 Control Register 2 (PM1_CNTRL 2)

Register Location:

Default Value:

Attribute:

<PM1_BLK>+5 System I/O Space

00h on VTR POR

Read/Write (Note 0)

8 bits

Size:

Table 77 - Power Management 1 Control Register 2

DESCRIPTION

BIT

0

NAME

Reserved

Reserved. This field always returns “0”.

1

PWRBTNOR_E

N

This bit controls the power button over-ride function. When set, then

any time the Button_In signal is asserted for more than four seconds

the system will transition to the off state. When a power button over-

ride event occurs, the logic should clear the PWRBTN_STS bit, and

set the PWRBTNOR_STS bit.

2-7

Reserved

Reserved. This field always returns “0”.

181

Power Management 1 Timer 1 (PM1_TMR 1)

Register Location:

Default Value:

Attribute:

<PM1_BLK>+8h System I/O Space

00h on VTR POR and RESET_DRV

Read-Only

8 bits

Size:

Table 78 - Power Management 1 Timer 1

BIT

0-7

NAME

TMR_VAL

DESCRIPTION

This read-only field returns the first byte of the running count of the

power management timer. Note: Reading this byte latches the other

two bytes. This is a 24-bit counter that runs off a 3.579545 MHz

clock, and counts while in the working system state. The timer is reset

to an initial value of “0” during a RESET_DRV or VTR POR and then

continues counting until the 14.31818 MHz input to the chip is

stopped. If the 14.31818 MHz clock is restarted without

a

RESET_DRV or VTR POR, then the counter will continue counting

from where it stopped. Any time bit 23 of the timer changes state

(goes from LOW to HIGH or HIGH to LOW), the TMR_STS bit is set.

If the TMR_EN bit is set an SCI interrupt is also generated.

Power Management 1 Timer 2 (PM1_TMR 2)

Register Location:

Default Value:

Attribute:

<PM1_BLK>+9h System I/O Space

00h on VTR POR and RESET_DRV

Read-Only

8 bits

Size:

Table 79 - Power Management 1 Timer 2

BIT

0-7

NAME

TMR_VAL

DESCRIPTION

This read-only field returns the second byte of the running count of the

power management timer. This is a 24-bit counter that runs off a

3.579545 MHz clock and counts while in the working system state.

The timer is reset to an initial value of “0” during a RESET_DRV or

VTR POR and then continues counting until the 14.31818 MHz input

to the chip is stopped. If the 14.31818 MHz clock is restarted without a

RESET_DRV or VTR POR, then the counter will continue counting

from where it stopped. Any time bit 23 of the timer changes state

(goes from LOW to HIGH or HIGH to LOW), the TMR_STS bit is set.

If the TMR_EN bit is set an SCI interrupt is also generated.

182

Power Management 1 Timer 3 (PM1_TMR 3)

Register Location:

Default Value:

Attribute:

<PM1_BLK>+Ah System I/O Space

00h on VTR POR and RESET_DRV

Read-Only

8 bits

Size:

Table 80 - Power Management 1 Timer 3

BIT

0-7

NAME

TMR_VAL

DESCRIPTION

This read-only field returns the third byte of the running count of the