DM9331A [ETC]
;
ETC 
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
1. General Description
The DM9331A is a physical-layer, single-chip, low
power transceiver for media converter application. On
the media side, it provides a direct interface either to
Unshielded Twisted Pair Category 5 Cable (UTP5) for
100BASE-TX Fast Ethernet, and it also provides
PECL interface to connect the external fiber optical
transceiver. Through the Media Converter Interface
(MCI), the DM9331A connects to another DM9331A
for the twisted pair to the fiber media converter, or
fiber to fiber repeater.
IEEE802.3u, including the Physical Coding Sublayer
(PCS), Physical Medium Attachment (PMA), Twisted
Pair Physical Medium Dependent Sublayer (TP-PMD)
and a PECL compliant interface for a fiber optical
module, compliant with ANSI X3.166. The DM9331A
provides a strong support for the auto-negotiation
function, utilizing automatic selection of full or half-
duplex mode. Furthermore, due to the built-in wave-
shaping filter, the DM9331A needs no external filter to
transport signals to the media on the 100base-TX
Ethernet operation.
The DM9331A uses
a
low-power and high-
performance CMOS process. It contains the entire
physical layer functions of 100BASE-TX as defined by
2. Block Diagram
100Base-FX
PECL
Interface
100Base-
Media
TX
PCS
Converter
Interface
100Base-TX
Transceiver
Auto-Negotiation
TX/RX Module
LED Driver
Clock
Circuit
Block
Biasing/
Power
Block
MII
MII
Register
Management
Control
Preliminary
1
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
Table of Contents
1. General Description ..............................................1
2. Block Diagram ......................................................1
3. Features................................................................4
4. Pin Configuration: DM9331A LQFP......................5
7.2.9 Remote Auto-loopback Diagnostic………..…..17
8. MII Register Description ..................................... 18
8.1 Basic Mode Control Register (BMCR) - 00....... 19
8.2 Basic Mode Status Register (BMSR) - 01 ........ 20
8.3 Auto-negotiation Advertisement Register (ANAR)
- 04 .................................................................. 21
8.4 Auto-negotiation Link Partner Ability Register
(ANLPAR) - 05 ................................................ 22
8.5 Auto-negotiation Expansion Register (ANER)
- 06 .................................................................. 22
8.6 DAVICOM Specified Configuration Register
(DSCR)-
5. Pin Description......................................................6
5.1 Media Converter Interface, 19 pins.....................6
5.2 Media Interface, 5 pins........................................7
5.3 LED Interface, 3 pins ..........................................7
5.4 Mode, 1 pin .........................................................8
5.5 Bias and Clock, 3 pins ........................................8
5.6 Power, 15 pins ....................................................8
5.7 Table A................................................................9
16 …………………………………...……23
8.7 DAVICOM Specified Configuration and Status
Register (DSCSR) - 17.................................... 24
8.8 DAVICOM Specified Interrupt Register - 21..... 25
6.LED Configuration................................................10
9. DC and AC Electrical Characteristics……………26
9.1 Absolute Maximum Ratings.............................. 26
9.2 Operating Conditions........................................ 26
9.3 DC Electrical Characteristics............................ 27
9.4 AC Electrical Characteristics & Timing
7. Functional Description ........................................11
7.1 MCI interface.....................................................11
7.2 100Base-TX Operation..................…………….12
7.2.1 100Base-TX Transmit....................................12
7.2.1.1 4B5B Encoder.............................................13
7.2.1.2 Scrambler ...................................................13
7.2.1.3 Parallel to Serial Converter.........................13
7.2.1.4 NRZ to NRZI Encoder.................................13
7.2.1.5 NRZI to MLT-3............................................13
7.2.1.6 MLT-3 Driver...............................................13
7.2.1.7 4B5B Code Group.......................................15
7.2.2 100Base-TX Receiver....................................15
7.2.2.1 Signal Detect...............................................15
7.2.2.2 Adaptive Equalizer ......................................15
7.2.2.3 MLT-3 to NRZI Decoder .............................15
7.2.2.4 Clock Recovery Module..............................15
7.2.2.5 NRZI to NRZ ...............................................15
7.2.2.6 Serial to Parallel..........................................15
7.2.2.7 Descrambler ...............................................15
7.2.2.8 Code Group Alignment ...............................15
7.2.2.9 4B5B Decoder.............................................16
7.2.3 Auto-Negotiation ............................................16
7.2.4 MII Serial Management..................................16
7.2.4.1 Serial Management Interface......................16
7.2.4.2 Management Interface – Read Frame
Waveforms...................................................... 28
9.4.1 TP Interface................................................... 28
9.4.2 Oscillator Timing............................................ 28
9.4.3 MDC/MDIO Timing ........................................ 28
9.4.4 MDIO Timing when OUTPUT by STA........... 28
9.4.5 MDIO Timing when OUTPUT by DM9331A .. 29
9.4.6 Auto-negotiation and Fast Link Pulse Timing
Parameters .................................................. 29
9.4.7 Auto-negotiation and Fast Link Pulse Timing
Diagram ....................................................... 29
9.4.8 TXD to TP or FX Transmit Latency Timing
Diagram ....................................................... 30
9.4.9 TXD to TP or FX Transmit Latency Parameters
..................................................................... 30
9.4.10 TP or FX to RXD Receive Latency Timing
Diagram ....................................................... 30
9.4.11 TP or FX to RXD Receive Latency Parameters
..................................................................... 30
10. Application Notes.............................................. 31
10.1 Network Interface Signal Routing................... 31
10.2 100Base-TX Side Application......................... 31
10.3 100Base-TX Side (Power Reduction Application)
..................................................................... 32
Structure………. .......................................16
7.2.4.3 Management Interface – Write Frame
Structure ..................................................17
7.2.5 Power Reduced Mode ...................................17
7.2.6 Power Down Mode.........................................17
7.2.7 Reduced Transmit Power Mode ....................17
7.2.8 Link Fault Propagation...................................17
10.4 100Base-FX Side Application......................... 33
10.5 Power Decoupling Capacitors ........................ 34
10.6 Ground Plane Layout...................................... 35
10.7 Power Plane Partitioning ................................ 36
2
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.8 Media Converter Interface...............................37
10.13 Magnetics Selection Guide ...........................42
11. Package Information.........................................43
12. Ordering Information.........................................44
10.9 Link Fault Propagation Application..................38
10.10 Auto-loopback Diagnostic .............................39
10.11 Media Converter or Repeater
Application…….40
10.12 Link Fault Propagation LED Display ........….41
Preliminary
3
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
3. Features
!
!
!
100Base-TX to 100Base-FX media converter
application chip set
100Base-FX to 100Base-FX repeater application
chip set under full duplex mode
100Base-TX to 100Base-TX repeater application
chip set under full duplex mode
Optional Fault propagation on no link condition.
Fully compliant with IEEE 802.3u 100Base-TX/FX
Compliant with ANSI X3T12 TP-PMD 1995
standard
Supports Auto-Negotiation function to 100 Mbps
full/half duplex, compliant with IEEE 802.3u
Remote fault detection capability
Far end fault signaling option in FX mode
Selectable twisted-pair or fiber mode output
Remote Auto-loopback Diagnostic in FX mode
!
!
Selectable full-duplex or half-duplex operation
Provides Loopback mode for easy system
diagnostics
LED status outputs indicate Link/Activity, Full/Half-
duplex and Fault LED
Single Low-Power Supply of 3.3V with 0.35 m CMOS
technology
Very Low Power consumption modes:
! Power Reduced mode (cable detection)
! Power Down mode
!
!
!
!
!
!
!
! Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction
Compatible with 3.3V and 5.0V tolerant I/Os
48-pin LQFP small package (1x1 cm)
!
!
!
ꢀ
!
!
4
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
4. Pin Configuration
RXDV
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
MDC
DIAG_ACT
DVDD
DVDD
TXCLK
RESET#
DVDD
TXEN
TXD[0]
NC
TXD[1]
DM9331A
OSCIN
DGND
SD
LNKFAULTEN
LNKFAULT#
DVDD
AGND
BGRESG
BGRES
DGND
TPFAULT
LINK/ACTLED#/OP2
Preliminary
5
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
5. Pin Description
I : Input, O : Output, LI : Latch input when power-up/reset, Z : Tri-State output, U : Pulled up
D : Pulled down
5.1 Media Converter Interface, 18 pins
Pin No.
Pin Name
I/O
Description
14
TPFAULT
O
Twisted Pair Fault
0 = Twisted pair link fault
1 = Twisted pair normal work
17
18
LNKFAULT#
I
I
Link Fault Propagation
0 = Link fault propagation is active
1 = normal operation
LNKFAULTEN
Link Fault Propagation Enable
0 = Link fault propagation disable
1 = Link fault propagation enable
20,19
21
TXD [0:1]
TXEN
I
I
Transmit Data
2-bit data inputs (synchronous to the 50MHz OSCIN)
Transmit Enable
Active high indicates the presence of valid data on the TXD [0:1] for
100Mbps mode
22
24
TXCLK
MDC
O
I
Transmit Clock
25MHz transmit clock
Management Data Clock
Synchronous clock for the MDIO management data. This clock is
provided by management entity, and it is up to 2.5MHz
25
26
MDIO
I/O Management Data I/O
Bi-directional management data that may be provided by the station
management entity or the PHY
O, Fiber Fault
Z, 0 = Fiber link fault; Fiber receive far end fault package or fiber
LI disconnect
FXFAULT/
TPSET1
(D) 1 = Fiber normal work
TPSET1 (reset latch input)
0 = Fiber mode; default pull low
1 = Twisted pair mode; need 10kΩ resistor to pull high
Z, Twisted Pair set (reset latch input)
LI 0 = Fiber mode; default pull low
27
TPSET0
(D)
1 = Twisted pair mode; need 10kΩ resistor to pull high
29,28
RXD [0:1]
O, Receive Data Output
Z, 2-bit data outputs (synchronous to the 50MHz OSCIN)
LI Chip PHY-address of Management Register (reset latch input)
(D)
RXD [0:1]
FX Mode:
0X00
0X01
0X02
0X03
TP Mode:
0X0C
0X0D
0X0E
0X0F
0,0 PHY-address =
0,1 PHY-address =
1,0 PHY-address =
1,1 PHY-address =
0 = Defaults
1 = Needs 10kꢀ register to pull high
6
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
32
34
35
36
MDINTR#
FAULTLED#
DIAG_STO
CHIPEN
O, Status Interrupt Output
Z
Asserted low whenever there is a status change (link, speed, duplex).
The MDINTR# pin has a high impedance output, a 2.2Kꢀ pulled high
resistor is needed
O, Link Fault LED
Z
Active Low
In TP mode, Indicates TP Fault LED
In FX mode, Indicates FX Fault LED
Diagnostic Status Output
O
When DIAG_ACT=1 and FX mode
1 = The route of fiber connect succeeds
0 = The route of fiber connect fails
Z, Chip Set Enable
LI
Need a 10kΩ resistor pull high for enabling a chip set
(D)
37
38
RXDV
O, Receive Data Valid
Z
Asserted high to indicate that the valid data is present on the RXD[0:1]
DIAG_ACT
I
Diagnostic Active
(L) 1 = Active fiber diagnostic
0 = Inactive fiber diagnostic
40
RESET#
I
Reset
Active low input initializes the DM9331A
5.2 Media Interface, 5 pins
Pin No.
Pin Name
I/O
Description
3,4
RX+/FXRD+
RX-/FXRD-
I
Differential Receive Pair/PECL Receive Pair
Differential data is received from the media
Differential Pseudo ECL signal is received from the media in fiber mode
Differential Transmit Pair/PECL Transmit Pair
Differential data is transmitted to the media in TP mode
Differential Pseudo ECL signal transmits to the media in fiber mode
Fiber-optic Signal Detect
7,8
45
TX+/FXTD+
TX-/FXTD-
O
I
SD
PECL signal which indicates whether or not the fiber-optic receive pair is
receiving valid signal levels
5.3 LED Interface, 3 pins
I/O
Pin No.
Pin Name
Description
11
FULL
/HALF LED#
/OP0
O, Full-Duplex/ Half-Duplex LED
LI Active states indicate Full-duplex mode. Active states see LED
(U) configuration
OP0 : (power up reset latch input)
This pin is used to control the forced or advertised operating mode of the
DM9331A according to the Table A. The value is latched into the
DM9331A registers at power-up/reset
12
LINK LED#
/OP1
O, Link LED
LI Active states indicate good link. Active states see LED configuration
Preliminary
7
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
(U) OP1 : (power up reset latch input)
This pin is used to control the forced or advertised operating mode of the
DM9331A according to the Table A. The value is latched into the
DM9331A registers at power-up/reset
13
LINK/ACT LED# O, Link LED & Activity LED :
/OP2
LI Active states indicate good link. It is also an activity LED function when
(U) transmitting or receiving data. Active states see LED configuration
OP2 : (power up reset latch input)
This pin is used to control the forced or advertised operating mode of the
DM9331A according to the Table A. The value is latched into the
DM9331A registers at power-up/reset
5.4 Mode, 1 pin
Pin No.
Pin Name
I/O
Description
10
PWRDWN
I
Power Down Control
Asserted high to force DM9331A into power down mode. When in power
down mode, most of the DM9331A circuit block’s power is turned off,
only the MII management interface (MDC, MDIO) logic is available. To
leave power down mode, DM9331A need the hardware or software reset
with the PWRDWN pin low
5.5 Bias and clock, 3 pins
Pin No.
47
Pin Name
BGRESG
BGRES
I/O
P
Description
Bandgap Ground
48
I/O Bandgap Voltage Reference Resistor 6.8K ohm
43
OSCIN
I
3.3V 50MHz clock input must be using 3.3v output oscillators
5.6 Power, 15 pins
Pin No.
1,2,9
Pin Name
AVDD
I/O
P
Description
Analog Power
5,6,46
AGND
P
Analog Ground
16,23,30,31,
39,41
DVDD
P
Digital Power
15,33,44
DGND
P
Digital Ground
5.7 Table A
OP2
OP1
OP0
Function
8
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
Auto negotiation enables 100TX Full/Half capabilities
Manually select 100TX HDX
Manually select 100TX FDX
Manually select 100FX HDX
Manually select 100FX FDX
Preliminary
9
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
6. LED Configuration
LEDs flash once for about 500ms after power-on reset
or software reset by writing PHY register. All LED
pins are dual function pins, which can be configured
as either active high or low by pulling them low or high
accordingly. If the pin is pulled high, the LED is
active low after reset. Likewise, if the pin is pulled
low, the LED is active high.
ꢀ
DM9331A
ꢀ
VCC
ꢀ
300 Ohm
ꢀ
10K Ohm
ꢀ
Pull High for
Reset
ꢀ
ꢀ
Pull Low for
300 Ohm
ꢀ
ꢀ
Reset
ꢀ
10K Ohm
ꢀ
10
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
7. Functional Description
Physical Medium Dependent) sublayer and a PECL
The DM9331A Fast Ethernet single-chip transceiver,
providing the functionality as specified in IEEE 802.3u,
integrates a complete 100Base-TX module and a complete
100Base-FX module. The DM9331A provides a Media
Converter Interface (MCI) as connection interface.
compliant interface for a fiber optic module. Figure 1
shows the major functional blocks implemented in the
DM9331A.
The DM9331A performs all PCS (Physical Coding Sublayer),
PMA (Physical Media Access), TP-PMD (Twisted Pair
100Base-TX/FX
Transmitter
Media
Converter
Interface
(MCI)
100Base-TX/FX
Receiver
MII Serial
Management
Auto
Negotiation
Interface
Figure 7-1
7.1 MCI Interface
RXDV signal reconciliation sublayer indicates that data
is being presented on the MCI for transmission on the
physical medium.
The DM 9331A provides a Media Converter Interface (MCI)
The purpose of the MCI interface is to provide a simple, easy
to implement connection to another DM9331A.
The MCI consists of a 2-bit receive data bus, a 2-bit transmit
data bus, and controls signals to facilitate data transfers
between the two DM9331A chips.
•
•
RXD (receive data) is a 2-bit data that are sampled by
the reconciliation sublayer synchronously with respect to
OSCIN clock. For each OSCIN clock period, which
RXDV is asserted, RXD (1:0) is transferred from the
PHY to another DM9331A.
•
•
TXD (transmit data) is a 2-bit data that is driven by the
reconciliation sublayer synchronously with respect to
OSCIN clock. For each OSCIN clock period, which
TXEN is asserted, TXD (1:0) is accepted for
transmission by the PHY.
RXDV (receive data valid) output to another DM9331A
TXEN signal indicates that the DM9331A is data ready.
TXEN (transmit enable) inputs from another DM9331A
Preliminary
11
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
7.2 100Base-TX Operation
7.2.1 100Base-TX Transmit
The 100Base-TX transmitter receives 2-bit data clocked in at
50MHz from the MCI, and outputs a scrambled 5-bit
encoded MLT-3 signal to the media at 100Mbps. The on-
chip clock circuit converts the 25MHz clock into a 125MHz
clock for internal use.
The 100Base-TX transmitter consists of the functional
blocks shown in figure 2. The 100Base-TX transmit section
converts 2-bits synchronous data provided by the MCI to a
scrambled MLT-3 125 million symbols per second serial
data stream.
These two busses include various controls and signal
indications that facilitate data transfers between the
DM9331A chip set.
50M OSCI
TX CGM
LED1-3#
LED
Driver
NRZ
to
NRZI
4B/5B
Encoder
Parallel
to Serial
NRZI to
MLT-3
MLT-3
Driver
Scrambler
ꢀ
TX
Rise/Fall
Time
CTL
25M CLK
125M CLK
MCI
Interface/
Control
MCI
Signals
Code-
group
Alignment
NRZI
to
NRZ
4B/5B
Decoder
Serial to
Parallel
MLT-3 to
NRZI
Adaptive
EQ
ꢀ
RX
Descrambler
RX
CRM
Digital
Logic
ꢀ
RX
ꢀ
TX
Auto-Negotiation
TX/RX Module
Register
Figure 7-2
12
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
100Base-TX Operation
spectrum at the media connector and on the twisted pair
cable in 100Base-TX operation.
The block diagram in figure 2 provides an overview of the
functional blocks contained in the transmit section.
The transmitter section contains the following functional
blocks:
By scrambling the data, the total energy presented to the
cable is randomly distributed over a wide frequency range.
Without the scrambler, energy levels on the cable could
peak beyond FCC limitations at frequencies related to
repeated 5B sequences like continuous transmission of
IDLE symbols. The scrambler output is combined with the
NRZ 5B data from the code-group encoder via an XOR logic
function. The result is a scrambled data stream with
sufficient randomization to decrease radiated emissions at
critical frequencies.
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Encoder
- NRZI to MLT-3
- MLT-3 Driver
7.2.1.1 4B5B Encoder
7.2.1.3 Parallel to Serial Converter
The 4B5B encoder converts 4-bit (4B) nibble data,
generated by the MAC Reconciliation Layer into a 5-bit (5B)
code group for transmission, refer to Table 1. This
conversion is required for control and packet data to be
combined in code groups. The 4B5B encoder substitutes
the first 8 bits of the MAC preamble with a J/K code-group
pair (11000 10001) upon transmit. The 4B5B encoder
continues to replace subsequent 4B preamble and data
nibbles with corresponding 5B code-groups. At the end of
the transmit packet, upon the deassertion of the Transmit
Enable signal from the MAC Reconciliation layer, the 4B5B
encoder injects the T/R code-group pair (01101 00111)
indicating end of frame. After the T/R code-group pair, the
4B5B encoder continuously injects IDLEs into the transmit
data stream until Transmit Enable is asserted and the next
transmit packet is detected.
The Parallel to Serial Converter receives parallel 5B
scrambled data from the scrambler and serializes it
(converts it from a parallel to a serial data stream).
The serialized data stream is then presented to the
NRZ to NRZI Encoder block
7.2.1.4 NRZ to NRZI Encoder
After the transmit data stream has been scrambled and
serialized, the data must be NRZI encoded for compatibility
with the TP-PMD standard for 100Base-TX transmission
over Category-5 unshielded twisted pair cable.
7.2.1.5 NRZI to MLT-3
The MLT-3 conversion is accomplished by converting the
data stream output from the NRZI encoder into two binary
data streams with alternately phased logic one events.
The DM9331A includes a Bypass 4B5B conversion option
within the 100Base-TX Transmitter for support of
applications like 100 Mbps repeaters which do not require
4B5B conversion.
7.2.1.6 MLT-3 Driver
The two binary data streams created at the MLT-3 converter
are fed to the twisted pair output driver which converts these
streams to current sources and alternately drives either side
of the transmit transformer primary winding resulting in a
minimal current MLT-3 signal.
7.2.1.2 Scrambler
The scrambler is required to control the radiated emissions
(EMI) by spreading the transmit energy across the frequency
Preliminary
13
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
7.2.1.7 4B5B Code Group
Symbol
Meaning
4B code
3210
5B code
43210
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
I
J
K
T
R
H
Idle
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Table 7-1
14
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
7.2.2 100Base-TX Receiver
7.2.2.3 MLT-3 to NRZI Decoder
The 100Base-TX receiver contains several function blocks
that convert the scrambled 125Mb/s serial data to
synchronous 2-bit nibble data that is then provided to the
MCI.
The DM9331A decodes the MLT-3 information from the
Digital Adaptive Equalizer into NRZI data.
7.2.2.4 Clock Recovery Module
The receive section contains the following functional blocks:
The Clock Recovery Module accepts NRZI data from the
MLT-3 to NRZI decoder. The Clock Recovery Module locks
onto the data stream and extracts the 125MHz reference
clock. The extracted and synchronized clock and data are
presented to the NRZI to NRZ decoder.
- Signal Detect
- Digital Adaptive Equalizer
- MLT-3 to NRZI Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
7.2.2.5 NRZI to NRZ
- Descrambler
- Code Group Alignment
- 4B5B Decoder
The transmit data stream is required to be NRZI encoded in
for compatibility with the TP-PMD standard for 100Base-TX
transmission over Category-5 unshielded twisted pair cable.
This conversion process must be reversed on the receive
end. The NRZI to NRZ decoder receives the NRZI data
stream from the Clock Recovery Module and converts
it to a NRZ data stream to be presented to the Serial to
Parallel conversion block.
7.2.2.1 Signal Detect
The signal detect function meets the specifications
mandated by the ANSI XT12 TP-PMD 100Base-TX
Standards for both voltage thresholds and timing
parameters.
7.2.2.6 Serial to Parallel
7.2.2.2 Adaptive Equalizer
The Serial to Parallel Converter receives a serial data
stream from the NRZI to NRZ converter, and converts
the data stream to parallel data to be presented to the
descrambler.
When transmitting data at high speeds over copper twisted
pair cable, attenuation based on frequency becomes a
concern. In high speed twisted pair signaling, the frequency
content of the transmitted signal can vary greatly during
normal operation based on the randomness of the
scrambled data stream. This variation in signal attenuation
caused by frequency variations must be compensated for to
ensure the integrity of the received data. In order to ensure
quality transmission when employing MLT-3 encoding, the
compensation must be able to adapt to various cable
lengths and cable types depending on the installed
environment. The selection of long cable lengths for a given
implementation, requires significant compensation which will
be over-killed in a situation that includes shorter, less
attenuating cable lengths. Conversely, the selection of short
or intermediate cable lengths requiring less compensation
will cause serious under-compensation for longer length
cables. Therefore, the compensation or equalization must
be adaptive to ensure proper conditioning of the received
signal independent of the cable length.
7.2.2.7 Descrambler
Because of the scrambling process required to control the
radiated emissions of transmit data streams, the receiver
must descramble the receive data streams. The
descrambler receives scrambled parallel data streams from
the Serial to Parallel converter, descrambles the data
streams, and presents the data streams to the Code Group
alignment block.
7.2.2.8 Code Group Alignment
The Code Group Alignment block receives un-aligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected, and subsequent data is aligned on
a fixed boundary.
Preliminary
15
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
device to advertise supported modes of operation to a
remote link partner, acknowledge the receipt and
7.2.2.9 4B5B Decoder
The 4B5B Decoder functions as a look-up table that
translates incoming 5B code groups into 4B (Nibble) data.
When receiving a frame, the first two 5-bit code groups
received are the start-of-frame delimiter (J/K symbols). The
J/K symbol pair is stripped and two nibbles of preamble
pattern are substituted. The last two code groups are the
end-of-frame delimiter (T/R symbols).
understanding of common modes of operation, and to reject
un-shared modes of operation. This allows devices on both
ends of a segment to establish a link at the best common
mode of operation. If more than one common mode exists
between the two devices, a mechanism is provided to allow
the devices to resolve to a single mode of operation using a
predetermined priority resolution function.
The T/R symbol pair is also stripped from the nibble
presented to the Reconciliation layer.
Auto-negotiation also provides a parallel detection function
for devices that do not support the Auto-negotiation feature.
During Parallel detection there is no exchange of
configuration information, instead, the receive signal is
examined. If it is discovered that the signal matches a
technology that the receiving device supports, a connection
will be automatically established using that technology. This
allows devices that do not support Auto-negotiation but
support a common mode of operation to establish a link.
7.2.3 Auto-Negotiation
The objective of Auto-negotiation is to provide a means to
exchange information between segment linked devices and
to automatically configure both devices to take maximum
advantage of their abilities. It is important to note that Auto-
negotiation does not test the link segment characteristics.
The Auto-Negotiation function provides a means for a
(OP):<10> indicates read operation and <01>
indicates write operation. For read operation, a 2-bit
turnaround (TA) filing between Register Address field
and Data field is provided for MDIO to avoid contention.
Following the turnaround time, 16-bit data is read from
or written onto management registers.
7.2.4 MII Serial Management
The MII serial management interface consists of a
data interface, basic register set, and a serial
management interface to the register set. Through this
interface it is possible to control and configure multiple
PHY devices, get status and error information, and
determine the type and capabilities of the attached
PHY device(s).
7.2.4.1 Serial Management Interface
The serial control interface uses a simple two-wired
serial interface to obtain and control the status of the
physical layer through the MII interface. The serial
control interface consists of MDC (Management Data
Clock), and MDI/O (Management Data Input/Output)
signals.
The DM9331A management functions correspond to
MII specification for IEEE 802.3u-1995 (Clause 22) for
registers 0 through 6 with vendor-specific registers
16,17, and 18.
In read/write operation, the management data frame is
64-bits long and starts with 32 contiguous logic one
bits (preamble) synchronization clock cycles on MDC.
The Start of Frame Delimiter (SFD) is indicated by a
<01> pattern followed by the operation code
The MDIO pin is bi-directional and may be shared by
up to 32 devices.
7.2.4.2 Management Interface - Read Frame Structure
MDC
MDIO Read
//
//
0
1
1
0
A4
A3
A0
R4
R3
R0
32 "1"s
0
D15
D14
D1
D0
Z
Idle Preamble
SFD
Op Code
PHY Address
Register Address
Turn Around
Data
Idle
Read
Write
Figure 7-3
16
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
7.2.4.3 Management Interface - Write Frame Structure
MDC
MDIO Write
32 "1"s
0
1
0
1
A4
A3
A0
R4
R3
R0
1
0
D15
D14
Data
D1
D0
Idle Preamble
SFD
Op Code
PHY Address
Register Address
Write
Turn Around
Idle
Figure 7-4
7.2.8 Link Fault Propagation
7.2.5 Power Reduced Mode
The DM9331A will propagate link fault signals from
media to another DM9331A. If link fault happens, the
DM9331A will send out fault signals to another
DM9331A.
The Signal detect circuit is always turned on to monitor
whether there is any signal on the media. In case of cable
disconnection, DM9331A will automatically turn off the
power and enter the Power Reduced mode, regardless of its
operation mode being N-way auto-negotiation or forced
mode. While in the Power Reduced mode, the transmit
circuit will continue sending out fast link pules with minimum
power consumption. If a valid signal is detected from the
media, which might be N-way fast link pules, 10Base-T
normal link pules, or 100Base-TX MLT3 signals, the device
wakes up and resumes normal operation mode.
In FX mode, their are two types of link failure, receive
link failure or remote fault (receive far end fault).In the
event of a fiber receive link failure, the DM9331A will
send out an FX fault signal. The DM9331A will send
out a far end fault signal to the fiber optic media, if the
DM9331A receive the fault signal from the other
device.
In TP mode, In the event of a TP receive link failure,
the DM9331A will send out a TP fault signal. The
DM9331A will stop to transmit idle signal to the CAT5
media, if the DM9331A receive the fault signal from
the other device.
Automatic reduced power down mode can be disabled by
writing Zero to Reg.16.4.
7.2.6 Power Down Mode
7.2.9 Remote Auto-loopback Diagnostic
Power Down mode is entered by setting Reg.0.11 to ONE
or pulling PWRDWN pin high, which disables all transmit,
receive functions and MCI interface functions except the
MDC/MDIO management interface.
Remote Auto-loopback Diagnostic is for detecting link
fault. It enables users to operate on one side, and
diagnose the status of fiber link. To achieve this
function, the FX should both use DM9331A.
7.2.7 Reduced Transmit Power Mode
When the local DIAG_ACT is active, the DM9331A will
auto break off the receive and transmit signals and
sends detecting signals. When the remote DM9331A
diagnoses a detecting signal, it will auto break off the
normal receive and transmit signal, and reply a
detecting signal to local at the same time.
Additional Transmit power reduction can be gained by
designing with 1.25:1 turns ration magnetics on its TX side
and using a 8.5Kꢀ resistor on BGRES and BGRESG pins,
and the TX+/TX- pull-high resistors being changed from 50
ꢀ to 78ꢀ. This configuration could reduce about 20% of
transmit power.
Therefore, when DIAG_ACT is active and DIAG_STO
is on, it means that the receive and transmit route of
FX is normal. On the other hand, if DIAG_ACT is
active and DIAG_STO is off, then it means that the
receive and transmit route of FX is invalid.
Preliminary
17
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
8. MII Register Description
ADD
00 CONTROL Reset Loop Speed Auto-N Power Isolate Restart Full
back select Enable Down
TX FDX TX HDX
Cap. Cap.
Name
15
14
13
12
11
10
9
8
7
Coll.
6
5
4
3
2
1
0
Reserved
Auto-N Duplex Test
Reserved
01
STATUS
T4
Cap.
Pream. Auto-N Remote Auto-N Link
Supr. Compl. Fault Cap. Status
TX FDX TX HDX Rsvd Rsvd
Rsvd
Extd
Cap.
04 Auto-Neg. Next FLP Rcv Remote
Reserved
FC
Adv
LP
T4
Adv
LP
Advertised Protocol Selector Field
Advertise Page
Ack
LP
Fault
LP
Adv
LP
Adv
LP
05 Link Part. LP Next
Reserved
LP
LP
Link Partner Protocol Selector Field
Ability
06 Auto-Neg.
Expansion
Page
Ack
RF
FC
Reserved
T4
TX FDX TX HDX 10 FDX 10 HDX
Pardet LP Next Next Pg New Pg LP AutoN
Fault Pg Able Able
Rcv
Cap.
16
17
21
Aux.
Config.
Aux.
Conf/Stat
MDINTR
BP
4B5B
100
FDX
INTR
PEND
BP
BP BP_A Rsvd TX/FX
FEF
RMCI Force SPDLE Rsvd RPDCT Reset Pream. Sleep Remote
SCR ALIGN DPOK
100
HDX
Select Enable Enable 100LNK D_CTL
Reserved
R-EN St. Mch Supr. mode LoopOut
Auto-N. Monitor Bit [3:0]
Reserved
Reserved
FDX
Rsvd
Link
Mask Mask
INTR
Reserved
FDX
Rsvd
Link
Rsvd
INTR
Mask
Change
Change
Status
Key to Default
In the register description that follows, the default
column takes the form:
<Access Type>:
RO = Read only
<Reset Value>, <Access Type> / <Attribute(s)>
RW = Read/Write
Whereꢁ
<Reset Value>:
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
1
0
X
Bit set to logic one
Bit set to logic zero
No default value
(PIN#) Value latched in from pin # at reset
18
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
8.1 Basic Mode Control Register (BMCR) - 00
Bit
0.15
Bit Name
Reset
Default
0,RW/SC Reset
1=Software reset
Description
0=Normal operation
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of
one until the reset process is completed
Loopback
0.14
Loopback
0, RW
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appears at the MCI receive outputs
Speed Select
1 = 100Mbps
0 = invalid
Auto-negotiation Enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in auto-
negotiation status
0.13
0.12
0.11
Speed Selection
1, RW
1, RW
0, RW
Auto-negotiation
Enable
Power Down
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down state
and while in the power-down state, the PHY should not generate
spurious signals on the MCI
1 = Power down
0 = Normal operation
0.10
Isolate
0,RW
Isolate
1 = Isolates the DM9331A from the MCI with the exception of the
serial management. (When this bit is asserted, the DM9331A does
not respond to the TXD [0:1] and TXEN inputs, and it shall present a
high impedance on its TXCLK, RXDV, and RXD [0:1] outputs. When
the PHY is isolated from the MCI, it shall respond to the
management transactions)
0 = Normal operation
0.9
Restart Auto-
negotiation
0,RW/SC Restart Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning a value of 1 until auto-
negotiation is initiated by the DM9331A. The operation of the auto-
negotiation process will not be affected by the management entity
that clears this bit
0 = Normal operation
Preliminary
19
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
0.8
Duplex Mode
1,RW
Duplex Mode
1 = Full duplex operation. Duplex selection is allowed when Auto-
negotiation is disabled (bit 12 of this register is cleared). With auto-
negotiation enabled, this bit reflects the duplex capability selected by
auto-negotiation
0 = Normal operation
0.7
Collision Test
Reserved
0,RW
0,RO
Collision Test
1 = Collision test enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TXEN
0 = Normal operation
0.6-0.0
Reserved
Write as 0, ignore on read
8.2 Basic Mode Status Register (BMSR) - 01
Bit
Bit Name
Default
Description
1.15
100BASE-T4
0,RO/P
100BASE-T4 Capable
1 = DM9331A is able to perform in 100BASE-T4 mode
0 = DM9331A is not able to perform in 100BASE-T4 mode
100BASE-TX Full Duplex Capable
1 = DM9331A is able to perform 100BASE-TX in full duplex mode
0 = DM9331A is not able to perform 100BASE-TX in full duplex mode
100BASE-TX Half Duplex Capable
1 = DM9331A is able to perform 100BASE-TX in half duplex mode
0 = DM9331A is not able to perform 100BASE-TX in half duplex
mode
1.14
1.13
100BASE-TX
Full Duplex
1,RO/P
1,RO/P
100BASE-TX
Half Duplex
1.12
1.11
1.10-1.7
Reserved
Reserved
Reserved
0,RO/P
0,RO/P
0,RO
Reserved
Reserved
Reserved
Write as 0, ignore on read
1.6
MF Preamble
Suppression
0,RO
MII Frame Preamble Suppression
1 = PHY will accept management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed
1.5
1.4
Auto-negotiation
Complete
0,RO
Auto-negotiation Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
Remote Fault
Remote Fault
0,
RO/LH
1 = Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is DM9331A
implementation specific. This bit will set after the RF bit in the
ANLPAR (bit 13, register address 05) is set
0 = No remote fault condition detected
Auto Configuration Ability
1.3
1.2
Auto-negotiation
Ability
1,RO/P
1 = DM9331A is able to perform auto-negotiation
0 = DM9331A is not able to perform auto-negotiation
Link Status
Link Status
0,RO/LL
1 = Valid link is established (for 100Mbps operation)
0 = Link is not established
The link status bit is implemented with a latching function, so that the
20
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
occurrence of a link failure condition causes the link status bit to be
cleared and remain cleared until it is read via the management
interface
1.1
1.0
Reserved
Extended
Capability
0,RO/LH Reserved
Extended Capability
1,RO/P
1 = Extended register capable. 0 = Basic register capable only
8.3 Auto-negotiation Advertisement Register (ANAR) - 04
This register contains the advertised abilities of this DM9331A device as they will be transmitted to its link partner
during Auto-negotiation.
Bit
Bit Name
Default
Description
4.15
NP
0,RO/P
Next Page Indication
0 = No next page available
1 = Next page available
The DM9331A has no next page, so this bit is permanently set to 0
4.14
ACK
0,RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9331A's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software
should not attempt to write to this bit
Remote Fault
4.13
RF
0, RW
1 = Local device senses a fault condition
0 = No fault detected
4.12-4.11
4.10
Reserved
FCS
0, RW
1, RW
Reserved
Write as 0, ignore on read
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
100BASE-T4 Support
4.9
T4
0, RO/P
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The DM9331A does not support 100BASE-T4 so this bit is
permanently set to 0
4.8
4.7
TX_FDX
TX_HDX
1, RW
1, RW
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the local device
0 = 100BASE-TX full duplex is not supported
100BASE-TX Support
1 = 100BASE-TX is supported by the local device
0 = 100BASE-TX is not supported
Reserved
4.6
4.5
4.4-4.0
Reserved
Reserved
Selector
0, RW
0, RW
Reserved
<00001>, RW Protocol Selection Bits
These bits contain the binary encoded protocol selector supported
by this node
<00001>indicates that this device supports IEEE 802.3 CSMA/CD
8.4 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Preliminary
21
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
Bit
5.15
Bit Name
Default
0, RO
Description
Next Page Indication
NP
0 = Link partner, no next page available
1 = Link partner, next page available
5.14
ACK
0, RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9331A's auto-negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not
attempt to write to this bit
5.13
RF
0, RO
Remote Fault
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
Reserved
Write as 0, ignore on read
Flow Control Support
5.12-5.11
5.10
Reserved
FCS
X, RO
0, RW
1 = Controller chip supports flow control ability by link partner
0 = Controller chip doesn’t support flow control ability by link partner
100BASE-T4 Support
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the link partner
0 = 100BASE-TX full duplex is not supported by the link partner
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the link partner
0 = 100BASE-TX half duplex is not supported by the link partner
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link partner
10BASE-T Support
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link partner
5.9
5.8
T4
0, RO
0, RO
0, RO
0, RO
0, RO
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
5.7
5.6
5.5
5.4-5.0
<00000>, RO Protocol Selection Bits
Link partner’s binary encoded protocol selector
8.5 Auto-negotiation Expansion Register (ANER)- 06
6.15-6.5
6.4
Reserved
PDF
X, RO
Reserved
Write as 0, ignore on read
Local Device Parallel Detection Fault
0, RO/LH
PDF = 1 : A fault detected via parallel detection function
PDF = 0 : No fault detected via parallel detection function
Link Partner Next Page Able
LP_NP_ABLE = 1 : Link partner, next page available
LP_NP_ABLE = 0 : Link partner, no next page
Local Device Next Page Able
6.3
6.2
LP_NP_ABLE
NP_ABLE
0, RO
0,RO/P
NP_ABLE = 1 : DM9331A, next page available
NP_ABLE = 0 : DM9331A, no next page
DM9331A does not support this function, so this bit is always 0
22
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
6.1
6.0
PAGE_RX
0, RO/LH
0, RO
New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management
Link Partner Auto-negotiation Able
LP_AN_ABLE
A “1” in this bit indicates that the link partner supports Auto-
negotiation
8.6 DAVICOM Specified Configuration Register (DSCR) - 16
Bit
16.15
Bit Name
BP_4B5B
Default
0, RW
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and
symbol decoding functions) bypassed. Transmit functions
( symbol encoder and scrambler) bypassed
0 = Normal operation
16.14
16.13
BP_SCR
0, RW
0, RW
BP_ALIGN
16.12
BP_ADPOK
0, RW
Bypass ADPOK
Force signal detector (SD) active. This register is for debug only,
not release to customer
1 = Force SD is OK
0 = Normal operation
16.11
16.10
Reserved
TX
0,RW
1, RW
Reserved
100BASE-TX or FX Mode Control
1 = 100BASE-TX operation
0 = 100BASE-FX operation
16.9
FEF
0, RW
Far End Fault Enable
Control the Far End Fault mechanism associated with 100Base-FX
operation
1 = Enable
0 = Disable
16.8
16.7
Reserved
1, RW
0, RW
Reserved
Write as 1
Force Good Link in 100Mbps
F_LINK_100
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Write as 0
Reserved
16.6
16.5
16.4
Reserved
Reserved
0, RW
0, RO
1, RW
Write as 0, ignore on read
RPDCTR-EN
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0: Disable automatic reduced power down
1: Enable automatic reduced power down
Reset State Machine
16.3
SMRST
0, RW
Preliminary
23
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed.
MF Preamble Suppression Control
MCI frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
16.2
16.1
MFPSC
SLEEP
0, RW
0, RW
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loopout Control
16.0
RLOUT
0, RW
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
8.7 DAVICOM Specified Configuration and Status Register (DSCSR) – 17
Bit
17.15
Bit Name
100FDX
Default
1, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M full duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
17.14
100HDX
1, RO
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M half-duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
17.13
17.12
17.11-
17.9
Reserved
Reserved
Reserved
0, RO
0, RO
0, RO
Reserved
Reserved
Reserved
Read as 0, ignore on write
17.8-17.4
Reserved
0, RW
Reserved
17.3-17.0
ANMB [3:0]
0, RO
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits
B3 B2 b1 b0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
24
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Auto-negotiation completed successfully
8.8 DAVICOM Specified Interrupt Register – 21
Bit
Bit Name
Default
Description
21.15
INTR PEND
0, RO
Interrupt Pending
Indicates that the interrupt is pending and is cleared by the current
read. This bit shows the same result as bit 0. (INTR Status)
Reserved
21.14-
21.12
21.11
Reserved
FDX Mask
0, RO
1, RW
Full-duplex Interrupt Mask
When this bit is set, the Duplex status change will not generate the
interrupt
21.10
21.9
Reserved
LINK Mask
1, RW
1, RW
Reserved
Link Interrupt Mask
When this bit is set, the link status change will not generate the
interrupt
21.8
INTR Mask
1, RW
Master Interrupt Mask
When this bit is set, no interrupts will be generated under any
condition
21.7-21.5
21.4
Reserved
FDX Change
0, RO
0,RO/LH
Reserved
Duplex Status Change Interrupt
“1” indicates a change of duplex since last register read. A read of
this register will clear this bit
21.3
21.2
Reserved
LINK Change
0, RO/LH
0, RO/LH
Reserved
Link Status Change Interrupt
“1” indicates a change of link since last register read. A read of this
register will clear this bit
21.1
21.0
Reserved
INTR Status
0, RO
0, RO/LH
Reserved
Interrupt Status
The status of MDINTR#. “1” indicates that the interrupt mask is off
that one or more of the change bits are set. A read of this register
will clear this bit
Preliminary
25
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
9. DC and AC Electrical Characteristics
9.1 Absolute Maximum Ratings ( 25°C )
Symbol
DVCC, AVCC
VIN
Parameter
Min.
-0.3
-0.5
-0.3
-65
0
Max.
3.6
5.5
3.6
+125
85
Unit
V
V
Conditions
Supply Voltage
DC Input Voltage (VIN)
VOUT
Tstg
Tc
DC Output Voltage (VOUT)
Storage Temperature Rang (Tstg)
Case Temperature
V
°C
°C
°C
EIAJ-4701B
LT
Lead Temp. (TL, Soldering, 10 sec.)
---
235
JEDEC J-STD-020A
9.2 Operating Conditions
Symbol
Parameter
Min.
Max.
Unit
Conditions
DVCC, AVCC
TA
Supply Voltage
3.135
ꢀ
3.465
70
85
88
25
45
18
3
V
°C
°C
mA
mA
mA
mA
mA
Operating Ambient Temperature
Case Temperature
100BASE-TX
100BASE-FX
Auto-negotiation
Tc
PD
0
---
---
---
---
---
As TA = 70°C
3.3V
(Power Dissipation)
3.3V
3.3V
3.3V
3.3V
Power Reduced Mode (without cable )
Power Down Mode
Comments
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
the device.
These are stress ratings only.
Functional operation of this device at these or any
26
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
9.3 DC Electrical Characteristics (VCC = 3.3V, TA = 0 ~ 70°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
TTL Inputs
(TXD0, TXD1, TXEN, LNKFAULTPROG, LNKFAULTEN, MDC, MDIO,CHIPEN, OPMODE0-2, TPSET0, TPSET1,
DISFEF,SCRAMEN, RESET# )
VIL
VIH
IIL
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
---
2.0
---
---
---
---
---
0.8
---
10
-10
V
V
uA
uA
VIN = 0.4V
VIN = 2.7V
IIH
---
MCI TTL Outputs
( RXD0, RXD1, RXDV, RXER,TPFAULT, FXFAULT MDIO)
VOL
VOH
Output Low Voltage
Output High Voltage
---
2.4
---
---
0.4
---
V
V
IOL = 4mA
IOH = -4mA
Non-MCI TTL Outputs
(LINKLED#, ACTIVELED#, FULL/HALFLED#, FAULTLED#, MDINTR#)
VOL
VOH
Output Low Voltage
Output High Voltage
---
2.4
---
---
0.4
---
V
V
IOL = 2mA
IOH = -2mA
Receiver
VICM
RX+/RX- Common mode Input Voltage
---
1.2
---
V
100 Ω Termination Across
Transmitter
VTD100 100TX+/- Differential Output Voltage
1.9
19
2.0
20
2.1
21
V
mA
V
Peak to Peak
ITD100
VOH
100TX+/- Differential Output Current
PECL Output Voltage – High
VCC-
1.05
VCC-
1.81
VCC-
1.16
VCC-
1.81
17
VCC-
0.88
VCC-
1.62
VCC-
0.88
VCC-
1.48
19
VOL
VIH
VIL
PECL Output Voltage – Low
PECL Input Voltage – High
PECL Input Voltage – Low
V
V
V
IFD100 100FX+/- Differential Output Current
18
mA
Preliminary
27
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
9.4 AC Electrical Characteristics & Timing Waveforms
9.4.1 TP Interface
Symbol
Parameter
Min.
3.0
0
Typ.
---
---
Max.
5.0
0.5
Unit
ns
Conditions
tTR/F
tTM
tTDC
100TX+/- Differential Rise/Fall Time
100TX+/- Differential Rise/Fall Time Mismatch
100TX+/- Differential Output Duty Cycle
Distortion
ns
ns
0
---
0.5
tT/T
XOST
100TX+/- Differential Output Peak-to-Peak Jitter
100TX+/- Differential Voltage Overshoot
0
0
---
---
1.4
5
ns
%
9.4.2 Oscillator Timing
Symbol
Parameter
Min.
Typ.
20
10
Max.
20.002
12
Unit
ns
ns
Conditions
tCKC
tPWH
tPWL
OSC Cycle Time
OSC Pulse Width High
OSC Pulse Width Low
19.998
50ppm
8
8
10
12
ns
9.4.3 MDC/MDIO Timing
Symbol
T0
Parameter
MDC Cycle Time
MDIO Setup Before MDC
MDIO Hold After MDC
MDC To MDIO Output Delay
Min.
80
10
10
0
Typ.
---
---
---
---
Max.
---
---
---
300
Unit
Conditions
ns
ns
ns
ns
T1
T2
T3
When OUTPUT By STA
When OUTPUT By STA
When OUTPUT By DM9331A
9.4.4 MDIO Timing When OUTPUT by STA
MDC
t0
10ns
(Min)
10ns
(Min)
t
2
t
1
MDIO
Figure 9-1
28
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
9.4.5 MDIO Timing When OUTPUT by DM9331A
ꢀꢁ
MDC
0 - 300 ns
t
3
MDIO
Figure 9-2
9.4.6 Auto-negotiation and Fast Link Pulse Timing Parameters
Symbol
Parameter
Clock/Data Pulse Width
Clock Pulse To Data Pulse Period
Clock Pulse To Clock Pulse Period
FLP Burst Width
Min.
---
55.5
111
-
Typ.
100
62.5
125
2
Max.
---
69.5
139
-
Unit
ns
us
Conditions
T1
T2
T3
T4
T5
-
DATA = 1
us
ms
ms
pulse
FLP Burst To FLP Burst Period
Clock/Data Pulses in a Burst
8
17
24
33
9.4.7 Auto-negotiation and Fast Link Pulse Timing Diagram
Clock Pulse
Data Pulse
Clock Pulse
FAST LINK
PULSES
t
1
t
1
t
2
t
3
FLP Burst
FLP Burst
FLP Bursts
t
4
t
5
Figure 9-3
Preliminary
29
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
9.4.8 TXD to TP or FX Transmit Latency Timing Diagram
TXD [1:0]
ꢀꢁ
ꢀ
TX
Figure 9-4
9.4.9 TXD to TP or FX Transmit Latency Parameters
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
td
-
-
165
ns
TXD[1:0] to TX± or FXTD± ( TX Latency )
9.4.10 TP or FX to RXD Receive Latency Timing Diagram
ꢀ
RX
ꢀꢁ
RXD [1:0]
Figure 9-5
9.4.11 TP or FX to RXD Receive Latency Parameters
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Td
-
-
205
ns
RX± or FXRD± to RXD[1:0] ( RX Latency )
30
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10. Application Notes
DM9331A. There should be no power or ground planes in
the area under the network side of the transformer to include
the area under the RJ-45 connector. (Refer to Figure 5 and
10.1 Network Interface Signal Routing
6.) Keep chassis ground away from all active signals. The
RJ-45 connector and any unused pin should be tied to
chassis ground through a resistor divider network and a 2KV
bypass capacitor.
Place the transformer as close as possible to the RJ-45
connector. Place all the 50 ꢀ resistors as close as
possible to the DM9331A RXꢂ and TXꢂ pins. Traces
routed from RXꢂ and TXꢂ to the transformer should run
in close pairs directly to the transformer. The designer
should be careful not to place the transmit pair across the
receive pair. As always, vias should be avoided as much
as possible. The network interface should be void of any
signals other than the TXꢂ and RXꢂ pairs between the
RJ-45 to the transformer and the transformer to the
The Band Gap resistor should be placed as physically close
to pins 47 and 48 as possible. (Refer to Figure 1, 2, 3-1, and
3-2). The designer should not run any high-speed signal
near the Band Gap resistor placement.
10.2 100Base-TX Side Application
3
Transformer
RJ45
RX+
50£
[
1:1
1%
1
2
3
4
5
4
ꢁ
0.1
RX-
F
50£
[
1%
3.3V AVCC
AGND
ꢁ
0.1
F
ꢁ
0.1
ꢀ
50
1%
F
AGND
DM9331A
AGND
1:1
7
6
7
8
TX+
ꢀ
50
1%
3.3V AVCC
8
TX-
ꢁ
0.1
F
75£
[
1%
75£
[
1%
47
48
ꢀ
75
1%
BGRES
75£
[
AGND
1%
ꢀ
6.8K , 1%
BGRESG
ꢁ
ꢁ
0.1 F/2KV or 0.01 F/
2KV
Chasis GND
Figure 10-1
Preliminary
31
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.3 100Base-TX Side (Power Reduction Application)
3
4
Transformer
RJ45
RX+
RX-
50£
[
1%
1:1
1
2
3
4
5
ꢁ
0.1
F
50£
[
1%
3.3V AVCC
AGND
ꢁ
0.1
F
ꢁ
0.1
ꢀ
78
1%
F
DM9331A
AGN
D
AGND
3.3V AVCC
1.25:1
7
6
7
8
TX+
ꢀ
78
1%
8
TX-
ꢁ
0.1
F
75£
[
1%
75£
[
1%
47
48
ꢀ
75
1%
BGRES
75£
[
AGND
ꢀ
8.5K , 1%
1%
BGRESG
ꢁ
ꢁ
0.1 F/2KV or 0.01 F/
2KV
Chasis GND
Figure 10-2
32
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.4 100Base-FX Side Application
FXVCC (3.3V)
ꢀ
127
3.3V Fiber
Transceiver
FXRD+
FXRD-
ꢀ
83
ꢀ
127
1 GND_RX
AGN
FXVCC (3.3V)
D
ꢀ
83
2 RD+
ꢀ
127
3 RD-
AGND
SD
4SD
83£
[
FXVCC (3.3V)
FXVCC (3.3V)
FXVCC (3.3V)
5VCC_RX
DM9331A
AGND
6VCC_TX
ꢀ
69
7TD-
FXTD-
FXTD+
ꢀ
182
8TD+
ꢀ
ꢀ
69
AGND
9GND_TX
182
BGRES
AGND
AGND
ꢀ
6.8K , 1%
BGRESG
Figure 10-3-1
FXVCC (5V)
ꢀ
83
5V Fiber
Transceiver
FXRD+
FXRD-
59£
[
ꢀ
83
1 GND_RX
2 RD+
ꢀ
68
FXVCC (5V)
ꢀ
ꢀ
59
AGN
D
ꢀ
83
68
3 RD-
AGND
SD
4SD
59£
[
FXVCC (5V)
FXVCC (5V)
62
5VCC_RX
68£
[
DM9331A
FXVCC (5V)
6VCC_TX
ꢀ
AGND
7TD-
FXTD-
FXTD+
ꢀ
268
8TD+
ꢀ
62
AGND
9GND_TX
ꢀ
268
BGRES
AGND
AGND
ꢀ
6.8K , 1%
BGRESG
Figure 10-3-2
Preliminary
33
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.5 Power Decoupling Capacitors
Davicom Semiconductor recommends all the decoupling
capacitors for all power supply pins are placed as close as
possible to the power pads of the DM9331A (The best
placed distance is < 3mm from the above mentioned pins).
The recommended decoupling capacitance is 0.1 F or
0.01 F, as required by the design layout.
41
39
1
2
31
30
DM9331A
9
Figure 10-4
34
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.6 Ground Plane Layout
A single ground plane approach is recommended to
minimize EMI. Bad ground plane partitioning can cause
more EMI emissions that could make the network interface
card not compliant with specific FCC regulations (part 15).
Figure 5 shows a recommended ground layout scheme.
DM9331A
DM9331A
Figure 10-5
Preliminary
35
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.7 Power Plane Partitioning
The power planes are approximately illustrated in Figure 6.
The ferrite bead used should have an impedance at least 75
ꢀ at 100MHz. A suitable bead is the Panasonic surface
mound bead, part number EXCCL4532U or an equivalent.
A 10 F electrolytic bypass capacitors should be connected
between VCC and Ground at each side of the ferrite bead.
DM9331A
DM9331A
Figure 10-6
36
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.8 Media Converter Interface
Through the Media Converter Interface (MCI), the
DM9331A connects to another DM9331A for the FX to TP
media converter or FX to FX, TP to TP repeater application.
50MHz
VCC
VCC
4.7K
4.7K
OSCIN
OSCIN
TPSET0
TXEN
TPSET1
RXDV
FXRD¡
Ó
TX¡
Ó
TXD[0:1]
RXD[0:1]
DM9331A
DM9331A
RX¡
Ó
TXD[0:1]
FXTD¡
Ó
RXD[0:1]
RXDV
TXEN
FX mode
TP mode
50MHz
OSCIN
OSCIN
RXDV
TXEN
FXRD¡
Ó
FXTD¡
Ó
TXD[0:1]
RXD[0:1]
DM9331A
DM9331A
FXRD¡
Ó
TXD[0:1]
FXTD¡
Ó
RXD[0:1]
RXDV
TXEN
FX mode
FX mode
50MHz
VCC
VCC
VCC
VCC
4.7
K
4.7
K
4.7
K
4.7K
OSCIN
OSCIN
TPSET0
TXEN
TPSET1
TPSET0
TPSET1
RXDV
RX¡
Ó
TX¡
Ó
TXD[0:1]
RXD[0:1]
DM9331A
DM9331A
RX¡
Ó
TXD[0:1]
RXD[0:1]
RXDV
ꢀ
TX
TXEN
TP mode
TP mode
Figure 10-7
Preliminary
37
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.9 Link Fault propagation Application
The DM9331A will propagate link fault signals from
media to another DM9331A. If link fault happens, the
DM9331A will send out fault signal to another
DM9331A.
DM9331A will send out a far end fault signal to the
fiber optic media, if the DM9331A receive the fault
signal from the other device.
In TP mode, in the event of a TP receive link failure,
the DM9331A will send out a TP fault signal. The
DM9331A will stop to transmit idle signal to the CAT5
media, if the DM9331A receive the fault signal from
the other device.
In FX mode, there are two types of link failures,
receive link failure or remote fault (receive far end
fault). In the event of a fiber receive link failure, the
DM9331A will send out an FX fault signal. The
VCC
VCC
VCC
VCC
4.7K
4.7K
TPSET0
TPSET1
LNKFAULTEN
FXRD¡
LNKFAULTEN
TX¡
Ó
TPFAULT
Ó
LNKFAULT#
DM9331A
DM9331A
RX¡
Ó
FXFAULT
FXTD¡
Ó
LNKFAULT#
(MCI)
(MCI)
FX mode
TP mode
VCC
VCC
LNKFAULTEN
LNKFAULT#
LNKFAULTEN
FXFAULT
FXRD¡
Ó
FXTD¡
Ó
DM9331A
DM9331A
FXRD¡
Ó
FXFAULT
FXTD¡
Ó
LNKFAULT#
(MCI)
(MCI)
FX mode
FX mode
VCC
VCC
VCC
VCC
VCC
VCC
4.7K
4.7K
4.7K
4.7K
TPSET1
TPSET0
TPSET0
RX¡
TPSET1
LNKFAULTEN
LNKFAULTEN
TX¡
TPFAULT
Ó
LNKFAULT#
Ó
DM9331A
DM9331A
RX¡
Ó
TPFAULT
TX¡
Ó
LNKFAULT#
(MCI)
(MCI)
TP mode
TP mode
Figure 10-8
38
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.10 Auto-loopback Diagostic
The DM9331A can be easily Diagnostic FX route with
remote DM9331A. This function can implement at single
and Cascade mode.
Single:
50MHz
50MHz
OSCIN
OSCIN
VCC
VCC
DIAG_ACT
DIAG_ACT
FXTDꢀ
FXRDꢀ
DM9331A
DM9331A
FXRDꢀ
FXTDꢀ
DIAG_STO
DIAG_STO
Figure 10-9
Cascade:
50MHz
50MHz
50MHz
OSCIN
OSCIN
VCC
VCC
OSCIN
OSCIN
DIAG_ACT
DIAG_ACT
DIAG_STO
DIAG_ACT
FXRD
FXTD
FXTD
FXRD
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
DM9331A
DM9331A
DM9331A
DM9331A
ꢁ
ꢁ
ꢂ
ꢂ
FXTD
FXRD
FXRD
FXTD
ꢀ
ꢀ
ꢀ
ꢀ
DIAG_STO
DIAG_STO
DIAG_ACT
DIAG_STO
Figure 10-10
Preliminary
39
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.11 Media Converter or Repeater Application
The DM9331A chip set can easily use media converters or
repeaters for long distance device connection. You can use
two media converters to connect two devices whose
distance is 2.2km. See Figure 9-1. If the distance is more
than 2.2km, you can add an FX repeater to extend distance.
See Figure 9-2. In the last miles, if the distance of the user
device is more than 100m, you can add TP repeaters to
extend the distance to 400m. See figure 9-3.
Converter
Converter
Cat5
Cat5
Fiber Optic
DM9331A
DM9331A
DM9331A
DM9331A
SW
SW
TP
FX
FX
TP
Figure 10-11
extend the distance
Fiber Optic
Converter
Repeater
Converter
Cat5
Fiber Optic
Cat5
DM9331A
DM9331A
DM9331A
DM9331A
DM9331A
DM9331A
SW
sw
FX
TP
FX
FX
FX
TP
under full-duplex mode
Figure 10-12
extend the distance
Cat5
Repeater
Repeater
Repeater
User
Cat5
Cat5
Cat5
DM9102A
DM9331A
DM9331A
DM9331A
DM9331A
DM9331A
DM9331A
SW
NIC
TP
TP
TP
TP
TP
TP
under full-duplex mode
Figure 10-13
40
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.12 Link Fault Propagation LED Display
Since the media converter is a ꢀdummyꢁ device, the link
fault propagation becomes very important. The devices at
both ends need to know whether the link is OK or Non-OK
on the whole path.
(LD), local converter (LC), remote converter (RC) and
remote device (RD), and three segments of transmit and
receive connection. Table 10 lists the LED status of all
devices. It shows the current link status of all the devices
when they are at auto-negotiation modes.
Figure 10 shows the DM9331A to the DM9331A
connection. The whole path is separated into local device
Local Device
LD
Local Converter
Remote Converter
Remote Device
RD
LT
LR
FT
RT
DM9331A
DM9331A
DM9331A
DM9331A
LC
RC
RR
FR
TP
FX
FX
TP
Figure 10-14
Local
device
Link
LED
Local Converter
Remote Converter
FX side TP side
Remote
device
Link
LED
Condition
(Auto-
negotiation )
TP side
FX side
Link LED Fault LED Link LED Fault LED Link LED Fault LED Link LED Fault LED
LT disconnect
LR disconnect
LT & LR
off
off
off
off
off
off
on
off
on
on
on
on
off
off
off
on
on
on
on
off
on
off
on
off
off
off
off
off
on
off
disconnect
FT disconnect
FR disconnect
FT & FR
off
off
off
off
off
off
off
off
off
on
off
off
on
on
on
off
on
off
on
on
on
off
off
off
off
off
off
off
off
off
disconnect
RT disconnect
RR disconnect
RT & RR
on
off
off
on
off
off
off
off
off
on
on
on
off
on
on
on
on
on
off
off
off
off
off
off
off
on
on
off
off
off
disconnect
Table 10
Preliminary
41
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.13 Magnetics Selection Guide
Refer to Table 2 for transformer requirements. Transformers
meeting these requirements are available from a variety of
magnetic manufacturers. Designers should test and qualify
all magnetics before using them in an application. The
transformers listed in Table 2 are electrical equivalents, but
may not be pin-to-pin equivalents.
Manufacturer
Part Number
Pulse Engineering
PE-68515, H1078, H1012
H1102
Delta
YCL
Halo
LF8200, LF8221x
20PMT04, 20PMT05
TG22-3506ND, TD22-3506G1, TG22-S010ND
TG22-S012ND
Nano Pulse Inc.
NPI 6181-37, NPI 6120-30, NPI 6120-37
NPI 6170-30
Fil-Mag
Bel Fuse
Valor
PT41715
S558-5999-01
ST6114, ST6118
Macronics
HS2123, HS2213
Table 2
42
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
11. Package Information
LQFP 48L (F.P. 2mm) Outline Dimensions
unit: inches/mm
ꢀ
Symbol
Dimensions in inches
Dimensions in mm
Notes:
Min.
-
Nom.
-
Max.
0.063
0.006
0.057
0.011
0.009
0.008
0.006
Min.
-
Nom.
-
Max.
1.6
A
A1
A2
b
1. To be determined at seating plane.
0.002
0.053
0.007
0.007
0.004
0.004
-
0.05
1.35
0.17
0.17
0.09
0.09
-
0.15
1.45
0.27
0.23
0.20
0.16
2. Dimensions D1 and E 1do not include mold protrusion.
D1 and E1 are maximum plastic body size dimensions
including mold mismatch.
3. Dimensions b do not include dambar protrusion. Total in
excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
4. Exact shape of each corner is optional.
5. These dimensions apply to the flat section of the lead
between 0.10mm and 0.25mm from the lead tip.
6. A1 is defined as the distance from the seating plane to the
lowest point of the package body.
0.055
1.40
0.009
0.22
b1
C
0.008
0.20
-
-
C1
D
-
-
0.354BSC
0.276BSC
0.354BSC
0.276BSC
0.020BSC
0.024
9.00BSC
7.00BSC
9.00BSC
7.00BSC
0.50BSC
0.60
D1
E
E1
e
7. Controlling dimension: millimeter.
8. Reference documents: JEDEC MS-026 , BBC.
L
0.018
0º
0.030
12º
0.45
0º
0.75
12º
L1
y
0.039REF
0.004MAX
-
1.00REF
0.1MAX
-
ꢃ
Preliminary
43
Version: DM9331A-DS-P01
April 28, 2002
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
DAVICOM will not be bound by any terms inconsistent with
these unless DAVICOM agrees otherwise in writing.
Acceptance of the buyer’s orders shall be based on these
12. Ordering Information
Part Number
Pin Count
Package
LQFP
terms.
DM9331AE
48
Disclaimer
Company Overview
The information appearing in this publication is believed to
be accurate. Integrated circuits sold by DAVICOM
DAVICOM Semiconductor, Inc. develops and manufactures
integrated circuits for integration into data communication
products. Our mission is to design and produce IC products
that are the industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal, we have
built an organization that is able to develop chipsets in
response to the evolving technology requirements of our
customers while still delivering products that meet their cost
requirements.
Semiconductor are covered by the warranty and patent
indemnification provisions stipulated in the terms of sale
only. DAVICOM makes no warranty, express, statutory,
implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s)
from patent infringement. FURTHER, DAVICOM MAKES
NO WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PURPOSE. DAVICOM deserves the right to halt
production or alter the specifications and prices at any time
without notice. Accordingly, the reader is cautioned to verify
that the data sheets and other information in this publication
are current before placing orders. Products described herein
are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability
requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without
additional processing by DAVICOM for such applications.
Please note that application circuits illustrated in this
document are for reference purposes only.
Products
We offer only products that satisfy high performance
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and soon to be released products are based on our
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DAVICOM’s terms and conditions printed on the order
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Contact Windows
For additional information about DAVICOM products, contact the sales department at:
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Sales & Marketing Office:
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WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
44
Preliminary
Version: DM9331A-DS-P01
April 28, 2002
相关型号：
DM9334J/883
IC 93 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16, FF/Latch
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