DM9332EP [DAVICOM]
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter; 10 / 100Mbps以太网光纤/双绞线单芯片收发器
| 型号： | DM9332EP |
| 厂家： | 
DAVICOM SEMICONDUCTOR, INC. |
| 描述： | 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| 文件： | 总61页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAVICOM Semiconductor, Inc.
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair
Single Chip Media Converter
DATA SHEET
Preliminary
Version: DM9332-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
CONTENT
1. GENERAL DESCRIPTION............................................................................................... 8
2. BLOCK DIAGRAM........................................................................................................... 8
3. FEATURES ...................................................................................................................... 9
4. PIN CONFIGURATION .................................................................................................. 10
5. PIN DESCRIPTION........................................................................................................ 11
5.1 P2 MII / RMII / Reverse MII Interfaces .......................................................................................................... 11
5.1.1 MII Interfaces ........................................................................................................................................... 11
5.1.2 RMII Interfaces......................................................................................................................................... 11
5.1.3 Reverse MII Interfaces............................................................................................................................. 12
5.2 EEPROM Interfaces....................................................................................................................................... 12
5.3 LED Pins......................................................................................................................................................... 12
5.4 Clock Interface............................................................................................................................................... 13
5.5 Network Interface .......................................................................................................................................... 13
5.6 Miscellaneous Pins ....................................................................................................................................... 13
5.7 Power Pins ..................................................................................................................................................... 13
5.8 Strap pins table.............................................................................................................................................. 14
6. CONTROL AND STATUS REGISTER SET................................................................... 15
6.1 EEPROM & PHY Control Register (0BH)..................................................................................................... 16
2
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.2 EEPROM & PHY Address Register (0CH) ................................................................................................... 16
6.3 EPROM & PHY Data Register (0DH~0EH) ................................................................................................... 16
6.4 Vendor ID Register (28H~29H) ..................................................................................................................... 16
6.5 Port 2 driving capability Register (3AH)...................................................................................................... 16
6.6 Switch Control Register (52H)...................................................................................................................... 17
6.7 VLAN Control Register (53H) ....................................................................................................................... 17
6.8 Switch Status Register (54H) ....................................................................................................................... 17
6.9 Per Port Control/Status Index Register (60H)............................................................................................. 18
6.10 Per Port Control Data Register (61H) ........................................................................................................ 18
6.11 Per Port Status Data Register (62H) .......................................................................................................... 18
6.12 Per Port Forward Control Register (65H).................................................................................................. 19
6.13 Per Port Ingress/Egress Control Register (66H) ...................................................................................... 20
6.14 Bandwidth Control Setting Register (67H)................................................................................................ 21
6.15 Per Port Block Unicast ports Control Register (68H) .............................................................................. 21
6.16 Per Port Block Multicast ports Control Register (69H)............................................................................ 22
6.17 Per Port Block Broadcast ports Control Register (6AH)......................................................................... 22
6.18 Per Port Block Unknown ports Control Register (6BH) .......................................................................... 22
6.19 Per Port Priority Queue Control Register (6DH)....................................................................................... 22
6.20 Per Port VLAN Tag Low Byte Register (6EH) ........................................................................................... 22
6.21 Per Port VLAN Tag High Byte Register (6FH)........................................................................................... 23
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
3
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.22 MIB counters Port Index Register (80H).................................................................................................... 23
6.23 MIB counter Data Register (81H~84H)....................................................................................................... 23
6.24 VLAN grouping table Registers (B0H~BFH)............................................................................................. 24
6.25 TOS Priority Map Registers (C0H~CFH).................................................................................................... 24
6.26 VLAN Priority Map Registers (D0H~D1H) ................................................................................................. 27
7. EEPROM FORMAT........................................................................................................ 28
8. PHY REGISTERS .......................................................................................................... 31
8.1 Basic Mode Control Register (BMCR) – 00H .............................................................................................. 32
8.2 Basic Mode Status Register (BMSR) – 01H ................................................................................................ 33
8.3 PHY ID Identifier Register #1 (PHYID1) – 02H............................................................................................. 34
8.4 PHY ID Identifier Register #2 (PHYID2) – 03H............................................................................................. 34
8.5 Auto-negotiation Advertisement Register (ANAR) – 04H.......................................................................... 35
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05H............................................................. 36
8.7 Auto-negotiation Expansion Register (ANER) - 06H ................................................................................. 37
8.8 DAVICOM Specified Configuration Register (DSCR) – 10H...................................................................... 37
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H................................................ 39
8.10 10BASE-T Configuration/Status (10BTCSR) – 12H.................................................................................. 40
8.11 Power down Control Register (PWDOR) – 13H........................................................................................ 40
8.12 (Specified config) Register – 14H .............................................................................................................. 41
8.13 DAVICOM Specified Receive Error Counter Register (RECR) – 16H ..................................................... 42
4
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) – 17H ........................................................ 42
8.15 Power Saving Control Register (PSCR) – 1DH......................................................................................... 42
9. FUNCTIONAL DESCRIPTION....................................................................................... 43
9.1 Serial Management Interface........................................................................................................................ 43
9.2 Switch function:............................................................................................................................................. 44
9.2.1 Address Learning..................................................................................................................................... 44
9.2.2 Address Aging.......................................................................................................................................... 44
9.2.3 Packet Forwarding ................................................................................................................................... 44
9.2.4 Inter-Packet Gap (IPG) ............................................................................................................................ 44
9.2.5 Back-off Algorithm.................................................................................................................................... 44
9.2.6 Late Collision............................................................................................................................................ 44
9.2.7 Full Duplex Flow Control.......................................................................................................................... 44
9.2.8 Half Duplex Flow Control ......................................................................................................................... 44
9.2.9 Partition Mode.......................................................................................................................................... 45
9.2.10 Broadcast Storm Filtering....................................................................................................................... 45
9.2.11 Bandwidth Control.................................................................................................................................. 45
9.2.12 Port Monitoring Support ......................................................................................................................... 45
9.2.13 VLAN Support ........................................................................................................................................ 46
9.2.13.1 Port-Based VLAN................................................................................................................................ 46
9.2.13.2 802.1Q-Based VLAN........................................................................................................................... 46
9.2.13.3 Tag/Untag ........................................................................................................................................... 46
9.2.14 Priority Support ...................................................................................................................................... 47
9.2.14.1 Port-Based Priority.............................................................................................................................. 47
9.2.14.2 802.1p-Based Priority.......................................................................................................................... 47
9.2.14.3 DiffServ-Based Priority........................................................................................................................ 47
9.3 MII Interface.................................................................................................................................................... 48
9.3.1 MII data interface ..................................................................................................................................... 48
9.3.2 MII Serial Management............................................................................................................................ 48
9.3.3 Serial Management Interface................................................................................................................... 49
9.3.4 Management Interface - Read Frame Structure ...................................................................................... 49
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
5
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
9.3.5 Management Interface - Write Frame Structure ...................................................................................... 49
9.4 Internal PHY functions.................................................................................................................................. 50
9.4.1 100Base-TX Operation ............................................................................................................................ 50
9.4.1.1 4B5B Encoder....................................................................................................................................... 50
9.4.1.2 Scrambler.............................................................................................................................................. 50
9.4.1.3 Parallel to Serial Converter ................................................................................................................... 50
9.4.1.4 NRZ to NRZI Encoder........................................................................................................................... 50
9.4.1.5 MLT-3 Converter................................................................................................................................... 50
9.4.1.6 MLT-3 Driver ......................................................................................................................................... 50
9.4.1.7 4B5B Code Group................................................................................................................................. 51
9.4.2 100Base-TX Receiver.............................................................................................................................. 52
9.4.2.1 Signal Detect......................................................................................................................................... 52
9.4.2.2 Adaptive Equalization............................................................................................................................ 52
9.4.2.3 MLT-3 to NRZI Decoder........................................................................................................................ 52
9.4.2.4 Clock Recovery Module ........................................................................................................................ 52
9.4.2.5 NRZI to NRZ ......................................................................................................................................... 52
9.4.2.6 Serial to Parallel.................................................................................................................................... 52
9.4.2.7 Descrambler.......................................................................................................................................... 52
9.4.2.8 Code Group Alignment.......................................................................................................................... 53
9.4.2.9 4B5B Decoder....................................................................................................................................... 53
9.4.3 10Base-T Operation................................................................................................................................. 53
9.4.4 Collision Detection ................................................................................................................................... 53
9.4.5 Carrier Sense........................................................................................................................................... 53
9.4.6 Auto-Negotiation ...................................................................................................................................... 53
9.5 HP Auto-MDIX Functional Descriptions...................................................................................................... 53
10.
DC AND AC ELECTRICAL CHARACTERISTICS..................................................... 55
10.1 Absolute Maximum Ratings ....................................................................................................................... 55
10.2 Operating Conditions.................................................................................................................................. 55
10.3 DC Electrical Characteristics ..................................................................................................................... 56
6
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
10.4 AC characteristics....................................................................................................................................... 56
10.4.1 Power On Reset Timing......................................................................................................................... 56
10.4.2 Port 2 MII Interface Transmit Timing...................................................................................................... 57
10.4.3 Port 2 MII Interface Receive Timing....................................................................................................... 57
10.4.4 MII Management or host SMI Interface Timing...................................................................................... 58
10.4.5 EEPROM timing..................................................................................................................................... 59
11.
12.
PACKAGE INFORMATION........................................................................................ 60
ORDERING INFORMATION ...................................................................................... 61
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
7
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
1. General Description
The DM9332 is a fully integrated and cost-effective
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip
Media Converter with MII/RMII Interface.
This new product provides basic Layer-2 switch
functions and advance IEEE 802.1Q VLAN, priority
queuing scheme.
data signal between 10/100 Base-TX and 100
Base-FX fast Ethernet.
Media converters are connected between Fiber
cable and twisted cable segments with network and
also the simplest way to interconnect any
equipment’s 100BASE-TX
/
10BASE-T to the
Besides the DM9332 Fiber converter is complies
with IEEE802.3 standards, and designed for convert
100BASE-FX interface network.
2. Block Diagram
Switch Engine
Memory
Switch Fabric
Embedded
BIST
Memory
100M PECL
TXMT/
RXCR
Port 0
100M
MAC
PECL
TX/RX
Switch
Memory
Port 1
10/100M
PHY
10/100M
MAC
Controller
Management
MDI / MDIX
LED
10/100/
1000M
MAC
LEDs
Port 2
Control
MII / RMII
SMI I/F
Control
MIB
EEPROM
Interface
EEPROM
Registers
Counters
8
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
3. Features
10/100BASE-TX/FX switch base single-chip media converter
Compliant with IEEE802.3u 100BASE-TX standard, Compliant with ANSI X3T12 TP-PMD 1995 standard,
Compliant with ANSI X3.166 FDDI-PMD
Ethernet Switch with two 10/100Mb PHY with one MII/RMII/Reverse MII interface
Per port supports 4 priority queues by Port-based, 802.1P VLAN, and IP TOS priority.
Support 802.1Q VLAN up-to 16 VLAN group.
Support VLAN ID tag/untag options
Per port support bandwidth, ingress and egress rate control.
Support Broadcast Storming filter function
Support Store and Forward switching approach
Support IEEE 802.3x Flow Control in Full-duplex mode.
Support Back Pressure Flow Control in Half-duplex mode.
Recode up-to 1K Uni-cast MAC addresses
Automatic aging scheme
EEPROM interface for power up configurations
Support MIB-II counters
Compatible with 3.3V and 5.0V tolerant I/O
DSP PHY with HP Auto-MDIX, DSP architecture PHY Transceiver.
64-pin LQFP, 0.18 um process, support Lead-Free and Halogen–Free
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
9
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
4. Pin Configuration
64 pin LQFP:
49
VCNTL
TEST1
GND
32
31
30
29
VREF
VCC3
50
51
PWRST#
X1
X2
52
53
54
55
56
57
58
59
EECS
EECK
28
27
EEDIO
GND
LNK1_LED
SPD1_LED
26
25
VCC3
RXD2_0
RXD2_1
DM9332
LNK0_LED
SPD0_LED
24
23
22
GND
TEST2
SMI_CK
VCCI
RXD2_2
RXD2_3
RXDV2
60
61
21
20
SMI_DIO
62
63
64
19
18
17
RXC2
RXER
COL2
TEST3
GND
10
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
5. Pin Description
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power, PD=internal pull-low (about 50K Ohm)
# = asserted Low
5.1 P2 MII / RMII / Reverse MII Interfaces
5.1.1 MII Interfaces
Pin No.
Pin Name
I/O
O,PD MII Serial Management Data Clock
I/O MII Serial Management Data
Description
2
3
MDC
MDIO
5,6,7,9
TXD2_3~0
O,PD Port 2 MII Transmit Data
4-bit nibble data outputs (synchronous to the TXC2)
10
12
TXE2
TXC2
O,PD Port 2 MII Transmit Enable
I/O
Port 2 MII Transmit Clock.
14
15
17
18
19
TXER2
CRS2
COL2
RXER2
RXC2
RXDV2
RXD2_3~0
O,PD Port 2 MII Transmit Error
I/O
I/O
I
I
I
I
Port 2 MII Carrier Sense
Port 2 MII Collision Detect.
Port 2 MII Receive Error
Port 2 MII Receive Clock
Port 2 MII Receive Data Valid
20
21,22,24,25
Port 2 MII Receive Data
4-bit nibble data input (synchronous to RXC2)
5.1.2 RMII Interfaces
Pin No.
Pin Name
I/O
Description
2
3
MDC
MDIO
O,PD MII Serial Management Data Clock
I/O MII Serial Management Data
5,6
7,9
10
TXD2_3~2
TXD2_1~0
TXE2
O,PD Reserved
O,PD RMII Transmit Data
O,PD RMII Transmit Enable.
12
14
15
TXC2
TXER2
CRS2
O
O
I
Reserved
Port 2 MII Transmit Error
RMII CRS_DV
17
18
19
COL2
RXER2
RXC2
I
I
I
Reserved, tie to ground in application.
Reserved, tie to ground in application.
50MHz reference clock.
20
21,22
24,25
RXDV2
RXD2_3~2
RXD2_1~0
I
I
I
Reserved, tie to ground in application.
Reserved, tie to ground in application.
RMII Receive Data.
Preliminarydatasheet
11
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
5.1.3 Reverse MII Interfaces
Pin No.
Pin Name
I/O
Description
2
3
MDC
MDIO
O,PD Reserved
I/O
Reserved
5,6,7,9
TXD2_3~0
O,PD Port 2 MII Transmit Data
4-bit nibble data outputs (synchronous to the TXC2)
10
12
14
15
TXE2
TXC2
TXER2
CRS2
O,PD Port 2 MII Transmit Enable
O
25MHz clock output
O,PD Port 2 MII Transmit Error
O
O
Port 2 carrier sense output when TXE2 or RXDV2
asserted.
Port 2 collision output when TXE2 and RXDV2
asserted.
17
COL2
18
19
20
RXER2
RXC2
RXDV2
I
I
I
I
Port 2 MII Receive Error
Port 2 MII Receive Clock
Port 2 MII Receive Data Valid
Port 2 MII Receive Data
21,22,24,25
RXD2_3~0
4-bit nibble data input (synchronous to RXC2)
5.2 EEPROM Interfaces
Pin No.
Pin Name
I/O
Description
27
28
EEDIO
EECK
I/O
EEPROM Data In/Out
O,PD EEPROM Serial Clock
This pin is used as the clock for the EEPROM data transfer.
EEPROM Chip Selection.
29
EECS
O,PD
5.3 LED Pins
Pin No.
Pin Name
I/O
Description
55
LNK1_LED
O
Port 1 Link / Active LED
It is the combined LED of link and carrier sense signal
of the internal PHY1
56
SPD1_LED
O
Port 1 Speed LED
Its low output indicates that the internal PHY1 is
operated in 100M/S, or it is floating for the 10M mode of
the internal PHY1
57
58
LNK0_LED
SPD0_LED
O
O
Port 0 Link / Active LED
It is the combined LED of link and carrier sense signal
of the internal PHY0
Port 0 Speed LED
Its low output indicates that the internal PHY0 is
operated in 100M/S, or it is floating for the 10M mode of
the internal PHY0
12
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
5.4 Clock Interface
Pin No.
Pin Name
I/O
Description
52
53
X1
X2
I
O
Crystal 25MHz In
Crystal 25MHz Out
5.5 Network Interface
Pin No.
Pin Name
I/O
Description
34,35
TX1+/-
I/O
Port 1 TP TX
These two pins are the Twisted Pair transmit in MDI
mode or receive in MDIX mode.
Port 1 TP RX
37,38
RX1+/-
I/O
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode.
Port 0 FX TX
Fiber transmitter data pair.
Port 0 FX RX
41,42
44,45
47
TX0+/-
RX0+/-
BGRES
I/O
I/O
I/O
Fiber receiver data pair.
Band gap Pin
Connect a 1.4K resistor to BGGND in application.
Fiber Signal Detect
1.8V Voltage control
48
49
50
SD
VCNTL
VREF
I
I/O
O
Voltage Reference
Connect a 0.1u capacitor to ground in application.
5.6 Miscellaneous Pins
Pin No.
Pin Name
I/O
Description
30
PWRST#
I
Power on Reset
Low active with minimum 1ms
Serial data management interface clock
60
62
32
59
63
SMI_CK
SMI_DIO
TEST1
I
I/O Serial data management interface in / out
I,PD Tie to VCC3 in application
TEST2
TEST3
I,PD Tie to GND in application
I,PD Tie to VCC3 in application
5.7 Power Pins
Pin No.
Pin Name
I/O
Description
1,13,26,51
11,61
4,8,16,23,31,54,64
39,46
VCC3
VCCI
GND
AVDD3
AVDDI
AGND
P
P
P
P
P
P
Digital 3.3V
Internal 1.8V core power
Digital GND
Analog 3.3V power
Analog 1.8V power
Analog GND
33,40
36,43
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
13
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
5.8 Strap pins table
1: pull-high 1K~10K, 0: floating (default), Pin 29 pull high in application.
Pin No.
Pin Name
Description
0: Port 2 in force 10 Mbps mode
1: Port 2 in force 100 Mbps mode
0= p0 in Copper mode
1= p0 in Fiber mode
0= p1 in Copper mode
1= p1 in Fiber mode
0: BIST
28
EECK
29
14
2
EECS
TXER2
MDC
1: Bypass BIST
5
6
TXD2_3
TXD2_2
TXD2_3
TXD2_2
Mode
MII mode
Reverse MII mode
RMII mode
Reserved (DO NOT USE)
0
0
1
1
0
1
0
1
7
9
TXD2_1
TXD2_0
TXE2
SMI device address 1
SMI device address 0
10
0: Port 2 normal mode
1: Port 2 force mode
14
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6. Control and Status Register Set
The DM9332 implements several control and status
their default values by hardware or software reset unless
specified
registers, which can be accessed by the serial management
interface. These CSRs are byte aligned. All CSRs are set to
Register
Description
Offset
Default value
after reset
00H
40H
XXH
XXH
0A46H
21H
EPCR
EPAR
EPDRL
EPDRH
VID
EEPROM & PHY Control Register
EEPROM & PHY Address Register
EEPROM & PHY Low Byte Data Register
EEPROM & PHY High Byte Data Register
Vendor ID
0BH
0CH
0DH
0EH
28H-29H
3AH
P2FRV
Port 2 driving capability Register
SWITCHCR SWITCH Control Register
VLANCR VLAN Control Register
SWITCHSR SWITCH Status Register
52H
53H
54H
00H
00H
00H
DSP1,2
P_INDEX
P_CTRL
P_STUS
P_RATE
P_BW
DSP Control Register I,II
Per Port Control/Status Index Register
Per Port Control Data Register
Per Port Status Data Register
Per Port Ingress and Egress Rate Control Register
Per Port Bandwidth Control Register
58H~59H
60H
61H
62H
66H
0000H
00H
00H
00H
00H
67H
00H
P_UNICAST Per Port Block Unicast ports Control Register
68H
00H
P_MULTI
P_BCAST
Per Port Block Multicast ports Control Register
Per Port Block Broadcast ports Control Register
69H
6AH
00H
00H
P_UNKNWN Per Port Block Unknown ports Control Register
P_PRI Per Port Priority Queue Control Register
VLAN_TAGL Per Port VLAN Tag Low Byte Register
VLAN_TAGH Per Port VLAN Tag High Byte Register
P_MIB_IDX Per Port MIB counter Index Register
6BH
6DH
6EH
6FH
80H
00H
00H
01H
00H
00H
MIB_DAT
MIB_DAT
MIB_DAT
MIB_DAT
PVLAN
MIB counter Data Register bit 0~7
MIB counter Data Register bit 8~15
MIB counter Data Register bit 16~23
MIB counter Data Register bit 24~31
Port-based VLAN mapping table registers
TOS Priority Map Register
81H
82H
83H
84H
B0-BFH
C0-CFH
D0-D1H
00H
00H
00H
00H
0FH
00H~FFH
50H,FAH
TOS_MAP
VLAN_MAP VLAN priority Map Register
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where:
E = default value from EEPROM setting
T = default value from strap pin
<Access Type>:
RO = Read only
<Reset Value>:
RW = Read/Write
1
0
X
Bit set to logic one
Bit set to logic zero
No default value
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
P = power on reset default value
H = hardware reset, by Reg. 52H bit 6, default value
Reserved bits should be written with 0.
Reserved bits are undefined on read access.
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
15
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.1 EEPROM & PHY Control Register (0BH)
Bit
7:6
5
Name
RESERVED
REEP
Default
0,RO
Description
Reserved
PH0,RW Reload EEPROM. Driver needs to clear it up after the operation completes
PH0,RW Write EEPROM Enable
4
WEP
3
EPOS
PH0,RW EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
2
1
0
ERPRR
ERPRW
ERRE
PH0,RW EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
PH0,RW EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
PH0,RO EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
6.2 EEPROM & PHY Address Register (0CH)
Bit
7:6
5:0
Name
PHY_ADR PH01,RW PHY Address bit 1 and 0; the PHY address bit [4:2] is force to 0.
EROA PH0,RW EEPROM Word Address or PHY Register Address
Default
Description
6.3 EPROM & PHY Data Register (0DH~0EH)
Bit
Name
Default
Description
7:0
EE_PHY_L
PH0,RW EEPROM or PHY Low Byte Data (0DH)
This data is made to write/read low byte of word address defined in Reg. CH to
EEPROM or PHY
7:0
EE_PHY_H
PH0,RW EEPROM or PHY High Byte Data (0EH)
This data is made to write/read high byte of word address defined in Reg. CH to
EEPROM or PHY
6.4 Vendor ID Register (28H~29H)
Bit
7:0
7:0
Name
VIDH
VIDL
Default
PE,0AH,RO
PE,46H.RO
Description
Vendor ID High Byte (29H)
Vendor ID Low Byte (28H)
6.5 Port 2 driving capability Register (3AH)
Bit
Name
Default
Description
7
Reserved
0,RO
Reserved
Port 2 TXD/TXE Driving/Sinking Capability
00: 2mA
6:5
P2_CURR
P01,RW 01: 4mA (default)
10: 6mA
11: 8mA
4:0
RESERVED P01,RW reserved
16
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.6 Switch Control Register (52H)
Bit Name Default
MEM_BIST PH0,RO
Description
Address Table Memory Test BIST Status
7
0: OK
1: Fail
6
5
RST_SW
RST_ANLG P0,RW
P0,RW
Reset Switch Core and auto clear after 10us
Reset Analog PHY Core and auto clear after 10us
4:3
SNF_PORT PE00,RW Sniffer Port Number
Define the port number to act as the sniffer port
00
Port 0
01
Port 1
10
11
Port 2
Reserved
2
CRC_DIS
AGE
PE0,RW
PE0,RW
CRC Checking Disable
When set, the received CRC error packet also accepts to receive memory.
Address Table Aging
00: no aging
1:0
01: 64 ± 32 sec
10: 128 ± 64 sec
11: 256 ±128 sec
6.7 VLAN Control Register (53H)
Bit
7
Name
TOS6
Default
Description
PE0,RW Full IP ToS Field for Priority Queue
1: check most significant 6-bit of TOS
0: check most significant 3-bit only of TOS
6
5
4
RESERVED
UNICAST
VIDFF
0,RO
Reserved
PE0,RW Unicast packet can across VLAN boundary
PE0,RW Replace VIDFF
If the received packet is a tagged VLAN with VID equal to “FFF”, its VLAN field is
replaced with VLAN tag defined in Reg. 6EH and 6FH.
PE0,RW Replace VID01
If the received packet is a tagged VLAN with VID equal to “001”, its VLAN field is
replaced with VLAN tag defined in Reg. 6EH and 6FH.
PE0,RW Replace VID0
3
2
VID1
VID0
If the received packet is a tagged VLAN with VID equal to “000”, its VLAN field is
replaced with VLAN tag defined in Reg. 6EH and 6FH.
PE0,RW Replace priority field in the tag with value define in Reg 6FH bit 7~5.
PE0,RW VLAN mode enable
1
0
PRI
VLAN
1: 802.1Q base VLAN mode enable
0: port-base VLAN only
6.8 Switch Status Register (54H)
Bit
7
Name
MEM_BIST
Default
Description
PH0,RO Address Table Memory Test BIST Status
0: OK
1: Fail
6:0
RESERVED
0,RO
Reserved
Preliminarydatasheet
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March 5, 2012
17
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.9 Per Port Control/Status Index Register (60H)
Bit
7:5
4:2
1:0
Name
reserved
reserved
INDEX
Default
PH0,RW reserved
0,RO
PH0,RW Port index for register 61h~84h
Write the port number to this register before write/read register 61h~84h.
Description
reserved
6.10 Per Port Control Data Register (61H)
Bit
7
6
Name
RESERVED
PARTI_EN
Default
Description
PE0,RW Reserved
PE0,RW Enable Partition Detection
5
NO_DIS_RX PE0,RW Not Discard RX Packets when Ingress Bandwidth Control
When received packets bandwidth reach Ingress bandwidth threshold,
the packets over the threshold are not discarded but with flow control.
4
FLOW_DIS
PE0,RW Flow control in full duplex mode, or back pressure in half duplex mode
enable
0 – enable
1 – disable
3
2
1
0
BANDWIDTH PE0,RW Bandwidth Control
0: Control with Ingress and Egress separately, ref to Register 66h.
1: Control with Ingress or Egress, ref to Register 67h
PE0,RW Broadcast packet filter
BP_DIS
0 – accept broadcast packets
1 – reject broadcast packets
MP_DIS
PE0,RW Multicast packet filter
0 – accept multicast packets
1 – reject multicast packets
MP_STORM PE0,RW Broadcast Storm Control
0 – only broadcast packets storm are controlled
1 – Multicast packets also same as broadcast storm control.
6.11 Per Port Status Data Register (62H)
Bit
7:6
5
Name
RESERVED
LP_FCS
BIST
Default
P0,RO
P0,RO
P0,RO
Description
Reserved
Link Partner Flow Control Enable Status
BIST status
4
1: SRAM BIST fail
0: SRAM BIST pass
Reserved
3
2
RESERVED
SPEED2
0,RO
P0,RO
PHY Speed Status
0: 10Mbps, 1:100Mbps
PHY Duplex Status
0: half-duplex, 1:full-duplex
PHY Link Status
1
0
FDX2
LINK2
P0,RO
P0,RO
0: link fail, 1: link OK
18
Preliminary datasheet
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March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.12 Per Port Forward Control Register (65H)
Bit Name Default
LOOPBACK PH0,RW
Description
Loop-Back Mode
7
6
The transmitted packet will be forward to this port itself.
MONI_TX
MONI_RX
DIS_BMP
PH0,RW
PH0,RW
TX Packet Monitored
The transmitted packets are also forward to sniffer port.
RX Packet Monitored
5
4
The received packets are also forward to sniffer port.
PH0,RW Broad/Multicast Not Monitored
The received broadcast or multicast packets are not forward to sniffer
port.
3
2
Reserved
TX_DIS
PH0,RW
PH0,RW
Reserved
Packet Transmit Disabled
All packets can not be forward to this port.
Packet receive Disabled
All received packets are discarded.
1
0
RX_DIS
PH0,RW
PH0,RW
ADR_DIS
Address Learning Disabled
The Source Address (SA) field of packet is not learned to address table.
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
19
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.13 Per Port Ingress/Egress Control Register (66H)
Bit
Name
Default
Description
7:4
INGRESS
PE0,RW Ingress Rate Control
These bits define the bandwidth threshold that received packets over the threshold
are discarded.
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
3:0
EGRESS
PE0,RW Egress Rate Control
These bits define the bandwidth threshold that transmitted packets over the
threshold are discarded.
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
20
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.14 Bandwidth Control Setting Register (67H)
Bit
7:4
Name
BSTH
Default
Description
PE0,RW Broadcast Storm Threshold
These bits define the bandwidth threshold that received broadcast packets over
the threshold are discarded
0000: no broadcast storm control
0001: 8K packets/sec
0010: 16K packets/sec
0011: 64K packets/sec
0100: 5%
0101: 10%
0110: 20%
0111: 30%
1000: 40%
1001: 50%
1010: 60%
1011: 70%
1100: 80%
1101: 90%
111X: no broadcast storm control
3:0
BW CTRL
PE0,RW Received and Transmitted Bandwidth Control
These bits define the bandwidth threshold that transmitted or received packets
over the threshold are discarded
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
6.15 Per Port Block Unicast ports Control Register (68H)
Bit
7:4
3:0
Name
RESERVED
BLK_UP
Default
PH0,RW Reserved
PH0,RW Ports of Unicast Packet Be Blocked
Description
The received unicast packets are not forward to the assigned ports.
Note that the assigned port definition: bit 0 for port 0, bit 1 for port 1,
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
21
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.16 Per Port Block Multicast ports Control Register (69H)
Bit
7:4
3:0
Name
RESERVED
BLK_MP
Default
PH0,RW Reserved
PH0,RW Ports of Multicast Packet Be Blocked
Description
The received multicast packets are not forward to the assigned ports.
6.17 Per Port Block Broadcast ports Control Register (6AH)
Bit
7:4
3:0
Name
RESERVED
BLK_BP
Default
PH0,RW Reserved
PH0,RW Ports of Broadcast Packet Be Blocked
Description
The received broadcast packets are not forward to the assigned ports.
6.18 Per Port Block Unknown ports Control Register (6BH)
Bit
7:4
3:0
Name
RESERVED
BLK_UKP
Default
PH0,RW Reserved
PH0,RW Ports of Unknown Packet Be Blocked
The packets with DA field not found in address table are not forward to
the assigned ports.
Description
6.19 Per Port Priority Queue Control Register (6DH)
Bit
7
Name
TAG_OUT
Default
Description
PE0,RW Output Packet Tagging Enable
The transmitted packets are containing VLAN tagged field.
PE0,RW Priority Queue Disable
Only one transmit queue is supported in this port.
PE0,RW Weighted Fair Queuing
6
5
PRI_DIS
WFQUE
1: The priority weight for queue 3, 2, 1, and 0 is 8, 4, 2, and 1
respectively.
0: The queue 3 has the highest priority, and the next priorities are queue
2, 1, and 0 respectively.
4
TOS_PRI
PE0,RW Priority ToS over VLAN
If an IP packet with VLAN tag, the priority of this packet is decode from
ToS field.
3
2
TOS_OFF
PRI_OFF
P_PRI
PE0,RW ToS Priority Classification Disable
The priority information from ToS field of IP packet is ignored.
PE0,RW 802.1 p Priority Classification Disable
The priority information from VLAN tag field is ignored.
PE0,RW Port Base priority
1:0
The priority queue number in port base.
00= queue 0, 01=queue 1, 10=queue 2, 11=queue 3
6.20 Per Port VLAN Tag Low Byte Register (6EH)
Bit
7:0
Name
VID70
Default
PE01,RW VID[7:0]
Description
22
Preliminary datasheet
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March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.21 Per Port VLAN Tag High Byte Register (6FH)
Bit
7:5
4
Name
PRI
CFI
Default
Description
PE0,RW Tag [15:13]
PE0,RW Tag[12]
PE0,RW VID[11:8]
3:0
VID118
6.22 MIB counters Port Index Register (80H)
Bit
7
Name
READY
Default
P0,RO
Description
MIB counter data is ready
When this register is written with INDEX data, this bit is cleared and the MIB
counter reading is in progress. After end of read MIB counter, the MIB data is
loaded into register 81H~84H, and this bit is set to indicate that the MIB data is
ready.
6:5
4:0
reserved
INDEX
0,RO
Reserved
PHS0,RW MIB counter index 0~9, each counter is 32-bit in Register 81h~84h.
Write the MIB counter index to this register before read them.
6.23 MIB counter Data Register (81H~84H)
Bit
Name
Default
X,RO
X,RO
X,RO
X,RO
Description
81H
82H
83H
84H
Counter0
Counter1
Counter2
Counter3
Counter’s data bit 7~0
Counter’s data bit 15~8
Counter’s data bit 23~16
Counter’s data bit 31~24
MIB counter: RX Byte Counter Registers (INDEX 00H)
MIB counter: RX Uni-cast Packet Counter Registers (INDEX 01H)
MIB counter: RX Multi-cast Packet Counter Registers (INDEX 02H)
MIB counter: RX Discard Packet Counter Registers (INDEX 03H)
MIB counter: RX Error Packet Counter Registers (INDEX 04H)
MIB counter: TX Byte Counter Registers (INDEX 05H)
MIB counter: TX Uni-cast Packet Counter Registers (INDEX 06H)
MIB counter: TX Multi-cast Packet Counter Registers (INDEX 07H)
MIB counter: TX Discard Packet Counter Registers (INDEX 08H)
MIB counter: TX Error Packet Counter Registers (INDEX 09H)
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
23
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.24 VLAN grouping table Registers (B0H~BFH)
Define the port member in VLAN group
There are 16 VLAN group that defined in Reg. B0H~BFH.
Group 0 defined in Reg. B0H, and group 1 defined in Reg. B1H … and so on.
Bit
7:4
2
1
0
Name
Default
PE0,RO
PE1,RW Mapping to port 2
PE1,RW Mapping to port 1
PE1,RW Mapping to port 0
Description
RESERVED
PORT_P2
PORT_P1
PORT_P0
Reserved
6.25 TOS Priority Map Registers (C0H~CFH)
Define the 6-bit or 3-bit of ToS field mapping to 2-bit priority queue number.
In 6-bit type, the Reg. 53H bit 7 is “1”, Reg. C0H bit [1:0] define the mapping for ToS value 0, Reg. 60H bit [3:2] define the
mapping for ToS value 1, … and so on, till Reg. CFH bit [7:6] define ToS value 63.
In 3-bit type, Reg. C0H bit [1:0] defines the mapping for ToS value 0, Reg. 60H bit [3:2] defines the mapping for ToS value 1 …
and so on, and till Reg. C1H bit [7:6] define ToS value 7.
C0H:
Bit
7:6
5:4
3:2
1:0
Name
TOS3
TOS2
TOS1
TOS0
Default
Description
PE0/1,RW If bit 53H.7 =1 :TOS[7:2]=03H, otherwise TOS]7:5]=03H
PE0,/1RW If bit 53H.7 =1 :TOS[7:2]=02H, otherwise TOS]7:5]=02H
PE0,RW If bit 53H.7 =1 :TOS[7:2]=01H, otherwise TOS]7:5]=01H
PE0,RW If bit 53H.7 =1 :TOS[7:2]=00H, otherwise TOS]7:5]=00H
C1H:
Bit
7:6
5:4
3:2
1:0
Name
TOS7
TOS6
TOS5
TOS4
Default
Description
PE0/3,RW If bit 53H.7 =1 :TOS[7:2]=07H, otherwise TOS]7:5]=07H
PE0/3,RW If bit 53H.7 =1 :TOS[7:2]=06H, otherwise TOS]7:5]=06H
PE0/2,RW If bit 53H.7 =1 :TOS[7:2]=05H, otherwise TOS]7:5]=05H
PE0/2,RW If bit 53H.7 =1 :TOS[7:2]=04H, otherwise TOS]7:5]=04H
C2H:
Bit
7:6
5:4
3:2
1:0
Name
TOSB
TOSA
TOS9
TOS8
Default
Description
PE0,RW If bit 53H.7 =1 :TOS[7:2]=0BH
PE0,RW If bit 53H.7 =1 :TOS[7:2]=0AH
PE0,RW If bit 53H.7 =1 :TOS[7:2]=09H
PE0,RW If bit 53H.7 =1 :TOS[7:2]=08H
C3H:
Bit
7:6
5:4
3:2
1:0
Name
TOSF
TOSE
TOSD
TOSC
Default
Description
PE0,RW If bit 53H.7 =1 :TOS[7:2]=0FH
PE0,RW If bit 53H.7 =1 :TOS[7:2]=0EH
PE0,RW If bit 53H.7 =1 :TOS[7:2]=0DH
PE0,RW If bit 53H.7 =1 :TOS[7:2]=0CH
24
Preliminary datasheet
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March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
C4H:
Bit
7:6
5:4
3:2
1:0
Name
TOS13
TOS12
TOS11
TOS10
Default
Description
PE1,RW If bit 53H.7 =1 :TOS[7:2]=13H
PE1,RW If bit 53H.7 =1 :TOS[7:2]=12H
PE1,RW If bit 53H.7 =1 :TOS[7:2]=11H
PE1,RW If bit 53H.7 =1 :TOS[7:2]=10H
C5H:
Bit
7:6
5:4
3:2
1:0
Name
TOS17
TOS16
TOS15
TOS14
Default
Description
Description
Description
Description
Description
PE1,RW If bit 53H.7 =1 :TOS[7:2]=17H
PE1,RW If bit 53H.7 =1 :TOS[7:2]=16H
PE1,RW If bit 53H.7 =1 :TOS[7:2]=15H
PE1,RW If bit 53H.7 =1 :TOS[7:2]=14H
C6H:
Bit
7:6
5:4
3:2
1:0
Name
TOS1B
TOS1A
TOS19
TOS18
Default
PE1,RW If bit 53H.7 =1 :TOS[7:2]=1BH
PE1,RW If bit 53H.7 =1 :TOS[7:2]=1AH
PE1,RW If bit 53H.7 =1 :TOS[7:2]=19H
PE1,RW If bit 53H.7 =1 :TOS[7:2]=18H
C7H:
Bit
7:6
5:4
3:2
1:0
Name
TOS1F
TOS1E
TOS1D
TOS1C
Default
PE1,RW If bit 53H.7 =1 :TOS[7:2]=1FH
PE1,RW If bit 53H.7 =1 :TOS[7:2]=1EH
PE1,RW If bit 53H.7 =1 :TOS[7:2]=1DH
PE1,RW If bit 53H.7 =1 :TOS[7:2]=1CH
C8H:
Bit
7:6
5:4
3:2
1:0
Name
TOS23
TOS22
TOS21
TOS20
Default
PE2,RW If bit 53H.7 =1 :TOS[7:2]=23H
PE2,RW If bit 53H.7 =1 :TOS[7:2]=22H
PE2,RW If bit 53H.7 =1 :TOS[7:2]=21H
PE2,RW If bit 53H.7 =1 :TOS[7:2]=20H
C9H:
Bit
7:6
5:4
3:2
1:0
Name
TOS27
TOS26
TOS25
TOS24
Default
PE2,RW If bit 53H.7 =1 :TOS[7:2]=27H
PE2,RW If bit 53H.7 =1 :TOS[7:2]=26H
PE2,RW If bit 53H.7 =1 :TOS[7:2]=25H
PE2,RW If bit 53H.7 =1 :TOS[7:2]=24H
Preliminarydatasheet
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March 5, 2012
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DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
CAH:
Bit
7:6
5:4
3:2
1:0
Name
TOS2B
TOS2A
TOS29
TOS28
Default
Description
PE2,RW If bit 53H.7 =1 :TOS[7:2]=2BH
PE2,RW If bit 53H.7 =1 :TOS[7:2]=2AH
PE2,RW If bit 53H.7 =1 :TOS[7:2]=29H
PE2,RW If bit 53H.7 =1 :TOS[7:2]=28H
CBH:
Bit
7:6
5:4
3:2
1:0
Name
TOS2F
TOS2E
TOS2D
TOS2C
Default
Description
Description
Description
Description
Description
PE2,RW If bit 53H.7 =1 :TOS[7:2]=2FH
PE2,RW If bit 53H.7 =1 :TOS[7:2]=2EH
PE2,RW If bit 53H.7 =1 :TOS[7:2]=2DH
PE2,RW
If bit 53H.7 =1 :TOS[7:2]=2CH
CCH:
Bit
7:6
5:4
3:2
1:0
Name
TOS33
TOS32
TOS31
TOS30
Default
PE3,RW If bit 53H.7 =1 :TOS[7:2]=33H
PE3,RW If bit 53H.7 =1 :TOS[7:2]=32H
PE3,RW If bit 53H.7 =1 :TOS[7:2]=31H
PE3,RW If bit 53H.7 =1 :TOS[7:2]=30H
CDH:
Bit
7:6
5:4
3:2
1:0
Name
TOS37
TOS36
TOS35
TOS34
Default
PE3,RW If bit 53H.7 =1 :TOS[7:2]=37H
PE3,RW If bit 53H.7 =1 :TOS[7:2]=36H
PE3,RW If bit 53H.7 =1 :TOS[7:2]=35H
PE3,RW If bit 53H.7 =1 :TOS[7:2]=34H
CEH:
Bit
7:6
5:4
3:2
1:0
Name
TOS3B
TOS3A
TOS39
TOS38
Default
PE3,RW If bit 53H.7 =1 :TOS[7:2]=3BH
PE3,RW If bit 53H.7 =1 :TOS[7:2]=3AH
PE3,RW If bit 53H.7 =1 :TOS[7:2]=39H
PE3,RW If bit 53H.7 =1 :TOS[7:2]=38H
CFH:
Bit
7:6
5:4
3:2
1:0
Name
TOS3F
TOS3E
TOS3D
TOS3C
Default
PE3,RW If bit 53H.7 =1 :TOS[7:2]=3FH
PE3,RW If bit 53H.7 =1 :TOS[7:2]=3EH
PE3,RW If bit 53H.7 =1 :TOS[7:2]=3DH
PE3,RW If bit 53H.7 =1 :TOS[7:2]=3CH
26
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
6.26 VLAN Priority Map Registers (D0H~D1H)
Define the 3-bit of priority field VALN mapping to 2-bit priority queue number.
D0H:
Bit
7:6
5:4
3:2
1:0
Name
TAG3
TAG2
TAG1
TAG0
Default
Description
Description
PE1,RW VLAN priority tag value = 03H
PE1,RW VLAN priority tag value = 02H
PE0,RW VLAN priority tag value = 01H
PE0,RW VLAN priority tag value = 00H
D1H:
Bit
7:6
5:4
3:2
1:0
Name
TAG7
TAG6
TAG5
TAG4
Default
PE3,RW VLAN priority tag value = 07H
PE3,RW VLAN priority tag value = 06H
PE2,RW VLAN priority tag value = 05H
PE2,RW VLAN priority tag value = 04H
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
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DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
7. EEPROM Format
name
Word
0~2
3
Description
Reserved
[1:0] Auto Load Control
RESERVED
Auto Load Control
Vendor ID
4
Vendor ID
RESERVED
PHY Control
RESERVED
Control
6
7
8~15
16
Reserved
PHY Control
Reserved
Bit 1:0=01: Accept setting of WORD 17,18
Bit 3:2=01: Accept setting of WORD 19~26
Bit 5:4=01: Accept setting of WORD 27~30
Bit 7:6=01: Accept setting of WORD 31
Bit 9:8=01: Accept setting of WORD 32~39
Bit 11:10=01: Accept setting of WORD 40~47
Bit 15:12 =01: Reserved
Switch Control 1
Switch Control 2
Port 0 Control 1
Port 0 Control 2
Port 1 Control 1
Port 1 Control 2
Port 2 Control 1
Port 2 Control 2
17
18
19
20
21
22
23
24
When word 16 bit 1:0 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. 52H bit 7~0
This word bit 15~8 will be loaded to Reg. 53H bit 7~0
When word 16 bit 1:0 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. 58H bit 7~0
This word bit 15~8 will be loaded to Reg. 59H bit 7~0
When word 16 bit 3:2 is “01”, after power on reset:
This word bit 7~0 will be loaded to port 0 Reg. 61H bit 7~0
This word bit 15~8 will be loaded to port 0 Reg. 66H bit 7~0
When word 16 bit 3:2 is “01”, after power on reset:
This word bit 7~0 will be loaded to port 0 Reg. 67H bit 7~0
This word bit 15~8 will be loaded to port 0 Reg. 6DH bit 7~0
When word 16 bit 3:2 is “01”, after power on reset:
This word bit 7~0 will be loaded to port 1 Reg. 61H bit 7~0
This word bit 15~8 will be loaded to port 1 Reg. 66H bit 7~0
When word 16 bit 3:2 is “01”, after power on reset:
This word bit 7~0 will be loaded to port 1 Reg. 67H bit 7~0
This word bit 15~8 will be loaded to port 1 Reg. 6DH bit 7~0
When word 16 bit 3:2 is “01”, after power on reset:
This word bit 7~0 will be loaded to port 2 Reg. 61H bit 7~0
This word bit 15~8 will be loaded to port 2 Reg. 66H bit 7~0
When word 16 bit 3:2 is “01”, after power on reset:
This word bit 7~0 will be loaded to port 2 Reg. 67H bit 7~0
This word bit 15~8 will be loaded to port 2 Reg. 6DH bit 7~0
Reserved
RESERVED
Port 0 VLAN Tag
25-26
27
When word 16 bit 5:4 is “01”, after power on reset:
This word bit 7~0 will be loaded to port 0 Reg. 6EH bit 7~0
This word bit 15~8 will be loaded to port 0 Reg. 6FH bit 7~0
When word 16 bit 5:4 is “01”, after power on reset:
This word bit 7~0 will be loaded to port 1 Reg. 6EH bit 7~0
This word bit 15~8 will be loaded to port 1 Reg. 6FH bit 7~0
When word 16 bit 5:4 is “01”, after power on reset:
This word bit 7~0 will be loaded to port 2 Reg. 6EH bit 7~0
Port 1 VLAN Tag
28
29
Port 2 VLAN Tag
28
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
This word bit 15~8 will be loaded to port 2 Reg. 6FH bit 7~0
Reserved
RESERVED
VLAN Priority Map
30
31
When word 16 bit 7:6 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. D0H bit 7~0
This word bit 15~8 will be loaded to Reg. D1H bit 7~0
When word 16 bit 9:8 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. B0H bit 7~0
This word bit 15~8 will be loaded to Reg. B1H bit 7~0
When word 16 bit 9:8 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. B2H bit 7~0
This word bit 15~8 will be loaded to Reg. B3H bit 7~0
When word 16 bit 9:8 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. B4H bit 7~0
This word bit 15~8 will be loaded to Reg. B5H bit 7~0
When word 16 bit 9:8 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. B6H bit 7~0
This word bit 15~8 will be loaded to Reg. B7H bit 7~0
When word 16 bit 9:8 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. B8H bit 7~0
This word bit 15~8 will be loaded to Reg. B9H bit 7~0
When word 16 bit 9:8 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. BAH bit 7~0
This word bit 15~8 will be loaded to Reg. BBH bit 7~0
When word 16 bit 9:8 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. BCH bit 7~0
This word bit 15~8 will be loaded to Reg. BDH bit 7~0
When word 16 bit 9:8 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. BEH bit 7~0
This word bit 15~8 will be loaded to Reg. BFH bit 7~0
When word 16 bit 11:10 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. C0H bit 7~0
This word bit 15~8 will be loaded to Reg. C1H bit 7~0
When word 16 bit 11:10 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. C2H bit 7~0
This word bit 15~8 will be loaded to Reg. C3H bit 7~0
When word 16 bit 11:10 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. C4H bit 7~0
This word bit 15~8 will be loaded to Reg. C5H bit 7~0
When word 16 bit 11:10 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. C6H bit 7~0
This word bit 15~8 will be loaded to Reg. C7H bit 7~0
When word 16 bit 11:10 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. C8H bit 7~0
This word bit 15~8 will be loaded to Reg. C9H bit 7~0
When word 16 bit 11:10 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. CAH bit 7~0
This word bit 15~8 will be loaded to Reg. CBH bit 7~0
When word 16 bit 11:10 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. CCH bit 7~0
Port VLAN Group
0,1
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Port VLAN Group
2,3
Port VLAN Group
4,5
Port VLAN Group
6,7
Port VLAN Group
8,9
Port VLAN Group
10,11
Port VLAN Group
12,13
Port VLAN Group
14,15
ToS Priority Map 0
ToS Priority Map 1
ToS Priority Map 2
ToS Priority Map 3
ToS Priority Map 4
ToS Priority Map 5
ToS Priority Map 6
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
29
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
This word bit 15~8 will be loaded to Reg. CDH bit 7~0
When word 16 bit 11:10 is “01”, after power on reset:
This word bit 7~0 will be loaded to Reg. CEH bit 7~0
This word bit 15~8 will be loaded to Reg. CFH bit 7~0
ToS Priority Map 7
47
30
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8. PHY Registers
MII Register Description
ADD Name
00H CONTR Reset
15
14
Loop
back
0
13
12
11
10
9
8
Full
7
6
5
4
3
2
1
0
Speed Auto-N Power Isolate Restart
select
1
Coll.
Test
0
Reserved
OL
Enable Down
1
Auto-N Duplex
0
0
0
0
1
000_0000
01H STATUS T4
TX FDX TX HDX 10 FDX 10 HDX
Reserved
Pream. Auto-N Remote Auto-N
Link
Status
0
Jabber
Detect
0
Extd
Cap.
1
Cap.
0
Cap.
Cap.
Cap.
Cap.
Supr.
Compl.
Fault
Cap.
1
0
0
1
0
1
1
0
1
1
0
1
0000
1
0
0
0
0
0
1
0
02H PHYID1
03H PHYID2
0
1
0
0
0
1
1
0
0
1
Model No.
01011
TX FDX TX HDX 10 FDX 10 HDX
Adv
LP
Version No.
0000
04H Auto-Neg. Next FLP Rcv Remote
Advertise Page
05H Link Part. LP
Reserved
FC
Adv
LP
T4
Adv
LP
Advertised Protocol Selector Field
Ack
Fault
Adv
LP
Adv
Adv
LP
LP
Reserved
LP
LP
Link Partner Protocol Selector Field
Ability
Next
Ack
RF
FC
T4
TX FDX TX HDX 10 FDX 10 HDX
Page
06H Auto-Neg.
Reserved
TX
Pardet LP Next Next Pg New Pg LP AutoN
Expansio
n
10H Specifie BP
Fault
Pg Able
Able
Rcv
Cap.
BP
SCR
BP
ALIGN
BP_ADP Reserve
Reserve Reserve Force Reserve Reserve RPDCTR Reset
100LNK -EN St. Mch
Pream.
Supr.
Sleep Reserved
mode
d
4B5B
OK
dr
d
d
d
d
Config.
11H Specifie 100
100
10
10 HDX Reserve Reverse Reverse
PHY ADDR [4:0]
Auto-N. Monitor Bit [3:0]
d
FDX
HDX
FDX
d
d
d
Conf/Stat
12H
10T
Conf/Stat
Rsvd
LP
Enable
HBE
SQUE
JAB
Reserve
d
Reserved
Polarity
Reverse
Enable Enable Enable
13H PWDOR
Reserved
PD10DR PD100l PDchip PDcrm PDaeq PDdrv
V
PDecli PDeclo PD10
14H Specified TSTSE1 TSTSE FORCE_ FORCE_
Reserved MDIX_C AutoNeg Mdix_fix Mdix_do MonSel1 MonSel0 Reserve PD_valu
PREA TX10M NWAY_
MBLE _PWR PWR
X
config
2
TXSD
FEF
NTL
_dlpbk
Value
wn
d
e
16H RCVER
Receiver Error Counter
17H DIS_conn
ect
Reversed
Disconnect_counter
Reversed
1DH PSCR
Reversed
PREA AMPLIT TX_PW
MBLEX UDE
R
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where:
<Reset Value>:
1
0
X
Bit set to logic one
Bit set to logic zero
No default value
<Access Type>:
RO = Read only,
<Attribute (s)>:
RW = Read/Write
SC = Self clearing, P = Value permanently set
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
31
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8.1 Basic Mode Control Register (BMCR) – 00H
Bit
Bit Name
Default
Description
15
Reset
0, RW/SC Reset
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their
default states. This bit, which is self-clearing, will keep returning a
value of one until the reset process is completed
Loopback
Loop-back control register
1 = Loop-back enabled
14
13
Loopback
0, RW
1, RW
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appears at the MII receive outputs
Speed Select
Speed selection
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will return
auto-negotiation selected medium type
Auto-negotiation Enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
auto-negotiation status
12
11
Auto-negotiation
enable
1, RW
0, RW
Power down
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down
state and while in the power-down state, the PHY should not
generate spurious signals on the MII
1=Power down
0=Normal operation
10
9
Isolate
0,RW
Isolate
Force to 0 in application.
Restart
Auto-negotiation
0,RW/SC Restart Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning to a value of 1 until
auto-negotiation is initiated by the DM9332. The operation of the
auto-negotiation process will not be affected by the management
entity that clears this bit
0 = Normal operation
8
Duplex mode
1,RW
Duplex Mode
1 = Full duplex operation. Duplex selection is allowed when
Auto-negotiation is disabled (bit 12 of this register is cleared). With
auto-negotiation enabled, this bit reflects the duplex capability
selected by auto-negotiation
0 = Normal operation
32
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
7
Collision test
Reserved
0,RW
Collision Test
1 = Collision test enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TX_EN in
internal MII interface.
0 = Normal operation
Reserved
6-0
0,RO
Read as 0, ignore on write
8.2 Basic Mode Status Register (BMSR) – 01H
Bit
Bit Name
Default
Description
15
100BASE-T4
0,RO/P 100BASE-T4 Capable
1 = DM9332 is able to perform in 100BASE-T4 mode
0 = DM9332 is not able to perform in 100BASE-T4 mode
1,RO/P 100BASE-TX Full Duplex Capable
1 = DM9332 is able to perform 100BASE-TX in full duplex mode
0 = DM9332 is not able to perform 100BASE-TX in full duplex mode
1,RO/P 100BASE-TX Half Duplex Capable
14
13
100BASE-TX
full-duplex
100BASE-TX
half-duplex
1 = DM9332 is able to perform 100BASE-TX in half duplex mode
0 = DM9332 is not able to perform 100BASE-TX in half duplex
mode
12
11
10BASE-T
full-duplex
1,RO/P 10BASE-T Full Duplex Capable
1 = DM9332 is able to perform 10BASE-T in full duplex mode
0 = DM9332 is not able to perform 10BASE-TX in full duplex mode
1,RO/P 10BASE-T Half Duplex Capable
10BASE-T
half-duplex
1 = DM9332 is able to perform 10BASE-T in half duplex mode
0 = DM9332 is not able to perform 10BASE-T in half duplex mode
10-7
6
Reserved
0,RO
1,RO
Reserved
Read as 0, ignore on write
MII Frame Preamble Suppression
1 = PHY will accept management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed
MF preamble
suppression
5
4
Auto-negotiation
Complete
0,RO
Auto-negotiation Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
Remote Fault
Remote fault
0, RO
1 = Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is DM9332
implementation specific. This bit will set after the RF bit in the
ANLPAR (bit 13, register address 05) is set
0 = No remote fault condition detected
3
2
Auto-negotiation
ability
1,RO/P Auto Configuration Ability
1 = DM9332 is able to perform auto-negotiation
0 = DM9332 is not able to perform auto-negotiation
Link status
0,RO
Link Status
1 = Valid link is established (for either 10Mbps or 100Mbps
operation)
0 = Link is not established
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
33
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
The link status bit is implemented with a latching function, so that
the occurrence of a link failure condition causes the link status bit to
be cleared and remain cleared until it is read via the management
interface
1
0
Jabber detect
0, RO
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a DM9332 reset. This bit works only in
10Mbps mode
Extended
capability
1,RO/P Extended Capability
1 = Extended register capable
0 = Basic register capable only
8.3 PHY ID Identifier Register #1 (PHYID1) – 02H
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9332. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default
Description
15-0
OUI_MSB
<0181h>
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) – 03H
Bit
Bit Name
Default
Description
15-10
OUI_LSB
<101110>, OUI Least Significant Bits
RO/P
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
9-4
3-0
VNDR_MDL
MDL_REV
<001011>, Vendor Model Number
RO/P
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
<0000>,
RO/P
Model Revision Number
Five bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 4)
34
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8.5 Auto-negotiation Advertisement Register (ANAR) – 04H
This register contains the advertised abilities of this DM9332 device as they will be transmitted to its link partner
during Auto-negotiation.
Bit
Bit Name
Default
Description
15
NP
0,RO/P
Next page Indication
0 = No next page available
1 = Next page available
The DM9332 has no next page, so this bit is permanently set to 0
Acknowledge
14
ACK
0,RO
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9332's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software
should not attempt to write to this bit.
Remote Fault
13
RF
0, RW
1 = Local device senses a fault condition
0 = No fault detected
12-11
10
Reserved
FCS
X, RW
0, RW
Reserved
Write as 0, ignore on read
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
100BASE-T4 Support
9
T4
0, RO/P
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The DM9332 does not support 100BASE-T4 so this bit is
permanently set to 0
8
7
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
1, RW
1, RW
1, RW
1, RW
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the local device
0 = 100BASE-TX full duplex is not supported
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the local device
0 = 100BASE-TX half duplex is not supported
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the local device
0 = 10BASE-T full duplex is not supported
10BASE-T Support
1 = 10BASE-T half duplex is supported by the local device
0 = 10BASE-T half duplex is not supported
6
5
4-0
<00001>, RW Protocol Selection Bits
These bits contain the binary encoded protocol selector supported
by this node
<00001> indicates that this device supports IEEE 802.3 CSMA/CD
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
35
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05H
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Bit
Bit Name
Default
Description
15
NP
0, RO
Next Page Indication
0 = Link partner, no next page available
1 = Link partner, next page available
14
ACK
0, RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9332's auto-negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not
attempt to write to this bit
13
RF
0, RO
Remote Fault
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
Reserved
Read as 0, ignore on write
Flow Control Support
12-11
10
Reserved
FCS
0, RO
0, RO
1 = Controller chip supports flow control ability by link partner
0 = Controller chip doesn’t support flow control ability by link
partner
9
8
T4
0, RO
0, RO
0, RO
0, RO
0, RO
100BASE-T4 Support
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the link partner
0 = 100BASE-TX full duplex is not supported by the link partner
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the link partner
0 = 100BASE-TX half duplex is not supported by the link partner
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link partner
10BASE-T Support
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
7
6
5
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link partner
4-0
<00000>, RO Protocol Selection Bits
Link partner’s binary encoded protocol selector
36
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8.7 Auto-negotiation Expansion Register (ANER) - 06H
Bit
Bit Name
Default
Description
15-5
Reserved
0, RO
Reserved
Read as 0, ignore on write
4
3
2
PDF
0, RO/LH
0, RO
Local Device Parallel Detection Fault
PDF = 1: A fault detected via parallel detection function.
PDF = 0: No fault detected via parallel detection function
Link Partner Next Page Able
LP_NP_ABLE = 1: Link partner, next page available
LP_NP_ABLE = 0: Link partner, no next page
Local Device Next Page Able
LP_NP_ABLE
NP_ABLE
0,RO/P
NP_ABLE = 1: DM9332, next page available
NP_ABLE = 0: DM9332, no next page
DM9332 does not support this function, so this bit is always 0
1
0
PAGE_RX
0, RO
0, RO
New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management
Link Partner Auto-negotiation Able
LP_AN_ABLE
A “1” in this bit indicates that the link partner supports
Auto-negotiation
8.8 DAVICOM Specified Configuration Register (DSCR) – 10H
Bit
15
Bit Name
BP_4B5B
Default
0,RW
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions (symbol
encoder and scrambler) bypassed
0 = Normal operation
14
13
BP_SCR
0, RW
0, RW
BP_ALIGN
12
BP_ADPOK
0, RW
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug only,
not release to customer
1=Forced SD is OK,
0=Normal operation
11
10
Reserved
TX
RW
Reserved
Force to 0 in application
100BASE-TX Mode Control
1, RW
1 = 100BASE-TX operation
0 = 100BASE-FX operation
9
Reserved
0, RO
Reserved
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
37
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8
7
Reserved
0, RW
Reserved
Force to 0 in application.
Force Good Link in 100Mbps
F_LINK_100
0, RW
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Force to 0 in application.
Reserved
6
5
4
Reserved
Reserved
0, RW
0, RW
1, RW
Force to 0 in application.
RPDCTR-EN
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
1 = Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
3
2
SMRST
MFPSC
0, RW
1, RW
1
0
SLEEP
0, RW
0, RW
Reserved
Reserved
Force to 0 in application.
38
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H
Bit
15
Bit Name
100FDX
Default
1, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M full duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
14
13
12
11
100HDX
10FDX
1, RO
1, RO
1, RO
0, RO
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10HDX
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
Reserved
Reserved
Read as 0, ignore on write
10
9
Reserved
Reserved
0,RW
0,RW
Reserved
Reserved
8-4
PHYADR[4: 0 or 1, RW PHY Address Bit 4:0
0]
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple PHY
entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
3-0
ANMB[3:0]
0, RO
These bits are for debug only. The auto-negotiation status will be written
to these bits.
B3 B2 B1 B0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal link ready
Parallel detects signal link ready fail
Auto-negotiation completed successfully
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
39
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8.10 10BASE-T Configuration/Status (10BTCSR) – 12H
Bit
Bit Name
Default
Description
15
Reserved
0, RO
Reserved
Read as 0, ignore on write
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation
Heartbeat Enable
14
13
LP_EN
HBE
1, RW
1,RW
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the DM9332 is configured for full duplex operation, this bit will
be ignored (the collision/heartbeat function is invalid in full duplex
mode)
12
11
SQUELCH
JABEN
1, RW
1, RW
Squelch Enable
1 = Normal squelch
0 = Low squelch
Jabber Enable
Enables or disables the Jabber function when the DM9332 is in
10BASE-T full duplex or 10BASE-T transceiver Loopback mode
1 = Jabber function enabled
0 = Jabber function disabled
10
9-1
0
SERIAL
Reserved
POLR
0, RW
0, RO
0, RO
10Mbps Serial Mode (only valid in PHY test mode)
Force to 0, in application.
Reserved
Read as 0, ignore on write
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity is
reversed. This bit is automatically set and cleared by 10BASE-T
module
8.11 Power down Control Register (PWDOR) – 13H
Bit
Bit Name
Default
Description
15-9
Reserved
0, RO
Reserved
Read as 0, ignore on write
8
7
6
5
4
3
2
1
0
PD10DRV
PD100DL
PDchip
PDcrm
PDaeq
PDdrv
PDedi
PDedo
PD10
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
Vendor power down control test
Vendor power down control test
Vendor power down control test
Vendor power down control test
Vendor power down control test
Vendor power down control test
Vendor power down control test
Vendor power down control test
Vendor power down control test
* When selected, the power down value is control by Register 14H
40
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8.12 (Specified config) Register – 14H
Bit
15
14
13
Bit Name
TSTSE1
TSTSE2
Default
0,RW
0,RW
0,RW
Description
Vendor test select 1 control
Vendor test select 2 control
Force Signal Detect
FORCE_TXSD
1: force SD signal OK in 100BASE-TX mode
0: normal SD signal.
12
11
FORCE_FEF
PREAMBLEX
0,RW
0,RW
Vendor test select control
Preamble Saving Control
0: when bit 10 is set, the 10BASE-T transmit preamble count is
reduced. When bit 11 of register 1DH is set, 12-bit preamble is
reduced; otherwise 22-bit preamble is reduced.
1: transmit preamble bit count is normal in 10BASE-T mode
10BASE-T mode Transmit Power Saving Control
1: enable transmit power saving in 10BASE-T mode
0: disable transmit power saving in 10BASE-T mode
Auto-negotiation Power Saving Control
10
9
TX10M_PWR
NWAY_PWR
1,RW
0,RW
0, RO
1: disable power saving during auto-negotiation period
0: enable power saving during auto-negotiation period
8
7
Reserved
Reserved
Read as 0, ignore on write
MDIX_CNTL
MDI/MDIX,RO The polarity of MDI/MDIX value
1: MDIX mode
0: MDI mode
6
5
4
AutoNeg_dpbk
Mdix_fix Value
Mdix_down
0,RW
0, RW
0,RW
Auto-negotiation Loopback
1: test internal digital auto-negotiation Loopback
0: normal.
MDIX_CNTL force value:
When Mdix_down = 1, MDIX_CNTL value depend on the register
value.
MDIX Down
Manual force MDI/MDIX.
0: Enable HP Auto-MDIX
1: Disable HP Auto-MDIX ,
MDIX_CNTL value depend on Reg.14H.bit5
Vendor monitor select 1
Vendor monitor select 0
Reserved
3
2
1
MonSel1
MonSel0
Reserved
0,RW
0,RW
0,RW
Force to 0, in application.
Power down control value
Decision the value of each field Reg.13H.
1: power down
0
PD_value
0,RW
0: normal
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
41
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8.13 DAVICOM Specified Receive Error Counter Register (RECR) – 16H
Bit
Bit Name
Default
Description
15-0
Rcv_ Err_ Cnt
0, RO
Receive Error Counter
Receive error counter that increments upon detection of RXER.
Clean by read this register.
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) – 17H
Bit
Bit Name
Default
Description
15-8
Reserved
0, RO
Reserved
7-0
Disconnect
Counter
0, RO
Disconnect Counter that increment upon detection of
disconnection. Clean by read this register.
8.15 Power Saving Control Register (PSCR) – 1DH
Bit
15-12
11
Bit Name
RESERVED
PREAMBLEX
Default
0,RO
0,RW
Description
RESERVED
Preamble Saving Control
when both bit 10and 11 of register 14H are set, the 10BASE-T
transmit preamble count is reduced.
1: 12-bit preamble is reduced.
0: 22-bit preamble is reduced.
10
9
AMPLITUDE
TX_PWR
0,RW
0.RW
0,RO
Transmit Amplitude Control Disabled
1: when cable is unconnected with link partner, the TX amplitude is
reduced for power saving.
0: disable Transmit amplitude reduce function
Transmit Power Saving Control Disabled
1: when cable is unconnected with link partner, the driving current
of transmit is reduced for power saving.
0: disable transmit driving power saving function
RESERVED
8-0
RESERVED
42
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
9. Functional Description
9.1 Serial Management Interface
Host SMI
SMI_CK
SMI_DIO
(SMI device address = 0~3)
MDC
Host / MAC
MDIO
Only one host is allowed to acccess the SMI_CK, SMI_DIO
DM9332
MII SMI
MDC
MDIO
MDC
MDIO
Port2 PHY
(PHY Address =
2)
External PHY can be accessed via the MDC, MDIO
Host SMI - Read Frame Structure
SMI_CK
SMI_DIO Read
//
//
A1
R0
0
1
1
0
A0
R7
R6
R5
32 "1"s
0
D15
D14
D1
D0
Z
Device Address
Write
Idle
Idle Preamble
SFD
Op Code
Register Address
Turn Around
Data
Read
Host SMI - Write Frame Structure
SMI_CK
SMI_DIO Write
32 "1"s
0
1
0
1
A1
A0
R7
R6
R5
R0
1
0
D15
D14
Data
D1
D0
Idle Preamble
SFD
Op Code
Device Address
Register Address
Write
Turn Around
Idle
DM9332 supports two type of serial management
interface (SMI), Host SMI and MII SMI. The
application of SMI illustrated as below.
pin (TXD2_0 & TXD2_1). The <Register Address>
field of the frame is mapped to address of control and
status register set of DM9332. The read/writ data is
valid on low byte (D7~D0) of <Data> field, the high
byte (D15~D8) of data is reserved.
1. The Host SMI consists of two pins, one is SMI_CK
and another is SMI_DIO. User can access DM9332’s
EEPROM, PHY registers, MIB counters and
2. DM9332 supports MII SMI auto-polling for
configuring speed, duplex mode, and 802.3x flow
control capability of the external PHY (Port2) via the
MDC, MDIO. More detail description and frame
format can refer to section 9.3.2.
Configuration registers through Host SMI. The format
is following. The <Device Address> field of the frame
means SMI device address that is configured by strap
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
43
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
9.2 Switch function:
9.2.1 Address Learning
(3). If incoming packet is UNICAST and its
destination port number is equal to source port
The DM9332 has a self-learning mechanism for
learning the MAC addresses of incoming packets in
real time. DM9332 stores MAC addresses, port
number and time stamp information in the
Hash-based Address Table. It can learn up to 1K
unicast address entry.
The switch engine updates address table with
new entry if incoming packet’s Source Address (SA)
does not exist and incoming packet is valid (non-error
and legal length).
number.
9.2.4 Inter-Packet Gap (IPG)
IPG is the idle time between any two valid packets
at the same port. The typical number is 96 bits time.
In other word, the value is 9.6u sec for 10Mbps and
960n sec for 100Mbps.
9.2.5 Back-off Algorithm
Besides, DM9332 has an option to disable
address learning for individual port. This feature can
be set by bit 0 of register 65h
The DM9332 implements the binary exponential
back-off algorithm in half-duplex mode compliant to
IEEE standard 802.3.
9.2.2 Address Aging
9.2.6 Late Collision
The time stamp information of address table is
used in the aging process. The switch engine
updates time stamp whenever the corresponding SA
receives. The switch engine would delete the entry if
its time stamp is not updated for a period of time.
The period can be programmed or disabled through
bit 0 & 1 of register 52h.
Late Collision is a type of collision. If a collision
error occurs after the first 512 bit times of data are
transmitted, the packet is dropped.
9.2.7 Full Duplex Flow Control
The DM9332 supports IEEE standard 802.3x flow
control frames on both transmit and receive sides.
On the receive side, The DM9332 will defer
transmitting next normal frames, if it receives a pause
frame from link partner.
On the transmit side, The DM9332 issues pause
frame with maximum pause time when internal
resources such as received buffers, transmit queue
and transmit descriptor ring are unavailable. Once
resources are available, The DM9332 sends out a
pause frame with zero pause time allows traffic to
resume immediately.
9.2.3 Packet Forwarding
The DM9332 forwards the incoming packet
according to following decision:
(1). If DA is Multicast/Broadcast, the packet is
forwarded to all ports, except to the port on which the
packet was received.
(2). Switch engine would look up address table
based on DA when incoming packets is UNICAST. If
the DA was not found in address table, the packet is
treated as a multicast packet and forward to other
ports. If the DA was found and its destination port
number is different to source port number, the packet
is forward to destination port.
9.2.8 Half Duplex Flow Control
The DM9332 supports half-duplex backpressure.
The inducement is the same as full duplex mode.
When flow control is required, the DM9332 sends jam
pattern and results in a collision.
(3). Switch engine also look up VLAN, Port
Monitor setting and other forwarding constraints for
the forwarding decision, more detail will discuss in
later sections.
The flow control ability can be set in bit 4 of
register 61h.
The DM9332 will filter incoming packets under
following conditions:
(1). Error packets, including CRC errors,
alignment errors, illegal size errors.
(2). PAUSE packets.
44
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
programmed by EEPROM or register 67h, the default
setting is no broadcast storm protecting.
9.2.9 Partition Mode
The DM9332 provides a partition mode for each
port, see bit 6 of register 61h. The port enters
partition mode when more than 64 consecutive
collisions are occurred. In partition mode the port
continuous to transmit but it will not receive. The port
returned to normal operation mode when a good
packet is seen on the wire. The detail description of
partition mode represent following:
9.2.11 Bandwidth Control
The DM9332 supports two types of bandwidth
control for each port. One is the ingress and egress
bandwidth rate can be controlled separately, the
other is combined together, this function can be set
through bit 3 of register 61h. The bandwidth control is
disabled by default.
(1). Entering Partition State
A port will enter the Partition State when either of
the following conditions occurs:
z The port detects a collision on every one of 64
consecutive re-transmit attempts to the same packet.
z The port detects a single collision which occurs
for more than 512 bit times.
To separate bandwidth control mode, the
threshold rate is defined in register 66h. For
combined mode, it is defined in register 67h.
The behavior of bandwidth control as below:
(1).For the ingress control, if flow control function
is enabled, Pause or Jam packet will be transmitted.
The ingress packets will be dropped if flow control is
disabled.
z Transmit defer timer time out, which indicates
the transmitting packet is deferred to long.
(2).For the egress control, the egress port will not
transmit any packets. On the other hand, the ingress
bandwidth of source port will be throttled that prevent
packets from forwarding.
(3).In combined mode, if the sum of ingress and
egress bandwidth over threshold, the bandwidth will
be throttled.
(2). While in Partition state:
The port will continue to transmit its pending
packet, regardless of the collision detection, and will
not allow the usual Back-off Algorithm. Additional
packets pending for transmission will be transmitted,
while ignoring the internal collision indication. This
frees up the ports transmit buffers which would
otherwise be filled up at the expense of other ports
buffers. The assumption is that the partition is
9.2.12 Port Monitoring Support
The DM9332 supports “Port Monitoring” function
on per port base, detail as below:
signifying
a
system failure situation (bad
connection/cable/station), thus dropping packets is a
small price to pay vs. the cost of halting the switch
due to a buffer full condition.
(1). Sniffer Port and Monitor Port
There is only one port can be selected as “sniffer
port” by register 52h, multiple ports can be set as
“receive monitor port” or “transmit monitor port” in
per-port register 65h.
(3). Exiting from Partition State
The Port exits from Partition State, following the
end of a successful packet transmission.
successful packet transmission is defined as no
collisions were detected on the first 512 bits of the
transmission.
(2).Receive monitor
A
All packets received on the “receive monitor port”
are send a copy to “sniffer port”. For example, port 0
is set as “receive monitor port” and port 2 is selected
as a “sniffer port”. If a packet is received form port 0
and predestined to port 1 after forwarding decision,
the DM9332 will forward it to port 1 and port 2 in the
end.
9.2.10 Broadcast Storm Filtering
The DM9332 has an option to limit the traffic of
broadcast or multicast packets, to protect the switch
from lower bandwidth availability.
There are two types of broadcast storm control,
one is throttling broadcast packet only, the other
includes multicast. This feature can be set through bit
1 of register 61h.
(3).Transmit monitor
All packets transmitted on the “transmit monitor
port” are send a copy to “sniffer port”. For example,
port 1 is set as “transmit monitor port” and port 2 is
selected as “sniffer port”. If a packet is received from
port 0 and predestined to port 1 after forwarding
decision, the DM9332 will forward it to port 1 and port
The broadcast storm threshold can be
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
45
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
2 in the end.
(4).Exception
(1). Set PVID of Port 0 to 0x01h.
(2). Set PVID of Port 1 to 0x02h.
The DM9332 has an optional setting that
broadcast/multicast packets are not monitored (see
bit 4 of register 65h). It’s useful to avoid unnecessary
bandwidth.
(3). Set PVID of Port 2 to 0x03h.
(4). Set register B1h to 0x06h.
(5). Set register B2h to 0x05h.
(6). Set register B3h to 0x03h.
9.2.13 VLAN Support
9.2.13.1 Port-Based VLAN
The DM9332 supports port-based VLAN as
default, up to 16 groups. Each port has a default VID
called PVID (Port VID, see register 6Fh). The
DM9332 used LSB 4-bytes of PVID as index and
mapped to register B0h~BFh, to define the VLAN
groups.
For instance, we intend to partition DM9332’s
ports into three groups. Port 0 and port 1 in group A,
port 1 and port 2 in group B, finally, port 2 and port 0
in group C. In this case, the setting as below:
9.2.13.2 802.1Q-Based VLAN
Regarding IEEE 802.1Q standard, Tag-based
VLAN uses an extra tag to identify the VLAN
membership of
a
frame across VLAN-aware
switch/router. A tagged frame is four bytes longer
than an untagged frame and contains two bytes of
TPID (Tag Protocol Identifier) and two bytes of TCI
(Tag Control Information).
Dest.
Dest.
Src.
Src.
Length/Type
Data
Standard frame
Tagged frame
TPID
Type
Length /
Data
TCI
0x8100
2 bytes
Priority CFI
VID
3 bits
1 bits
12 bits
User can define each port as Tag port or Un-tag
The DM9332 also supports 16 802.1Q-based
VLAN groups, as specified in bit 1 of register 53h. It’s
obvious that the tagged packets can be assigned to
several different VLANs which are determined
according to the VID inside the VLAN Tag. Therefore,
the operation is similar to port-based VLAN. The
DM9332 used LSB 4-bytes VID of received packet
with VLAN tag and VLAN Group Mapping Register
(B0h~BFh) to configure the VLAN partition. If the
destination port of received packet is not same VLAN
group with received port, it will be discarded.
port by bit 7 of register 6Dh in 802.1Q-based VLAN
mode. The operation of Tag and Un-tag can explain
as below conditions:
(1). Receive untagged packet and forward to
Un-tag port.
Received packet will forward to destination port
without modification.
(2). Receive tagged packet and forward to Un-tag
port.
The DM9332 will remove the tag from the
packet and recalculate CRC before sending it out.
(3). Receive untagged packet and forward to Tag
port.
9.2.13.3 Tag/Untag
46
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
The DM9332 will insert the PVID tag when an
untagged packet enters the port, and recalculate
CRC before delivering it.
(4). Receive tagged packet and forward to Tag
port.
Received packet will forward to destination port
without modification.
9.2.14.1 Port-Based Priority
Port based priority is the simplest scheme and as
default. Each port has a 2-bit priority value as index
for splitting ingress packets to the corresponding
transmit queue. This value can be set in bit 0 and 1 of
register 6Dh.
9.2.14 Priority Support
9.2.14.2 802.1p-Based Priority
802.1p priority can be disabled by bit 2 of register
6Dh, it is enabled by default.
The DM9332 extracts 3-bit priority field from
received packet with 802.1p VLAN tag, and maps this
field against VLAN Priority Map Registers (D0h~D1h)
to determine which transmit queue is designated. The
VLAN Priority Map is programmable.
The DM9332 supports Quality of Service (QoS)
mechanism for multimedia communication such as
VoIP and video conferencing.
The DM9332 provides three priority classifications:
Port-based, 802.1p-based and DiffServ-based priority.
See next section for more detail. The DM9332 offers
four level queues for transmit on per-port based.
The DM9332 provides two packet scheduling
algorithms: Weighted Fair Queuing and Strict Priority
Queuing. Weighted Fair Queuing (WFQ) based on
their priority and queue weight. Queues with larger
weights get more service than smaller. This
mechanism can get highly efficient bandwidth and
smooth the traffic. Strict Priority Queuing (SPQ)
based on priority only. The Packet on the highest
priority queue is transmitted first. The next
highest-priority queue is work until last queue empties,
and so on. This feature can be set in bit 5 of register
6Dh.
9.2.14.3 DiffServ-Based Priority
DiffServ based priority uses the most significant
6-bit of the ToS field in standard IPv4 header, and
maps this field against ToS Priority Map Registers
(C0h~CFh) to determine which transmit queue is
designated. The ToS Priority Map is programmable
too. In addition, User can only refer to most
significant 3-bit of the ToS field optionally, see bit 7 of
register 53h.
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
47
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
9.3 MII Interface
9.3.1 MII data interface
The DM9332 port 2 provides a Media Independent
Interface (MII) as defined in the IEEE 802.3u
standard (Clause 22).
transmitted from the external device to the DM9332
port 2 MAC.
•
CRS2 (carrier sense) is asserted by the
The MII consists of a nibble wide receive data bus,
a nibble wide transmit data bus, and control signals to
facilitate data transfers between the DM9332 port 2
and external device (a PHY or a MAC in reverse MII).
external device when either the transmit or receive
medium is non-idle, and de-asserted by the external
device when the transmit and receive medium are
idle. The CRS2 can also in output mode when the
DM9332 port 2 is configured to reversed MII mode.
•
TXD2 (transmit data) is a nibble (4 bits) of
•
COL2 (collision detection) is asserted by the
data that are driven by the DM9332 synchronously
with respect to TXC2. For each TXC2 period, which
TXE2 is asserted, TXD2 (3:0) are accepted for
transmission by the external device.
external device, when both the transmit and receive
medium is non-idle, and de-asserted by the external
device when the either transmit or receive medium
are idle. The COL2 can also in output mode when the
DM9332 port 2 is configured to reversed MII mode.
•
TXC2 (transmit clock) from the external
device is a continuous clock that provides the timing
reference for the transfer of the TXE2, TXD2. The
DM9332 can drive 25MHz clock if it is configured to
reversed MII mode.
9.3.2 MII Serial Management
The MII serial management interface consists of a
data interface, basic register set in DM9332 port 0
and 1, and a serial management interface to the
register set. Through this interface it is possible to
control and configure multiple PHY devices, include
internal two ports, get status and error information,
and determine the type and capabilities of the
attached PHY device(s). The DM9332 default is
polling 3 ports basic registers 0, 1, 4, and 5 to get the
link, duplex, and speed status automatically.
Alternatively, the DM9332 can be programmed to
read or write any registers of 3 ports by section
6.8~11 CSR B, C, D, and E.
•
TXE2 (transmit enable) from the DM9332 port
2 MAC indicates that nibbles are being presented on
the MII for transmission to the external device.
•
RXD2 (receive data) is a nibble (4 bits) of data
that are sampled by the DM9332 port 2 MAC
synchronously with respect to RXC2. For each RXC2
period which RXDV2 is asserted, RXD2 (3:0) are
transferred from the external device to the DM9332
port 2 MAC reconciliation sub layer.
•
RXC2 (receive clock) from external device to
the DM9332 port 2 MAC reconciliation sub layer is a
continuous clock that provides the timing reference
for the transfer of the RXDV2, RXD2, and RXER2
signals.
The DM9332 management functions correspond
to MII specification for IEEE 802.3u-1995 (Clause 22)
for registers 0 through 6 with vendor-specific registers
16,17, 18, 21, 22, 23 and 24~27.
•
RXDV2 (receive data valid) input from the
In read/write operation, the management data
frame is 64-bits long and starts with 32 contiguous
logic one bits (preamble) synchronization clock cycles
on MDC. The Start of Frame Delimiter (SFD) is
indicated by a <01> pattern followed by the operation
code (OP) :< 10> indicates Read operation and <01>
indicates Write operation. For read operation, a 2-bit
turnaround (TA) filing between Register Address field
and Data field is provided for MDIO to avoid
contention. Following the turnaround time, 16-bit data
is read from or written onto management registers.
external device to indicates that the external device is
presenting recovered and decoded nibbles to the
DM9332 port 2 MAC reconciliation sub layer. To
interpret a receive frame correctly by the
reconciliation sub layer, RXDV2 must encompass the
frame, starting no later than the Start-of-Frame
delimiter and excluding any End-Stream delimiter.
•
RXER2 (receive error) input from the external
device is synchronously with respect to RXC2.
RXER2 will be asserted for 1 or more clock periods to
indicate to the reconciliation sub layer that an error
was detected somewhere in the frame being
48
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
9.3.3 Serial Management Interface
The serial control interface uses a simple
two-wired serial interface to obtain and control the
status of the physical layer through the MII interface.
The serial control interface consists of MDC
(Management Data Clock), and MDI/O (Management
Data Input/Output) signals.
The MDIO pin is bi-directional and may be shared
by up to 32 devices.
9.3.4 Management Interface - Read Frame Structure
MDC
MDIO Read
//
//
0
1
1
0
A4
A3
A0
R4
R3
R0
32 "1"s
0
D15
D14
D1
D0
Z
Idle Preamble
SFD
Op Code
PHY Address
Register Address
Turn Around
Data
Idle
Read
Write
9.3.5 Management Interface - Write Frame Structure
MDC
MDIO Write
32 "1"s
0
1
0
1
A4
A3
A0
R4
R3
R0
1
0
D15
D14
Data
D1
D0
Idle Preamble
SFD
Op Code
PHY Address
Register Address
Write
Turn Around
Idle
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
49
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
By scrambling the data, the total energy presented to
the cable is randomly distributed over a wide
frequency range. Without the scrambler, energy
levels on the cable could peak beyond FCC
9.4 Internal PHY functions
9.4.1 100Base-TX Operation
The transmitter section contains the following
functional blocks:
limitations at frequencies related to the repeated 5B
sequences, like the continuous transmission of IDLE
symbols. The scrambler output is combined with the
NRZ 5B data from the code-group encoder via an
XOR logic function. The result is a scrambled data
stream with sufficient randomization to decrease
radiated emissions at critical frequencies.
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Converter
- NRZI to MLT-3
- MLT-3 Driver
9.4.1.3 Parallel to Serial Converter
9.4.1.1 4B5B Encoder
The Parallel to Serial Converter receives parallel 5B
scrambled data from the scrambler, and serializes it
(converts it from a parallel to a serial data stream).
The serialized data stream is then presented to the
NRZ to NRZI encoder block
The 4B5B encoder converts 4-bit (4B) nibble data
generated by the MAC Reconciliation Layer into a
5-bit (5B) code group for transmission, see reference
Table 1. This conversion is required for control and
packet data to be combined in code groups. The
4B5B encoder substitutes the first 8 bits of the MAC
preamble with a J/K code-group pair (11000 10001)
upon transmit. The 4B5B encoder continues to
replace subsequent 4B preamble and data nibbles
with corresponding 5B code-groups. At the end of the
transmit packet, upon the desertions of the Transmit
Enable signal from the MAC Reconciliation layer, the
4B5B encoder injects the T/R code-group pair (01101
00111) indicating the end of frame. After the T/R
code-group pair, the 4B5B encoder continuously
injects IDLEs into the transmit data stream until
Transmit Enable is asserted and the next transmit
packet is detected.
9.4.1.4 NRZ to NRZI Encoder
After the transmit data stream has been scrambled
and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard, for 100Base
-TX transmission over Category-5 unshielded twisted
pair cable.
9.4.1.5 MLT-3 Converter
The MLT-3 conversion is accomplished by converting
The data stream output, from the NRZI encoder into
two binary data streams, with alternately phased logic
One event.
9.4.1.6 MLT-3 Driver
9.4.1.2 Scrambler
The scrambler is required to control the radiated
emissions (EMI) by spreading the transmit energy
across the frequency spectrum at the media
connector and on the twisted pair cable in
100Base-TX operation.
The two binary data streams created at the MLT-3
converter are fed to the twisted pair output driver,
which converts these streams to current sources and
alternately drives either side of the transmit
transformer’s primary winding, resulting in a minimal
current MLT-3 signal.
50
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
9.4.1.7 4B5B Code Group
Symbol
Meaning
4B code
3210
5B Code
43210
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
I
J
K
T
R
H
Idle
undefined
0101
11111
11000
10001
01101
00111
00100
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
0101
undefined
undefined
undefined
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Table 1
Preliminarydatasheet
51
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
9.4.2 100Base-TX Receiver
The 100Base-TX receiver contains several function
blocks that convert the scrambled 125Mb/s serial
data to synchronous 4-bit nibble data.
The receive section contains the following functional
blocks:
9.4.2.3 MLT-3 to NRZI Decoder
The DM9332 decodes the MLT-3 information from
the Digital Adaptive Equalizer into NRZI data.
9.4.2.4 Clock Recovery Module
- Signal Detect
The Clock Recovery Module accepts NRZI data from
the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the
125 MHz reference clock. The extracted and
synchronized clock and data are presented to the
NRZI to NRZ decoder.
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
9.4.2.5 NRZI to NRZ
The transmit data stream is required to be NRZI
encoded for compatibility with the TP-PMD standard
for 100Base-TX transmission over Category-5
unshielded twisted pair cable. This conversion
process must be reversed on the receive end. The
NRZI to NRZ decoder receives the NRZI data stream
from the Clock Recovery Module and converts it to a
NRZ data stream to be presented to the Serial to
Parallel conversion block.
9.4.2.1 Signal Detect
The signal detects function meets the specifications
mandated by the ANSI XT12 TP-PMD 100Base-TX
standards for both voltage thresholds and timing
parameters.
9.4.2.2 Adaptive Equalization
When transmitting data over copper twisted pair
cable at high speed, attenuation based on frequency
becomes a concern. In high speed twisted pair
signaling, the frequency content of the transmitted
signal can vary greatly during normal operation based
on the randomness of the scrambled data stream.
This variation in signal attenuation, caused by
frequency variations, must be compensated for to
ensure the integrity of the received data. In order to
ensure quality transmission when employing MLT-3
encoding, the compensation must be able to adapt to
various cable lengths and cable types depending on
the installed environment. The selection of long cable
9.4.2.6 Serial to Parallel
The Serial to Parallel Converter receives a serial data
stream from the NRZI to NRZ converter. It converts
the data stream to parallel data to be presented to the
descrambler.
9.4.2.7 Descrambler
Because of the scrambling process requires to
control the radiated emissions of transmit data
streams, the receiver must descramble the receive
data streams. The descrambler receives scrambled
parallel data streams from the Serial to Parallel
converter, and it descrambles the data streams, and
presents the data streams to the Code Group
alignment block.
lengths for
a
given implementation requires
significant compensation, which will be over-killed in
a situation that includes shorter, less attenuating
cable lengths. Conversely, the selection of short or
intermediate
cable
lengths
requiring
less
compensation will cause serious under-compensation
for longer length cables. Therefore, the compensation
or equalization must be adaptive to ensure proper
conditioning of the received signal independent of the
cable length.
52
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
9.4.2.8 Code Group Alignment
9.4.6 Auto-Negotiation
The Code Group Alignment block receives un-aligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected and subsequent data is aligned on
a fixed boundary.
The objective of Auto-negotiation is to provide a
means to exchange information between linked
devices and to automatically configure both devices
to take maximum advantage of their abilities. It is
important to note that Auto-negotiation does not test
the characteristics of the linked segment. The
Auto-Negotiation function provides a means for a
device to advertise supported modes of operation to
a remote link partner, acknowledge the receipt and
understanding of common modes of operation, and to
reject un-shared modes of operation. This allows
devices on both ends of a segment to establish a link
at the best common mode of operation. If more than
one common mode exists between the two devices, a
mechanism is provided to allow the devices to
resolve to a single mode of operation using a
predetermined priority resolution function.
9.4.2.9 4B5B Decoder
The 4B5B Decoder functions as a look-up table that
translates incoming 5B code groups into 4B (Nibble)
data. When receiving a frame, the first 2 5-bit code
groups receive the start-of-frame delimiter (J/K
symbols). The J/K symbol pair is stripped and two
nibbles of preamble pattern are substituted. The last
two code groups are the end-of-frame delimiter (T/R
Symbols).
The T/R symbol pair is also stripped from the nibble,
presented to the Reconciliation layer.
Auto-negotiation also provides a parallel detection
function for devices that do not support the
Auto-negotiation feature. During Parallel detection
there is no exchange of information of configuration.
Instead, the receive signal is examined. If it is
discovered that the signal matches a technology,
which the receiving device supports, a connection will
be automatically established using that technology.
This allows devices not to support Auto-negotiation
but support a common mode of operation to establish
a link.
9.4.3 10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant.
When the DM9332 is operating in 10Base-T mode,
the coding scheme is Manchester. Data processed
for transmit is presented in nibble format, converted
to a serial bit stream, then the Manchester encoded.
When receiving, the bit stream, encoded by the
Manchester, is decoded and converted into nibble
format.
9.5 HP Auto-MDIX Functional Descriptions
9.4.4 Collision Detection
The DM9332 supports the automatic detect cable
connection type, MDI/MDIX (straight through/cross
over). A manual configuration by register bit for MDI
or MDIX is still accepted.
For half-duplex operation, a collision is detected
when the transmit and receive channels are active
simultaneously. Collision detection is disabled in full
duplex operation.
When set to automatic, the polarity of MDI/MDIX
controlled timing is generated by 16-bits LFSR. The
switching cycle time is located from 200ms to 420ms.
The polarity control is always switch until detect
received signal. After selected MDI or MDIX,
This feature is able to detect the required cable
connection type. (Straight through or crossed over)
and make correction automatically
9.4.5 Carrier Sense
Carrier Sense (CRS) is asserted in half-duplex
operation during transmission or reception of data.
During full-duplex mode, CRS is asserted only during
Receive operations.
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
53
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
RX + /- from DM9332
RX+/- to RJ45
TX + /- from DM9332
TX+/- to RJ45
* MDI: __________
* MDIX: - - - - - - - - -
54
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
10.DC and AC Electrical Characteristics
10.1 Absolute Maximum Ratings
Symbol
Parameter
Min.
-0.3
-0.3
-0.3
-0.3
-0.5
-65
0
Max.
3.6
1.95
3.6
1.95
5.5
+150
+70
+260
Unit
V
V
V
V
Conditions
VCC3
VCCI
AVDD3
AVDDI
VIN
TSTG
TA
3.3V Supply Voltage
1.8V core power supply
Analog power supply 3.3V
Analog power supply 1.8V
DC Input Voltage (VIN)
Storage Temperature range
Ambient Temperature
V
°C
°C
°C
Lead Temperature
(TL, soldering, 10 sec.).
-
LT
Lead-free Device
10.2 Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
-
VCC3
VCCI
AVDD3
AVDDI
PD
3.3V Supply Voltage
3.135
1.71
3.135
1.71
3.300
1.80
3.300
1.80
90
120
20
50
90
110
40
40
90
3.465
1.89
3.465
1.89
V
V
V
V
1.8V core power supply
Analog power supply 3.3V
Analog power supply 1.8V
100BASE-TX with 100BASE-FX
Data utilization rate is 100%
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1.8VD only
1.8VA only
3.3VD only
3.3VA only
1.8VD only
1.8VA only
3.3VD only
3.3VA only
1.8VD only
1.8VA only
3.3VD only
3.3VA only
1.8VD only
1.8VA only
3.3VD only
3.3VA only
(Power
Dissipation)
Ethernet Link O.K.
Fiber Link O.K.
120
60
20
80
80
Auto-negotiation or cable off
30
40
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
55
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
10.3 DC Electrical Characteristics
Symbol
Parameter
Min.
Typ. Max. Unit
Conditions
Inputs
VIL
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
-
2.0
-1
-
-
-
-
-
0.8
-
-
V
V
uA
uA
Vcond1
Vcond1
VIN = 0.0V, Vcond1
VIN = 3.3V, Vcond1
VIH
IIL
IIH
1
Outputs
VOL
VOH
Receiver
VICM
Output Low Voltage
Output High Voltage
-
-
-
0.4
-
V
V
IOL = 4mA
IOH = -4mA
2.4
RX+/RX- Common Mode Input
Voltage
-
1.8
-
V
100 Ω Termination
Across
Transmitter
VTD100 100TX+/- Differential Output Voltage
VTD10 10TX+/- Differential Output Voltage
ITD100 100TX+/- Differential Output Current │19│ │20│ │21│
ITD10 10TX+/- Differential Output Current │40│ │50│ │56│
1.9
4.0
2.0
5
2.1
5.6
V
V
mA
mA
Peak to Peak
Peak to Peak
Absolute Value
Absolute Value
Note: Vcond1 = VCC3 = 3.3V, VCCI = 1.8V, AVDD3 = 3.3V, AVDDI = 1.8V.
10.4 AC characteristics
10.4.1 Power On Reset Timing
T1
PWRST#
T4
Strap pins
T2
EECS
T3
Symbol
T1
Parameter
Min.
Typ.
Max.
Unit Conditions
PWRST# Low Period
1
40
-
-
-
-
-
ms
ns
-
-
T2
Strap pin hold time with PWRST#
PWRST# high to EECS high
PWRST# high to EECS burst end
T3
5
--
-
us
T4
-
4
ms
56
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
10.4.2 Port 2 MII Interface Transmit Timing
TXC2
TXE2
T1
T2
TXD2_3~0
Symbol
Parameter
TXE2,TXD2_3~0 Setup Time
TXE2,TXD2_3~0 Hold Time
Min.
Typ.
32
8
Max.
Unit
ns
ns
T1
T2
10.4.3 Port 2 MII Interface Receive Timing
RXC2
RXER2,RXDV2
RXD2_3~0
T1
T2
Symbol
Parameter
RXER2, RXDV2,RXD2_3~0 Setup Time
RXER2, RXDV2,RXD2_3~0 Hold Time
Min.
5
5
Typ.
Max.
Unit
ns
ns
T1
T2
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
57
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
10.4.4 MII Management or host SMI Interface Timing
T1
MDC
or SMI_CK
T2
MDIO (drived by DM9332)
or SMI_DIO
T4
T3
MDIO (drived by exetrnal MII)
or SMI_DIO
T5
Symbol
Parameter
MDC or SMI_CK Frequency
MDIO or SMI_DIO by DM9332 Setup Time
MDIO or SMI_DIO by DM9332 Hold Time
MDIO or SMI_DIO by External MII Setup Time
MDIO or SMI_DIO by External MII Hold Time
Min.
Typ.
0.52
955
960
Max.
Unit
MHz
ns
ns
ns
T1
T2
T3
T4
T5
40
40
ns
58
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
10.4.5 EEPROM timing
T1
T2
EECS
T3
EECK
T6
T4
EEDIO
T5
T7
Symbol
T1
Parameter
Min.
Typ.
480
2080
0.38
460
Max.
Unit
ns
ns
MHz
ns
ns
EECS Setup Time
EECS Hold Time
EECK Frequency
T2
T3
T4
T5
T6
T7
EEDIO Setup Time in output state
EEDIO Hold Time in output state
EEDIO Setup Time in input state
EEDIO Hold Time in input state
2100
8
8
ns
ns
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
59
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
11.Package Information
64 Pins LQFP Package Outline Information:
Dimension in mm
Dimension in inch
Nom Max
Symbol
Min
-
Nom
-
-
1.40
0.22
0.20
-
Max
1.60
0.15
1.45
0.27
0.23
0.20
0.16
Min
-
A
-
-
0.063
0.006
0.057
0.011
0.009
0.008
0.006
A1
A2
b
b1
c
c1
D
D1
E
0.05
1.35
0.17
0.17
0.09
0.09
0.002
0.053
0.007
0.007
0.004
0.004
0.055
0.009
0.008
-
-
-
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.50 BSC
0.60
0.472 BSC
0.394 BSC
0.472 BSC
0.394 BSC
0.020 BSC
0.024
E1
e
L
0.45
0.75
0.018
0.030
L1
R1
R2
S
1.00 REF
-
0.039 REF
-
0.08
0.08
0.20
0o
-
0.20
-
0.003
0.003
0.008
0o
-
-
-
-
-
0.008
-
7o
-
θ
3.5o
7o
-
3.5o
θ1
θ2
θ3
0o
-
0o
-
12o TYP
12o TYP
12o TYP
12o TYP
1. Dimension D1 and E1 do not include resin fin.
2. All dimensions are base on metric system.
3. General appearance spec should base on its final visual inspection spec.
60
Preliminary datasheet
DM9332-15-DS-P01
March 5, 2012
DM9332
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
reference purposes only.
12.Ordering Information
DAVICOM’s terms and conditions printed on the
order acknowledgment govern all sales by DAVICOM.
DAVICOM will not be bound by any terms
inconsistent with these unless DAVICOM agrees
Part Number
DM9332EP
Pin Count
Package
LQFP
(Pb-free)
64
otherwise in writing. Acceptance of the buyer’s orders
shall be based on these terms.
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the described
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the
industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal,
we have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
products that meet their cost requirements.
chip(s) from patent infringement.
DAVICOM MAKES NO WARRANTY
FURTHER,
OF
MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at
any time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications. Please note that
application circuits illustrated in this document are for
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
available and soon to be released products are based
on our proprietary designs and deliver high quality,
high performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the Sales department at:
Headquarters
Hsin-chu Office:
No.6 Li-Hsin Rd. VI,
Science-based Park,
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HTTP: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of
the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
Preliminarydatasheet
DM9332-15-DS-P01
March 5, 2012
61
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