CS8141YDW24 [ETC]
Positive Fixed Voltage Regulator ; 正固定电压稳压器\n
| 型号： | CS8141YDW24 |
| 厂家： | 
ETC |
| 描述： | Positive Fixed Voltage Regulator
|
| 文件： | 总20页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8140, CS8141
5.0 V, 500 mA Linear
Regulator with ENABLE,
RESET, and Watchdog
The CS8140 and CS8141 are linear regulators suited for
microprocessor applications in automotive environments.
These ON Semiconductor parts provide the power for the
microprocessors along with many of the control functions needed in
today’s computer based systems. Incorporating all of these features
saves both cost, and board space.
http://onsemi.com
TO–220
SEVEN LEAD
T SUFFIX
CASE 821E
Packages are available for surface mounting as well as through hole
mounting.
1
7
The CS8141 has the same feature set as the CS8140 with the
exception of the response to the watchdog signals (WDI). The CS8141
only responds to input signals (WDI) which are below the preset
watchdog frequency threshold.
TO–220
SEVEN LEAD
TVA SUFFIX
CASE 821J
1
TO–220
Features
• 5.0 V ±4.0%, 500 mA Output Voltage
• µP Compatible Control Functions
– Watchdog
SEVEN LEAD
THA SUFFIX
CASE 821H
1
– RESET
– ENABLE
7
2
D PAK
• Low Dropout Voltage (1.25 V @ 500 mA)
• Low Quiescent Current (7.0 mA @ 500 mA)
• Low Noise, Low Drift
7–PIN
DPS SUFFIX
CASE 936H
1
7
• Low Current SLEEP Mode (I = 250 µA)
Q
• Fault Protection
SO–24L
DW SUFFIX
CASE 751E
– Thermal Shutdown
– Short Circuit
24
– 60 V Peak Transient Voltage
1
DIP–14
N SUFFIX
CASE 646
14
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 14 of this data sheet.
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
September, 2001 – Rev. 13
CS8140/D
CS8140, CS8141
PIN CONNECTIONS
DIP–14
TO–220
SO–24L
SEVEN LEAD
1
14
RESET
ENABLE
1
24
NC
Delay
WDI
RESET
ENABLE
NC
Delay
WDI
V
OUT
V
IN
V
OUT
V
IN
Sense
GND
GND
NC
NC
NC
NC
NC
NC
NC
Sense
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
Tab = GND
Pin 1. V
IN
2. ENABLE
3. RESET
4. GND
1
GND
5. Delay
6. WDI
2
D PAK
SEVEN PIN
7. V
OUT
1
V
IN
Overvoltage
Overtemperature
Reference & Bias
Regulation
ENABLE
WDI
Control Logic
ENABLE
RESET
V
OUT
Delay
Short Circuit
Undervoltage
Internally tied
on TO–220
& D PAK
2
Sense
GND
Watchdog
RESET
Delay
Figure 1. Block Diagram
http://onsemi.com
2
CS8140, CS8141
MAXIMUM RATINGS*
Rating
Value
–0.5 to 26
60
Unit
V
Input Operating Range
Peak Transient Voltage (46 V Load Dump @ 14 V V
Electrostatic Discharge (Human Body Model)
)
V
BAT
4.0
kV
WDI Input Signal Range
Internal Power Dissipation
–0.3 to 7.0
Internally Limited
–40 to +150
V
–
Junction Temperature Range (T )
°C
°C
J
Storage Temperature Range
ENABLE
–65 to +150
–0.3 to V
V
IN
Package Thermal Resistance, TO–220 Seven Lead
Junction–to–Case, R
Junction–to–Ambient, R
1.6
50
°C/W
°C/W
θ
JC
θ
JA
2
Package Thermal Resistance, D PAK 7–Pin
Junction–to–Case, R
1.5
10–50†
°C/W
°C/W
θ
JC
Junction–to–Ambient, R
θ
JA
Package Thermal Resistance, SO–24L
Junction–to–Case, R
16
80
°C/W
°C/W
θ
JC
Junction–to–Ambient, R
θ
JA
Package Thermal Resistance, DIP–14
Junction–to–Case, R
48
85
°C/W
°C/W
θ
JC
Junction–to–Ambient, R
θ
JA
Lead Temperature Soldering:
Wave Solder (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
260 peak
230 peak
°C
*The maximum package power dissipation must be observed.
†Depending on thermal properties of substrate R
1. 10 second maximum.
= R
+ R
.
CA
θ
θ
θ
JA
JC
2. 60 seconds max above 183°C.
ELECTRICAL CHARACTERISTICS (7.0 ≤ V ≤ 26 V, 5.0 mA ≤ I
≤ 500 mA, –40°C ≤ T ≤ 150°C,
IN
OUT
J
–40°C ≤ T ≤ 125°C, unless otherwise noted.) Note 3.
A
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Stage (V
)
OUT
Output Voltage, V
7.0 V ≤ V ≤ 26 V, 5.0 mA < I < 500 mA
OUT
4.8
–
5.0
1.25
5.0
5.2
1.50
25
V
OUT
IN
Dropout Voltage (V – V
)
I = 500 mA
OUT
V
IN
OUT
Line Regulation
Load Regulation
I
= 50 mA, 7.0 V ≤ V ≤ 26 V,
–
mV
mV
mΩ
OUT
IN
V
IN
= 14 V, 50 mA ≤ I
≤ 500 mA
–
5.0
80
OUT
Output Impedance, R
500 mA DC and 10 mA AC,
–
200
–
OUT
100 Hz ≤ f ≤ 10 kHz
Quiescent Current, (I )
Q
Active Mode
Sleep Mode
0 ≤ I
≤ 500 mA, 7.0 V ≤ V ≤ 26 V
–
–
7.0
0.25
15
0.50
mA
mA
OUT
IN
I
= 0 mA, V = 13 V, ENABLE = 0 V
OUT
IN
Ripple Rejection
7.0 V ≤ V ≤ 17 V, I
= 250 mA,
60
75
–
dB
IN
OUT
f = 120 Hz
Current Limit
–
700
150
30
1200
180
34
2000
–
mA
°C
V
Thermal Shutdown
Overvoltage Shutdown
–
V
OUT
< 1.0 V
38
3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
http://onsemi.com
3
CS8140, CS8141
ELECTRICAL CHARACTERISTICS (continued) (7.0 ≤ V ≤ 26 V, 5.0 mA ≤ I
≤ 500 mA, –40°C ≤ T ≤ 150°C,
J
IN
OUT
–40°C ≤ T ≤ 125°C, unless otherwise noted.) Note 4.
A
Characteristic
ENABLE
Test Conditions
Min
Typ
Max
Unit
Threshold
HIGH
LOW
V
OUT
V
OUT
≥ 0.5 V, (V
< 0.5 V, (V
)
–
3.5
4.05
3.95
4.50
–
V
V
OUT(ON)
)
OUT(OFF)
Threshold Hysteresis
(HIGH – LOW)
–
100
–
mV
RESET
Threshold HIGH V
V
V
Increasing
4.65
4.50
150
–
4.90
4.70
200
–
V – 0.05
OUT
V
V
R(HI)
OUT
Threshold LOW V
Decreasing
4.90
250
25
R(LOW)
OUT
Threshold Hysteresis (V
)
(HIGH – LOW)
V ≥ V
OUT
mV
µA
RH
RESET Output Leakage
RESET = HIGH
R(HI)
Output Voltage Low (V
Output Voltage Low (V
)
1.0 V ≤ V
≤ V
, R = 2.7 kΩ, Note 5.
–
–
0.1
0.6
0.4
1.0
65
V
V
L(LOW)
OUT
R(LOW)
P
)
V , Power up, Power down
OUT
Rpeak
Delay Times t
Delay Times t
Watchdog
C
C
= 0.1 µF
= 0.1 µF
30
0.5
47.5
1.0
ms
ms
POR
WDI(RESET)
DELAY
DELAY
1.5
Input Voltage High
Input Voltage Low
Input Current
–
–
2.0
–
–
–
–
V
0.8
10
V
WDI ≤ V
–
0
µA
Hz
Hz
OUT
Threshold Frequency f
C
C
= 0.1 µF
64
218
77
262
96
WDI(LOWER)
WDI(UPPER)
DELAY
DELAY
Threshold Frequency f
(Note 6.)
= 0.1 µF
326
4. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
5. R is connected to RESET and V
P
OUT.
6. CS8140 only.
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD #
LEAD SYMBOL
LEAD SYMBOL
2
TO–220
D PAK
SO–24L
21
DIP–14
12
FUNCTION
Supply voltage to IC, usually direct from the battery.
CMOS compatible logical input. V is disabled when
1
2
1
2
V
IN
23
13
ENABLE
OUT
ENABLE is LOW and WDI is beyond its preset limits.
3
3
24
14
RESET
CMOS compatible output lead. RESET goes low whenever
V
OUT
drops below 4.5% of it’s typical value for more than
2.0 µs or WDI signal falls outside it’s window limits.
4
5
6
4
5
6
12, 20
8, 11
GND
Delay
WDI
Ground Connection.
2
3
1
2
Timing capacitor for Watchdog and RESET functions.
CMOS compatible input lead. The Watchdog function monitors
the falling edge of the incoming digital pulse train. The signal is
usually generated by the system microprocessor.
7
–
–
7
–
–
4
3
V
Regulated output voltage, 5.0 V (typ).
No connection.
OUT
1, 6–11,
13–19, 22
5–7, 9, 10
NC
5
4
Sense
Kelvin connection which allows remote sensing of output volt-
age for improved regulation.
http://onsemi.com
4
CS8140, CS8141
TYPICAL PERFORMANCE CHARACTERISTICS
5.5
5.0
5.5
V
= V
IN
V
= V
IN
ENABLE
ENABLE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
R
= NO LOAD
4.5
4.0
3.5
LOAD
TEMP = 125°C
R
= 6.67 Ω
LOAD
TEMP = –40°C
3.0
2.5
TEMP = 25°C
R
LOAD
10 Ω
2.0
1.5
1.0
0.5
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
IN
(V)
V
IN
(V)
Figure 3. VOUT vs. VIN Over Temperature; RLOAD = 25 Ω
Figure 2. VOUT vs. VIN over RLOAD; T = 25°C
1800
1600
1400
3.5
–40°C
0
25°C
–3.5
–7
V
IN
= 14 V
1200
1000
–10.5
–14
–40°C
125°C
–17.5
800
600
–21
25°C
125°C
–24.5
400
200
–28
–31.5
–35
0
0
100
200
300
I
400
500
600
700
800
0
100
200
300
400
(mV)
500
600
700
800
I
(mA)
OUT
OUT
Figure 5. Load Regulation vs. Output
Current Over Temperature
Figure 4. Dropout Voltage vs. Output
Current Over Temperature
18
16
10
9
V
IN
= 14 V
V
IN
= 14 V
14
12
–40°C
10
8
–40°C
8
6
7
6
4
25°C
125°C
2
0
25°C
–2
–4
5
4
125°C
–6
0
100
200
300
400
500
600
700
800
0
100
200
300
400
(mA)
500
600
700
800
I
(mA)
I
OUT
OUT
Figure 6. Line Regulation vs. Output
Current Over Temperature
Figure 7. Quiescent Current vs. Output
Current Over Temperature
http://onsemi.com
5
CS8140, CS8141
TYPICAL PERFORMANCE CHARACTERISTICS
20
18
16
20
V
= V
IN
ENABLE
V
= V
IN
ENABLE
18
16
TEMP = 25°C
14
12
10
8
14
12
10
8
R
= 6.67
LOAD
TEMP = –40°C
R
= 25
LOAD
6
6
R
= NO LOAD
LOAD
TEMP = 125°C
4
2
0
4
2
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
IN
(V)
V
IN
(V)
Figure 8. Quiescent Current vs. VIN Over RLOAD
;
Figure 9. Quiescent Current vs. VIN Over
T = 25°C
Temperature; RLOAD = 25 Ω
7
300
280
260
240
220
10
6
5
4
Upper Threshold
10
10
C
= 0.1 µF
Upper Threshold
DELAY
200
180
160
140
10
3
10
Lower Threshold
2
10
10
10
120
100
80
Lower Threshold
1
0
60
–40
1
2
3
4
5
6
0
10
10
–30–20–10
20 30 40 50 60 70 80 90 100 110120130140 150
10
10
10
10
10
10
Capacitance (pF)
T (°C)
J
Figure 10. Watchdog Frequency Thresholds
vs. Temperature
Figure 11. Watchdog Frequency Threshold vs.
CDELAY
90
2000
I
= 250 mA
O
1800
1600
1400
1200
80
70
60
50
C
= 10 µF, ESR = 1.0
O
V
IN
= 5.0 V
& 0.1 µF, ESR = 0
1000
800
40
30
20
C
OUT
= 10 µF, ESR = 1.0 Ω
600
400
200
0
C
OUT
= 10 µF, ESR = 1.0 Ω
10
0
0
1
2
3
4
5
6
7
8
1
5
10
15
20
25
30
35
40
10
10
10
10
10
10
10
10
10
Frequency (Hz)
RESET Output Current (mA)
Figure 12. Ripple Rejection vs. Frequency
Figure 13. RESET Output Voltage vs.
Output Current
http://onsemi.com
6
CS8140, CS8141
DEFINITION OF TERMS
Dropout Voltage: The input–output voltage differential
such that the average chip temperature is not significantly
affected.
Load Regulation: The change in output voltage for a
change in load current at constant chip temperature.
Quiescent Current: The part of the positive input current
that does not contribute to the positive load current. The
regulator ground lead current.
Ripple Rejection: The ratio of the peak–to–peak input
ripple voltage to the peak–to–peak output ripple voltage.
Current Limit: Peak current that can be delivered to the
output.
at which the circuit ceases to regulate against further
reduction in input voltage. Measured when the output
voltage has dropped 100 mV from the nominal value
obtained at 14 V input, dropout voltage is dependent upon
load current and junction temperature.
Input Voltage: The DC voltage applied to the input
terminals with respect to ground.
Line Regulation: The change in output voltage for a
change in the input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
CIRCUIT DESCRIPTION
VOLTAGE REFERENCE AND OUTPUT CIRCUITRY
The CS8140 is a 5.0 V Watchdog Regulator with protection
circuitry and three logic control functions that allow a
microprocessor to control its own power supply. The CS8140
is designed for use in automotive, switch mode power supply
post regulator, and battery powered systems.
Precision Voltage Reference
The regulated output voltage depends on the precision
band gap voltage reference in the IC. By adding an error
amplifier into the feedback loop, the output voltage is
maintained within ±4.0% over temperature and supply
variation.
Basic regulator performance characteristics include a low
noise, low drift, 5.0 V ±4.0% precision output voltage with
low dropout voltage (1.25 V @ I
= 500 mA) and low
OUT
quiescent current (7.0 mA @ I
= 500 mA). On board
OUT
Output Stage
short circuit, thermal, and overvoltage protection make it
possible to use this regulator in particularly harsh operating
environments.
The Watchdog logic function monitors an input signal
(WDI) from the microprocessor or other signal source.
When the signal frequency moves outside externally
programmable window limits, a RESET signal is generated
The composite PNP–NPN output structure (Figure 14)
provides 500 mA (min) of output current while maintaining
a low drop out voltage (1.25 V) and drawing little quiescent
current (7.0 mA).
V
IN
(RESET). An external capacitor (C
) programs the
DELAY
watchdog window frequency limits as well as the power on
reset (POR) and RESET delay.
The RESET function is activated by any of three
conditions: the watchdog signal moves outside of its preset
limits; the output voltage drops out of regulation by more
than 4.5%; or the IC is in its power up sequence. The RESET
V
OUT
Figure 14. Composite Output Stage of the CS8140/1
signal is independent of V and reliable down to V
=
IN
OUT
1.0 V.
The NPN pass device prevents deep saturation of the
output stage which in turn improves the IC’s efficiency by
preventing excess current from being used and dissipated by
the IC.
In conjunction with the Watchdog, the ENABLE function
controls the regulator’s power consumption. The CS8140’s
output stage and its attendant circuitry are enabled by setting
the ENABLE lead high. The regulator goes into sleep mode
when the ENABLE lead goes low and the watchdog signal
moves outside its preset window limits. This unique
combination of control functions in the CS8140 gives the
microprocessor control over its own power down sequence:
i.e. it gives the microprocessor the flexibility to perform
housekeeping functions before it powers down.
Output Stage Protection
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (Figure 15).
If the input voltage rises above 30 V (e.g. load dump), the
output shuts down. This response protects the internal
circuitry and enables the IC to survive unexpected voltage
transients.
The CS8141 has the same features as the CS8140, except
that the CS8141 only responds to input signals (WDI) which
are below the preset watchdog frequency threshold.
Using an emitter sense scheme, the amount of current
through the NPN pass transistor is monitored. Feedback
http://onsemi.com
7
CS8140, CS8141
circuitry insures that the output current never exceeds a
preset limit.
The lower and upper window threshold limits of the
watchdog function are set by the value of C . The limits
DELAY
are determined according to the following equations for the
CS8140:
> 30 V
5)
+ (1.3 10
(a)
t
f
t
f
C
or
DELAY
DELAY
WDI(LOWER)
WDI(LOWER)
WDI(UPPER)
WDI(UPPER)
DELAY
V
IN
–6
+ (7.69 10 )C
–1
or
V
OUT
–4
+ (3.82 10 )C
(b)
–5
+ (2.62 10 )C
–1
DELAY
I
O
For the CS8141 the lower limit is determined by the
equations in (a) above.
Short
Circuit
Thermal
Shutdown
Load
Dump
The capacitor C
also determines the frequency of
DELAY
Figure 15. Typical Circuit Waveforms for
Output Stage Protection
the RESET signal and the POWER–ON–RESET (POR)
delay period.
RESET Function
The RESET function is activated when the Watchdog
signal is outside of its preset window (Figure 16), when the
Should the junction temperature of the power device
exceed 180°C (typ), the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
regulator is in its power up state (Figure 17) or when V
OUT
drops below V
–4.5% for more than 2.0 µs (Figure 18)
OUT
If the Watchdog signal falls outside of the preset voltage
and frequency window, a frequency programmable pulse
train is generated at the RESET lead (Figure 16) until the
correct Watchdog input signal reappears at the lead. The
REGULATOR CONTROL FUNCTIONS
The CS8140 differs from all other linear regulators in its
unique combination of control features.
duration of the RESET pulse is determined by C
according to the following equation:
DELAY
Watchdog and ENABLE Function
V
OUT
is controlled by the logic functions ENABLE and
4)
+ (1.0 10
t
C
DELAY
WDI(RESET)
Watchdog (Table 1).
Table 1. VOUT as a Function of ENABLE and Watchdog
RESET CIRCUIT WAVEFORMS WITH DELAYS
INDICATED
V
OUT
(V)
If an undervoltage condition exists, the voltage on the
WDI
RESET lead goes low and the delay capacitor, C
, is
DELAY
Slow
Normal
Fast
High
Low
ENABLE
discharged. RESET remains low until output is in
regulation, the voltage on C exceeds the upper
H
L
5
0
5
5
5
0
5
0
5
0
DELAY
switching threshold and the Watchdog input signal is within
its set window limits (Figures 17 and 18). The delay after the
output is in regulation is:
As long as ENABLE is high or ENABLE is low and the
Watchdog signal is normal, V will be at 5.0 V (typ). If
OUT
5)
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and the
IC goes into SLEEP mode. Only the ENABLE circuitry in
the IC remains powered up, drawing a quiescent current of
250 µA.
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
RESET lead (Figure 16) until the correct Watchdog input
signal reappears at the lead (ENABLE = HIGH).
t
+ (4.75 10
C
POR(typ)
DELAY
The RESET delay circuit is also programmed with the
external cap C
.
DELAY
The output of the reset circuit is an open collector NPN.
RESET is operational down to V = 1.0 V. Both RESET
OUT
and its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
http://onsemi.com
8
CS8140, CS8141
Batt
Batt
V
IN
ENABLE
WDI 0 V
VOUT When Watchdog is Held
High and ENABLE = HIGH
RESET
0 V
V
OUT
0 V
POR Normal Operation
WDI held High
Batt
Batt
V
IN
ENABLE
WDI 0 V
VOUT When Watchdog is Held Low
and ENABLE = HIGH
RESET
0 V
0 V
V
OUT
Normal Operation
POR
WDI held Low
Batt
Batt
V
IN
ENABLE
WDI 0 V
V
OUT When Watchdog is too Slow
and ENABLE = HIGH
RESET
0 V
0 V
V
OUT
POR Normal Operation
Slow WDI signal
Batt
Batt
V
IN
ENABLE
V
OUT When Watchdog is too Fast and
ENABLE = HIGH
WDI 0 V
RESET
0 V
0 V
V
OUT
POR Normal Operation
Fast WDI signal
Batt
Batt
V
IN
ENABLE
WDI Held High After a Normal Period
of Operation; ENABLE = LOW
WDI 0 V
RESET
0 V
0 V
V
OUT
WDI
high
POR Normal Operation
Sleep Mode POR Normal Operation
Batt
Batt
V
IN
ENABLE
WDI 0 V
WDI Held Low or is too Slow after
a Normal Period of Operation;
ENABLE = LOW
RESET
0 V
0 V
V
OUT
Normal
Operation
WDI
low
POR
Sleep Mode POR Normal Operation
Batt
Batt
V
IN
WDI Frequency Rises Above the
Upper Frequency Threshold After a
Normal Period of Operation;
ENABLE
WDI 0 V
ENABLE = LOW (for CS8140 only)
RESET
0 V
0 V
V
OUT
Normal
Operation
Normal Operation
Sleep Mode
POR
POR
Figure 16. Timing Diagrams for Watchdog and ENABLE Functions
http://onsemi.com
9
CS8140, CS8141
V
OUT
V
OUT
V
R(HI)
V
OUT
–4.5%
V
R(LO)
< 2.0 µs ≥ 2.0 µs
RESET
RESET
5.0 V
V
R(LO)
V
R(PEAK)
t
POR
t
POR
Figure 17. Power RESET and Power Down
Figure 18. Undervoltage Triggered RESET
APPLICATION NOTES
CS8140 DESIGN EXAMPLE
5
+ (1.3 10 )C
DELAY
t
t
WDI(LOWER)
The CS8140 with its unique integration of linear regulator
and control features: RESET, ENABLE and WATCHDOG,
provides a single IC solution for a microprocessor power
supply. The reset delay, reset duration and watchdog
frequency limits are all determined by a single capacitor. For
a particular microprocessor the overriding requirement is
usually the reset delay (also known as power on reset). The
capacitor is chosen to meet this requirement and the reset
duration and watchdog frequency follow.
4
+ (3.82 10 )C
WDI(UPPER)
DELAY
There is a tolerance of ±20% due to the CS8140.
With a capacitor tolerance of ±10%:
5
+ (1.3 10 ) 1.2 1.1 C
Delay
t
WDI(LOWER)
4
t
+ (3.82 10 ) 0.8 0.9 C
WDI(UPPER)
Delay
t
t
+ 141 ms (max)
+ 22.5 ms (max)
5
+ (1.3 10 ) 0.8 0.9 C
WDI(LOWER)
The reset delay is given by:
5)
WDI(UPPER)
t
+ (4.75 10
C
POR(typ)
DELAY
Assume that the reset delay must be 200 ms minimum.
From the CS8140 data sheet the reset delay has a ±37%
tolerance due to the regulator.
t
WDI(LOWER)
DELAY
4
+ (3.82 10 ) 1.2 1.1 C
DELAY
t
WDI(UPPER)
Assume the capacitor tolerance is ±10%.
t
+ 76 ms (min)
+ 41 ms (min)
WDI(LOWER)
5
t
(min) + (4.75 10 0.63) C
0.9
POR
DELAY
t
WDI(UPPER)
t
(min)
POR
C
(min) +
DELAY
The software must be written so that a watchdog signal
5
2.69 10
arrives at least every 76 ms but not faster than every 41 ms
(Figure 19).
C
(min) + 0.743 mF
DELAY
Closest standard value is 0.82 µF.
Minimum and maximum delays using 0.82 µF are 220 ms
and 586 ms.
PASS
FAIL
FAIL
The duration of the reset pulse is given by:
4)
Hz
ms
7
9
13
76
24
41
32
44
T
(typ) + (1.0 10 C
WDI(RESET)
DELAY
141 107
31 22.5
This has a tolerance of ±50% due to the IC, and ±10% due
to the capacitor.
C = 0.1 µF ±10%
The duration of the reset pulse ranges from 3.69 ms to
13.5 ms.
Figure 19. WDI Signal for CDelay = 0.82 µF using
CS8140
The watchdog signal can be expressed as a frequency or
time. From a programmers point of view, time is more useful
since they must ensure that a watchdog signal is issued
consistently several times per second.
The maximum and minimum watchdog times are given
by:
The CS8141 is identical to the CS8140 except that the
CS8141 only has a lower watchdog frequency threshold.
The designer using this part need only be concerned with
t
as shown in Figure 20.
WDI(LOWER)
http://onsemi.com
10
CS8140, CS8141
When the voltage across C1 reaches 3.95 V ( the enable
threshold), the output switches on and V
rises to 5.0 V.
, a frequency
OUT
FAIL
After a delay period determined by C
Delay
PASS
programmable reset pulse train is generated at the reset
output. The pulse train continues until the correct watchdog
signal appears at the WDI lead. C1 is now left to discharge
through the input impedance of the enable lead
(approximately 150 kΩ) and the enable signal disappears.
The output voltage remains at 5.0 V as long as the CS8140
continues to receive the correct watchdog signal.
Hz
ms
7
13
76
141
Figure 20. WDI Signal for CDelay = 0.82 µF using
CS8141
The microprocessor can power itself down by terminating
its watchdog signal. When the microprocessor finishes its
housekeeping or power down software routine, it stops
sending a watchdog signal. In response, the regulator
generates a reset signal and goes into a sleep mode where
ENERGY CONSERVATION AND SMART FEATURES
Energy conservation is another benefit of using a
regulator with integrated microprocessor control features.
Using the CS8140 or CS8141 as indicated in Figure 21, the
microprocessor can control its own power down sequence.
The momentary contact switch quickly charges C1 through
R1.
V
OUT
drops to 0 V, shutting down the microprocessor.
9.0 V
V
OUT
V
IN
CS8140/1
Switch
R
110 K
RESET
WDI
1
ENABLE
C
C
1
0.1 µF
GND
DELAY
C
2
0.1 µF
V
CC
10 µF
2.7 kΩ
Microprocessor
RESET
WATCHDOG PORT
Figure 21. Application Diagram for CS8140. The CS8140 Provides a 5.0 V Tightly Regulated
Supply and Control Function to the Microprocessor. In this Application, the Microprocessor
Controls its own Power Down Sequence (see text).
http://onsemi.com
11
CS8140, CS8141
V
OUT
Battery
Ignition
V
IN
C *
2
10 µF*
C *
1
0.1 µF
2.7 kΩ
CS8140
V
CC
(optional)
RESET
ENABLE
DELAY
RESET
WDI
WATCHDOG
PORT
0.1 µF
GND
R***
Microprocessor
*C1 is required if regulator is located far from the power source filter.
**C2 is required for stability.
***R ≤ 80 kΩ.
Figure 22. Application Diagram
STABILITY CONSIDERATIONS
Step 4: Maintain the worst case load conditions set in
step 3 and vary the input voltage until the oscillations
increase. This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Increase the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ± 20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
The output or compensation capacitor C in Figure 22
2
helps determine three main characteristics of a linear
regulator: start–up delay, load transient response and loop
stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (–25°C to –40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor C shown in Figure 22
2
should work for most applications, however it is not
necessarily the optimized solution.
To determine an acceptable value for C for a particular
2
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 23) is:
NJ
Nj
I
P
+ V
IN(max)
* V
OUT(min) OUT(max)
) V
I
(1)
D(max)
IN(max) Q
where:
V
V
I
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the
IN(max)
OUT(min)
OUT(max)
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
application, and
I is the quiescent current the regulator consumes at
Q
I
.
OUT(max)
http://onsemi.com
12
CS8140, CS8141
I
IN
I
OUT
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
SMART
REGULATOR
V
IN
V
OUT
Control
Features
HEAT SINKS
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
I
Q
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
Figure 23. Single Output Regulator With Key
Performance Parameters Labeled
determine the value of R
.
ΘJA
) R
R
QJA
+ R
QJC
) R
QCS QSA
(3)
Once the value of P
is known, the maximum
D(max)
where:
permissible value of R
can be calculated:
ΘJA
R
R
R
R
= the junction–to–case thermal resistance,
= the case–to–heatsink thermal resistance, and
= the heatsink–to–ambient thermal resistance.
ΘJC
ΘCS
ΘSA
ΘJC
150°C * T
+
A
R
(2)
QJA
P
D
The value of R
can then be compared with those in the
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
ΘJA
appears in the package section of the data sheet. Like
and R
R
, it too is a function of package type. R
ΘJA
ΘCS
ΘSA
R
ΘJA
are functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
the die temperature below 150°C.
http://onsemi.com
13
CS8140, CS8141
MARKING DIAGRAMS
2
D PAK
TO–220
SEVEN PIN
SO–24L
DIP–14
SEVEN LEAD
14
1
24
CS814x
AWLYYWW
CS814x
CS814x
AWLYWW
AWLYYWW
CS814x
AWLYWW
1
1
1
x
A
= 0 or 1
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
DEVICE ORDERING INFORMATION
Device
Package
Shipping
50 Units/Rail
50 Units/Rail
50 Units/Rail
50 Units/Rail
750 Tape & Reel
31 Units/Rail
1000 Tape & Reel
25 Units/Rail
50 Units/Rail
50 Units/Rail
50 Units/Rail
50 Units/Rail
750 Tape & Reel
31 Units/Rail
1000 Tape & Reel
25 Units/Rail
CS8140YT7
TO–220 Seven Lead, Straight
TO–220 Seven Lead, Vertical
TO–220 Seven Lead, Horizontal
CS8140YTVA7
CS8140YTHA7
CS8140YDPS7
CS8140YDPSR7
CS8140YDW24
CS8140YDWR24
CS8140YN14
2
D PAK, 7–Pin
2
D PAK, 7–PIN
SO–24L
SO–24L
DIP–14
CS8141YT7
TO–220 Seven Lead, Straight
TO–220 Seven Lead, Vertical
TO–220 Seven Lead, Horizontal
CS8141YTVA7
CS8141YTHA7
CS8141YDPS7
CS8141YDPSR7
CS8141YDW24
CS8141YDWR24
CS8141YN14
2
D PAK, 7–Pin
2
D PAK, 7–PIN
SO–24L
SO–24L
DIP–14
http://onsemi.com
14
CS8140, CS8141
PACKAGE DIMENSIONS
TO–220
SEVEN LEAD
T SUFFIX
CASE 821E–04
ISSUE C
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
Q
A
ąă2. CONTROLLING DIMENSION: INCH.
ąă3. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.003 (0.076) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
G
B
INCHES
DIM MIN MAX
MILLIMETERS
D
MIN
15.24
9.80
4.32
0.71
1.15
2.24
0.46
26.11
9.02
5
MAX
15.49
10.23
4.56
L
A
B
C
D
G
H
J
0.600
0.386
0.170
0.028
0.045
0.088
0.018
1.028
0.355
5
0.610
0.403
0.180
0.037
0.055
0.102
0.026
1.042
0.365
U
0.94
1.39
K
2.59
0.66
OPTIONAL
CHAMFER
K
L
26.47
9.27
M
M
Q
U
V
NOM
NOM
_
_
M
0.142
0.490
0.045
0.148
0.501
0.055
3.61
12.45
1.15
3.75
12.72
1.39
C
H
SEATING
PLANE
M
V
M
J
TO–220
SEVEN LEAD
TVA SUFFIX
CASE 821J–02
ISSUE A
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–T–
ąă2. CONTROLLING DIMENSION: INCH.
ąă3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
C
B
–Q–
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.22
9.77
MAX
14.99
10.54
4.82
A
B
C
D
E
F
0.560
0.385
0.160
0.023
0.045
0.540
0.590
0.415
0.190
0.037
0.055
0.555
W
4.06
0.58
A
0.94
1.40
U
1.14
13.72
H
F
14.10
L
G
H
J
0.050 BSC
1.27 BSC
0.570
0.014
0.785
0.322
0.073
0.090
0.146
0.289
0.164
0.460
0.595
0.022
0.800
0.337
0.088
0.115
0.156
0.304
0.179
0.475
14.48
0.36
19.94
8.18
1.85
2.28
3.70
7.34
4.17
11.68
15.11
0.56
20.32
8.56
2.24
2.91
3.95
7.72
4.55
12.07
K
K
L
M
M
N
Q
R
S
U
W
N
S
D
7 PL
3 °
3 °
M
M
T Q
0.356 (0.014)
G
R
J
http://onsemi.com
15
CS8140, CS8141
TO–220
SEVEN LEAD
THA SUFFIX
CASE 821H–02
ISSUE A
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–T–
ąă2. CONTROLLING DIMENSION: INCH.
ąă3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
1. LEADS MAINTAIN A RIGHT ANGLE WITH
RESPECT TO THE PACKAGE BODY TO WITH
$0.020".
C
B
E
–Q–
W
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.22
9.77
MAX
14.99
10.54
4.82
A
A
B
C
D
E
F
0.560
0.385
0.160
0.023
0.045
0.568
0.590
0.415
0.190
0.037
0.055
0.583
U
F
4.06
0.58
L
K
0.94
1.40
1.14
14.43
14.81
G
J
0.050 BSC
1.27 BSC
M
0.015
0.728
0.322
0.101
0.090
0.146
0.150
0.460
0.022
0.743
0.337
0.116
0.115
0.156
0.200
0.475
0.38
18.49
8.18
0.56
18.87
8.56
K
L
M
N
Q
S
U
W
2.57
2.28
2.95
2.91
3.70
3.81
3.95
5.08
D
7 PL
J
N
11.68
12.07
M
M
T Q
0.356 (0.014)
G
3 °
3 °
S
D2PAK
7–PIN
DPS SUFFIX
CASE 936H–01
ISSUE O
SEATING
PLANE
–T–
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS
B AND M.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAX.
B
U
C
M
E
8
V
INCHES
DIM MIN MAX
MILLIMETERS
MIN
8.28
10.05
4.31
0.66
1.14
1.41
MAX
8.53
10.31
4.57
0.91
1.40
1.98
A
A
B
C
D
E
F
0.326
0.396
0.170
0.026
0.045
0.058
0.336
0.406
0.180
0.036
0.055
0.078
1 2 3 4 5 6 7
K
F
G
H
J
0.050 BSC
1.27 BSC
0.100
0.110
0.025
0.214
0.066
0.004
2.54
0.46
5.18
1.40
0.00
2.79
0.64
5.44
1.68
0.10
0.018
0.204
0.055
0.000
G
K
M
N
U
V
H
D
7 PL
J
0.256 REF
0.305 REF
6.50 REF
7.75 REF
M
M
T B
0.13 (0.005)
N
http://onsemi.com
16
CS8140, CS8141
SO–24L
DW SUFFIX
CASE 751E–04
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
24
13
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B– 12X P
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
B
0.010 (0.25)
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
MIN
0.601
M
S
S
0.010 (0.25)
T A
B
DIM MIN
MAX
MAX
0.612
0.299
0.104
0.019
0.035
A
B
C
D
F
15.25
7.40
2.35
0.35
0.41
15.54
7.60 0.292
2.65 0.093
0.49 0.014
0.90 0.016
F
R X 45
_
G
J
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32 0.009
0.29 0.005
0.013
0.011
8
C
K
K
M
P
R
–T–
SEATING
PLANE
8
10.55
0
0.395
_
_
_
_
M
10.05
0.25
0.415
0.029
0.75 0.010
22X G
DIP–14
N SUFFIX
CASE 646–04
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
14
1
8
7
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
MILLIMETERS
A
MIN
18.16
6.10
4.06
0.38
1.02
MAX
18.80
6.60
4.57
0.51
1.52
A
B
C
D
F
0.715
0.240
0.160
0.015
0.040
0.740
0.260
0.180
0.020
0.060
F
L
N
C
G
H
J
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
---
0.072
0.012
0.135
0.310
10
1.32
0.20
2.92
7.37
---
1.83
0.30
3.43
7.87
10
–T–
SEATING
PLANE
K
L
J
K
M
N
_
_
0.020
0.040
0.51
1.02
D 14 PL
H
G
M
M
0.13 (0.005)
http://onsemi.com
17
CS8140, CS8141
Notes
http://onsemi.com
18
CS8140, CS8141
Notes
http://onsemi.com
19
CS8140, CS8141
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
CS8140/D
相关型号：
©2020 ICPDF网 联系我们和版权申明