CS8141YT7 [CHERRY]
5V, 500mA Linear Regulator with ENABLE, , and Watchdog RESET; 5V ， 500mA线性稳压器具有使能，以及看门狗复位
| 型号： | CS8141YT7 |
| 厂家： | 
CHERRY SEMICONDUCTOR CORPORATION |
| 描述： | 5V, 500mA Linear Regulator with ENABLE, , and Watchdog RESET |
| 文件： | 总12页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8140/1
5V, 500mA Linear Regulator
with
, and Watchdog
Features
RESET
ENABLE,
Description
The CS8140 is a 5V Watchdog
of three conditions: the watchdog sig-
nal moves outside of its preset limits;
the output voltage drops out of regula-
tion by more than 4.5%; or the IC is in
5V ± 4%, 500mA Output
■
Regulator with protection circuitry and
three logic control functions that allow
a microprocessor to control its own
power supply. The CS8140 is designed
for use in automotive, switch mode
power supply post regulator, and bat-
tery powered systems.
Voltage
µP Compatible Control
Functions
■
RESET
its power up sequence. The
sig-
Watchdog
nal is independent of VIN and reliable
down to VOUT = 1V.
RESET
ENABLE
In conjunction with the Watchdog, the
ENABLE function controls the regula-
torÕs power consumption. The CS8140Õs
output stage and its attendant circuitry
are enabled by setting the ENABLE
lead high. The regulator goes into sleep
mode (IOUT = 250µA) when the
ENABLE lead goes low and the watch-
dog signal moves outside its preset
window limits. This unique combina-
tion of control functions in the CS8140
gives the microprocessor control over
its own power down sequence: i.e. it
gives the microprocessor the flexibility
to perform housekeeping functions
before it powers down.
Low Dropout Voltage
(1.25V @ 500mA)
■
■
Basic regulator performance character-
istics include a low noise, low drift, 5V
± 4% precision output voltage with low
dropout voltage (1.25V @ IOUT = 500mA)
and low quiescent current (7mA @ IOUT
= 500mA). On board short circuit, ther-
mal, and overvoltage protection make it
possible to use this regulator in particu-
larly harsh operating environments.
Low Quiescent Current
(7mA @ 500mA)
Low Noise, Low Drift
■
■
Low Current SLEEP Mode
(IQ = 250µA)
Fault Protection
Thermal Shutdown
Short Circuit
■
The Watchdog logic function monitors
an input signal (WDI) from the micro-
processor or other signal source. When
the signal frequency moves outside
externally programmable window lim-
signal is generated
). An external capacitor
(CDELAY) programs the watchdog win-
dow frequency limits as well as the
60V Peak Transient
Voltage
Package Options
24 Lead SOIC Wide
RESET
RESET
its, a
(
The CS8141 has the same features as the
CS8140, except that the CS8141 only
responds to input signals (WDI) which
are below the preset watchdog frequen-
cy threshold.
1
NC
Delay
WDI
RESET
ENABLE
RESET
power on reset (POR) and
delay.
NC
V
OUT
V
IN
RESET
The
function is activated by any
Sense
NC
Gnd
NC
NC
NC
NC
NC
NC
NC
Block Diagram
NC
NC
V
IN
NC
NC
Overvoltage
Overtemperature
Reference
& Bias
NC
Gnd
Regulation
14 Lead PDIP
7 Lead TO-220
ENABLE
WDI
Control Logic
ENABLE
RESET
Tab (Gnd)
1
Delay
RESET
V
OUT
WDI
ENABLE
Delay
Short Circuit
Undervoltage
*NOTE: shorted together
on 7 Lead TO-220
1
2
3
4
5
6
7
VIN
*
V
V
IN
OUT
ENABLE
RESET
Gnd
Delay
WDI
Sense
Sense
Gnd
NC
NC
NC
Gnd
Watchdog
NC
NC
NC
RESET
VOUT
Delay
1
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 2/23/99
1
A
¨
Company
Absolute Maximum Ratings
Input Voltage
Operating Range.................................................................................................................................................-0.5 to +26V
Peak Transient Voltage (46V Load Dump @ 14V VBAT)..............................................................................................60V
Electrostatic Discharge
(Human Body Model)...............................................................................................................................................4kV
WDI Input Signal Range...............................................................................................................................................-0.3 to +7V
Internal Power Dissipation ..............................................................................................................................Internally limited
Junction Temperature Range (TJ).......................................................................................................................-40¡C to +150¡C
Storage Temperature Range................................................................................................................................-65¡C to +150¡C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak
ENABLE .......................................................................................................................................................................-0.3V to VIN
Electrical Characteristics: 7V ² VIN ² 26V, 5mA ² IOUT ² 500mA, -40ûC ² TJ ² +150ûC, -40ûC ² TA ² 125ûC
unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
■ Output Stage (VOUT
)
Output Voltage, VOUT
7V ² VIN ² 26V
4.8
5.0
5.2
V
5mA < IOUT < 500mA
Dropout Voltage (VIN - VOUT
)
IOUT = 500mA
1.25
5
1.50
25
V
Line Regulation
IOUT = 50mA,
mV
7V ² VIN ² 26V
Load Regulation
VIN = 14V,
50mA ² IOUT ² 500mA
5
80
mV
m½
Output Impedance, ROUT
500mA DC and 10mA AC ,
200
100Hz ² f ² 10kHz
Quiescent Current, (IQ)
Active Mode
0 ² IOUT ² 500mA, 7V ² VIN ² 26V
IOUT = 0mA, VIN = 13V, ENABLE = 0V
7.00
0.25
15.00
0.50
mA
mA
Sleep Mode
Ripple Rejection
7 ² VIN ² 17V, IOUT = 250mA,
60
75
dB
f = 120Hz
Current Limit
700
150
30
1200
180
34
2000
38
mA
¡C
V
Thermal Shutdown
Overvoltage Shutdown
VOUT < 1V
■ ENABLE
Threshold
HIGH
LOW
VOUT ³ 0.5V, (VOUT(ON)
VOUT < 0.5V, (VOUT(OFF)
)
)
4.05
3.95
4.50
V
V
3.50
Threshold Hysteresis
(HIGH - LOW)
100
mV
2
Electrical Characteristics: continued
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
■
RESET
Threshold
HIGH VR(HI)
VOUT increasing
4.65
4.50
150
4.90
4.70
200
VOUT - 0.05
V
LOW VR(LOW)
VOUT decreasing
(HIGH - LOW)
VOUT ³ VR(HI)
4.90
250
25
V
Threshold Hysteresis(VRH
)
mV
µA
Reset Output Leakage
= HIGH
RESET
Output Voltage
Low(VL(LOW)
)
1V ² VOUT ² VR(LOW)
Rp = 2.7k½*
VOUT, Power up, Power down
0.1
0.6
0.4
1.0
V
V
Low (VRpeak
)
Delay Times
tPOR
CDELAY = 0.1µF
30.0
0.5
47.5
1.0
65.0
1.5
ms
ms
tWDI(
)
RESET
■ Watchdog
Input Voltage
HIGH
2.0
V
V
LOW
0.8
10
Input Current
WDI ² VOUT
DELAY = 0.1µF
0
µA
Threshold Frequency
C
fWDI
fWDI(UPPER)**
64
218
77
262
96
326
Hz
Hz
LOWER
* R is connected to
and V
.
RESET
P
OUT
** CS8140 only
To observe safe operating junction temperature, low duty cycle pulse testing is used on tests where applicable.
Package Lead Description
Package Lead #
Lead Symbol
Function
7 Lead
TO-220
24 Lead *
SOIC Wide
14 Lead
PDIP
1
21
12
VIN
Supply voltage to IC, usually direct from the battery.
2
23
13
ENABLE
CMOS compatible logical input. VOUT is disabled when
ENABLE is LOW and WDI is beyond its preset limits.
3
24
14
CMOS compatible output lead.
VOUT drops below 4.5% of its typical value for more than
2µs or WDI signal falls outside itÕs window limits.
goes low whenever
RESET
RESET
4
5
6
12, 20
11
1
Gnd
Ground connection.
2
3
Delay
WDI
Timing capacitor for Watchdog and
functions.
RESET
2
CMOS compatible input lead. The Watchdog function mon-
itors the falling edge of the incoming digital pulse train. The
signal is usually generated by the system microprocessor.
7
4
5
3
4
VOUT
Regulated output voltage, 5V (typ).
N/A
Sense
Kelvin connection which allows remote sensing of output
voltage for improved regulation.
1,6-11,13-19,22
5-10
NC
No connection.
* The CS8141 uses a fused lead package. Leads 6-8 and 17-19 are fused together through the lead frame. These leads are
electrically connected to IC ground and should be connected to system ground for a good thermal connection.
3
Typical Performance Characteristics
VOUT vs. VIN over RLOAD; T = 25ûC
VOUT vs. VIN over Temperature; RLOAD = 25½
5.5
5.5
VENABLE = VIN
V
= V
IN
ENABLE
5.0
4.5
4.0
3.5
3.0
2.5
5.0
4.5
4.0
3.5
3.0
2.5
Rload = NO LOAD
TEMP = 125°C
Rload = 6.67W
TEMP = -40 °C
TEMP = 25°C
Rload = 10W
2.0
1.5
1.0
0.5
0.0
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
(V)
V
IN
(V)
IN
Dropout Voltage vs. Output Current over Temperature
Load Regulation vs. Output Current over Temperature
3.5
1800
1600
1400
-40°C
0
-3.5
25°C
-7.0
1200
-10.5
-14.0
-17.5
-40°C
1000
125°C
VIN = 14V
25°C
800
-21.0
-24.5
-28.0
-31.5
-35.0
600
400
125°C
200
0
0
100
200
300
400
500
600
700
800
0
100
200
300
400
500
600
700
800
IOUT (mA)
IOUT (mA)
Line Regulation vs. Output Current over Temperature
Quiescent Current vs. Output Current over Temperature
10
18
V
= 14V
IN
V
IN = 14V
16
14
9
8
-40°C
12
10
8
-40°C
7
6
6
4
25°C
125°C
2
0
25°C
125°C
-2
-4
-6
5
4
0
100
200
300
400
500
600
700
800
0
100
200
300
400
500
600
700
800
I
(mA)
OUT
I
(mA)
OUT
4
Typical Performance Characteristics: continued
Quiescent Current vs. VIN over RLOAD; T = 25¡C
Quiescent Current vs. VIN over Temperature; RLOAD = 25½
20
20
VENABLE = VIN
V
= V
IN
ENABLE
18
16
14
18
16
14
TEMP = 25°C
12
10
12
10
Rload = 6.67
Rload = 25
TEMP =- 40°C
8
6
8
6
Rload = NO LOAD
TEMP = 125°C
4
4
2
0
2
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
IN
(V)
V
IN
(V)
Watchdog Frequency Thresholds vs. Temperature
Watchdog Frequency Threshold vs CDELAY
7
10
300
280
6
5
4
3
2
10
10
10
10
10
260
Upper Threshold
240
220
200
180
160
140
120
C
= 0.1mF
DELAY
Upper Threshold
Lower Threshold
Lower Threshold
100
80
1
0
10
10
60
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
1
2
3
4
5
6
7
T
J
(°C)
10
10
10
10
10
10
10
CAPACITANCE (pF)
Ripple Rejection vs Frequency
RESET Output Voltage vs Output Current
90
2000
1800
1600
1400
1200
1000
800
I
O
=250mA
80
70
60
50
V
IN
= 5V
C
= 10mF, ESR=1&0.1mF, ESR=0
O
40
30
20
10
600
C
= 10mF,ESR=1W
O
400
200
0
C
= 10mF, ESR=10W
O
0
10
0
1
2
3
4
5
6
7
8
1
5
10
15
20
25
30
35
40
10
10
10
10
10
10
10
10
RESET OUTPUT CURRENT (mA)
FREQUENCY (Hz)
5
Definition of Terms
Dropout Voltage
Load Regulation
The change in output voltage for a change in load current
at constant chip temperature.
The input-output voltage differential at which the circuit
ceases to regulate against further reduction in input volt-
age. Measured when the output voltage has dropped
100mV from the nominal value obtained at 14V input,
dropout voltage is dependent upon load current and junc-
tion temperature.
Quiescent Current
The part of the positive input current that does not con-
tribute to the positive load current. The regulator ground
lead current.
Input Voltage
Ripple Rejection
The ratio of the peak-to-peak input ripple voltage to the
peak-to-peak output ripple voltage.
The DC voltage applied to the input terminals with respect
to ground.
Line Regulation
Current Limit
Peak current that can be delivered to the output.
The change in output voltage for a change in the input
voltage. The measurement is made under conditions of
low dissipation or by using pulse techniques such that the
average chip temperature is not significantly affected.
Circuit Description
circuitry insures that the output current never exceeds a
preset limit.
Voltage Reference and Output Circuitry
Precision Voltage Reference
The regulated output voltage depends on the precision
band gap voltage reference in the IC. By adding an error
amplifier into the feedback loop , the output voltage is main-
tained within ±4% over temperature and supply variation.
> 30V
V
IN
V
OUT
Output Stage
The composite PNP-NPN output structure (Figure1) pro-
vides 500mA (min) of output current while maintaining a
low drop out voltage (1.25V) and drawing little quiescent
current (7mA).
I
O
V
IN
Load
Dump
Short
Circuit
Thermal
Shutdown
Figure 2: Typical Circuit Waveforms for Output Stage Protection.
Should the junction temperature of the power device
exceed 180ûC (typ), the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
V
OUT
Figure 1: Composite Output Stage of the CS8140/1
Regulator Control Functions
The NPN pass device prevents deep saturation of the out-
put stage which in turn improves the ICÕs efficiency by
preventing excess current from being used and dissipated
by the IC.
The CS8140 differs from all other linear regulators in its
unique combination of control features.
Watchdog and ENABLE Functions
V
OUT is controlled by the logic functions ENABLE and
Output Stage Protection
Watchdog (Table 1).
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (Figure 2).
VOUT (V)
WDI
If the input voltage rises above 30V (e.g. load dump), the
output shuts down. This response protects the internal cir-
cuitry and enables the IC to survive unexpected voltage
transients.
ENABLE Slow
Normal
Fast
High
Low
H
L
5
0
5
5
5
0
5
0
5
0
Using an emitter sense scheme, the amount of current
through the NPN pass transistor is monitored. Feedback
Table 1: VOUT as a Function of ENABLE and Watchdog
6
Figure 3: Timing Diagrams for Watchdog and ENABLE Functions
3a: VOUT when Watchdog is held high and ENABLE = HIGH.
Battery
Battery
VIN
ENABLE
0V
0V
0V
WDI
RESET
VOUT
POR
Normal Operation
WDI held High
3b: VOUT when Watchdog is held low and ENABLE = HIGH.
Battery
Battery
VIN
ENABLE
WDI
0V
0V
RESET
VOUT
0V
POR
Normal Operation
WDI held Low
3c: VOUT when Watchdog is too slow and ENABLE = HIGH.
Battery
Battery
VIN
ENABLE
0V
WDI
0V
RESET
VOUT
0V
POR
Normal Operation
Slow WDI signal
3d: VOUT when Watchdog is too fast and ENABLE = HIGH.
Battery
Battery
VIN
ENABLE
0V
WDI
0V
RESET
VOUT
0V
POR
Normal Operation
Fast WDI signal
3e: WDI held high after a normal period of operation; ENABLE = LOW.
Battery
Battery
VIN
ENABLE
WDI
0V
0V
0V
RESET
VOUT
POR
Normal Operation
WDI
high
Sleep Mode
POR
Normal Operation
3f: WDI held low or is too slow after a normal period of operation; ENABLE = LOW.
Battery
Battery
VIN
ENABLE
0V
0V
0V
WDI
RESET
VOUT
POR
Normal Operation WDI
low
Sleep Mode
POR
Normal Operation
3g: WDI frequency rises above the upper frequency threshold after a normal period of operation; ENABLE = LOW
(for the CS8140 only).
Battery
Battery
VIN
ENABLE
0V
WDI
RESET
VOUT
0V
0V
POR
Normal Operation
Sleep Mode
POR
Normal Operation
7
Circuit Description: continued
As long as ENABLE is high or ENABLE is low and the
RESET Circuit Waveforms with Delays Indicated
Watchdog signal is normal, VOUT will be at 5V (typ). If
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and
the IC goes into SLEEP mode. Only the ENABLE circuitry
in the IC remains powered up, drawing a quiescent cur-
rent of 250µA.
VOUT
VR
HI
VR
LO
RESET
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
VR
LO
VR
PEAK
lead (Figure 3) until the correct Watchdog input
RESET
tPOR
signal reappears at the lead (ENABLE = HIGH).
The lower and upper window threshold limits of the
watchdog function are set by the value of CDELAY. The lim-
its are determined according to the following equations for
the CS8140:
4a: Power RESET and Power Down
VOUT
tWDILOWER = (1.3 x 105)CDELAY or
VOUT -4.5%
(a)
³2ms
<2mS
fWDI(LOWER) = (7.69 x 10-6)CDELAY
-1
(b)
tWDI(UPPER) = (3.82 x 10-4)CDELAY or
fWDI(UPPER) = (2.62 x 10-5)CDELAY
-1
RESET
5V
For the CS8141 the lower limit is determined by the equa-
tions in (a) above.
tPOR
The capacitor CDELAY also determines the frequency of the
signal and the POWER-ON-
(POR) delay
RESET
period.
RESET
4b: Undervoltage Triggered RESET
If an undervoltage condition exists, the voltage on the
RESET
RESET
Function
lead goes low and the delay capacitor, CDELAY, is
discharged. remains low until output is in regula-
The
function is activated when the Watchdog sig-
RESET
RESET
nal is outside of its preset window (Figure 3), when the
regulator is in its power up state (Figure 4a) or when VOUT
drops below VOUT -4.5% for more than 2µs (Figure 4b.)
tion, the voltage on CDELAY exceeds the upper switching
threshold and the Watchdog input signal is within its set
window limits (Figure 4). The delay after the output is in
regulation is:
If the Watchdog signal falls outside of the preset voltage
and frequency window, a frequency programmable pulse
tPOR(typ) = (4.75 x 105) CDELAY
train is generated at the
lead (Figure 3) until the
RESET
correct Watchdog input signal reappears at the lead. The
duration of the pulse is determined by C
The
delay circuit is also programmed with the
RESET
external cap CDELAY
RESET
according to the following equation:
DELAY
.
The output of the reset circuit is an open collector NPN.
is operational down to V = 1V. Both and
RESET
RESET
tWDI(
) = (1 x104)CDELAY
OUT
RESET
its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
Application Notes
Assume that the reset delay must be 200ms minimum.
CS8140 Design Example
From the CS8140 data sheet the reset delay has a ±37% tol-
erance due to the regulator.
The CS8140 with its unique integration of linear regulator
and control features: , ENABLE and WATCHDOG,
RESET
Assume the capacitor tolerance is ±10%.
provides a single IC solution for a microprocessor power
supply. The reset delay, reset duration and watchdog fre-
quency limits are all determined by a single capacitor. For
a particular microprocessor the overriding requirement is
usually the reset delay (also known as power on reset).
The capacitor is chosen to meet this requirement and the
reset duration and watchdog frequency follow.
tPOR (min) = (4.75 x 105 x 0.63) x CDELAY x 0.9
tPOR (min)
CDELAY (min) =
2.69 x 105
CDELAY = (min) = 0.743 µF
Closest standard value is 0.82µF.
The reset delay is given by:
Minimum and maximum delays using 0.82µF are 220ms
and 586ms.
tPOR(typ) = (4.75 x 105)CDELAY
8
Application Notes
The duration of the reset pulse is given by:
TWDI(RESET)(typ) = (1 x 104) x CDELAY
Energy Conservation and Smart Features
Energy conservation is another benefit of using a regulator
with integrated microprocessor control features. Using the
CS8140 or CS8141 as indicated in Figure 8, the micropro-
cessor can control its own power down sequence. The
momentary contact switch quickly charges C1 through R1.
This has a tolerance of ±50% due to the IC, and ±10% due
to the capacitor.
The duration of the reset pulse ranges from 3.69ms to
13.5ms.
When the voltage across C1 reaches 3.95V ( the enable
threshold), the output switches on and VOUT rises to 5V.
After a delay period determined by CDelay, a frequency
programmable reset pulse train is generated at the reset
output. The pulse train continues until the correct watch-
dog signal appears at the WDI lead. C1 is now left to dis-
charge through the input impedance of the enable lead
(approximately 150k½) and the enable signal disappears.
The output voltage remains at 5V as long as the CS8140
continues to receive the correct watchdog signal.
The watchdog signal can be expressed as a frequency or
time. From a programmers point of view, time is more
useful since they must ensure that a watchdog signal is
issued consistently several times per second.
The maximum and minimum watchdog times are given
by:
tWDI(LOWER) = (1.3 x 105)CDELAY
tWDI(UPPER) = (3.82 x 104)CDELAY
There is a tolerance of ±20% due to the CS8140.
The microprocessor can power itself down by terminating
its watchdog signal. When the microprocessor finishes its
housekeeping or power down software routine, it stops
sending a watchdog signal. In response, the regulator
generates a reset signal and goes into a sleep mode where
VOUT drops to 0V, shutting down the microprocessor.
With a capacitor tolerance of ±10%:
tWDI(LOWER) = (1.3 x 105) x 1.20 x 1.1 x CDELAY
tWDI(UPPER) = (3.82 x 104) x 0.8 x 0.9 x CDELAY
tWDI(LOWER) = 141ms(max)
tWDI(UPPER) = 22.5ms (max)
Stability Considerations
The output or compensation capacitor C2 in Figure 7 helps
determine three main characteristics of a linear regulator:
start-up delay, load transient response and loop stability.
tWDI(LOWER) = (1.3 x 105) x 0.8 x 0.9 x CDELAY
tWDI(UPPER) = (3.82 x 104) x 1.2 x 1.1 x CDELAY
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instabili-
ty. The aluminum electrolytic capacitor is the least expen-
sive solution, but, if the circuit operates at low tempera-
tures (-25¡C to -40¡C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufac-
turers data sheet usually provide this information.
tWDI(LOWER) = 76ms(min)
tWDI(UPPER) = 41ms (min)
The software must be written so that a watchdog signal
arrives at least every 76ms but not faster than every 41ms
(Figure 5).
PASS
FAIL
FAIL
The value for the output capacitor C2 in Figure 7 should
work for most applications, however it is not necessarily
the optimized solution.
7
9
24
41
32
31
44
13
76
Hz
ms
To determine an acceptable value for C2 for a particular
application, start with a tantalum capacitor of the recom-
mended value and work towards a less expensive alterna-
tive part.
141
107
22.5
C = 0.1mF ± 10%
Figure 5: WDI signal for CDelay = 0.82µF using CS8140.
Step 1: Place the completed circuit with a tantalum capac-
itor of the recommended value in an environmental cham-
ber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by the
longer leads is negligible.
The CS8141 is identical to the CS8140 except that the
CS8141 only has a lower watchdog frequency threshold.
The designer using this part need only be concerned with
tWDI(LOWER) as shown in Figure 6.
FAIL
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscil-
lations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
PASS
7
13
76
Hz
ms
141
Figure 6: WDI signal for CDelay = 0.82µF using CS8141.
9
Application Diagrams
5V
V
OUT
Battery
Ignition
V
IN
C **
2
C *
1
10mF*
0.1mF
CS8140
V
cc
2.7kW
(optional)
ENABLE
DELAY
RESET
WDI
RESET
WATCHDOG
PORT
0.1mF
Gnd
R***
MICROPROCESSOR
*C1 is required if regulator is located far from the power source filter.
**C2 required for stability
***R ² 80k½
Figure 7. Application Diagram
9V
V
OUT
V
IN
CS8140/1
Switch
R
110K
1
RESET
WDI
ENABLE
C
0.1mF
1
C
Gnd
Delay
C
0.1mF
2
V
cc
10mF
2.7k
MICROPROCESSOR
RESET
WATCHDOG PORT
Figure 8. Applications diagram for CS8140. The CS8140 provides a 5V tightly regulated supply and control function to the microprocessor. In this
application, the microprocessor controls its own power down sequence (see text).
10
Application Notes: continued
Step 3: Increase the ESR of the capacitor from zero using
I
IN
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
I
OUT
V
IN
Smart
Regulator
V
OUT
Control
Features
}
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage condi-
tions.
I
Q
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger stan-
dard capacitor value.
Figure 9: Single output regulator with key performance parameters
labeled.
Once the value of PD(max) is known, the maximum permis-
sible value of RQJA can be calculated:
150¡C - TA
(2)
RQJA
=
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
PD
The value of RQJA can then be compared with those in
the package section of the data sheet. Those packages
with RQJA's less than the calculated value in equation 2 will
keep the die temperature below 150¡C.
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regula-
tor performance. Most good quality aluminum electrolytic
capacitors have a tolerance of +/- 20% so the minimum
value found should be increased by at least 50% to allow
for this tolerance plus the variation which will occur at
low temperatures. The ESR of the capacitor should be less
than 50% of the maximum allowable ESR found in step 3
above.
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed
Calculating Power Dissipation
in a Single Output Linear Regulator
to determine the value of RQJA
:
R
QJA = RQJC + RQCS + RQSA
(3)
The maximum power dissipation for a single output regu-
lator (Figure 9) is:
where:
R
R
R
QJC = the junctionÐtoÐcase thermal resistance,
QCS = the caseÐtoÐheatsink thermal resistance, and
QSA = the heatsinkÐtoÐambient thermal resistance.
PD(max) = VIN(max) - VOUT(min)
I
OUT(max) + VIN(max) Q
I
(1)
{
}
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
R
R
QJC appears in the package section of the data sheet. Like
QJA, it too is a function of package type. RQCS and RQSA
IOUT(max) is the maximum output current for the applica-
tion, and
are functions of the package type, heatsink and the inter-
face between them. These values appear in heatsink data
sheets of heatsink manufacturers.
IQ is the quiescent current the regulator consumes at
IOUT(max)
.
11
Package Specification
Thermal
PACKAGE DIMENSIONS IN mm (INCHES)
D
PACKAGE THERMAL DATA
7 L 24L 24L (Fused) 14 L
Data
TO-220 CS8140
CS8141
PDIP
Lead Count
Metric
English
Min
RQJC typ
1.6
16
9
48
ûC/W
ûC/W
Max Min Max
RQJA typ
50
80
55
85
24 Lead SOIC Wide
14 Lead PDIP
15.60
19.69
15.20 .614 .598
18.67 .775 .735
7 Lead TO-220 (T) Straight
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
1.40 (.055)
1.14 (.045)
4.83 (.190)
4.06 (.160)
10.54 (.415)
9.78 (.385)
2.87 (.113)
2.62 (.103)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
14.99 (.590)
14.22 (.560)
6.55 (.258)
5.94 (.234)
3.96 (.156)
3.71 (.146)
2.49 (.098)
2.24 (.088)
2.65 (.104)
2.35 (.093)
0.32 (.013)
0.23 (.009)
1.27 (.050)
0.40 (.016)
14.22 (.560)
13.72 (.540)
0.30 (.012)
0.10 (.004)
D
REF: JEDEC MS-013
Plastic DIP (N); 300 mil wide
0.94 (.037)
0.58 (.023)
0.56 (.022)
0.36 (.014)
1.40 (.055)
1.14 (.045)
0.64 (.025)
0.38 (.015)
7.11 (.280)
6.10 (.240)
7.75 (.305)
7.49 (.295)
2.92 (.115)
2.29 (.090)
1.77 (.070)
1.14 (.045)
8.26 (.325)
7.62 (.300)
2.54 (.100) BSC
7 Lead TO-220 (TVA) Vertical
3.68 (.145)
2.92 (.115)
1.40 (.055)
1.14 (.045)
10.54 (.415)
9.78 (.385)
3.96 (.156)
3.71 (.146)
2.87 (.113)
2.62 (.103)
0.39 (.015)
MIN.
.356 (.014)
.203 (.008)
14.99 (.590)
14.22 (.560)
6.55 (.258)
5.94 (.234)
.558 (.022)
.356 (.014)
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
REF: JEDEC MS-001
D
11.86 (.467)
All specs are the same.
2.03 (.080)
Ordering Information
2.92 (.115)
2.29 (.090)
2.92
(.115)
Part Number
CS8140YT7
Description
8.26
(.325)
7L TO-220 Straight
7L TO-220 Vertical
7L TO-220 Horizontal
24L SO
CS8140YTVA7
CS8140YTHA7
CS8140YDW24
CS8140YDWR24
CS8140YN14
4.34
0.56 (.022)
0.36 (.014)
1.27
(.050)
TYP
(.171)
0.81
(.030)
7.52 (.296)
7.62 (.300)
24L SO (tape & reel)
14L PDIP
CS8141YT7
7L TO-220 Straight
7L TO-220 Vertical
7L TO-220 Horizontal
24L SO (internally fused leads)
24L SO (internally fused leads)
(tape & reel)
4.83 (.190)
4.06 (.160)
CS8141YTVA7
CS8141YTHA7
CS8141YDWF24
CS8141YDWFR24
Ch erry Sem icon du ctor Corporation reserves th e
righ t to m ake ch an ges to th e specification s with ou t
n otice. Please con tact Ch erry Sem icon du ctor
Corporation for th e latest available in form ation .
CS8141YN14
14L PDIP
Rev. 2/23/99
© 1999 Cherry Semiconductor Corporation
12
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