CS8147YTVA5 [ONSEMI]
10 V/5.0 V Low Dropout Dual Regulator with ENABLE; 10 V / 5.0 V低压降稳压器双用ENABLE
| 型号： | CS8147YTVA5 |
| 厂家： | 
ONSEMI |
| 描述： | 10 V/5.0 V Low Dropout Dual Regulator with ENABLE |
| 文件： | 总12页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8147
10 V/5.0 V Low Dropout
Dual Regulator with ENABLE
The CS8147 is a 10 V/5.0 V dual output linear regulator. The 10V
±5.0% output sources 500 mA and the 5.0 V ±3% output sources 70
mA. The secondary output is inherently stable and does not require an
external capacitor.
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The on board ENABLE function controls the regulator’s two
outputs. When ENABLE is high, the regulator is placed in SLEEP
mode. Both outputs are disabled and the regulator draws only 70 µA of
quiescent current.
The regulator is protected against overvoltage conditions. Both
outputs are protected against short circuit and thermal runaway
conditions.
TO–220
FIVE LEAD
T SUFFIX
CASE 314D
1
5
The CS8147 is packaged in a 5 lead TO–220 with copper tab. The
copper tab can be connected to a heat sink if necessary.
TO–220
FIVE LEAD
TVA SUFFIX
CASE 314K
1
Features
• Two Regulated Outputs
– 10 V ±5.0%; 500 mA
– 5.0 V ±3.0%; 70 mA
• 70 µA SLEEP Mode Current
• Inherently Stable Secondary Output (No Output Capacitor Required)
• Fault Protection
TO–220
FIVE LEAD
THA SUFFIX
CASE 314A
1
5
– Overvoltage Shutdown
– Reverse Battery
PIN CONNECTIONS AND
MARKING DIAGRAM
– 60 V Peak Transient
– –50 V Reverse Transient
– Short Circuit
– Thermal Shutdown
Tab = GND
Pin 1. ENABLE
2. V
IN
CS8147
AWLYWW
3. GND
4. V
5. V
(10 V)
(5.0 V)
OUT1
OUT2
• CMOS Compatible ENABLE Input with Low (I
) Input
OUT(max)
Current
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
CS8147YT5
CS8147YTVA5
CS8147YTHA5
*Five lead.
TO–220*
50 Units/Rail
STRAIGHT
TO–220*
VERTICAL
50 Units/Rail
50 Units/Rail
TO–220*
HORIZONTAL
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
January, 2001 – Rev. 6
CS8147/D
CS8147
Primary Output
V
OUT1
V
IN
Overvoltage
Shutdown
Anti–saturation
and
Current Limit
+
–
ENABLE
–
+
Pre–Regulator
Secondary Output
Bandgap
Reference
–
+
V
OUT2
GND
Thermal
Shutdown
Current Limit
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
Input Voltage:
DC
–18 to 26
60
–50
V
V
V
Positive Peak Transient Voltage (Note 1.)
Negative Peak Transient Voltage
ESD (Human Body Model)
ENABLE Input
2.0
kV
V
–0.3 to 10
Internal Power Dissipation
Junction Temperature Range
Storage Temperature Range
Lead Temperature Soldering:
Internally Limited
–40 to +150
–65 to +150
260 peak
–
°C
°C
°C
Wave Solder (through hole styles only) (Note 2.)
1. 46 V Load Dump @ V = 14 V
IN
2. 10 second maximum.
*The maximum package power dissipation must be observed.
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2
CS8147
ELECTRICAL CHARACTERISTICS for VOUT: (V = 14 V, I
= I
= 5.0 mA, –40°C < T < 150°C,
OUT2 J
IN
OUT1
–40°C ≤ T ≤ 125°C, ENABLE = LOW; unless otherwise specified.)
A
Characteristic
Test Conditions
Min
Typ
Max
Unit
Primary Output (V
)
OUT1
Output Voltage
13 V ≤ V ≤ 26 V, I
≤ 500 mA
9.50
10.00
0.5
45
10.5
0.7
90
V
V
IN
OUT1
Dropout Voltage
Line Regulation
Load Regulation
Quiescent Current
I
= 500 mA
–
–
–
OUT1
11 V ≤ V ≤ 18 V, I
= 250 mA
mV
mV
IN
OUT1
5.0 mA ≤ I
≤ 500 mA
15
75
OUT1
I
I
≤ 1.0 mA, No Load on V
= 500 mA, No Load on V
, V = 18 V
, V = 11 V
IN
–
–
3.0
60
7.0
120
mA
mA
OUT1
OUT1
OUT2
IN
OUT2
Quiescent Current
Current Limit
ENABLE = HIGH, V
, V
OUT2
= OFF
–
0.55
–
70
0.80
50
200
–
µA
A
OUT1
–
Long Term Stability
–
–
mV/khr
V
Overvoltage Shutdown
V
OUT1
and V
32
36
40
OUT2
Secondary Output (V
Output Voltage
Dropout Voltage
Line Regulation
Load Regulation
Current Limit
)
OUT2
6.0 V ≤ V ≤ 26 V, 1.0 mA ≤ I
≤ 70 mA
4.85
5.00
1.5
4.0
10
5.15
2.5
50
50
–
V
IN
OUT2
I
≤ 70 mA
–
–
–
–
V
OUT2
11 ≤ V ≤ 18 V, I
= 70 µA
mV
mV
mA
IN
OUT
1.0 mA ≤ I
≤ 70 mA, V = 14 V
OUT2
IN
–
150
ENABLE Function (ENABLE)
Input ENABLE Threshold
V
V
–
0.8
1.40
1.40
2.50
–
V
V
OUT2(ON)
OUT1(OFF)
Input ENABLE Current
Input Voltage Range 0 to 5.0 V
–10
–
10
µA
PACKAGE PIN DESCRIPTION
PACKAGE LEAD #
5 Lead TO–220
1
LEAD SYMBOL
FUNCTION
ENABLE
CMOS compatible input lead; switches V
and V
on
OUT2
OUT1
and off. When ENABLE is low, V
and V
are active.
OUT1
OUT2
2
3
4
5
V
Supply voltage, usually direct from battery.
Ground connection.
IN
GND
V
Regulated output 10 V, 500 mA (typ).
Secondary output 5.0 V, 70 mA (typ).
OUT1
OUT2
V
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CS8147
TYPICAL PERFORMANCE CHARACTERISTICS
600
550
500
450
400
350
300
250
200
150
100
50
2.00
–40°C
1.80
1.60
1.40
1.20
25°C
125°C
25°C
125°C
1.00
0.80
0.60
0.40
0.20
0
–40°C
V
= 6.00 V
IN
0
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
0
0
0
10 20 30 40 50 60 70 80 90 100
Output Current (mA), V (5.0 V)
OUT2
Figure 2. Dropout Voltage vs.
Figure 3. Dropout Voltage vs.
Output Current (VOUT2
Output Current (VOUT1
)
)
100
90
80
70
60
50
40
30
20
10
0
7.0
6.0
25°C
125°C
5.0
4.0
–40°C
–40°C
25°C
V
IN
= 14 V
3.0
2.0
1.0
0
125°C
V
IN
= 14 V
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
10 20 30 40 50 60 70 80 90 100
Output Current (mA), V (5.0 V)
OUT2
Figure 4. Quiescent Current vs.
Figure 5. Quiescent Current vs.
Output Current (VOUT2
Output Current (VOUT1
)
)
5.02
5.01
5.00
4.99
4.98
120
110
100
90
80
70
60
50
40
30
20
10
0
125°C
V
IN
= 11 V – 26 V
25°C
–40°C
–50 –30 –10 10
30
50
70
90 110 130
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA), V (10 V)
Temp (C°)
OUT1
PART1 V = 14 V, No Load
IN
Figure 7. Line Regulation vs.
Output Current (VOUT1
Figure 6. VOUT2 vs. Temperature
)
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4
CS8147
30
26
22
18
14
10
6
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
125°C
25°C
V
IN
= 14 V
V
IN
= 14 V
25°C
–40°C
–40°C
2
125°C
–2
–6
–10
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA), V (10 V)
0
10 20 30 40 50 60 70 80 90 100
Output Current (mA), V (5.0 V)
OUT1
OUT2
Figure 8. Load Regulation vs.
Output Current (VOUT1
Figure 9. Load Regulation vs.
Output Current (VOUT2
)
)
350
300
–40°C
25°C
100.0
V10 = 500 mA Load
V5 = 70 mA Load
250
200
20.00
/div
0
150
100
50
125°C
0
–100.0
–1.000
0
9.000
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
V
1.000/div (V)
V
IN
(V)
ENABLE
Figure 10. ENABLE Input Current vs.
Input Voltage
Figure 11. Quiescent Current (ICQ) vs.
VIN Overtemperature
300
10.025
10.020
10.015
10.010
10.005
10.000
9.995
V
V
= 500 mA Load
= 100 mA Load
OUT1
OUT2
V
O
= 14 V
= 30 mA
IN
I
250
200
150
100
50
V
= 500 mA Load
OUT1
V
= No Load
OUT2
9.990
9.985
V
V
= No Load
OUT1
OUT2
9.980
= No Load
0
9.975
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
–50 –30 –10 10 30 50
70
90 110 130 150
TEMP (°C)
V
IN
(V)
Figure 12. Quiescent Current (ICQ) vs.
VIN Over RLOAD
Figure 13. VOUT1 vs. Temperature
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CS8147
DEFINITION OF TERMS
Dropout Voltage – The input–output voltage differential
Load Regulation – The change in output voltage for a
change in load current at constant chip temperature.
Long Term Stability – Output voltage stability under
accelerated life–test conditions after 1000 hours with
maximum rated voltage and junction temperature.
Output Noise Voltage – The rms AC voltage at the
output, with constant load and no input ripple, measured
over a specified frequency range.
at which the circuit ceases to regulate against further
reduction in input voltage. Measured when the output
voltage has dropped 100 mV from the nominal value
obtained at 14 V input, dropout voltage is dependent upon
load current and junction temperature.
Current Limit – Peak current that can be delivered to the
output.
Input Voltage – The DC voltage applied to the input
terminals with respect to ground.
Quiescent Current – The part of the positive input
current that does not contribute to the positive load current.
The regulator ground lead current.
Ripple Rejection – The ratio of the peak–to–peak input
ripple voltage to the peak–to–peak output ripple voltage.
Input Output Differential – The voltage difference
between the unregulated input voltage and the regulated
output voltage for which the regulator will operate.
Line Regulation – The change in output voltage for a
change in the input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that the average chip temperature is not significantly
affected.
Temperature Stability of V
– The percentage
OUT
change in output voltage for a thermal variation from room
temperature to either temperature extreme.
60 V
31 V
26 V
14V
V
IN
14 V
5.0 V
2.0 V
0.8 V
ENABLE
10 V
10 V
10 V
10 V
10 V
5.0 V
3.0 V
0 V
0 V
0 V
0 V
0 V
0 V
V
0 V
0 V
OUT1
5.0 V
5.0 V
5.0 V
5.0 V
5.0 V
V
OUT2
Turn
On
Load
Dump
Low V
Line
Noise, Etc.
V
Short
Thermal
Shutdown
Turn
Off
IN
OUT
Circuit
Figure 14. Typical Circuit Waveform
C *
0.1 µF
1
V
IN
10V
V
V
OUT1
C **
2
Control
ENABLE
10 µF
5.0V
Tuner IC
OUT2
GND
* C is required if the regulator is located away from the power source filter.
1
** C is required for stability.
2
Figure 15. Test & Applications Circuit
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CS8147
APPLICATION NOTES
Since both outputs are controlled by the same ENABLE,
This point represents the worst case input voltage
the CS8147 is ideal for applications where a sleep mode is
required. Using the CS8147, a section of circuitry such as a
display and nonessential 5.0 V circuits can be shut down
under microprocessor control to conserve energy.
The test applications circuit diagram shows an automotive
radio application where the display is powered by 10 V from
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4 with
the next smaller valued capacitor. A smaller capacitor will
usually cost less and occupy less board space. If the output
oscillates within the range of expected operating conditions,
repeat steps 3 and 4 with the next larger standard capacitor
value.
V
OUT1
and the Tuner IC is powered by 5.0 V from V
.
OUT2
Neither output is required unless both the ignition and the
Radio On/OFF switch are on.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found for each output, a safety factor should be added
to allow for the tolerance of the capacitor and any variations
in regulator performance. Most good quality aluminum
electrolytic capacitors have a tolerance of ±20% so the
minimum value found should be increased by at least 50%
to allow for this tolerance plus the variation which will occur
at low temperatures. The ESR of the capacitors should be
less than 50% of the maximum allowable ESR found in step
3 above.
Stability Considerations
The secondary output V
is inherently stable and does
OUT2
not require
a
compensation capacitor. However
a
compensation capacitor connected between V
and
OUT1
ground is required for stability in most applications.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start–up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (–25°C to –40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor C2 shown in the test and
applications circuit should work for most applications,
however it is not necessarily the optimized solution.
To determine acceptable value for C2 for a particular
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using the
decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Calculating Power Dissipation in a
Dual Output Linear Regulator
The maximum power dissipation for a dual output
regulator (Figure 16) is
NJ
NJ
Nj
I
V
V
* V
* V
)
P
+
IN(max)
IN(max)
OUT1(min) OUT1(max)
D(max)
Nj
(1)
I
) V
IQ
IN(max)
OUT2(min) OUT2(max)
where:
V
V
V
is the maximum input voltage,
IN(max)
is the minimum output voltage from V
is the minimum output voltage from V
,
,
OUT1(min)
OUT2(min)
OUT1
OUT2
I
is the maximum output current, for the
OUT1(max)
application,
I
is the maximum output current, for the
OUT2(max)
application, and
I
I
is the quiescent current the regulator consumes at
Q
.
OUT(max)
Once the value of P
is known, the maximum
D(max)
permissible value of R
can be calculated:
ΘJA
150°C * T
+
A
R
QJA
(2)
P
D
The value of R
can be compared with those in the
ΘJA
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
R
ΘJA
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
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CS8147
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
I
IN
I
I
OUT1
Smart
Regulator
V
V
IN
OUT1
determine the value of R
ΘJA
:
OUT2
R
+ R
) R
) R
QCS QSA
(3)
QJA
QJC
Control
Features
V
OUT2
where:
R
ΘJC
R
ΘCS
R
ΘSA
= the junction–to–case thermal resistance,
= the case–to–heatsink thermal resistance, and
= the heatsink–to–ambient thermal resistance.
I
Q
R
ΘJC
appears in the package section of the data sheet. Like
R
, it too is a function of package type. R
and R
ΘJA
ΘCS ΘSA
Figure 16. Dual Output Regulator With Key
Performance Parameters Labeled.
are functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
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CS8147
PACKAGE DIMENSIONS
TO–220
FIVE LEAD
T SUFFIX
CASE 314D–04
ISSUE E
SEATING
–T–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
PLANE
C
–Q–
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
B
E
A
U
INCHES
DIM MIN MAX
0.613 14.529 15.570
MILLIMETERS
L
MIN MAX
1 2 3 4 5
A
B
C
D
E
G
H
J
0.572
0.390
0.170
0.025
0.048
K
0.415
0.180
0.038
0.055
9.906 10.541
4.318
0.635
1.219
4.572
0.965
1.397
0.067 BSC
1.702 BSC
0.087
0.015
0.990
0.320
0.140
0.105
0.112 2.210
0.025 0.381
2.845
0.635
1.045 25.146 26.543
J
H
G
K
L
D 5 PL
0.365 8.128
0.153 3.556
0.117 2.667
9.271
3.886
2.972
Q
U
M
M
T Q
0.356 (0.014)
TO–220
FIVE LEAD
TVA SUFFIX
CASE 314K–01
ISSUE O
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
–T–
ąă2. CONTROLLING DIMENSION: INCH.
ąă3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
C
B
–Q–
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.22
9.78
MAX
14.99
10.54
4.83
W
A
B
C
D
E
F
0.560
0.385
0.160
0.027
0.045
0.530
0.590
0.415
0.190
0.037
0.055
0.545
4.06
0.69
A
0.94
1.40
U
1.14
13.46
F
13.84
L
G
J
0.067 BSC
1.70 BSC
K
0.014
0.785
0.321
0.063
0.146
0.271
0.146
0.460
0.022
0.800
0.337
0.078
0.156
0.321
0.196
0.475
0.36
19.94
8.15
0.56
20.32
8.56
1
2
3
4
5
K
L
M
Q
R
S
U
W
1.60
3.71
1.98
3.96
6.88
3.71
8.15
4.98
M
11.68
12.07
5 °
5 °
J
D
5 PL
G
M
M
T Q
0.356 (0.014)
S
R
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CS8147
TO–220
FIVE LEAD
THA SUFFIX
CASE 314A–03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 0.043 (1.092) MAXIMUM.
SEATING
PLANE
–T–
B
C
–P–
E
Q
OPTIONAL
CHAMFER
INCHES
DIM MIN MAX
0.613 14.529 15.570
MILLIMETERS
MIN MAX
A
B
C
D
E
F
0.572
0.390
0.170
0.025
0.048
0.570
A
0.415
0.180
0.038
0.055
9.906 10.541
U
F
4.318
0.635
1.219
4.572
0.965
1.397
L
K
0.585 14.478 14.859
1.702 BSC
0.381 0.635
0.745 18.542 18.923
G
J
0.067 BSC
0.015
0.730
0.320
0.140
0.210
0.468
0.025
K
L
G
5X J
0.365
0.153
0.260
8.128
3.556
5.334
9.271
3.886
6.604
Q
S
U
S
5X D
0.505 11.888 12.827
M
M
T P
0.014 (0.356)
PACKAGE THERMAL DATA
Parameter
TO–220
2.4
Unit
°C/W
°C/W
R
R
Typical
Typical
Θ
Θ
JC
JA
50
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CS8147
Notes
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11
CS8147
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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