CS8129/D [ETC]
5V， 750mA Low Dropout LinearRegulator with Lower RESETbar Threshold ; 5V ， 750毫安低压差LinearRegulator与下RESETbar阈值\n
| 型号： | CS8129/D |
| 厂家： | 
ETC |
| 描述： | 5V， 750mA Low Dropout LinearRegulator with Lower RESETbar Threshold
|
| 文件： | 总12页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8129
5.0 V, 750 mA Low Dropout
Linear Regulator with
Lower RESET Threshold
The CS8129 is a precision 5.0 V linear regulator capable of sourcing
750 mA. The RESET threshold voltage has been lowered to 4.2 V so
that the regulator can be used with 4.0 V microprocessors. The lower
RESET threshold also permits operation under low battery conditions
(5.5 V plus a diode). The RESET’s delay time is externally
programmed using a discrete RC network. During power up, or when
the output goes out of regulation, RESET remains in the low state for
the duration of the delay. This function is independent of the input
voltage and will function correctly as long as the output voltage
remains at or above 1.0 V. Hysteresis is included in the Delay and the
RESET comparators to improve noise immunity. A latching discharge
circuit is used to discharge the delay capacitor when it is triggered by a
brief fault condition.
The regulator is protected against a variety of fault conditions: i.e.
reverse battery, overvoltage, short circuit and thermal runaway
conditions. The regulator is protected against voltage transients ranging
from –50 V to +40 V. Short circuit current is limited to 1.2 A (typ).
The CS8129 is packaged in a 5 lead TO–220 and a 16 lead surface
mount package.
http://onsemi.com
TO–220
FIVE LEAD
T SUFFIX
CASE 314D
1
5
TO–220
FIVE LEAD
TVA SUFFIX
CASE 314K
1
TO–220
FIVE LEAD
THA SUFFIX
CASE 314A
1
5
Features
• 5.0 V ±3.0% Regulated Output
• Low Dropout Voltage (0.6 V @ 0.5 A)
• 750 mA Output Current Capability
• Reduced RESET Threshold for use with 4.0 V Microprocessors
• Externally Programmed RESET Delay
• Fault Protection
SO–16L
DW SUFFIX
CASE 751G
16
1
ORDERING INFORMATION
– Reverse Battery
– 60 V, –50 V Peak Transient Voltage
– Short Circuit
Device
Package
Shipping
TO–220*
STRAIGHT
CS8129YT5
50 Units/Rail
– Thermal Shutdown
TO–220*
VERTICAL
CS8129YTHA5
50 Units/Rail
TO–220*
HORIZONTAL
CS8129YTVA5
CS8129YDW16
50 Units/Rail
46 Units/Rail
SO–16L
SO–16L
1000 Tape & Reel
CS8129YDWR16
*Five lead.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 8 of this data sheet.
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
April, 2001 – Rev. 6
CS8129/D
CS8129
PIN CONNECTIONS
TO–220 5 LEAD
SO–16L
1
16
V
OUT
V
IN
NC
NC
GND
GND
RESET
NC
NC
V
GND
GND
GND
NC
Pin 1. V
IN
2. RESET
3. GND
4. Delay
OUT(SENSE)
5. V
OUT
Delay
NC
1
V
IN
Over Voltage
Shutdown
V
OUT
Regulated Supply
for Circuit Bias
Pre–Regulator
Error
Amplifier
–
Anti–Saturation
and
Bandgap
Reference
Charge
Current
V
OUT
Current Limit
(SENSE)
Generator
Thermal
Shutdown
Latching Discharge
Delay
–
+
S
R
Q
–
Delay
Comparator
RESET
V
+
DISCHARGE
–
GND
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
V
Input Operating Range
Power Dissipation
–0.5 to 26
Internally Limited
–50, 60
–
Peak Transient Voltage (46 V Load Dump @ 14 V V
Output Current
)
V
IN
Internally Limited
4.0
–
Electrostatic Discharge (Human Body Model)
Junction Temperature
kV
°C
°C
–55 to +150
–55 to +150
Storage Temperature Range
Lead Temperature Soldering:
Wave Solder (through hole styles only) (Note 1.)
Reflow (SMD styles only) (Note 2.)
260 peak
230 peak
°C
1. 10 second maximum.
2. 60 seconds max above 183°C.
*The maximum package power dissipation must be observed.
http://onsemi.com
2
CS8129
ELECTRICAL CHARACTERISTICS (–40°C ≤ T ≤ 125°C, –40 ≤ T ≤ 150°C, 6.0 ≤ V ≤ 26 V, 5.0 mA ≤ I
≤ 500 mA,
A
J
IN
OUT
R
= 4.7 kΩ to V
unless otherwise noted.) Note 3.
OUT
RESET
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Stage (V
OUT)
Output Voltage
–
4.85
–
5.0
5.15
0.60
V
V
Dropout Voltage
Supply Current
I
= 500 mA
0.35
OUT
I
= 10 mA
= 100 mA
= 500 mA
–
–
–
2.0
6.0
55
7.0
12
100
mA
mA
mA
OUT
I
OUT
I
OUT
Line Regulation
6.0 V ≤ V ≤ 26 V, I
= 50 mA
–
–
5.0
10
50
50
–
mV
mV
dB
A
IN
OUT
Load Regulation
50 mA ≤ I ≤ 500 mA, V = 14 V
OUT IN
Ripple Rejection
f = 120 Hz, V = 7.0 to 17 V, I
= 250 mA
54
75
IN
OUT
Current Limit
–
–
0.75
32
1.20
–
–
Overvoltage Shutdown
Reverse Polarity Input Voltage DC
Thermal Shutdown
40
–
V
V
OUT
≥ –0.6 V, 10 Ω Load
–15
150
–30
180
V
Guaranteed by Design
210
°C
RESET and Delay Functions
Delay Charge Current
RESET Threshold
V
= 2.0 V
5.0
10
15
µA
DELAY
V
OUT
V
OUT
Increasing, V
Decreasing, V
4.05
4.00
4.35
4.20
4.50
4.45
V
V
RT(ON)
RT(OFF)
RESET Hysteresis
Delay Threshold
V
= V
– V
50
150
250
mV
RH
RT(ON)
RT(OFF)
Charge, V
Discharge, V
3.25
2.85
3.50
3.10
3.75
3.35
V
V
DC(HI)
DC(LO)
Delay Hysteresis
200
–
400
0.1
0
800
0.4
10
mV
V
–
RESET Output Voltage Low
RESET Output Leakage
Delay Capacitor Discharge Voltage
Delay Time
1.0 V < V
< V
, 3.0 kΩ to V
OUT
RT(L) OUT
V
OUT
> V
Current
–
µA
V
RT(H)
Discharge Latched “ON”, V
> V
–
0.2
32
0.5
48
OUT
RT
C
= 0.1 µF, Note 4.
16
ms
DELAY
3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
4. Assuming ideal capacitor.
C
V
Delay Threshold Charge
Delay
5
3.5 10 (typ)
Delay
DelayTime +
+ C
I
Charge
http://onsemi.com
3
CS8129
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD #
TO–220
5 LEAD
SO–16L
LEAD SYMBOL
FUNCTION
1
1
5
3
V
Unregulated supply voltage to IC.
Regulated 5.0 V output.
Ground Connection.
IN
16
V
OUT
4, 5, 11, 12,
13
GND
8
6
4
2
Delay
Timing capacitor for RESET function.
RESET
CMOS/TTL compatible output lead. RESET goes low whenever V
low 6.0% of it’s regulated value.
drops be-
OUT
14
N/A
V
Remote sensing of output voltage.
OUT(SENSE)
TYPICAL PERFORMANCE CHARACTERISTICS
55
120
Room Temp
R
LOAD
= 25 Ω
50
R
LOAD
= 6.67 Ω
100
80
45
40
35
30
25
125°C
60
R
LOAD
= 10 Ω
20
15
40
25°C
10
5
20
0
R
= 25 Ω
LOAD
–40°C
R
6
= NO LOAD
LOAD
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
7
8
9
10
V
IN
(V)
V
IN
(V)
Figure 3. Quiescent Current vs. Input
Voltage Over Load Resistance
Figure 2. Quiescent Current vs. Input Voltage
Over Temperature
5.5
5.0
4.5
4.0
3.5
3.0
2.5
5.5
5.0
Room Temp
R
= 25 Ω
LOAD
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
R
= 6.67 Ω
LOAD
R
LOAD
=
125°C
NO LOAD
2.0
1.5
1.0
0.5
0
–40°C
R
LOAD
= 10 Ω
25°C
0.5
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
IN
(V)
V
IN
(V)
Figure 4. Output Voltage vs. Input Voltage
Over Temperature
Figure 5. VOUT vs. VIN Over RLOAD
http://onsemi.com
4
CS8129
TYPICAL PERFORMANCE CHARACTERISTICS
100
80
100
80
V
IN
= 6–26 V
TEMP = –40°C
TEMP = 25°C
60
60
40
20
40
TEMP = 25°C
20
TEMP = –40°C
0
–20
–40
–60
0
–20
–40
–60
V
= 14 V
IN
TEMP = 125°C
TEMP = 125°C
–80
–80
–100
–100
0
100
200
300
400
500
600
700
800
0
100
200
300
400
500
600
700
800
Output Current (mA)
Output Current (mA)
Figure 6. Line Regulation vs. Output Current
Figure 7. Load Regulation vs. Output Current
900
800
700
100
90
80
V
IN
= 14 V
25°C
70
60
600
500
400
300
25°C
125°C
50
40
30
20
125°C
–40°C
200
100
–40°C
10
0
0
0
100
200
300
400
500
600
700 800
0
100
200
300
400
500
600
700 800
Output Current (mA)
Output Current (mA)
Figure 9. Quiescent Current vs. Output Current
Figure 8. Dropout Voltage vs. Output Current
I
= 250 mA
OUT
90
80
70
60
50
3
10
C
= 10 µF, ESR = 1.0
OUT
& 0.1 µF, ESR = 0
2
1
0
10
C
C
= 47/68 µF
= 47 µF
10
O
Stable Region
10
–1
40
30
20
10
10
C
OUT
= 10 µF, ESR = 1.0 Ω
O
–2
10
C
= 68 µF
–3
O
C
OUT
= 10 µF, ESR = 1.0 Ω
10
10
–4
0
0
1
2
3
4
5
6
7
8
0
1
2
3
10
10
10
10
10
10
10
10
10
10
10
10
10
Frequency (Hz)
Output Current (mA)
Figure 10. Ripple Rejection
Figure 11. Output Capacitor ESR
http://onsemi.com
5
CS8129
V
OUT
(1) = No Delay Capacitor
V
RH
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0 V)
V
RT(ON)
V
RT(OFF)
RESET
(1)
(3)
(2)
V
RL
t
DELAY
DELAY
V
DH
V
DC(HI)
V
DC(LO)
(2)
V
DIS
Figure 12. RESET Circuit Waveform
CIRCUIT DESCRIPTION
The CS8129 RESET function has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1.0 V.
condition. The circuit allows the RESET output transistor to
go to the OFF (open) state only when the voltage on the
Delay lead is higher than V
.
DC(HI)
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram on page 2).
V
V
OUT
IN
C
*
R
RST
4.7 kΩ
C
**
IN
OUT
CS8129
100 nF
10 µF to
100 µF
RESET
GND
Low Voltage Inhibit Circuit
Delay
This circuit monitors output voltage, and when output
voltage is below the specified minimum causes the RESET
output transistor to be in the ON (saturation) state. When the
output voltage is above the specified level, this circuit permits
the RESET output transistor to go into the OFF state if
allowed by the RESET Delay circuit.
Delay
0.1 µF
*C is required if regulator is far from the power source filter.
IN
**C
is required for stability.
OUT
Reset Delay Circuit
Figure 13. Test & Application Circuit
This circuit provides a programmable (by external
capacitor) delay on the RESET output lead. The Delay lead
provides source current to the external delay capacitor only
when the “Low Voltage Inhibit” circuit indicates that output
The Delay time for the RESET function is calculated from
the formula:
C
V
Delay
Delay Threshold
Delay time +
I
voltage is above V . Otherwise, the Delay lead sinks
RT(ON)
Charge
current to ground (used to discharge the delay capacitor).
The discharge current is latched ON when the output voltage
5
Delay time + C
3.2 10
Delay(mF)
is below V
. The Delay capacitor is fully discharged
RT(OFF)
If C
= 0.1 µF, Delay time (ms) = 32 ms ±50%: i.e.
Delay
anytime the output voltage falls out of regulation, even for
a short period of time. This feature ensures that a controlled
RESET pulse is generated following detection of an error
16 ms to 48 ms. The tolerance of the capacitor must be taken
into account to calculate the total variation in the delay time.
http://onsemi.com
6
CS8129
APPLICATION NOTES
STABILITY CONSIDERATIONS
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ± 20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start–up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (–25°C to –40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 14) is:
The value for the output capacitor C
shown in Figure
OUT
13 should work for most applications, however it is not
necessarily the optimized solution.
NJ
Nj
I
P
+ V
IN(max)
* V
OUT(min) OUT(max)
) V
I
(1)
D(max)
IN(max) Q
To determine an acceptable value for C
for a particular
OUT
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
where:
V
V
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the
IN(max)
OUT(min)
OUT(max)
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
I
application, and
I is the quiescent current the regulator consumes at
Q
I
.
OUT(max)
Once the value of P
permissible value of R
is known, the maximum
D(max)
can be calculated:
ΘJA
150°C * T
+
A
R
(2)
QJA
P
D
The value of R
can then be compared with those in the
ΘJA
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
R
ΘJA
the die temperature below 150°C.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in
step 3 and vary the input voltage until the oscillations
increase. This point represents the worst case input voltage
conditions.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
I
IN
I
OUT
SMART
V
IN
V
OUT
REGULATOR
Control
Features
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.
I
Q
Figure 14. Single Output Regulator With Key
Performance Parameters Labeled
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
http://onsemi.com
7
CS8129
HEAT SINKS
where:
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
R
R
R
R
= the junction–to–case thermal resistance,
= the case–to–heatsink thermal resistance, and
= the heatsink–to–ambient thermal resistance.
appears in the package section of the data sheet. Like
ΘJC
ΘCS
ΘSA
ΘJC
R
, it too is a function of package type. R and R
ΘCS ΘSA
ΘJA
are functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
determine the value of R
.
ΘJA
R
QJA
+ R
QJC
) R ) R
QCS QSA
(3)
MARKING DIAGRAMS
TO–220
FIVE LEAD
SO–16L
16
CS8129
AWLYYWW
CS8129
AWLYWW
1
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
http://onsemi.com
8
CS8129
PACKAGE DIMENSIONS
TO–220
FIVE LEAD
T SUFFIX
CASE 314D–04
ISSUE E
SEATING
–T–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
PLANE
C
–Q–
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
B
E
A
U
INCHES
DIM MIN MAX
0.613 14.529 15.570
MILLIMETERS
L
MIN MAX
1 2 3 4 5
A
B
C
D
E
G
H
J
0.572
0.390
0.170
0.025
0.048
K
0.415
0.180
0.038
0.055
9.906 10.541
4.318
0.635
1.219
4.572
0.965
1.397
0.067 BSC
1.702 BSC
0.087
0.015
0.990
0.320
0.140
0.105
0.112 2.210
0.025 0.381
2.845
0.635
1.045 25.146 26.543
J
H
G
K
L
D 5 PL
0.365 8.128
0.153 3.556
0.117 2.667
9.271
3.886
2.972
Q
U
M
M
T Q
0.356 (0.014)
TO–220
FIVE LEAD
TVA SUFFIX
CASE 314K–01
ISSUE O
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
–T–
ąă2. CONTROLLING DIMENSION: INCH.
ąă3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
C
B
–Q–
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.22
9.78
MAX
14.99
10.54
4.83
W
A
B
C
D
E
F
0.560
0.385
0.160
0.027
0.045
0.530
0.590
0.415
0.190
0.037
0.055
0.545
4.06
0.69
A
0.94
1.40
U
1.14
13.46
F
13.84
L
G
J
0.067 BSC
1.70 BSC
K
0.014
0.785
0.321
0.063
0.146
0.271
0.146
0.460
0.022
0.800
0.337
0.078
0.156
0.321
0.196
0.475
0.36
19.94
8.15
0.56
20.32
8.56
1
2
3
4
5
K
L
M
Q
R
S
U
W
1.60
3.71
1.98
3.96
6.88
3.71
8.15
4.98
M
11.68
12.07
5 °
5 °
J
D
5 PL
G
M
M
T Q
0.356 (0.014)
S
R
http://onsemi.com
9
CS8129
TO–220
FIVE LEAD
THA SUFFIX
CASE 314A–03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 0.043 (1.092) MAXIMUM.
SEATING
PLANE
–T–
B
C
–P–
E
Q
OPTIONAL
CHAMFER
INCHES
DIM MIN MAX
0.613 14.529 15.570
MILLIMETERS
MIN MAX
A
B
C
D
E
F
0.572
0.390
0.170
0.025
0.048
0.570
A
0.415
0.180
0.038
0.055
9.906 10.541
U
F
4.318
0.635
1.219
4.572
0.965
1.397
L
K
0.585 14.478 14.859
1.702 BSC
0.381 0.635
0.745 18.542 18.923
G
J
0.067 BSC
0.015
0.730
0.320
0.140
0.210
0.468
0.025
K
L
G
5X J
0.365
0.153
0.260
8.128
3.556
5.334
9.271
3.886
6.604
Q
S
U
S
5X D
0.505 11.888 12.827
M
M
T P
0.014 (0.356)
SO–16L
DW SUFFIX
CASE 751G–03
ISSUE B
A
D
NOTES:
q
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
16
9
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS
1
8
DIM MIN
MAX
2.65
0.25
0.49
0.32
10.45
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
10.15
7.40
B
16X B
M
S
S
B
0.25
T A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
q
_
_
SEATING
PLANE
14X
e
C
T
PACKAGE THERMAL DATA
Parameter
TO–220
FIVE LEAD
SO–16L
Unit
R
R
Typical
Typical
2.1
50
23
°C/W
°C/W
Θ
Θ
JC
JA
105
http://onsemi.com
10
CS8129
Notes
http://onsemi.com
11
CS8129
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
CENTRAL/SOUTH AMERICA:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–spanish@hibbertco.com
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
Toll–Free from Mexico: Dial 01–800–288–2872 for Access –
then Dial 866–297–9322
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone: 1–303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
001–800–4422–3781
EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET)
Email: ONlit–german@hibbertco.com
French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET)
Email: ONlit–french@hibbertco.com
Email: ONlit–asia@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT)
Email: ONlit@hibbertco.com
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
For additional information, please contact your local
Sales Representative.
*Available from Germany, France, Italy, UK, Ireland
CS8129/D
相关型号：
©2020 ICPDF网 联系我们和版权申明