CS8129YT5 [ONSEMI]
5.0 V, 750 mA Low Dropout Linear Regulator with Lower RESET Threshold; 5.0 V 750 mA低压差线性稳压器，低复位阈值
| 型号： | CS8129YT5 |
| 厂家： | 
ONSEMI |
| 描述： | 5.0 V, 750 mA Low Dropout Linear Regulator with Lower RESET Threshold |
| 文件： | 总11页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8129
5.0 V, 750 mA Low Dropout
Linear Regulator with
Lower RESET Threshold
The CS8129 is a precision 5.0 V linear regulator capable of sourcing
750 mA. The RESET threshold voltage has been lowered to 4.2 V so
that the regulator can be used with 4.0 V microprocessors. The lower
RESET threshold also permits operation under low battery conditions
(5.5 V plus a diode). The RESET’s delay time is externally
programmed using a discrete RC network. During powerup, or when
the output goes out of regulation, RESET remains in the low state for
the duration of the delay. This function is independent of the input
voltage and will function correctly as long as the output voltage
remains at or above 1.0 V. Hysteresis is included in the Delay and the
RESET comparators to improve noise immunity. A latching discharge
circuit is used to discharge the delay capacitor when it is triggered by a
brief fault condition.
The regulator is protected against a variety of fault conditions: i.e.
reverse battery, overvoltage, short circuit and thermal runaway
conditions. The regulator is protected against voltage transients ranging
from −50 V to +40 V. Short circuit current is limited to 1.2 A (typ).
The CS8129 is packaged in a 5 lead TO−220 and a 16 lead surface
mount package.
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TO−220
FIVE LEAD
T SUFFIX
CASE 314D
1
5
TO−220
FIVE LEAD
TVA SUFFIX
CASE 314K
1
TO−220
FIVE LEAD
THA SUFFIX
CASE 314A
1
Features
5
• 5.0 V 3.0% Regulated Output
• Low Dropout Voltage (0.6 V @ 0.5 A)
• 750 mA Output Current Capability
• Reduced RESET Threshold for Use with 4.0 V Microprocessors
• Externally Programmed RESET Delay
• Fault Protection
SO−16WB
DW SUFFIX
CASE 751G
16
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
− Reverse Battery
dimensions section on page 8 of this data sheet.
− 60 V, −50 V Peak Transient Voltage
− Short Circuit
− Thermal Shutdown
DEVICE MARKING INFORMATION
• Pb−Free Packages are Available*
See general marking information in the device marking
section on page 8 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 8
CS8129/D
CS8129
PIN CONNECTIONS
TO−220 5−LEAD
SO−16 WB
1
16
Pin 1. V
V
IN
V
IN
OUT
NC
NC
2. RESET
3. GND
NC
V
OUT(SENSE)
GND
GND
RESET
NC
Delay
GND
GND
GND
NC
4. Delay
5. V
OUT
NC
1
V
IN
Over Voltage
Shutdown
V
OUT
Regulated Supply
for Circuit Bias
Pre−Regulator
Error
Amplifier
−
Anti−Saturation
and
Current Limit
Bandgap
Reference
Charge
Current
V
OUT
(SENSE)
Generator
Thermal
Shutdown
Latching Discharge
Delay
−
+
S
R
Q
−
Delay
Comparator
RESET
V
+
DISCHARGE
−
GND
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS
Rating
Value
Unit
V
Input Operating Range
Power Dissipation
−0.5 to 26
Internally Limited
−50, 60
−
Peak Transient Voltage (46 V Load Dump @ 14 V V
Output Current
)
IN
V
Internally Limited
4.0
−
Electrostatic Discharge (Human Body Model)
Junction Temperature
kV
°C
°C
−55 to +150
−55 to +150
Storage Temperature Range
Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
260 peak
230 peak
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 10 second maximum.
2. 60 seconds max above 183°C.
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2
CS8129
ELECTRICAL CHARACTERISTICS (−40°C ≤ T ≤ 125°C, −40 ≤ T ≤ 150°C, 6.0 ≤ V ≤ 26 V, 5.0 mA ≤ I
≤ 500 mA,
A
J
IN
OUT
R
= 4.7 kW to V
unless otherwise noted.) (Note 3)
RESET
OUT
Characteristic
Test Conditions
Min
Typ
Max
Unit
OUTPUT STAGE (V
Output Voltage
OUT)
−
4.85
−
5.0
5.15
0.60
V
V
Dropout Voltage
Supply Current
I
= 500 mA
0.35
OUT
I
= 10 mA
= 100 mA
= 500 mA
−
−
−
2.0
6.0
55
7.0
12
100
mA
mA
mA
OUT
I
OUT
I
OUT
Line Regulation
Load Regulation
Ripple Rejection
Current Limit
6.0 V ≤ V ≤ 26 V, I
= 50 mA
OUT
−
−
5.0
10
50
50
−
mV
mV
dB
A
IN
50 mA ≤ I
≤ 500 mA, V = 14 V
IN
OUT
f = 120 Hz, V = 7.0 to 17 V, I
= 250 mA
54
75
IN
OUT
−
−
0.75
32
1.20
−
−
Overvoltage Shutdown
Reverse Polarity Input Voltage DC
Thermal Shutdown
40
−
V
V
≥ −0.6 V, 10 W Load
−15
150
−30
180
V
OUT
Guaranteed by Design
210
°C
RESET AND DELAY FUNCTIONS
Delay Charge Current
V
= 2.0 V
5.0
10
15
mA
DELAY
RESET Threshold
V
V
Increasing, V
Decreasing, V
4.05
4.00
4.35
4.20
4.50
4.45
V
V
OUT
OUT
RT(ON)
RT(OFF)
RESET Hysteresis
Delay Threshold
V
= V
− V
RT(ON)
50
150
250
mV
RH
RT(OFF)
Charge, V
Discharge, V
3.25
2.85
3.50
3.10
3.75
3.35
V
V
DC(HI)
DC(LO)
Delay Hysteresis
200
−
400
0.1
0
800
0.4
10
mV
V
−
RESET Output Voltage Low
RESET Output Leakage
Delay Capacitor Discharge Voltage
Delay Time
1.0 V < V
< V
, 3.0 kW to V
RT(L) OUT
OUT
V
> V
Current
−
mA
V
OUT
RT(H)
Discharge Latched “ON”, V
> V
−
0.2
32
0.5
48
OUT
RT
C
DELAY
= 0.1 mF, (Note 4)
16
ms
3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
4. Assuming ideal capacitor.
C
V
Delay Threshold Charge
Delay
5
+ C 3.5 10 (typ)
Delay
Delay Time +
I
Charge
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD #
TO−220
5 LEAD
SO−16WB
LEAD SYMBOL
FUNCTION
1
1
5
3
4
2
V
Unregulated supply voltage to IC.
Regulated 5.0 V output.
Ground Connection.
IN
16
V
OUT
4, 5, 11, 12, 13
GND
Delay
8
6
Timing capacitor for RESET function.
RESET
CMOS/TTL compatible output lead. RESET goes low whenever V
below 6.0% of it’s regulated value.
drops
OUT
14
N/A
V
Remote sensing of output voltage.
OUT(SENSE)
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3
CS8129
TYPICAL PERFORMANCE CHARACTERISTICS
55
50
120
Room Temp
R
LOAD
= 25 W
R
LOAD
= 6.67 W
100
80
45
40
35
30
25
125°C
60
R
LOAD
= 10 W
20
15
40
25°C
10
5
20
0
R
= 25 W
LOAD
−40°C
R
6
= NO LOAD
LOAD
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
7
8
9
10
V
(V)
V
(V)
IN
IN
Figure 3. Quiescent Current vs. Input
Voltage Over Load Resistance
Figure 2. Quiescent Current vs. Input Voltage
Over Temperature
5.5
5.0
4.5
4.0
3.5
3.0
2.5
5.5
5.0
Room Temp
R
= 25 W
LOAD
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
R
= 6.67 W
LOAD
R
LOAD
=
125°C
NO LOAD
2.0
1.5
1.0
0.5
0
−40°C
R
LOAD
= 10 W
25°C
0.5
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
(V)
V
(V)
IN
IN
Figure 4. Output Voltage vs. Input Voltage
Over Temperature
Figure 5. VOUT vs. VIN Over RLOAD
100
80
100
80
V
= 6−26 V
IN
TEMP = −40°C
TEMP = 25°C
60
60
40
20
40
20
TEMP = 25°C
TEMP = −40°C
0
−20
−40
−60
0
−20
−40
−60
V
= 14 V
IN
TEMP = 125°C
TEMP = 125°C
−80
−80
−100
−100
0
100
200
300
400
500
600
700 800
0
100
200
300
400
500
600
700
800
Output Current (mA)
Output Current (mA)
Figure 6. Line Regulation vs. Output Current
Figure 7. Load Regulation vs. Output Current
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4
CS8129
900
800
100
90
V
= 14 V
IN
80
700
25°C
70
60
600
500
400
300
25°C
125°C
50
40
30
20
125°C
−40°C
200
100
−40°C
10
0
0
0
100
200
300
400
500
600
700 800
0
100
200
300
400
500
600
700 800
Output Current (mA)
Output Current (mA)
Figure 8. Dropout Voltage vs. Output Current
Figure 9. Quiescent Current vs. Output Current
I
= 250 mA
OUT
90
80
70
60
50
3
10
C
= 10 mF, ESR = 1.0
OUT
& 0.1 mF, ESR = 0
2
1
0
10
C
C
= 47/68 mF
= 47 mF
10
O
Stable Region
10
−1
40
30
20
10
C
OUT
= 10 mF, ESR = 1.0 W
O
−2
10
C
= 68 mF
−3
O
C
OUT
= 10 mF, ESR = 1.0 W
10
10
10
0
−4
0
1
2
3
4
5
6
7
8
0
1
2
3
10
10
10
10
10
10
10
10
10
10
10
10
10
Frequency (Hz)
Output Current (mA)
Figure 10. Ripple Rejection
Figure 11. Output Capacitor ESR
V
OUT
V
RH
(1) = No Delay Capacitor
(2) = With Delay Capacitor
V
RT(ON)
V
RT(OFF)
(3) = Max: RESET Voltage (1.0 V)
RESET
(1)
(3)
(2)
V
RL
t
DELAY
DELAY
V
DH
V
DC(HI)
V
DC(LO)
(2)
V
DIS
Figure 12. RESET Circuit Waveform
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5
CS8129
CIRCUIT DESCRIPTION
The CS8129 RESET function has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1.0 V.
condition. The circuit allows the RESET output transistor to
go to the OFF (open) state only when the voltage on the
Delay lead is higher than V
.
DC(HI)
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram on page 2).
V
V
OUT
IN
C
*
R
RST
4.7 kW
C
**
IN
OUT
CS8129
100 nF
10 mF to
100 mF
RESET
GND
Low Voltage Inhibit Circuit
Delay
This circuit monitors output voltage, and when output
voltage is below the specified minimum causes the RESET
output transistor to be in the ON (saturation) state. When the
output voltage is above the specified level, this circuit permits
the RESET output transistor to go into the OFF state if
allowed by the RESET Delay circuit.
Delay
0.1 mF
*C is required if regulator is far from the power source filter.
IN
**C
is required for stability.
OUT
Reset Delay Circuit
Figure 13. Test & Application Circuit
This circuit provides a programmable (by external
capacitor) delay on the RESET output lead. The Delay lead
provides source current to the external delay capacitor only
when the “Low Voltage Inhibit” circuit indicates that output
The Delay time for the RESET function is calculated from
the formula:
C
V
I
Delay
Delay Threshold
Charge
voltage is above V . Otherwise, the Delay lead sinks
RT(ON)
Delay time +
current to ground (used to discharge the delay capacitor).
The discharge current is latched ON when the output voltage
5
Delay time + C
3.2 10
Delay(mF)
is below V . The Delay capacitor is fully discharged
RT(OFF)
If C
= 0.1 mF, Delay time (ms) = 32 ms 50%: i.e.
Delay
anytime the output voltage falls out of regulation, even for
a short period of time. This feature ensures that a controlled
RESET pulse is generated following detection of an error
16 ms to 48 ms. The tolerance of the capacitor must be taken
into account to calculate the total variation in the delay time.
APPLICATION NOTES
STABILITY CONSIDERATIONS
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in
step 3 and vary the input voltage until the oscillations
increase. This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.
The value for the output capacitor C
shown in Figure
OUT
13 should work for most applications, however it is not
necessarily the optimized solution.
To determine an acceptable value for C
for a particular
OUT
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
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6
CS8129
I
I
OUT
Step 6: Test the load transient response by switching in
IN
SMART
V
V
OUT
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
IN
REGULATOR®
Control
Features
I
Q
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of 20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
Figure 14. Single Output Regulator With Key
Performance Parameters Labeled
HEAT SINKS
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
The maximum power dissipation for a single output
regulator (Figure 14) is:
NJ
Nj
I
P
+ V
IN(max)
* V
OUT(min) OUT(max)
) V
I
determine the value of R
.
(1)
D(max)
IN(max) Q
qJA
) R
R
qJA
+ R
qJC
) R
qCS qSA
(3)
where:
V
V
I
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the
IN(max)
OUT(min)
OUT(max)
where:
R
qJC
R
qCS
R
qSA
R
qJC
= the junction−to−case thermal resistance,
= the case−to−heatsink thermal resistance, and
= the heatsink−to−ambient thermal resistance.
application, and
I is the quiescent current the regulator consumes at
Q
appears in the package section of the data sheet. Like
and R are
I
.
OUT(max)
R , it too is a function of package type. R
qJA
qCS
qSA
Once the value of P
permissible value of R
is known, the maximum
D(max)
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
can be calculated:
qJA
150°C * T
A
R
qJA
+
(2)
P
D
The value of R
can then be compared with those in the
qJA
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
R
qJA
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
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7
CS8129
MARKING DIAGRAMS
SO−16 WB
TO−220 5−LEAD
16
CS8129
AWLYYWWG
CS
8129
CS
8129
AWLYWWG
CS8129
AWLYWWG
AWLYWWG
1
1
1
1
A
WL
= Assembly Location
= Wafer Lot
YY, Y
WW
G
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
†
Package
Shipping
CS8129YT5
TO−220*
STRAIGHT
CS8129YT5G
TO−220*
STRAIGHT
(Pb−Free)
CS8129YTHA5
TO−220*
HORIZONTAL
50 Units / Rail
CS8129YTHA5G
TO−220*
HORIZONTAL
(Pb−Free)
CS8129YTVA5
TO−220*
VERTICAL
CS8129YTVA5G
TO−220*
VERTICAL
(Pb−Free)
CS8129YDW16
SO−16WB
47 Units / Rail
CS8129YDW16G
SO−16WB
(Pb−Free)
CS8129YDWR16
CS8129YDWR16G
SO−16WB
1000 / Tape & Reel
SO−16WB
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
CS8129
PACKAGE DIMENSIONS
TO−220
CASE 314D−04
ISSUE F
SEATING
−T−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
PLANE
B
C
E
−Q−
DETAIL A−A
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
B1
A
U
INCHES
DIM MIN MAX
MILLIMETERS
MIN MAX
L
1 2 3 4 5
A
0.572
0.390
B1 0.375
0.613 14.529 15.570
0.415 9.906 10.541
0.415 9.525 10.541
K
B
C
D
E
G
H
J
0.170
0.025
0.048
0.180 4.318
0.038 0.635
0.055 1.219
4.572
0.965
1.397
0.067 BSC
1.702 BSC
J
H
0.087
0.015
0.977
0.320
0.140
0.105
0.112 2.210 2.845
0.025 0.381 0.635
1.045 24.810 26.543
G
D 5 PL
K
L
0.365 8.128
0.153 3.556
0.117 2.667
9.271
3.886
2.972
M
M
0.356 (0.014)
T Q
Q
U
B
B1
DETAIL A−A
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9
CS8129
PACKAGE DIMENSIONS
TO−220
TVA SUFFIX
CASE 314K−01
ISSUE O
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
ꢀꢁ2. CONTROLLING DIMENSION: INCH.
ꢀꢁ3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
C
B
E
−Q−
INCHES
DIM MIN MAX
0.590 14.22
MILLIMETERS
MIN
MAX
14.99
10.54
4.83
W
A
B
C
D
E
F
0.560
0.385
0.160
0.027
0.045
0.530
0.415
0.190
0.037
0.055
9.78
4.06
0.69
1.14
A
0.94
1.40
U
F
0.545 13.46
13.84
L
G
J
0.067 BSC
1.70 BSC
K
0.014
0.785
0.321
0.063
0.146
0.271
0.146
0.460
0.022
0.36
0.800 19.94
0.56
20.32
8.56
1
2
3
4
5
K
L
0.337
0.078
0.156
0.321
0.196
0.475
8.15
1.60
3.71
6.88
3.71
11.68
M
Q
R
S
U
W
1.98
3.96
8.15
4.98
M
12.07
5 °
5 °
J
D
5 PL
G
M
M
T Q
0.356 (0.014)
S
R
TO−220
THA SUFFIX
CASE 314A−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 0.043 (1.092) MAXIMUM.
B
C
−P−
E
Q
OPTIONAL
CHAMFER
INCHES
DIM MIN MAX
0.613 14.529 15.570
MILLIMETERS
MIN MAX
A
B
C
D
E
F
0.572
0.390
0.170
0.025
0.048
0.570
A
0.415
0.180
0.038
0.055
9.906 10.541
U
F
4.318
0.635
1.219
4.572
0.965
1.397
L
K
0.585 14.478 14.859
1.702 BSC
0.381 0.635
0.745 18.542 18.923
G
J
0.067 BSC
0.015
0.730
0.320
0.140
0.210
0.468
0.025
K
L
G
5X J
0.365
0.153
0.260
8.128
3.556
5.334
9.271
3.886
6.604
Q
S
U
S
5X D
0.505 11.888 12.827
M
M
T P
0.014 (0.356)
http://onsemi.com
10
CS8129
PACKAGE DIMENSIONS
SO−16 WB
CASE 751G−03
ISSUE C
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
A
D
q
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
A
1
8
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
B
16X B
M
S
S
B
0.25
T A
0.25
0.50
0
0.75
0.90
7
_
_
SEATING
PLANE
14X
e
C
T
PACKAGE THERMAL DATA
Parameter
TO−220
FIVE LEAD
SO−16WB
23
Unit
R
R
Typical
Typical
2.1
50
°C/W
°C/W
q
JC
JA
105
q
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