CS8129YDWR16 [CHERRY]
5V, 750mA Low Dropout Linear Regulator with Lower RESET Threshold; 5V ， 750毫安低压差线性稳压器，具有低复位阈值
| 型号： | CS8129YDWR16 |
| 厂家： | 
CHERRY SEMICONDUCTOR CORPORATION |
| 描述： | 5V, 750mA Low Dropout Linear Regulator with Lower RESET Threshold |
| 文件： | 总8页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8129
5V, 750mA Low Dropout Linear
Regulator with Lower RESET Threshold
Description
Features
■ 5V +/- 3% Regulated
The CS8129 is a precision 5V linear reg-
ulator capable of sourcing 750mA.
RESET
RESET
the Delay and the
comparators
Output
to improve noise immunity. A latching
discharge circuit is used to discharge
the delay capacitor when it is triggered
by a brief fault condition.
The
threshold voltage has been
lowered to 4.2V so that the regulator
can be used with 4V microprocessors.
■ Low Dropout Voltage
(0.6V @ 0.5A)
RESET
The lower
mits operation under low battery condi-
RESET
threshold also per-
■ 750mA Output Current
The regulator is protected against a
variety of fault conditions: i.e. reverse
battery, overvoltage, short circuit and
thermal runaway conditions. The regu-
lator is protected against voltage tran-
sients ranging from -50V to +40V. Short
circuit current is limited to 1.2A (typ).
Capability
tions (5.5V plus a diode). The
Õs
delay time is externally programmed
using a discrete RC network. During
■ Reduced RESET Threshold
for use with 4V Micro-
processors
power up, or when the output goes out
RESET
of regulation,
remains in the
low state for the duration of the delay.
This function is independent of the
input voltage and will function correct-
ly as long as the output voltage remains
at or above 1V. Hysteresis is included in
■ Externally Programmed
The CS8129 is packaged in a 5 lead
TOÐ220 and a 16 lead surface mount
package.
RESET Delay
■ Fault Protection
Reverse Battery
60V, -50V Peak Transient
Voltage
Block Diagram
Short Circuit
Thermal Shutdown
Package Options
V
V
IN
Over Voltage
Shutdown
16 Lead SOIC Wide
OUT
1
VIN
NC
NC
VOUT
Regulated Supply
for Circuit Bias
Pre-
NC
Error
Regulator
VOUT(SENSE)
Gnd
Amplifier
Bandgap
Reference
-
Anti-Saturation
and
Current Limit
Gnd
Gnd
+
Gnd
Charge
V
Current
Thermal
Shutdown
OUT
SENSE
Gnd
RESET
NC
Generator
NC
NC
Delay
Latching Discharge
Delay
-
5 Lead TO-220
Q
S
R
+
-
+
VDISCHARGE
1
2
3
4
VIN
RESET
Delay Comparator
+
-
RESET
Gnd
Gnd
Delay
VOUT
5
1
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 3/31/99
A
¨
Company
1
Absolute Maximum Ratings
Input Operating Range..................................................................................................................................................-0.5 to 26V
Power Dissipation.............................................................................................................................................Internally Limited
Peak Transient Voltage (46V Load Dump @ 14V VIN) ...............................................................................................-50V, 60V
Output Current .................................................................................................................................................Internally Limited
ESD Susceptibility (Human Body Model)..............................................................................................................................4kV
Junction Temperature.............................................................................................................................................-55¡C to 150¡C
Storage Temperature...............................................................................................................................................-55¡C to 150¡C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak
Electrical Characteristics: -40ûC ² TA ² + 125ûC, -40ûC ² TJ ² +150ûC, 6V ² VIN ² 26V, 5mA ² IOUT ² 500mA, R RESET = 4.7k½ to VOUT
unless otherwise noted*
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
■
Output Stage (VOUT
Output Voltage
Dropout Voltage
Supply Current
)
4.85
5.00
0.35
5.15
0.60
V
V
IOUT = 500mA
IOUT ² 10mA
IOUT ² 100mA
IOUT ² 500mA
2
6
55
7
12
100
mA
Line Regulation
Load Regulation
Ripple Rejection
6V ² VIN ² 26V, IOUT = 50mA
5
50
50
mV
mV
dB
50mA ² IOUT ² 500mA, VIN = 14V
10
75
f = 120Hz, VIN = 7 to 17V,
IOUT = 250mA
54
Current Limit
0.75
32
1.20
A
V
V
Overvoltage Shutdown
40
Reverse Polarity Input
Voltage DC
VOUT ³ -0.6V, 10½ Load
Guaranteed by Design
-15
-30
Thermal Shutdown
150
180
210
¡C
■
and Delay Functions
RESET
Delay Charge Current
VDELAY = 2V
5
10
15
µA
Threshold
Hysteresis
VOUT Increasing, VRT(ON)
VOUT Decreasing, VRT(OFF)
4.05
4.00
4.35
4.20
4.50
4.45
V
V
RESET
RESET
VRH=VRT(ON) - VRT(OFF)
50
150
250
mV
Delay Threshold
Charge, VDC(HI)
Discharge, VDC(LO)
3.25
2.85
3.50
3.10
3.75
3.35
V
V
Delay Hysteresis
200
400
0.1
0
800
0.4
10
mV
V
Output Voltage Low1V < VOUT < VRT(L) , 3k½ to VOUT
RESET
RESET
Output Leakage
VOUT > VRT(H)
Current
µA
Delay Capacitor
Discharge Voltage
Discharge Latched ÒONÓ,
VOUT > VRT
0.2
32
0.5
48
V
Delay Time
CDELAY = 0.1µF (Note 1)
16
ms
* To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
Delay x VDelay Threshold Charge
C
Delay Time =
= CDelay x 3.5 x 105 (typ)
I Charge
Note 1: assuming ideal capacitor
2
Package Lead Description
LEAD SYMBOL
PACKAGE LEAD #
16L SOIC Wide 5L TO-220
FUNCTION
1
1
5
3
4
2
VIN
Unregulated supply voltage to IC.
16
VOUT
Gnd
Regulated 5V output.
Ground connection.
Timing capacitor for
4, 5, 11, 12, 13
8
6
Delay
RESET
function.
RESET
CMOS/TTL compatible output lead.
er VOUT drops below 6% of it's regulated value.
goes low whenev-
RESET
14
N/A
VOUT(SENSE)
Remote sensing of output voltage.
Typical Performance Characteristics
Quiescent Current vs Input Voltage over Temperature
Quiescent Current vs Input Voltage over Load Resistance
55.0
120.0
Rload = 25W
Room Temp.
50.0
45.0
40.0
35.0
30.0
Rload = 6.67W
100.0
80.0
25ûC
60.0
125ûC
25.0
20.0
15.0
10.0
5.0
Rload = 10W
40.0
20.0
0.0
Rload = 25W
-40ûC
Rload = NO LOAD
0.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VIN (V)
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VIN (V)
VOUT vs. VIN over RLOAD
Output Voltage vs Input Voltage over Temperature
5.5
5.0
Room Temp.
5.5
Rload=25½
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
Rload = 6.67W
3.0
125ûC
2.5
Rload =
2.0
NO LOAD
25ûC
1.5
-40ûC
1.0
Rload = 10W
0.5
0.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VIN (V)
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VIN (V)
Line Regulation vs. Output Current
Load Regulation vs. Output Current
100
6
VIN 6-26V
80
60
4
TEMP = -40ûC
2
0
40
TEMP = 25ûC
TEMP = -40ûC
20
-2
-4
TEMP = 25ûC
0
VIN = 14V
-20
-40
-60
-80
-100
-6
-8
TEMP = 125ûC
TEMP = 125ûC
-10
-12
-14
0
100 200 300 400 500 600 700 800
OUTPUT CURRENT (mA)
0
100 200 300 400 500 600 700 800
OUTPUT CURRENT (mA)
3
Typical Performance Characteristics Continued
Quiescent Current vs. Output Current
Dropout Voltage vs. Output Current
900
800
700
600
500
400
300
200
100
0
100
90
80
70
60
50
40
30
20
10
0
125ûC
25ûC
VIN = 14V
25ûC
125ûC
-40ûC
-40ûC
0
100 200 300 400 500 600 700 800
OUTPUT CURRENT (mA)
0
100 200 300 400 500 600 700 800
OUTPUT CURRENT (mA)
Ripple Rejection
Output Capacitor ESR
103
I
= 250mA
OUT
90
80
70
60
50
40
30
20
10
0
102
101
COUT= 10mF, ESR = 1 & 0.1mF,
ESR = 0
C
= 47/68mF
OUT
Stable Region
100
10-1
COUT= 10mF, ESR = 1W
C
= 47mF
OUT
10-2
C
= 68mF
OUT
COUT= 10mF, ESR = 10W
10-3
10-4
100 101 102 103 104 105 106 107 108
FREQUENCY (Hz)
101
102
103
100
Output Current (mA)
Test & Application Circuit
VOUT
VIN
C
*
IN
100nF
C
**
10mF to 100mF
RRST
4.7kW
OUT
CS8129
Delay
RESET
Gnd
Delay
0.1mF
*CIN required if regulator is far from the power source filter.
**COUT required for stability.
4
RESET
Circuit Waveform
(1) = No Delay Capacitor
(2) = With Delay Capacitor
V
OUT
V
RH
V
V
RT(ON)
RESET
(3) = Max:
Voltage (1.0V)
RT(OFF)
(1)
RESET
(2)
(3)
V
RL
t
Delay
Delay
V
DH
V
DC(HI)
V
DC(LO)
V
DIS
(2)
RESET Circuit Functional Description
put voltage is above VRT(ON). Otherwise, the Delay lead
sinks current to ground (used to discharge the delay
capacitor). The discharge current is latched ON when the
output voltage is below VRT(OFF). The Delay capacitor is
fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
The CS8129
function has hysteresis on both the
RESET
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
The
circuit output is an open collector type with
RESET
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
ensures a controlled
pulse is generated following
RESET
detection of an error condition. The circuit allows
the output transistor to go to the OFF (open) state
RESET
only when the voltage on the Delay lead is higher than
VDC(HI)
Low Voltage Inhibit Circuit
.
This circuit monitors output voltage, and when output
voltage is below the specified minimum causes the
The Delay time for the
the formula:
function is calculated from
RESET
output transistor to be in the ON (saturation)
RESET
C
Delay x VDelay Threshold
ICharge
state. When the output voltage is above the specified level,
this circuit permits the RESET output transistor to go into
Delay time =
the OFF state if allowed by the
Delay circuit.
RESET
Delay time = CDelay(µF) x 3.2 x 105
Reset Delay Circuit
If CDelay=0.1µF, Delay time (ms)=32ms ± 50%: i.e. 16ms to
48ms. The tolerance of the capacitor must be taken into
account to calculate the total variation in the delay time.
This circuit provides a programmable (by external capaci-
tor) delay on the output lead. The Delay lead pro-
vides source current to the external delay capacitor only
when the "Low Voltage Inhibit" circuit indicates that out-
RESET
5
Application Notes
low temperatures. The ESR of the capacitor should be less
Stability Considerations
than 50% of the maximum allowable ESR found in step 3
above.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start-up
delay, load transient response and loop stability.
Calculating Power Dissipation
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instabil-
ity. The aluminum electrolytic capacitor is the least expen-
sive solution, but, if the circuit operates at low tempera-
tures (-25¡C to -40¡C), both the value and ESR of the least
expensive will vary considerably. The capacitor manufac-
turers data sheet usually provides this information.
in a Single Output Linear Regulator
The maximum power dissipation for a single output regu-
lator (Figure 1) is:
PD(max)= VIN(max)ÐVOUT(min)}
I
OUT(max)+VIN(max) Q
I
(1)
{
where
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
The value for the output capacitor COUT shown in the test
and applications circuit should work for most applica-
tions, however it is not necessarily the optimized solution.
IOUT(max) is the maximum output current for the applica-
tion, and
To determine an acceptable value for COUT for a particular
application, start with a tantalum capacitor of the recom-
mended value and work towards a less expensive alterna-
tive part.
IQ is the quiescent current the regulator consumes at
IOUT(max)
.
Once the value of PD(max) is known, the maximum permis-
sible value of RQJA can be calculated:
Step 1: Place the completed circuit with a tantalum capac-
itor of the recommended value in an environmental cham-
ber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by
the longer leads is negligible.
150¡C - TA
(2)
RQJA
=
PD
The value of RQJA can then be compared with those in
the package section of the data sheet. Those packages
with RQJA's less than the calculated value in equation 2
will keep the die temperature below 150¡C.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscil-
lations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage condi-
tions.
I
IN
I
OUT
V
IN
Smart
Regulator
V
OUT
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capaci-
tor will usually cost less and occupy less board space. If
the output oscillates within the range of expected operat-
ing conditions, repeat steps 3 and 4 with the next larger
standard capacitor value.
Control
Features
}
I
Q
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Figure 1: Single output regulator with key performance parameters
labeled.
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regula-
tor performance. Most good quality aluminum electrolytic
capacitors have a tolerance of +/- 20% so the minimum
value found should be increased by at least 50% to allow
for this tolerance plus the variation which will occur at
6
Application Notes: continued
where
Heat Sinks
R
R
R
QJC = the junctionÐtoÐcase thermal resistance,
QCS = the caseÐtoÐheatsink thermal resistance, and
QSA = the heatsinkÐtoÐambient thermal resistance.
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
R
R
QJC appears in the package section of the data sheet. Like
QJA, it too is a function of package type. RQCS and RQSA
are functions of the package type, heatsink and the inter-
face between them. These values appear in heat sink data
sheets of heat sink manufacturers.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed
to determine the value of RQJA
.
R
QJA = RQJC + RQCS + RQSA
(3)
7
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
D
Thermal Data
16 Lead
SOIC Wide
5 Lead
TO-220
Lead Count
Metric
English
RQJC
RQJA
typ
typ
23
105
2.1
50
ûC/W
ûC/W
Max
10.50
Min
Max Min
16 L SOIC Wide
10.10 .413 .398
Surface Mount Wide Body (DW); 300 mil wide
5 Lead TO-220 (THA) Horizontal
4.83 (.190)
4.06 (.160)
10.54 (.415)
9.78 (.385)
1.40 (.055)
1.14 (.045)
3.96 (.156)
3.71 (.146)
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
2.87 (.113)
2.62 (.103)
14.99 (.590)
14.22 (.560)
6.55 (.258)
5.94 (.234)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.77 (.109)
2.49 (.098)
2.24 (.088)
6.83 (.269)
1.68
2.65 (.104)
2.35 (.093)
2.92 (.115)
2.29 (.090)
0.56 (.022)
(.066)
TYP
0.81(.032)
0.36 (.014)
6.60 (.260)
5.84 (.230)
0.32 (.013)
0.23 (.009)
1.27 (.050)
0.40 (.016)
1.70 (.067)
6.81(.268)
0.30 (.012)
0.10 (.004)
D
REF: JEDEC MS-013
5 Lead TO-220 (T) Straight
5 Lead TO-220 (TVA) Vertical
1.40 (.055)
1.14 (.045)
4.83 (.190)
4.06 (.160)
4.83 (.190)
4.06 (.160)
10.54 (.415)
9.78 (.385)
3.96 (.156)
3.71 (.146)
2.87 (.113)
3.96 (.156)
3.71 (.146)
10.54 (.415)
9.78 (.385)
2.62 (.103)
6.55 (.258)
5.94 (.234)
1.40 (.055)
1.14 (.045)
14.99 (.590)
14.22 (.560)
6.55 (.258)
5.94 (.234)
2.87 (.113)
2.62 (.103)
14.99 (.590)
14.22 (.560)
14.22 (.560)
13.72 (.540)
1.78 (.070)
2.92 (.115)
2.29 (.090)
8.64 (.340)
7.87 (.310)
1.02 (.040)
0.76 (.030)
4.34 (.171)
7.51 (.296)
0.56 (.022)
0.36 (.014)
1.68
(.066) typ
0.56 (.022)
0.36 (.014)
1.70 (.067)
1.83(.072)
1.57(.062)
1.02(.040)
0.63(.025)
6.80 (.268)
6.93(.273)
6.68(.263)
2.92 (.115)
2.29 (.090)
.94 (.037)
.69 (.027)
Ordering Information
Description
Part Number
CS8129YDW16
CS8129YDWR16
16 Lead SOIC Wide
16 Lead SOIC Wide
(tape & reel)
Ch erry Sem icon du ctor Corporation reserves th e
righ t to m ake ch an ges to th e specification s with ou t
n otice. Please con tact Ch erry Sem icon du ctor
Corporation for th e latest available in form ation .
CS8129YT5
CS8129YTHA5
CS8129YTVA5
5 Lead TO-220 Straight
5 Lead TO-220 Horizontal
5 Lead TO-220 Vertical
© 1999 Cherry Semiconductor Corporation
Rev. 3/31/99
8
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