CS51031/D [ETC]
Fast PFET Buck Controller ; 快PFET降压控制器\n
| 型号： | CS51031/D |
| 厂家： | 
ETC |
| 描述： | Fast PFET Buck Controller
|
| 文件： | 总12页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS51031
Fast PFET Buck Controller
The CS51031 is a switching controller for use in DC–DC
converters. It can be used in the buck topology with a minimum
number of external components. The CS51031 consists of a V
CC
monitor for controlling the state of the device, 1.0 A power driver for
controlling the gate of a discrete P–channel transistor, fixed frequency
oscillator, short circuit protection timer, programmable soft start,
precision reference, fast output voltage monitoring comparator, and
output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and
output capacitors, minimizing PC board area and systems cost. The
programmable soft start reduces current surges at start up. The short
circuit protection timer significantly reduces the duty cycle to
approximately 1/30 of its cycle during short circuit conditions.
The CS51031 is available in 8 Lead SO and 8 Lead PDIP plastic
packages.
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MARKING
DIAGRAMS
8
SO–8
D SUFFIX
CASE 751
51031
ALYW
8
1
1
8
Features
• 1.0 A Totem Pole Output Driver
• High Speed Oscillator (700 kHz max)
• No Stability Compensation Required
• Lossless Short Circuit Protection
DIP–8
N SUFFIX
CASE 626
CS51031
AWL
YYWW
8
1
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
• V Monitor
CC
• 2.0% Precision Reference
• Programmable Soft Start
WW, W = Work Week
• Wide Ambient Temperature Range:
– Industrial Grade: –40°C to 85°C
– Commercial Grade: 0°C to 70°C
PIN CONNECTIONS
1
5.0 V–12 V
V
GATE
V
C
PGND
CS
C
IN
47 µF
C
V
CC
V
FB
OSC
20 Ω
GND
MP
1
IRF7416
V
GATE
MBRS360
V
GATE
V
C
ORDERING INFORMATION*
D
1
Device
Package
SO–8
Shipping
95 Units/Rail
PGND
CS
CS51031YD8
CS51031YDR8
CS51031YN8
CS51031GD8
CS51031GDR8
RV
CC
CS
0.1 µF
10 Ω
SO–8
2500 Tape & Reel
50 Units/Rail
L
C
V
CC
OSC
CV
4.7 µH
CC
C
100 µF
.01 µF
DIP–8
SO–8
OSC
100 pF
100
R
B
95 Units/Rail
GND
V
FB
V
O
2.5 kΩ
3.3 V @ 3 A
SO–8
2500 Tape & Reel
C
RR
*Additional ordering information can be found on
page 9 of this data sheet.
0.1 µF
C
O
R
A
100 µF × 2
1.5 kΩ
Figure 1. Typical Application Diagram
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
May, 2001 – Rev. 8
CS51031/D
CS51031
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
20
Unit
V
Power Supply Voltage, V
CC
Driver Supply Voltage, V
Driver Output Voltage, V
20
V
C
20
V
GATE
C
, CS, V (Logic Pins)
6.0
V
OSC
FB
Peak Output Current
1.0
A
Steady State Output Current
Operating Junction Temperature, T
200
mA
°C
°C
°C
kV
150
J
Operating Temperature Range, T
–40 to 85
–65 to 150
2.0
A
Storage Temperature Range, T
ESD (Human Body Model)
Lead Temperature Soldering:
S
Wave Solder: (through hole styles only) (Note 1.)
Reflow (SMD styles only) (Note 2.)
260 peak
230 peak
°C
°C
1. 10 sec. maximum.
2. 60 sec. max above 183°C.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (Specifications apply for 4.5 ≤ V ≤ 16 V, 3.0 V ≤ V ≤ 16 V;
CC
C
Industrial Grade: –40°C < T < 85°C; –40°C < T < 125°C: Commercial Grade: 0°C < T < 70°C; 0°C < T < 125°C, unless otherwise specified.)
A
J
A
J
Characteristic
Test Conditions
Min
Typ
Max
Unit
Oscillator
V
FB
= 1.2 V
Frequency
C
= 470 pF
160
–
200
110
660
83.3
240
–
kHz
µA
µA
%
OSC
Charge Current
1.4 V < V
2.7 V > V
< 2.0 V
> 2.0 V
COSC
COSC
Discharge Current
Maximum Duty Cycle
Short Circuit Timer
Charge Current
–
–
1 – (t
/t
)
80.0
–
OFF ON
V
= 1.0 V; CS = 0.1 mF; V
= 2.0 V
FB
COSC
1.0 V < V < 2.0 V
175
40
264
66
325
80
µA
µA
µA
ms
ms
ms
%
CS
Fast Discharge Current
Slow Discharge Current
Start Fault Inhibit Time
Valid Fault Time
2.55 V > V > 2.4 V
CS
2.4 V > V > 1.5 V
4.0
0.70
0.2
9.0
2.5
6.0
0.85
0.3
15
10
CS
0 V < V < 2.5 V
1.40
0.45
23
CS
2.6 V > V > 2.4 V
CS
GATE Inhibit Time
2.4 V > V > 1.5 V
CS
Fault Duty Cycle
–
–
3.1
4.6
CS Comparator
V
FB
= 1.0 V
Fault Enable CS Voltage
Max. CS Voltage
–
–
2.5
2.6
–
–
V
V
V
V
V
V
V
FB
= 1.5 V
Fault Detect Voltage
Fault Inhibit Voltage
Hold Off Release Voltage
Regulator Threshold Voltage Clamp
V
CS
when GATE goes high
–
2.4
–
Minimum V
–
1.5
–
CS
V
FB
V
CS
= 0 V
0.4
0.725
0.7
1.0
1.035
= 1.5 V
0.866
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2
CS51031
ELECTRICAL CHARACTERISTICS (continued) (Specifications apply for 4.5 ≤ V ≤ 16 V, 3.0 V ≤ V ≤ 16 V;
CC
C
Industrial Grade: –40°C < T < 85°C; –40°C < T < 125°C: Commercial Grade: 0°C < T < 70°C; 0°C < T < 125°C, unless otherwise specified.)
A
J
A
J
Characteristic
Test Conditions
= V = 2.0 V
Min
Typ
Max
Unit
V
FB
Comparators
V
COSC
CS
Regulator Threshold Voltage
T = 25°C (Note 3.)
T = –40 to 125°C
J
1.225
1.210
1.250
1.250
1.275
1.290
V
V
J
Fault Threshold Voltage
T = 25°C (Note 3.)
T = –40 to 125°C
J
1.12
1.10
1.15
1.15
1.17
1.19
V
V
J
Threshold Line Regulation
Input Bias Current
4.5 V ≤ V ≤ 16 V
–
–
6.0
1.0
100
4.0
15
4.0
120
20
mV
µA
CC
V
FB
= 0 V
Voltage Tracking
(Regulator Threshold – Fault Threshold Voltage)
–
70
–
mV
mV
Input Hysteresis Voltage
Power Stage
V
CC
= V = 10 V; V = 1.2 V
C FB
GATE DC Low Saturation Voltage
GATE DC High Saturation Voltage
Rise Time
V
= 1.0 V; 200 mA Sink
–
–
–
–
1.2
1.5
25
1.5
2.1
60
V
V
COSC
COSC
V
= 2.7 V; 200 mA Source; V = V
C GATE
C
C
= 1.0 nF; 1.5 V < V
= 1.0 nF; 9.0 V > V
< 9.0 V
> 1.5 V
ns
ns
GATE
GATE
GATE
GATE
Fall Time
25
60
V
CC
Monitor
Turn On Threshold
Turn Off Threshold
Hysteresis
–
–
–
4.200
4.085
65
4.400
4.300
130
4.600
4.515
200
V
V
mV
Current Drain
I
I
4.5 V < V < 16 V, Gate switching
–
–
–
4.5
2.7
6.0
4.0
mA
mA
µA
CC
C
CC
3.0 V < V < 16 V, Gate non–switching
C
Shutdown I
V
CC
= 4.0
500
900
CC
3. Guaranteed by design, not 100% tested in production.
PACKAGE LEAD DESCRIPTION
PACKAGE PIN NUMBER
SO–8
DIP–8
PIN SYMBOL
FUNCTION
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
V
Driver pin to gate of external PFET.
Output power stage ground connection.
Oscillator frequency programming capacitor.
Logic ground.
GATE
PGND
C
OSC
GND
V
Feedback voltage input.
FB
V
Logic supply voltage.
CC
CS
Soft start and fault timing capacitor.
Driver supply voltage.
V
C
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3
CS51031
V
V
C
V
REF
RG
I
C
Oscillator
Comparator
V
GATE
GATE
+
C
Flip–Flop
OSC
A1
7I
C
G1
R
Q
–
F2
PGND
S
Q
V
G2
+
–
+
FB
Comparator
–
+
1.5 V
2.5 V
–
V
FB
A6
1.25 V
+
–
+ 0.7 V
+
Hold Off
Comp
–
V
CC
–
V
REF
V
CC
V
CC
OK
3.3 V
–
+
Fault
Comp
1.15 V
+
–
CS Charge
Sense
Comparator
G4
V
REF
= 3.3 V
G3
A4
–
+
–
I
CS
Comparator
T
2.3 V
+
CS
A2
R
S
Q
Q
–
F1
I
T
I
T
5
G5
+
–
+
–
55
1.5 V
2.5 V
Slow Discharge
Flip–Flop
–
A3
+
Slow Discharge
Comparator
+
–
2.4 V
GND
Figure 2. Block Diagram
CIRCUIT DESCRIPTION
THEORY OF OPERATION
duration of the charge time. The PFET gets turned off and
remains off during the oscillator’s discharge time with the
maximum duty cycle to 80%. It requires 7.0 mV typical, and
Control Scheme
The CS51031 monitors and the output voltage to
20 mV maximum ripple on the V pin is required to
FB
determine when to turn on the PFET. If V falls below the
FB
operate. This method of control does not require any loop
stability compensation.
internal reference voltage of 1.25 V during the oscillator’s
charge cycle, the PFET is turned on and remains on for the
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4
CS51031
Startup
Lossless Short Circuit Protection
The CS51031 has an externally programmable soft start
feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.
The CS51031 has “lossless” short circuit protection since
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage ) reaches
2.5 V during startup, the fault timing circuitry is enabled.
During normal operation the CS voltage is 2.6 V. During a
short circuit or a transient condition, the output voltage
At startup, the voltage on all pins is zero. As V rises, the
CC
V
voltage along with the internal resistor R keeps the
C
G
PFET off. As V and V continue to rise, the oscillator
CC
C
capacitor (C
) and the Soft Start/Fault Timing capacitor
moves lower and the voltage at V drops. If V drops
OSC
FB FB
(CS) charges via internal current sources. C
by the current source IC and CS gets charged by the I source
gets charged
below 1.15 V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
OSC
T
combination described by:
timing capacitor, CS, discharges to 2.4 V. If the V voltage
FB
is still below 1.15 V when the CS pin reaches 2.4 V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which sets
I
55
I
T
5
T
* ǒ
Ǔ
I
+ I
)
CS
T
The internal Holdoff Comparator ensures that the external
the slow discharge flip flop. The V
flip flop resets and
GATE
PFET is off until V > 0.7 V, preventing the GATE flip–flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
the output switch is turned off. The fault timing capacitor is
slowly discharged to 1.5 V. The CS51031 then enters a
normal startup routine. If the fault is still present when the
fault timing capacitor voltage reaches 2.5 V, the fast and
slow discharge cycles repeat as shown in figure 3.
CS
start is obtained by clamping the V comparator’s (A6)
FB
reference input to approximately 1/2 of the voltage at the CS
pin during startup, permitting the control loop and the output
voltage to slowly increase. Once the CS pin charges above
the Holdoff Comparator trip point of 0.7 V, the low feedback
If the V voltage is above 1.15 V when CS reaches
FB
2.4 V a fault condition is not detected, normal operation
resumes and CS charges back to 2.6 V. This reduces the
chance of erroneously detecting a load transient as a fault
condition.
to the V Comparator sets the GATE flip–flop during
FB
C
OSC
’s charge cycle. Once the GATE flip–flop is set,
V
GATE
goes low and turns on the PFET. When V exceeds
CS
2.4 V, the CS charge sense comparator (A4) sets the V
FB
comparator reference to 1.25 V completing the startup cycle.
2.6 V
S2
2.5 V
0 V
S2
S1
V
CS
S2
2.4 V
S3
S3
S1
S1
S3
S3
1.5 V
0 V
T
td1
t
t
td2
t
FAULT
START
FAULT
RESTART
START
NORMAL OPERATION
FAULT
V
GATE
1.25 V
1.15 V
V
FB
Figure 3. Voltage on Start Capacitor (VGS), the Gate (VGATE), and in the
Feedback Loop (VFB), During Startup, Normal and Fault Conditions.
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5
CS51031
Buck Regulator Operation
and R2 and the reference voltage V , the power transistor
REF
A block diagram of a typical buck regulator is shown in
Figure 4. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
Q1 switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(V – V
)/L. The duty cycle (or “on” time) for the
OUT
IN
inductor current I is zero and the output voltage is at its
CS51031 is limited to 80%. If output voltage remains higher
than nominal during the entire C change time, the Q1
does not turn on, skipping the pulse.
L
nominal value. The current drawn by the load is supplied by
the output capacitor C . When the voltage across C drops
OSC
O
O
below the threshold established by the feedback resistors R1
L
Q
1
V
IN
R
R
1
2
C
IN
C
R
LOAD
O
D
1
Control
Feedback
Figure 4. Buck Regulator Block Diagram.
APPLICATIONS INFORMATION
CS51031 DESIGN EXAMPLE
5.6
9.0
D
+
+ 0.62
+ 0.40
MAX
Specifications 12 V to 5.0 V, 3.0 A Buck Controller
5.6
13.8
• V = 12 V ±20% (i.e. 14.4 V max., 12 V nom., 9.6 V
IN
min.)
D
+
MIN
• V
• I
= 5.0 V ±2%
OUT
2) Switching Frequency and On and Off Time
Calculations
= 0.3 A to 3.0 A
OUT
• Output ripple voltage < 50 mV max.
• Efficiency > 80%
Given that f = 200 kHz and D
= 0.80
SW
MAX
1.0
T +
+ 5.0 ms
• f = 200 kHz
SW
f
SW
1) Duty Cycle Estimates
T
+ T D
+ T D
+ 5.0 ms 0.62 ^ 3.0 ms
+ 5.0 ms 0.40 ^ 2.0 ms
ON(max)
MAX
Since the maximum duty cycle D, of the CS51031 is
limited to 80% min., it is necessary to estimate the duty cycle
for the various input conditions over the complete operating
range.
The duty cycle for a buck regulator operating in a
continuous conduction mode is given by:
T
ON(min)
MIN
T
+ T
+ 5.0 ms * 2.0 ms + 3.0 ms
ON(min)
OFF(max)
3) Oscillator Capacitor Selection
The switching frequency is set by C
given by:
V
) V
F
SAT
OUT
* V
, whose value is
OSC
D +
V
IN
where:
*6
95 10
C
in pF +
OSC
V
SAT
= R
× I
max. and R
is the value at T
2
ds(on)
OUT
ds(on) J
3
F
30 10
SW
* ǒ
Ǔ
SWǒ1 )
Ǔ
F
6
100°C.
F
3 10
SW
If V = 0.60 V and V
= 0.60 V then the above equation
F
SAT
becomes:
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6
CS51031
4) Inductor Selection
6) VFB Divider
The inductor value is chosen for continuous mode
operation down to 0.3 Amps.
R1 ) R2
R1
ǒ
R2
+ 1.25 Vǒ
Ǔ + 1.25 V
) 1.0Ǔ
V
OUT
R2
The ripple current ∆I = 2 × I min = 2 × 0.3 A = 0.6 A.
OUT
The input bias current to the comparator is 4.0 µA. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this permits a divider current of 1mA and simplifies
the calculations.
(
)
) V T
D
V
5.6 V 3.0 ms
OUT
OFF(max)
L
+
+
+ 28 mH
min
DI
0.6 A
This is the minimum value of inductor to keep the ripple
current < 0.6 A during normal operation.
A smaller inductor will result in larger ripple current.
Ripple current at a minimum off time is
5.0 V
1.0 mA
+ R1 ) R2 + 5.0 KW
(
)
F
V
) V T
5.6 V 2.0 ms
28 mH
OUT
OFF(min)
DI +
+
+ 0.4 A
L
MIN
Let R2 = 1.0 K
Rearranging the divider equation gives:
The core must not saturate with the maximum expected
current, here given by:
V
5.0 V
1.25
OUT
R1 + R2ǒ
* 1.0Ǔ+ 1.0 kW
ǒ
* 1.0Ǔ+ 3.0 kW
1.25
I
+ I ) DIń2 + 3.0 A ) 0.4 Ań2 + 3.2 A
OUT
MAX
7) Divider Bypass Capacitor CRR
5) Output Capacitor
Since the feedback resistors divide the output voltage by
a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0 × 15 mV) to trip the
The output capacitor and the inductor form a low pass
filter. The output capacitor should have a low ESL and ESR.
Low impedance aluminum electrolytic, tantalum or organic
semiconductor capacitors are a good choice for an output
capacitor. Low impedance aluminum are less expensive.
Solid tantalum chip capacitors are available from a number
of suppliers and are the best choice for surface mount
applications.
feedback comparator. We use a capacitor C to act as an
RR
AC short.
The ripple voltage frequency is equal to the switching
frequency so we choose C = 1.0 nF.
RR
The output capacitor limits the output ripple voltage. The
CS51031 needs a maximum of 20 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak to peak is given by:
8) Soft Start and Fault Timing Capacitor CS
CS performs several important functions. First it provides
a delay time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
soft start by clamping the reference voltage during startup,
allowing it to rise slowly, and, finally it controls the hiccup
short circuit protection circuitry. This reduces the duty cycle
to approximately 0.035 during short circuit conditions.
An important consideration in calculating CS is that it’s
voltage does not reach 2.5 V (the voltage at which the fault
0.6 A
DI
C +
+
+ 7.5mF
3
*3
)
V
(
)
(
8.0 f
DV
8.0 200 10 Hz 50 10
SW
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak to peak is:
detect circuitry is enabled) before V reaches 1.15 V
FB
*3
0.6 A
otherwise the power supply will never start.
50 10
DV
DI
ESR +
+
+ 83 mW
If the V pin reaches 1.15 V, the fault timing comparator
FB
will discharge CS and the supply will not start. For the V
voltage to reach 1.15 V the output voltage must be at least
4 × 1.15 = 4.6 V.
If we choose an arbitrary startup time of 900 µs, the value
of CS is:
FB
The output capacitor should be chosen so that its ESR is
less than 83 mΩ.
During the minimum off time, the ripple current is 0.4 A
and the output voltage ripple will be:
DV + ESR DI + 83m W 0.4 + 33 mV
CS 2.5 V
Charge
t
+
Startup
I
900 ms 264 mA
CS
+
+ 950 nF ^ 0.1 mF
min
2.5 V
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7
CS51031
9) Input Capacitor
The fault time is the sum of the slow discharge time the
fast discharge time and the recharge time. It is dominated by
the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage on
the V and V pins. This capacitor must also ensure that
CC
C
the V remains above the UVLO voltage in the event of an
CC
output short circuit. A low ESR capacitor of at least 100 µF
is good. A ceramic surface mount capacitor should also be
(
)
CS 2.4 V * 1.5 V
connected between V and ground to filter high frequency
t
+
CC
SlowDischarge(t)
I
Discharge
noise.
where I
is 6.0 µA typical.
Discharge
10) MOSFET Selection
The CS51031 drives a P–channel MOSFET. The V
GATE
5
+ CS 1.5 10
t
SlowDischarge(t)
pin swings from GND to V . The type of PFET used
C
depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.
The fast discharge time occurs when a fault is first
detected. The CS capacitor is discharged from 2.5 V to 2.4 V.
A PFET with a continuous drain current (I ) rating greater
D
(
)
CS 2.5 V * 2.4 V
than the maximum output current is required.
t
+
FastDischarge(t)
I
FastDischarge
The Gate–to–Source voltage V
and the Drain–to
GS
Source Breakdown Voltage should be chosen based on the
input supply voltage.
where I
is 66 µA typical.
FastDischarge
The power dissipation due to the conduction losses is
given by:
t
+ CS 1515
FastDischarge(t)
The recharge time is the time for CS to charge from 1.5 V
to 2.5 V.
2
P
+ I
OUT
R
D
DS(ON)
D
(
I
)
CS 2.5 V * 1.5 V
where
t
+
Charge(t)
Charge
R
is the value at T + 100°C
DS(ON)
J
where I
is 264 µA typical.
Charge
The power dissipation of the PFET due to the switching
losses is given by:
t
+ CS 3787
Charge(t)
( )
t f
SW
P
+ 0.5 V I
IN OUT
The fault time is given by:
D
r
5
( )
+ CS 3787 ) 1515 ) 1.5 10
where t = Rise Time.
t
r
Fault
11) Diode Selection
5
( )
+ CS 1.55 10
t
Fault
The flyback or catch diode should be a Schottky diode
because of it’s fast switching ability and low forward voltage
drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should be
at least 20 V for this 12 V application.
For this circuit
*6
+ 0.1 10
5
1.55 10 + 15.5 ms
t
Fault
A larger value of CS will increase the fault time out time
but will also increase the soft start time.
The diode power dissipation is given by:
(
+ I V 1.0 * D
OUT D min
)
P
D
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8
CS51031
ORDERING INFORMATION
Operating
Temperature Range
Device
Package
SO–8
Shipping
95 Units/Rail
CS51031YD8
CS51031YDR8
CS51031YN8
CS51031GD8
CS51031GDR8
–40°C < T < 85°C
A
–40°C < T < 85°C
SO–8
2500 Tape & Reel
50 Units/Rail
A
–40°C < T < 85°C
DIP–8
SO–8
A
0°C < T < 70°C
95 Units/Rail
A
0°C < T < 70°C
SO–8
2500 Tape & Reel
A
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9
CS51031
PACKAGE DIMENSIONS
SO–8
D SUFFIX
CASE 751–07
ISSUE V
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
–Y–
G
MILLIMETERS
INCHES
DIM MIN
MAX
5.00
4.00
1.75
0.51
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
4.80
3.80
1.35
0.33
0.189
0.150
0.053
0.013
C
N X 45
_
SEATING
PLANE
–Z–
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25
0.25
1.27
8
0.004
0.010
0.010
0.050
8
0.007
0.016
0
M
J
H
D
K
M
N
S
_
_
_
_
0.25
5.80
0.50
6.20
0.010
0.228
0.020
0.244
M
S
S
X
0.25 (0.010)
Z
Y
DIP–8
N SUFFIX
CASE 626–05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
8
5
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–B–
MILLIMETERS
INCHES
MIN
1
4
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
–A–
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
K
L
C
7.62 BSC
0.300 BSC
M
N
---
0.76
10
_
1.01
---
0.030
10
0.040
_
J
–T–
SEATING
PLANE
N
M
D
K
G
H
M
M
M
B
0.13 (0.005)
T A
PACKAGE THERMAL DATA
Parameter
SO–8
45
DIP–8
52
Unit
°C/W
°C/W
R
R
Typical
Typical
Θ
Θ
JC
JA
165
100
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10
CS51031
Notes
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11
CS51031
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