CS51031GD8G [ONSEMI]
Fast P−Ch FET Buck Controller; 快速P沟道FET降压控制器
| 型号： | CS51031GD8G |
| 厂家： | 
ONSEMI |
| 描述： | Fast P−Ch FET Buck Controller |
| 文件： | 总10页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS51031
Fast P−Ch FET
Buck Controller
The CS51031 is a switching controller for use in DC−DC
converters. It can be used in the buck topology with a minimum
number of external components. The CS51031 consists of a V
CC
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monitor for controlling the state of the device, 1.0 A power driver for
controlling the gate of a discrete P−Channel transistor, fixed frequency
oscillator, short circuit protection timer, programmable Soft−Start,
precision reference, fast output voltage monitoring comparator, and
output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and
output capacitors, minimizing PC board area and systems cost. The
programmable Soft−Start reduces current surges at startup. The short
circuit protection timer significantly reduces the duty cycle to
approximately 1/30 of its cycle during short circuit conditions.
8
1
SOIC−8
D SUFFIX
CASE 751
Features
• 1.0 A Totem Pole Output Driver
• High Speed Oscillator (700 kHz max)
• No Stability Compensation Required
• Lossless Short Circuit Protection
MARKING DIAGRAM
8
• V Monitor
CC
51031
ALYWx
G
• 2.0% Precision Reference
• Programmable Soft−Start
• Wide Ambient Temperature Range:
♦ Industrial Grade: −40°C to 85°C
♦ Commercial Grade: 0°C to 70°C
1
• Pb−Free Packages are Available
51031 = Device Code
A
L
= Assembly Location
= Wafer Lot
5.0 V−12 V
Y
W
x
= Year
= Work Week
= Continuation of Device Code
x = Y or G
= Pb−Free Package
C
47 mF
IN
MP
1
G
IRF7416
V
GATE
MBRS360
V
V
C
GATE
PIN CONNECTIONS
D
1
PGND
CS
1
RV
100 W
V
V
CC
GATE
C
CS
0.1 mF
PGND
CS
L
C
OSC
V
CC
CV
0.1 mF
4.7 mH
CC
C
V
CC
V
FB
OSC
C
OSC
GND
470 pF
R
B
GND
V
FB
V
O
2.5 kW
3.3 V @ 3 A
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
C
0.1 mF
RR
C
O
R
A
100 mF × 2
1.5 kW
Figure 1. Typical Application Diagram
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
October, 2005 − Rev. 11
CS51031/D
CS51031
ORDERING INFORMATION
Operating
Temperature Range
†
Device
CS51031YD8
Package
Shipping
SOIC−8
98 Units / Rail
98 Units / Rail
CS51031YD8G
SOIC−8
(Pb−Free)
−40°C < T < 85°C
A
CS51031YDR8
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
CS51031YDR8G
SOIC−8
(Pb−Free)
CS51031GD8
SOIC−8
98 Units / Rail
98 Units / Rail
CS51031GD8G
SOIC−8
(Pb−Free)
0°C < T < 70°C
A
CS51031GDR8
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
CS51031GDR8G
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
Rating
Value
20
Unit
V
Power Supply Voltage, V
CC
Driver Supply Voltage, V
Driver Output Voltage, V
20
V
C
20
V
GATE
C
OSC
, CS, V (Logic Pins)
6.0
V
FB
Peak Output Current
1.0
A
Steady State Output Current
Operating Junction Temperature, T
200
mA
°C
°C
°C
kV
150
J
Operating Temperature Range, T
−40 to 85
−65 to 150
2.0
A
Storage Temperature Range, T
S
ESD (Human Body Model)
Lead Temperature Soldering:
Wave Solder: (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
260 peak
230 peak
°C
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 10 sec. maximum.
2. 60 sec. max above 183°C.
PACKAGE LEAD DESCRIPTION
Package Pin Number
Pin Symbol
Function
Driver pin to gate of external P−Ch FET.
1
2
3
4
5
6
7
8
V
GATE
PGND
Output power stage ground connection.
Oscillator frequency programming capacitor.
Logic ground.
C
OSC
GND
V
Feedback voltage input.
FB
V
Logic supply voltage.
CC
CS
Soft−Start and fault timing capacitor.
Driver supply voltage.
V
C
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2
CS51031
ELECTRICAL CHARACTERISTICS (Specifications apply for 4.5 ≤ V ≤ 16 V, 3.0 V ≤ V ≤ 16 V;
CC
C
Industrial Grade: −40°C < T < 85°C; −40°C < T < 125°C: Commercial Grade: 0°C < T < 70°C; 0°C < T < 125°C, unless otherwise specified.)
A
J
A
J
Characteristic
Test Conditions
Min
Typ
Max
Unit
Oscillator
V
= 1.2 V
FB
Frequency
C
= 470 pF
160
−
200
110
240
−
kHz
mA
mA
%
OSC
Charge Current
1.4 V < V
< 2.0 V
> 2.0 V
COSC
COSC
Discharge Current
2.7 V > V
1 − (t /t
−
660
83.3
−
Maximum Duty Cycle
Short Circuit Timer
Charge Current
)
80.0
−
OFF ON
V
= 1.0 V; CS = 0.1 mF; V
= 2.0 V
COSC
FB
1.0 V < V < 2.0 V
175
40
264
66
325
80
mA
mA
mA
ms
ms
ms
%
CS
Fast Discharge Current
Slow Discharge Current
Start Fault Inhibit Time
Valid Fault Time
2.55 V > V > 2.4 V
CS
2.4 V > V > 1.5 V
4.0
0.70
0.2
9.0
2.5
6.0
0.85
0.3
15
10
CS
0 V < V < 2.5 V
1.40
0.45
23
CS
2.6 V > V > 2.4 V
CS
GATE Inhibit Time
2.4 V > V > 1.5 V
CS
Fault Duty Cycle
−
−
3.1
4.6
CS Comparator
V
= 1.0 V
FB
Fault Enable CS Voltage
Max CS Voltage
−
−
2.5
2.6
−
−
V
V
V
V
V
V
V
= 1.5 V
FB
CS
Fault Detect Voltage
Fault Inhibit Voltage
Hold Off Release Voltage
Regulator Threshold Voltage Clamp
V
when GATE goes high
−
2.4
−
Minimum V
−
1.5
−
CS
V
V
= 0 V
0.4
0.725
0.7
1.0
1.035
FB
CS
= 1.5 V
= V = 2.0 V
0.866
V
Comparators
V
COSC
FB
CS
Regulator Threshold Voltage
T = 25°C (Note 3)
T = −40 to 125°C
J
1.225
1.210
1.250
1.250
1.275
1.290
V
V
J
Fault Threshold Voltage
T = 25°C (Note 3)
T = −40 to 125°C
J
1.12
1.10
1.15
1.15
1.17
1.19
V
V
J
Threshold Line Regulation
Input Bias Current
4.5 V ≤ V ≤ 16 V
−
−
6.0
1.0
100
4.0
15
4.0
120
20
mV
mA
CC
V
= 0 V
FB
Voltage Tracking
(Regulator Threshold − Fault Threshold Voltage)
−
70
−
mV
mV
Input Hysteresis Voltage
Power Stage
V
= V = 10 V; V = 1.2 V
C FB
CC
GATE DC Low Saturation Voltage
GATE DC High Saturation Voltage
Rise Time
V
= 1.0 V; 200 mA Sink
−
−
−
−
1.2
1.5
25
1.5
2.1
60
V
V
COSC
COSC
V
= 2.7 V; 200 mA Source; V = V
C GATE
C
C
= 1.0 nF; 1.5 V < V
= 1.0 nF; 9.0 V > V
< 9.0 V
> 1.5 V
ns
ns
GATE
GATE
GATE
Fall Time
25
60
GATE
V
Monitor
CC
Turn−On Threshold
Turn−Off Threshold
Hysteresis
−
−
−
4.200
4.085
65
4.400
4.300
130
4.600
4.515
200
V
V
mV
Current Drain
I
I
4.5 V < V < 16 V, Gate switching
−
−
−
4.5
2.7
500
6.0
4.0
900
mA
mA
mA
CC
C
CC
3.0 V < V < 16 V, Gate non−switching
C
Shutdown I
V
= 4.0
CC
CC
3. Guaranteed by design, not 100% tested in production.
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3
CS51031
V
V
C
V
REF
RG
I
C
C
Oscillator
Comparator
V
GATE
GATE
+
C
OSC
Flip−Flop
A1
7I
G1
Q
R
−
F2
PGND
Q
S
V
FB
Comparator
G2
+
−
+
−
+
1.5 V
2.5 V
−
V
FB
A6
1.25 V
+
−
0.7 V
+
−
+
−
Hold Off
Comp
V
CC
V
REF
V
V
OK
CC
CC
3.3 V
−
+
Fault
Comp
1.15 V
+
−
CS Charge
Sense
Comparator
G4
V
= 3.3 V
REF
G3
A4
−
+
−
I
CS
Comparator
T
2.3 V
+
CS
A2
Q
Q
R
S
−
F1
I
I
T
5
T
G5
+
−
+
−
55
1.5 V
2.5 V
Slow Discharge
Flip−Flop
−
A3
+
Slow Discharge
Comparator
+
−
2.4 V
GND
Figure 2. Block Diagram
CIRCUIT DESCRIPTION
THEORY OF OPERATION
duration of the charge time. The P−Ch FET gets turned off
and remains off during the oscillator’s discharge time with
the maximum duty cycle to 80%. It requires 7.0 mV typical,
Control Scheme
The CS51031 monitors the output voltage to determine
and 20 mV maximum ripple on the V pin is required to
FB
when to turn on the P−Ch FET. If V falls below the internal
FB
operate. This method of control does not require any loop
stability compensation.
reference voltage of 1.25 V during the oscillator’s charge
cycle, the P−Ch FET is turned on and remains on for the
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4
CS51031
Startup
comparator (A4) sets the V comparator reference to
FB
The CS51031 has an externally programmable Soft−Start
1.25 V completing the startup cycle.
feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.
Lossless Short Circuit Protection
The CS51031 has “lossless” short circuit protection since
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage) reaches
2.5 V during startup, the fault timing circuitry is enabled by
A2. During normal operation the CS voltage is 2.6 V. During
a short circuit or a transient condition, the output voltage
At startup, the voltage on all pins is zero. As V rises, the
CC
V
C
voltage along with the internal resistor R keeps the
G
P−Ch FET off. As V and V continue to rise, the oscillator
CC
C
capacitor (C
) and the Soft−Start/Fault Timing capacitor
OSC
(CS) charges via internal current sources. C
gets charged
OSC
by the current source IC and CS gets charged by the I source
T
moves lower and the voltage at V drops. If V drops
FB
FB
combination described by:
below 1.15 V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
timing capacitor, CS, discharges to 2.4 V. If the V voltage
is still below 1.15 V when the CS pin reaches 2.4 V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which sets
I
I
T
5
T
* ǒ
Ǔ
I
+ I
)
CS
T
55
FB
The internal Holdoff Comparator ensures that the external
P−Ch FET is off until V > 0.7 V, preventing the GATE
CS
flip−flop (F2) from being set. This allows the oscillator to
reach its operating frequency before enabling the drive
the slow discharge flip−flop. The V
flip−flop resets and
GATE
output. Soft−Start is obtained by clamping the V
FB
the output switch is turned off. The fault timing capacitor is
slowly discharged to 1.5 V. The CS51031 then enters a
normal startup routine. If the fault is still present when the
fault timing capacitor voltage reaches 2.5 V, the fast and
slow discharge cycles repeat as shown in figure 3.
comparator’s (A6) reference input to approximately 1/2 of
the voltage at the CS pin during startup, permitting the
control loop and the output voltage to slowly increase. Once
the CS pin charges above the Holdoff Comparator trip point
of 0.7 V, the low feedback to the V Comparator sets the
FB
If the V voltage is above 1.15 V when CS reaches 2.4 V
FB
GATE flip−flop during C
’s charge cycle. Once the
goes low and turns on the
OSC
a fault condition is not detected, normal operation resumes
and CS charges back to 2.6 V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
GATE flip−flop is set, V
GATE
P−Ch FET. When V exceeds 2.3 V, the CS charge sense
CS
2.6 V
S2
2.5 V
0 V
S2
S1
V
S2
CS
2.4 V
S3
S3
S1
S1
S3
S3
1.5 V
0 V
0.7 V
T
td1
t
t
td2
t
FAULT
START
FAULT
RESTART
START
NORMAL OPERATION
FAULT
V
GATE
1.25 V
1.15 V
V
FB
Figure 3. Voltage on Start Capacitor (VGS), the Gate (VGATE), and in the
Feedback Loop (VFB), During Startup, Normal and Fault Conditions
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5
CS51031
Buck Regulator Operation
and R2 and the reference voltage V , the power transistor
REF
A block diagram of a typical buck regulator is shown in
Figure 4. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
Q1 switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(V − V
)/L. The duty cycle (or “on” time) for the
IN
OUT
inductor current I is zero and the output voltage is at its
CS51031 is limited to 80%. If output voltage remains higher
than nominal during the entire C change time, the Q1
does not turn on, skipping the pulse.
L
nominal value. The current drawn by the load is supplied by
the output capacitor C . When the voltage across C drops
OSC
O
O
below the threshold established by the feedback resistors R1
L
Q
1
V
IN
R
R
1
C
IN
C
O
R
LOAD
D
1
2
Control
Feedback
Figure 4. Buck Regulator Block Diagram
APPLICATIONS INFORMATION
CS51031 DESIGN EXAMPLE
If V = 0.60 V and V
= 0.60 V then the above equation
F
SAT
becomes:
Specifications 12 V to 5.0 V, 3.0 A Buck Controller
5.6
9.0
D
+
+ 0.62
+ 0.40
• V = 12 V 20% (i.e. 14.4 V max, 12 V nom, 9.6 V
MAX
IN
min)
5.6
13.8
D
MIN
+
• V
• I
= 5.0 V 2%
OUT
= 0.3 A to 3.0 A
OUT
2) Switching Frequency and On and Off Time
Calculations
Given that f = 200 kHz and D
• Output ripple voltage < 50 mV max
• Efficiency > 80%
= 0.80
SW
MAX
• f = 200 kHz
SW
1.0
T +
+ 5.0 ms
f
SW
1) Duty Cycle Estimates
T
+ T D
+ 5.0 ms 0.62 ^ 3.0 ms
+ 5.0 ms 0.40 ^ 2.0 ms
Since the maximum duty cycle D, of the CS51031 is
limited to 80% min, it is necessary to estimate the duty cycle
for the various input conditions over the complete operating
range.
The duty cycle for a buck regulator operating in a
continuous conduction mode is given by:
ON(max)
MAX
MIN
T
+ T D
ON(min)
T
+ T
+ 5.0 ms * 2.0 ms + 3.0 ms
ON(min)
OFF(max)
3) Oscillator Capacitor Selection
The switching frequency is set by C
given by:
, whose value is
V
) V
F
SAT
OSC
OUT
* V
D +
V
IN
)6
95 10
where:
C
OSC
in pF +
2
3
F
SW
30 10
V
SAT
= R
× I
max and R is the value at
DS(ON)
DS(ON)
OUT
* ǒ
Ǔ
SWǒ1 )
Ǔ
F
6
F
3 10
SW
T 100°C.
J
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CS51031
4) Inductor Selection
6) VFB Divider
The inductor value is chosen for continuous mode
operation down to 0.3 Amps.
R1 ) R2
R1
R2
+ 1.25 Vǒ
Ǔ + 1.25 V
ǒ
) 1.0Ǔ
V
OUT
R2
The ripple current DI = 2 × I
min = 2 × 0.3 A = 0.6 A.
OUT
The input bias current to the comparator is 4.0 mA. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this permits a divider current of 1.0 mA and
simplifies the calculations.
(
V
)
) V T
D
5.6 V 3.0 ms
OUT
OFF(max)
L
+
+
+ 28 mH
min
DI
0.6 A
This is the minimum value of inductor to keep the ripple
current < 0.6 A during normal operation.
A smaller inductor will result in larger ripple current.
Ripple current at a minimum off time is:
5.0 V
1.0 mA
+ R1 ) R2 + 5.0 KW
(
V
)
F
) V T
5.6 V 2.0 ms
28 mH
OUT
OFF(min)
DI +
+
+ 0.4 A
Let R2 = 1.0 K
L
MIN
Rearranging the divider equation gives:
The core must not saturate with the maximum expected
current, here given by:
V
OUT
5.0 V
1.25
R1 + R2ǒ
* 1.0Ǔ+ 1.0 kW
ǒ
* 1.0Ǔ+ 3.0 kW
1.25
I
+ I
) DIń2 + 3.0 A ) 0.4 Ań2 + 3.2 A
OUT
MAX
7) Divider Bypass Capacitor CRR
5) Output Capacitor
Since the feedback resistors divide the output voltage by
a factor of 4.0, i.e. 5.0 V/1.25 V = 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0 × 15 mV) to trip the
The output capacitor and the inductor form a low pass
filter. The output capacitor should have a low ESL and ESR.
Low impedance aluminum electrolytic, tantalum or organic
semiconductor capacitors are a good choice for an output
capacitor. Low impedance aluminum are less expensive.
Solid tantalum chip capacitors are available from a number
of suppliers and are the best choice for surface mount
applications.
feedback comparator. We use a capacitor C to act as an
RR
AC short.
The ripple voltage frequency is equal to the switching
frequency so we choose C = 1.0 nF.
RR
The output capacitor limits the output ripple voltage. The
CS51031 needs a maximum of 20 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak−to−peak is given by:
8) Soft−Start and Fault Timing Capacitor CS
CS performs several important functions. First it provides
a delay time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
Soft−Start by clamping the reference voltage during startup,
allowing it to rise slowly, and, finally it controls the hiccup
short circuit protection circuitry. This reduces the duty cycle
to approximately 0.035 during short circuit conditions.
An important consideration in calculating CS is that it’s
voltage does not reach 2.5 V (the voltage at which the fault
DI
0.6 A
C +
+
+ 7.5mF
3
*3
)
V
(
)
(
8.0 f
DV
8.0 200 10 Hz 50 10
SW
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak−to−peak is:
detect circuitry is enabled) before V reaches 1.15 V
otherwise the power supply will never start.
*3
0.6 A
FB
50 10
DV
DI
ESR +
+
+ 83 mW
If the V pin reaches 1.15 V, the fault timing comparator
The output capacitor should be chosen so that its ESR is
less than 83 mW.
FB
will discharge CS and the supply will not start. For the V
FB
voltage to reach 1.15 V the output voltage must be at least
4 × 1.15 = 4.6 V.
During the minimum off time, the ripple current is 0.4 A
and the output voltage ripple will be:
If we choose an arbitrary startup time of 900 ms, the value
of CS is:
DV + ESR DI + 83m W 0.4 + 33 mV
CS 2.5 V
Charge
t
+
Startup
I
900 ms 264 mA
CS
+
+ 950 nF ^ 0.1 mF
min
2.5 V
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CS51031
The fault time is the sum of the slow discharge time the
the V and V pins. This capacitor must also ensure that
CC C
fast discharge time and the recharge time. It is dominated by
the slow discharge time.
the V remains above the UVLO voltage in the event of an
output short circuit. A low ESR capacitor of at least 100 mF
CC
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:
is good. A ceramic surface mount capacitor should also be
connected between V and ground to filter high frequency
CC
noise.
(
)
CS 2.4 V * 1.5 V
10) MOSFET Selection
The CS51031 drives a P−Channel MOSFET. The V
t
+
SlowDischarge(t)
I
Discharge
GATE
pin swings from GND to V . The type of P−Ch FET used
depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.
C
where I
is 6.0 mA typical.
Discharge
5
+ CS 1.5 10
t
SlowDischarge(t)
The fast discharge time occurs when a fault is first
detected. The CS capacitor is discharged from 2.5 V to 2.4 V.
A P−Ch FET with a continuous drain current (I ) rating
greater than the maximum output current is required.
D
The Gate−to−Source voltage V
Source Breakdown Voltage should be chosen based on the
input supply voltage.
and the Drain−to
GS
(
)
CS 2.5 V * 2.4 V
t
+
FastDischarge(t)
I
FastDischarge
where I
is 66 mA typical.
The power dissipation due to the conduction losses is
given by:
FastDischarge
t
+ CS 1515
FastDischarge(t)
2
P
+ I
R
D
DS(ON)
The recharge time is the time for CS to charge from 1.5 V
to 2.5 V.
D
OUT
where
(
I
)
CS 2.5 V * 1.5 V
R
is the value at T + 100°C
The power dissipation of the P−Ch FET due to the
switching losses is given by:
t
+
DS(ON)
J
Charge(t)
Charge
where I
is 264 mA typical.
Charge
t
+ CS 3787
Charge(t)
( )
t f
SW
P
D
+ 0.5 V I
IN
OUT
r
The fault time is given by:
where t = Rise Time.
r
5
( )
+ CS 3787 ) 1515 ) 1.5 10
t
Fault
11) Diode Selection
5
( )
+ CS 1.55 10
t
The flyback or catch diode should be a Schottky diode
because of it’s fast switching ability and low forward voltage
drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should be
at least 20 V for this 12 V application.
Fault
For this circuit
*6
+ 0.1 10
5
1.55 10 + 15.5 ms
t
Fault
A larger value of CS will increase the fault time out time
but will also increase the Soft−Start time.
The diode power dissipation is given by:
(
V 1.0 * D
OUT D min
)
P
D
+ I
9) Input Capacitor
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage on
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8
CS51031
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AG
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
A
8
5
4
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)
Z
Y
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
PACKAGE THERMAL DATA
Parameter
SOIC−8
Unit
R
R
Typical
Typical
45
°C/W
°C/W
q
JC
JA
165
q
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9
CS51031
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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CS51031/D
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