ATMEGA103(L)

更新时间:2024-09-18 02:54:53
品牌:ETC
描述:ATmega103(L) Summary [Updated 9/01. 12 Pages] Not recommended for new design. Replaced by ATmega128

ATMEGA103(L) 概述

ATmega103(L) Summary [Updated 9/01. 12 Pages] Not recommended for new design. Replaced by ATmega128 ATmega103的( L)摘要[更新9/01 。 12页]不建议用于新设计。用ATmega128取代\n

ATMEGA103(L) 数据手册

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Features  
Utilizes the AVR® RISC Architecture  
AVR – High-performance and Low-power RISC Architecture  
– 121 Powerful Instructions – Most Single Clock Cycle Execution  
– 32 x 8 General-purpose Working Registers + Peripheral Control Registers  
– Up to 6 MIPS Throughput at 6 MHz  
Data and Nonvolatile Program Memory  
– 128K Bytes of In-System Programmable Flash  
Endurance: 1,000 Write/Erase Cycles  
– 4K Bytes Internal SRAM  
– 4K Bytes of In-System Programmable EEPROM  
Endurance: 100,000 Write/Erase Cycles  
– Programming Lock for Flash Program and EEPROM Data Security  
– SPI Interface for In-System Programming  
Peripheral Features  
8-bit  
Microcontroller  
with 128K Bytes  
In-System  
Programmable  
Flash  
– On-chip Analog Comparator  
– Programmable Watchdog Timer with On-chip Oscillator  
– Programmable Serial UART  
– Master/Slave SPI Serial Interface  
– Real-time Counter (RTC) with Separate Oscillator  
– Two 8-bit Timer/Counters with Separate Prescaler and PWM  
– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,  
Capture Modes and Dual 8-, 9-, or 10-bit PWM  
– Programmable Watchdog Timer with On-chip Oscillator  
– 8-channel, 10-bit ADC  
Special Microcontroller Features  
ATmega103(L)  
Summary  
– Low-power Idle, Power-save and Power-down Modes  
– Software Selectable Clock Frequency  
– External and Internal Interrupt Sources  
Specifications  
– Low-power, High-speed CMOS Process Technology  
– Fully Static Operation  
Power Consumption at 4 MHz, 3V, 25°C  
– Active: 5.5 mA  
– Idle Mode: 1.6 mA  
– Power-down Mode: < 1 µA  
I/O and Packages  
– 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines  
– 64-lead TQFP  
Operating Voltages  
– 2.7 - 3.6V for ATmega103L  
– 4.0 - 5.5V for ATmega103  
Speed Grades  
– 0 - 4 MHz for ATmega103L  
– 0 - 6 MHz for ATmega103  
Rev. 0945GS–09/01  
Note: This is a summary document. A complete document is  
available on our web site at www.atmel.com.  
Pin Configuration  
TQFP  
2
ATmega103(L)  
0945GS–09/01  
ATmega103(L)  
Description  
The ATmega103(L) is a low-power, CMOS, 8-bit microcontroller based on the AVR  
RISC architecture. By executing powerful instructions in a single clock cycle, the  
ATmega103(L) achieves throughputs approaching 1 MIPS per MHz, allowing the sys-  
tem designer to optimize power consumption versus processing speed.  
The AVR core is based on an enhanced RISC architecture that combines a rich instruc-  
tion set with 32 general-purpose working registers. All the 32 registers are directly  
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be  
accessed in one single instruction executed in one clock cycle. The resulting architec-  
ture is more code efficient while achieving throughputs up to ten times faster than  
conventional CISC microcontrollers.  
The ATmega103(L) provides the following features: 128K bytes of In-System Program-  
mable Flash, 4K bytes EEPROM, 4K bytes SRAM, 32 general-purpose I/O lines, 8 input  
lines, 8 output lines, 32 general-purpose working registers, real-time counter (RTC), 4  
flexible timer/counters with compare modes and PWM, UART, programmable watchdog  
timer with internal oscillator, an SPI serial port and 3 software-selectable power saving  
modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port  
and interrupt system to continue functioning. The Power-down mode saves the register  
contents but freezes the oscillator, disabling all other chip functions until the next inter-  
rupt or hardware reset. In Power-save mode, the timer oscillator continues to run,  
allowing the user to maintain a timer base while the rest of the device is sleeping.  
The device is manufactured using Atmel’s high-density nonvolatile memory technology.  
The On-chip ISP Flash allows the program memory to be reprogrammed in-system  
through a serial interface or by a conventional nonvolatile memory programmer. By  
combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the  
Atmel ATmega103(L) is a powerful microcontroller that provides a highly flexible and  
cost-effective solution to many embedded control applications.  
The ATmega103(L) AVR is supported with a full suite of program and system develop-  
ment tools including: C compilers, macro assemblers, program debugger/simulators, in-  
circuit emulators and evaluation kits.  
3
0945GS–09/01  
Block Diagram  
Figure 1. The ATmega103(L) Block Diagram  
PF0 - PF7  
PA0 - PA7  
PC0 - PC7  
VCC  
GND  
PORTF BUFFERS  
PORTA DRIVER/BUFFERS  
PORTC DRIVERS  
AVCC  
DATA REGISTER  
PORTC  
DATA REGISTER  
PORTA  
DATA DIR.  
REG. PORTA  
ANALOG MUX  
ADC  
8-BIT DATA BUS  
AGND  
AREF  
XTAL1  
INTERNAL  
OSCILLATOR  
OSCILLATOR  
OSCILLATOR  
XTAL1  
PROGRAM  
COUNTER  
STACK  
POINTER  
WATCHDOG  
TIMER  
TOSC2  
TIMING AND  
CONTROL  
TOSC1  
PROGRAM  
FLASH  
MCU CONTROL  
REGISTER  
SRAM  
RESET  
ALE  
INSTRUCTION  
REGISTER  
TIMER/  
COUNTERS  
GENERAL  
PURPOSE  
REGISTERS  
WR  
RD  
X
Y
Z
INSTRUCTION  
DECODER  
INTERRUPT  
UNIT  
CONTROL  
LINES  
ALU  
EEPROM  
PEN  
STATUS  
REGISTER  
PROGRAMMING  
LOGIC  
SPI  
UART  
DATA REGISTER  
PORTE  
DATA DIR.  
REG. PORTE  
DATA REGISTER  
PORTB  
DATA DIR.  
REG. PORTB  
DATA REGISTER  
PORTD  
DATA DIR.  
REG. PORTD  
VCC  
GND  
PORTE DRIVER/BUFFERS  
PORTB DRIVER/BUFFERS  
PORTD DRIVER/BUFFERS  
PE0 - PE7  
PB0 - PB7  
PD0 - PD7  
4
ATmega103(L)  
0945GS–09/01  
ATmega103(L)  
Pin Descriptions  
VCC  
Supply voltage.  
Ground.  
GND  
Port A (PA7..PA0)  
Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors  
(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-  
plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,  
they will source current if the internal pull-up resistors are activated.  
Port A serves as Multiplexed Address/Data bus when using external SRAM.  
The Port A pins are tri-stated when a reset condition becomes active, even if the clock is  
not running.  
Port B (PB7..PB0)  
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output  
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source  
current if the pull-up resistors are activated.  
Port B also serves the functions of various special features.  
The Port B pins are tri-stated when a reset condition becomes active, even if the clock is  
not running.  
Port C (PC7..PC0)  
Port D (PD7..PD0)  
Port C is an 8-bit output port. The Port C output buffers can sink 20 mA.  
Port C also serves as Address output when using external SRAM.  
Since Port C is an output only port, the Port C pins are not tri-stated when a reset condi-  
tion becomes active.  
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output  
buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source  
current if the pull-up resistors are activated.  
Port D also serves the functions of various special features.  
The Port D pins are tri-stated when a reset condition becomes active, even if the clock is  
not running.  
Port E (PE7..PE0)  
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output  
buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source  
current if the pull-up resistors are activated.  
Port E also serves the functions of various special features.  
The Port E pins are tri-stated when a reset condition becomes active, even if the clock is  
not running  
Port F (PF7..PF0)  
RESET  
Port F is an 8-bit input port. Port F also serves as the analog inputs for the ADC.  
Reset input. An external reset is generated by a low level on the RESET pin. Reset  
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter  
pulses are not guaranteed to generate a reset.  
XTAL1  
XTAL2  
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.  
Output from the inverting oscillator amplifier.  
5
0945GS09/01  
TOSC1  
TOSC2  
WR  
Input to the inverting Timer/Counter oscillator amplifier.  
Output from the inverting Timer/Counter oscillator amplifier.  
External SRAM write strobe  
RD  
External SRAM read strobe  
ALE  
ALE is the Address Latch Enable used when the External Memory is enabled. The ALE  
strobe is used to latch the low-order address (8 bits) into an address latch during the first  
access cycle, and the AD0-7 pins are used for data during the second access cycle.  
AVCC  
Supply voltage for Port F, including ADC. The pin must be connected to VCC when not  
used for the ADC. See ADC Noise Canceling Techniqueson page 74 for details when  
using the ADC.  
AREF  
AGND  
PEN  
AREF is the analog reference input for the ADC converter. For ADC operations, a volt-  
age in the range AGND to AVCC must be applied to this pin.  
If the board has a separate analog ground plane, this pin should be connected to this  
ground plane. Otherwise, connect to GND.  
PEN is a programming enable pin for the serial programming mode. By holding this pin  
low during a power-on reset, the device will enter the serial programming mode. PEN  
has no function during normal operation.  
6
ATmega103(L)  
0945GS09/01  
ATmega103(L)  
Register Summary  
Address  
$3F ($5F)  
$3E ($5E)  
$3D ($5D)  
$3C ($5C)  
$3B ($5B)  
$3A ($5A)  
$39 ($59)  
$38 ($58)  
$37 ($57)  
$36 ($56)  
$35 ($55)  
$34 ($54)  
$33 ($53)  
$32 ($52)  
$31 ($51)  
$30 ($50)  
$2F ($4F)  
$2E ($4E)  
$2D ($4D)  
$2C ($4C)  
$2B ($4B)  
$2A ($4A)  
$29 ($49)  
$28 ($48)  
$27 ($47)  
$26 ($46)  
$25 ($45)  
$24 ($44)  
$23 ($43)  
$21 ($47)  
$1F ($3F)  
$1E ($3E)  
$1D ($3D)  
$1C ($3C)  
$1B ($3B)  
$1A ($3A)  
$19 ($39)  
$18 ($38)  
$17 ($37)  
$16 ($36)  
$15 ($35)  
$12 ($32)  
$11 ($31)  
$10 ($30)  
$0F ($2F)  
$0E ($2E)  
$0D ($2D)  
$0C ($2C)  
$0B ($2B)  
$0A ($2A)  
$09 ($29)  
$08 ($28)  
$07 ($27)  
$06 ($26)  
$05 ($25)  
$04 ($24)  
$03 ($23)  
$02 ($22)  
$01 ($21)  
$00 ($20)  
Name  
SREG  
Bit7  
I
Bit6  
T
Bit5  
H
Bit4  
S
Bit3  
V
Bit2  
N
Bit1  
Z
Bit0  
C
Page  
page 19  
page 20  
page 20  
page 22  
page 20  
page 29  
page 28  
page 29  
page 30  
page 31  
page 21  
page 27  
page 37  
page 38  
page 39  
page 40  
page 45  
page 46  
page 47  
page 47  
page 47  
page 47  
page 48  
page 48  
page 48  
page 48  
page 37  
page 38  
page 39  
page 51  
page 53  
page 53  
page 53  
page 53  
page 79  
page 79  
page 79  
page 81  
page 81  
page 81  
page 87  
page 88  
page 88  
page 88  
page 60  
page 59  
page 58  
page 64  
page 64  
page 65  
page 67  
page 68  
page 73  
page 73  
page 74  
page 74  
page 92  
page 92  
page 92  
page 96  
SPH  
SPL  
XDIV  
RAMPZ  
EICR  
EIMSK  
EIFR  
TIMSK  
TIFR  
MCUCR  
MCUSR  
TCCR0  
TCNT0  
OCR0  
ASSR  
TCCR1A  
TCCR1B  
TCNT1H  
TCNT1L  
OCR1AH  
OCR1AL  
OCR1BH  
OCR1BL  
ICR1H  
ICR1L  
TCCR2  
TCNT2  
OCR2  
WDTCR  
EEARH  
EEARL  
EEDR  
EECR  
PORTA  
DDRA  
PINA  
PORTB  
DDRB  
PINB  
PORTC  
PORTD  
DDRD  
PIND  
SPDR  
SPSR  
SPCR  
UDR  
SP15  
SP7  
XDIVEN  
ISC71  
INT7  
INTF7  
OCIE2  
OCF2  
SRE  
SP14  
SP6  
XDIV6  
ISC70  
INT6  
INTF6  
TOIE2  
TOV2  
SRW  
SP13  
SP5  
XDIV5  
ISC61  
INT5  
INTF5  
TICIE1  
ICF1  
SE  
SP12  
SP4  
XDIV4  
ISC60  
INT4  
INTF4  
OCIE1A  
OCF1A  
SM1  
SP11  
SP3  
XDIV3  
ISC51  
INT3  
OCIE1B  
OCF1B  
SM0  
SP10  
SP2  
XDIV2  
ISC50  
INT2  
TOIE1  
TOV1  
SP9  
SP1  
XDIV1  
ISC41  
INT1  
OCIE0  
OCF0  
EXTRF  
CS01  
SP8  
SP0  
XDIV0  
RAMPZ0  
ISC40  
INT0  
TOIE0  
TOV0  
PORF  
CS00  
PWM0  
COM01  
COM00  
Timer/Counter0 (8-bit)  
Timer/Counter0 Output Compare Register  
CTC0  
CS02  
COM1B1  
COM1B0  
AS0  
CTC1  
TCN0UB  
CS12  
OCR0UB  
PWM11  
CS11  
TCR0UB  
PWM10  
CS10  
COM1A1  
ICNC1  
COM1A0  
ICES1  
Timer/Counter1 – Counter Register High Byte  
Timer/Counter1 – Counter Register Low Byte  
Timer/Counter1 – Output Compare Register A High Byte  
Timer/Counter1 – Output Compare Register A Low Byte  
Timer/Counter1 – Output Compare Register B High Byte  
Timer/Counter1 – Output Compare Register B Low Byte  
Timer/Counter1 – Input Capture Register High Byte  
Timer/Counter1 – Input Capture Register Low Byte  
PWM2  
COM21  
COM20  
Timer/Counter2 (8-bit)  
Timer/Counter2 Output Compare Register  
CTC2  
CS22  
CS21  
CS20  
WDTOE  
EEPROM Address Register L  
EEPROM Data Register  
WDE  
EEAR11  
WDP2  
EEAR10  
WDP1  
EEAR9  
WDP0  
EEAR8  
EERIE  
PORTA3  
DDA3  
PINA3  
PORTB3  
DDB3  
EEMWE  
PORTA2  
DDA2  
PINA2  
PORTB2  
DDB2  
EEWE  
PORTA1  
DDA1  
PINA1  
PORTB1  
DDB1  
EERE  
PORTA0  
DDA0  
PINA0  
PORTB0  
DDB0  
PORTA7  
DDA7  
PINA7  
PORTB7  
DDB7  
PINB7  
PORTC7  
PORTD7  
DDD7  
PORTA6  
DDA6  
PINA6  
PORTB6  
DDB6  
PINB6  
PORTC6  
PORTD6  
DDD6  
PORTA5  
DDA5  
PINA5  
PORTB5  
DDB5  
PINB5  
PORTC5  
PORTD5  
DDD5  
PORTA4  
DDA4  
PINA4  
PORTB4  
DDB4  
PINB4  
PORTC4  
PORTD4  
DDD4  
PIND4  
SPI Data Register  
MSTR  
UART I/O Data Register  
FE  
RXEN  
UART Baud Rate Register  
ACI  
ADIF  
ADC4  
PORTE4  
DDE4  
PINE4  
PINF4  
PINB3  
PINB2  
PINB1  
PINB0  
PORTC3  
PORTD3  
DDD3  
PORTC2  
PORTD2  
DDD2  
PORTC1  
PORTD1  
DDD1  
PORTC0  
PORTD0  
DDD0  
PIND7  
PIND6  
PIND5  
PIND3  
PIND2  
PIND1  
PIND0  
SPIF  
SPIE  
WCOL  
SPE  
DORD  
CPOL  
CPHA  
SPR1  
SPR0  
USR  
UCR  
RXC  
RXCIE  
TXC  
TXCIE  
UDRE  
UDRIE  
OR  
TXEN  
CHR9  
RXB8  
TXB8  
UBRR  
ACSR  
ADMUX  
ADCSR  
ADCH  
ADCL  
PORTE  
DDRE  
PINE  
ACD  
ADEN  
ADC7  
PORTE7  
DDE7  
PINE7  
PINF7  
ACO  
ACIE  
ADIE  
ADC3  
PORTE3  
DDE3  
PINE3  
PINF3  
ACIC  
MUX2  
ADPS2  
ADC2  
PORTE2  
DDE2  
PINE2  
PINF2  
ACIS1  
MUX1  
ADPS1  
ADC9  
ADC1  
PORTE1  
DDE1  
ACIS0  
MUX0  
ADPS0  
ADC8  
ADC0  
PORTE0  
DDE0  
ADSC  
ADC6  
PORTE6  
DDE6  
PINE6  
PINF6  
ADC5  
PORTE5  
DDE5  
PINE5  
PINF5  
PINE1  
PINF1  
PINE0  
PINF0  
PINF  
Note:  
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses  
should never be written. Some of the status flags are cleared by writing a logical 1to them. Note that the CBI and SBI instruc-  
tions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and  
SBI instructions work with registers $00 to $1F only.  
7
0945GS09/01  
Instruction Set Summary  
Mnemonic  
Operands  
Description  
Operation  
Flags  
# Clocks  
ARITHMETIC AND LOGIC INSTRUCTIONS  
ADD  
ADC  
ADIW  
SUB  
SUBI  
SBC  
SBCI  
SBIW  
AND  
ANDI  
OR  
Rd, Rr  
Rd, Rr  
Rdl, K  
Rd, Rr  
Rd, K  
Rd, Rr  
Rd, K  
Rdl, K  
Rd, Rr  
Rd, K  
Rd, Rr  
Rd, K  
Rd, Rr  
Rd  
Add Two Registers  
Rd Rd + Rr  
Rd Rd + Rr + C  
Rdh:Rdl Rdh:Rdl + K  
Rd Rd - Rr  
Z,C,N,V,H  
Z,C,N,V,H  
Z,C,N,V,S  
Z,C,N,V,H  
Z,C,N,V,H  
Z,C,N,V,H  
Z,C,N,V,H  
Z,C,N,V,S  
Z,N,V  
Z,N,V  
Z,N,V  
Z,N,V  
Z,N,V  
Z,C,N,V  
Z,C,N,V,H  
Z,N,V  
Z,N,V  
Z,N,V  
Z,N,V  
Z,N,V  
Z,N,V  
None  
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry Two Registers  
Add Immediate to Word  
Subtract Two Registers  
Subtract Constant from Register  
Subtract with Carry Two Registers  
Subtract with Carry Constant from Reg.  
Subtract Immediate from Word  
Logical AND Registers  
Logical AND Register and Constant  
Logical OR Registers  
Logical OR Register and Constant  
Exclusive OR Registers  
One’s Complement  
Two’s Complement  
Set Bit(s) in Register  
Rd Rd - K  
Rd Rd - Rr - C  
Rd Rd - K - C  
Rdh:Rdl Rdh:Rdl - K  
Rd Rd Rr  
Rd Rd K  
Rd Rd v Rr  
Rd Rd v K  
Rd Rd Rr  
Rd $FF - Rd  
Rd $00 - Rd  
Rd Rd v K  
Rd Rd ($FF - K)  
Rd Rd + 1  
ORI  
EOR  
COM  
NEG  
SBR  
CBR  
INC  
DEC  
TST  
CLR  
SER  
Rd  
Rd, K  
Rd, K  
Rd  
Rd  
Rd  
Clear Bit(s) in Register  
Increment  
Decrement  
Test for Zero or Minus  
Clear Register  
Set Register  
Rd Rd - 1  
Rd Rd Rd  
Rd Rd Rd  
Rd $FF  
Rd  
Rd  
BRANCH INSTRUCTIONS  
RJMP  
IJMP  
JMP  
RCALL  
ICALL  
CALL  
RET  
k
Relative Jump  
Indirect Jump to (Z)  
Direct Jump  
Relative Subroutine Call  
Indirect Call to (Z)  
Direct Subroutine Call  
Subroutine Return  
Interrupt Return  
PC PC + k + 1  
PC Z  
PC k  
PC PC + k + 1  
PC Z  
PC k  
PC STACK  
PC STACK  
None  
None  
None  
None  
None  
None  
None  
I
2
2
3
3
3
4
4
4
k
k
k
RETI  
CPSE  
CP  
CPC  
Rd, Rr  
Rd, Rr  
Rd, Rr  
Rd, K  
Rr, b  
Rr, b  
P, b  
P, b  
s, k  
s, k  
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Compare, Skip if Equal  
Compare  
Compare with Carry  
if (Rd = Rr) PC PC + 2 or 3  
Rd - Rr  
Rd - Rr - C  
None  
Z,N,V,C,H  
Z,N,V,C,H  
Z,N,V,C,H  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
1/2/3  
1
1
CPI  
Compare Register with Immediate  
Skip if Bit in Register Cleared  
Skip if Bit in Register is Set  
Skip if Bit in I/O Register Cleared  
Skip if Bit in I/O Register is Set  
Branch if Status Flag Set  
Branch if Status Flag Cleared  
Branch if Equal  
Branch if Not Equal  
Branch if Carry Set  
Branch if Carry Cleared  
Branch if Same or Higher  
Branch if Lower  
Rd - K  
1
SBRC  
SBRS  
SBIC  
SBIS  
if (Rr(b) = 0) PC PC + 2 or 3  
if (Rr(b) = 1) PC PC + 2 or 3  
if (P(b) = 0) PC PC + 2 or 3  
if (P(b) = 1) PC PC + 2 or 3  
if (SREG(s) = 1) then PC =PC + k + 1  
if (SREG(s) = 0) then PC =PC + k + 1  
if (Z = 1) then PC PC + k + 1  
if (Z = 0) then PC PC + k + 1  
if (C = 1) then PC PC + k + 1  
if (C = 0) then PC PC + k + 1  
if (C = 0) then PC PC + k + 1  
if (C = 1) then PC PC + k + 1  
if (N = 1) then PC PC + k + 1  
if (N = 0) then PC PC + k + 1  
if (N V = 0) then PC PC + k + 1  
if (N V = 1) then PC PC + k + 1  
if (H = 1) then PC PC + k + 1  
if (H = 0) then PC PC + k + 1  
if (T = 1) then PC PC + k + 1  
if (T = 0) then PC PC + k + 1  
if (V = 1) then PC PC + k + 1  
if (V = 0) then PC PC + k + 1  
if (I = 1) then PC PC + k + 1  
if (I = 0) then PC PC + k + 1  
1/2/3  
1/2/3  
1/2/3  
1/2/3  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
BRBS  
BRBC  
BREQ  
BRNE  
BRCS  
BRCC  
BRSH  
BRLO  
BRMI  
BRPL  
BRGE  
BRLT  
BRHS  
BRHC  
BRTS  
BRTC  
BRVS  
BRVC  
BRIE  
BRID  
Branch if Minus  
Branch if Plus  
Branch if Greater or Equal, Signed  
Branch if Less Than Zero, Signed  
Branch if Half-carry Flag Set  
Branch if Half-carry Flag Cleared  
Branch if T-flag Set  
Branch if T-flag Cleared  
Branch if Overflow Flag is Set  
Branch if Overflow Flag is Cleared  
Branch if Interrupt Enabled  
Branch if Interrupt Disabled  
k
DATA TRANSFER INSTRUCTIONS  
ELPM  
MOV  
LDI  
Extended Load Program Memory  
Move between Registers  
Load Immediate  
R0 (Z + RAMPZ)  
Rd Rr  
Rd K  
None  
None  
None  
3
1
1
Rd, Rr  
Rd, K  
8
ATmega103(L)  
0945GS09/01  
ATmega103(L)  
Instruction Set Summary (Continued)  
Mnemonic  
Operands  
Description  
Operation  
Flags  
# Clocks  
LD  
LD  
LD  
LD  
LD  
LD  
LDD  
LD  
LD  
Rd, X  
Load Indirect  
Rd (X)  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
Rd, X+  
Rd, -X  
Rd, Y  
Rd, Y+  
Rd, -Y  
Rd, Y+q  
Rd, Z  
Rd, Z+  
Rd, -Z  
Rd, Z+q  
Rd, k  
Load Indirect and Post-increment  
Load Indirect and Pre-decrement  
Load Indirect  
Load Indirect and Post-increment  
Load Indirect and Pre-decrement  
Load Indirect with Displacement  
Load Indirect  
Load Indirect and Post-increment  
Load Indirect and Pre-decrement  
Load Indirect with Displacement  
Load Direct from SRAM  
Store Indirect  
Store Indirect and Post-increment  
Store Indirect and Pre-decrement  
Store Indirect  
Store Indirect and Post-increment  
Store Indirect and Pre-decrement  
Store Indirect with Displacement  
Store Indirect  
Store Indirect and Post-increment  
Store Indirect and Pre-decrement  
Store Indirect with Displacement  
Store Direct to SRAM  
Rd (X), X X + 1  
X X - 1, Rd (X)  
Rd (Y)  
Rd (Y), Y Y + 1  
Y Y - 1, Rd (Y)  
Rd (Y + q)  
Rd (Z)  
Rd (Z), Z Z + 1  
Z Z - 1, Rd (Z)  
Rd (Z + q)  
LD  
LDD  
LDS  
ST  
ST  
ST  
ST  
ST  
ST  
STD  
ST  
Rd (k)  
(X) Rr  
X, Rr  
X+, Rr  
-X, Rr  
Y, Rr  
Y+, Rr  
-Y, Rr  
Y+q, Rr  
Z, Rr  
Z+, Rr  
-Z, Rr  
Z+q, Rr  
k, Rr  
(X) Rr, X X + 1  
X X - 1, (X) Rr  
(Y) Rr  
(Y) Rr, Y Y + 1  
Y Y - 1, (Y) Rr  
(Y + q) Rr  
(Z) Rr  
ST  
ST  
(Z) Rr, Z Z + 1  
Z Z - 1, (Z) Rr  
(Z + q) Rr  
(k) Rr  
R0 (Z)  
Rd P  
P Rr  
STACK Rr  
Rd STACK  
STD  
STS  
LPM  
IN  
OUT  
PUSH  
POP  
Load Program Memory  
In Port  
Out Port  
Push Register on Stack  
Pop Register from Stack  
Rd, P  
P, Rr  
Rr  
Rd  
BIT AND BIT-TEST INSTRUCTIONS  
SBI  
CBI  
LSL  
P, b  
P, b  
Rd  
Rd  
Rd  
Rd  
Rd  
Rd  
s
Set Bit in I/O Register  
Clear Bit in I/O Register  
Logical Shift Left  
Logical Shift Right  
Rotate Left through Carry  
Rotate Right through Carry  
Arithmetic Shift Right  
Swap Nibbles  
Flag Set  
Flag Clear  
Bit Store from Register to T  
Bit Load from T to Register  
Set Carry  
Clear Carry  
Set Negative Flag  
Clear Negative Flag  
Set Zero Flag  
Clear Zero Flag  
Global Interrupt Enable  
Global Interrupt Disable  
Set Signed Test Flag  
Clear Signed Test Flag  
Set Two’s Complement Overflow  
Clear Two’s Complement Overflow  
Set T in SREG  
I/O(P,b) 1  
I/O(P,b) 0  
Rd(n+1) Rd(n), Rd(0) 0  
Rd(n) Rd(n+1), Rd(7) 0  
Rd(0) =C, Rd(n+1) Rd(n), C =Rd(7)  
Rd(7) =C, Rd(n) Rd(n+1), C =Rd(0)  
Rd(n) Rd(n+1), n = 0..6  
Rd(3..0) =Rd(7..4), Rd(7..4) =Rd(3..0)  
SREG(s) 1  
SREG(s) 0  
T Rr(b)  
Rd(b) T  
C 1  
C 0  
N 1  
N 0  
Z 1  
Z 0  
I 1  
I 0  
S 1  
S 0  
V 1  
V 0  
T 1  
None  
None  
Z,C,N,V  
Z,C,N,V  
Z,C,N,V  
Z,C,N,V  
Z,C,N,V  
None  
SREG(s)  
SREG(s)  
T
None  
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None  
None  
None  
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LSR  
ROL  
ROR  
ASR  
SWAP  
BSET  
BCLR  
BST  
BLD  
SEC  
CLC  
SEN  
CLN  
SEZ  
CLZ  
SEI  
s
Rr, b  
Rd, b  
CLI  
SES  
CLS  
SEV  
CLV  
SET  
CLT  
SEH  
CLH  
NOP  
SLEEP  
WDR  
Clear T in SREG  
T 0  
H 1  
H 0  
Set Half-carry Flag in SREG  
Clear Half-carry Flag in SREG  
No Operation  
Sleep  
Watchdog Reset  
(see specific descr. for Sleep function)  
(see specific descr. for WD timer)  
9
0945GS09/01  
Ordering Information  
Speed (MHz)  
Power Supply  
Ordering Code  
Package  
Operation Range  
4
2.7 - 3.6V  
ATmega103L-4AC  
64A  
Commercial  
(0°C to 70°C)  
ATmega103L-4AI  
ATmega103-6AC  
ATmega103-6AI  
64A  
64A  
64A  
Industrial  
(-40°C to 85°C)  
6
4.0 - 5.5V  
Commercial  
(0°C to 70°C)  
Industrial  
(-40°C to 85°C)  
Package Type  
64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)  
64A  
10  
ATmega103(L)  
0945GS09/01  
ATmega103(L)  
Packaging Information  
64A  
64-lead, Thin (1.0 mm) Plastic Quad Flat Package  
(TQFP), 14x14mm body, 2.0mm footprint, 0.8mm pitch.  
Dimensions in Millimeters and (Inches)*  
JEDEC STANDARD MS-026 AEB  
16.25(0.640)  
15.75(0.620)  
SQ  
PIN 1 ID  
PIN 1  
0.45(0.018)  
0.30(0.012)  
0.80(0.0315) BSC  
14.10(0.555)  
13.90(0.547)  
SQ  
1.20 (0.047) MAX  
0.20(0.008)  
0˚~7˚  
0.09(0.004)  
0.15(0.006)  
0.05(0.002 )  
0.75(0.030)  
0.45(0.018)  
*Controlliing dimension: millimeter  
REV. A 04/11/2001  
11  
0945GS09/01  
Atmel Headquarters  
Atmel Product Operations  
Corporate Headquarters  
2325 Orchard Parkway  
San Jose, CA 95131  
TEL (408) 441-0311  
FAX (408) 487-2600  
Atmel Colorado Springs  
1150 E. Cheyenne Mtn. Blvd.  
Colorado Springs, CO 80906  
TEL (719) 576-3300  
FAX (719) 540-1759  
Europe  
Atmel Grenoble  
Atmel SarL  
Avenue de Rochepleine  
BP 123  
Route des Arsenaux 41  
Casa Postale 80  
CH-1705 Fribourg  
Switzerland  
38521 Saint-Egreve Cedex, France  
TEL (33) 4-7658-3000  
FAX (33) 4-7658-3480  
TEL (41) 26-426-5555  
FAX (41) 26-426-5500  
Atmel Heilbronn  
Theresienstrasse 2  
POB 3535  
Asia  
Atmel Asia, Ltd.  
Room 1219  
D-74025 Heilbronn, Germany  
TEL (49) 71 31 67 25 94  
FAX (49) 71 31 67 24 23  
Chinachem Golden Plaza  
77 Mody Road Tsimhatsui  
East Kowloon  
Hong Kong  
TEL (852) 2721-9778  
FAX (852) 2722-1369  
Atmel Nantes  
La Chantrerie  
BP 70602  
44306 Nantes Cedex 3, France  
TEL (33) 0 2 40 18 18 18  
FAX (33) 0 2 40 18 19 60  
Japan  
Atmel Japan K.K.  
9F, Tonetsu Shinkawa Bldg.  
1-24-8 Shinkawa  
Chuo-ku, Tokyo 104-0033  
Japan  
Atmel Rousset  
Zone Industrielle  
13106 Rousset Cedex, France  
TEL (33) 4-4253-6000  
FAX (33) 4-4253-6001  
TEL (81) 3-3523-3551  
FAX (81) 3-3523-7581  
Atmel Smart Card ICs  
Scottish Enterprise Technology Park  
East Kilbride, Scotland G75 0QR  
TEL (44) 1355-357-000  
FAX (44) 1355-242-743  
e-mail  
literature@atmel.com  
Web Site  
http://www.atmel.com  
BBS  
1-(408) 436-4309  
© Atmel Corporation 2001.  
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty  
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors  
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does  
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted  
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical  
components in life support devices or systems.  
ATMEL® and AVR® are the registered trademarks of Atmel.  
Other terms and product names may be the trademarks of others.  
Printed on recycled paper.  
0945GS–09/01/xM  

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