ATMEGA103_07_技术文档

Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 121 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers + Peripheral Control Registers

– Up to 6 MIPS Throughput at 6 MHz

• Data and Nonvolatile Program Memory

– 128K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– 4K Bytes Internal SRAM

– 4K Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

– SPI Interface for In-System Programming

• Peripheral Features

8-bit

Microcontroller

with 128K Bytes

In-System

Programmable

Flash

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– Programmable Serial UART

– Master/Slave SPI Serial Interface

– Real-time Counter (RTC) with Separate Oscillator

– Two 8-bit Timer/Counters with Separate Prescaler and PWM

– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,

Capture Modes and Dual 8-, 9-, or 10-bit PWM

– Programmable Watchdog Timer with On-chip Oscillator

– 8-channel, 10-bit ADC

• Special Microcontroller Features

ATmega103

ATmega103L

– Low-power Idle, Power-save and Power-down Modes

– Software Selectable Clock Frequency

– External and Internal Interrupt Sources

• Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 5.5 mA

– Idle Mode: 1.6 mA

– Power-down Mode: < 1 µA

• I/O and Packages

– 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines

– 64-lead TQFP

• Operating Voltages

– 2.7 - 3.6V for ATmega103L

– 4.0 - 5.5V for ATmega103

• Speed Grades

– 0 - 4 MHz for ATmega103L

– 0 - 6 MHz for ATmega103

Note:

Not recommended in new

designs.

Rev. 0945I–AVR–02/07

1

Pin Configuration

TQFP

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ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Description

The ATmega103(L) is a low-power, CMOS, 8-bit microcontroller based on the AVR

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega103(L) achieves throughputs approaching 1 MIPS per MHz, allowing the sys-

tem designer to optimize power consumption versus processing speed.

The AVR core is based on an enhanced RISC architecture that combines a rich instruc-

tion set with 32 general purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be

accessed in one single instruction executed in one clock cycle. The resulting architec-

ture is more code efficient while achieving throughputs up to ten times faster than

conventional CISC microcontrollers.

The ATmega103(L) provides the following features: 128K bytes of In-System Program-

mable Flash, 4K bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O lines, 8 input

lines, 8 output lines, 32 general purpose working registers, Real Time Counter (RTC), 4

flexible Timer/Counters with compare modes and PWM, UART, programmable Watch-

dog Timer with internal Oscillator, an SPI serial port and 3 software-selectable power

saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters,

SPI port and interrupt system to continue functioning. The Power-down mode saves the

register contents but freezes the Oscillator, disabling all other chip functions until the

next Interrupt or Hardware Reset. In Power-save mode, the Timer Oscillator continues

to run, allowing the user to maintain a timer base while the rest of the device is sleeping.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The On-chip ISP Flash allows the Program memory to be reprogrammed In-System

through a serial interface or by a conventional nonvolatile memory programmer. By

combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the

Atmel ATmega103(L) is a powerful microcontroller that provides a highly flexible and

cost-effective solution to many embedded control applications.

The ATmega103(L) AVR is supported with a full suite of program and system develop-

ment tools including: C compilers, macro assemblers, program debugger/simulators, In-

Circuit Emulators and evaluation kits.

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0945I–AVR–02/07

Block Diagram

Figure 1. The ATmega103(L) Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

VCC

GND

PORTF BUFFERS

PORTA DRIVER/BUFFERS

PORTC DRIVERS

AVCC

DATA REGISTER

PORTC

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

ANALOG MUX

ADC

8-BIT DATA BUS

AGND

AREF

XTAL1

INTERNAL

OSCILLATOR

XTAL1

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TOSC2

TIMING AND

CONTROL

TOSC1

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

RESET

ALE

INSTRUCTION

REGISTER

TIMER/

COUNTERS

GENERAL

PURPOSE

REGISTERS

WR

RD

X

Y

Z

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

PEN

STATUS

REGISTER

PROGRAMMING

LOGIC

SPI

UART

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

VCC

GND

PORTE DRIVER/BUFFERS

PORTB DRIVER/BUFFERS

PORTD DRIVER/BUFFERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

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ATmega103(L)

Pin Descriptions

VCC

Supply voltage.

Ground.

GND

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-

plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,

they will source current if the internal pull-up resistors are activated.

Port A serves as Multiplexed Address/Data bus when using external SRAM.

The Port A pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source

current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

The Port B pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port C (PC7..PC0)

Port D (PD7..PD0)

Port C is an 8-bit output port. The Port C output buffers can sink 20 mA.

Port C also serves as Address output when using external SRAM.

Since Port C is an output only port, the Port C pins are not tri-stated when a reset condi-

tion becomes active.

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port D also serves the functions of various special features.

The Port D pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output

buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port E also serves the functions of various special features.

The Port E pins are tri-stated when a reset condition becomes active, even if the clock is

not running

Port F (PF7..PF0)

RESET

Port F is an 8-bit input port. Port F also serves as the analog inputs for the ADC.

Reset input. An external reset is generated by a low level on the RESET pin. Reset

pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset.

XTAL1

XTAL2

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

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TOSC1

TOSC2

WR

Input to the inverting Timer/Counter Oscillator amplifier.

Output from the inverting Timer/Counter Oscillator amplifier.

External SRAM write strobe

RD

External SRAM read strobe

ALE

ALE is the Address Latch Enable used when the External Memory is enabled. The ALE

strobe is used to latch the low-order address (8 bits) into an address latch during the first

access cycle, and the AD0 - 7 pins are used for data during the second access cycle.

AVCC

Supply voltage for Port F, including ADC. The pin must be connected to VCC when not

used for the ADC. See “ADC Noise Canceling Techniques” on page 82 for details when

using the ADC.

AREF

AGND

PEN

AREF is the analog reference input for the ADC converter. For ADC operations, a volt-

age in the range AGND to AVCC must be applied to this pin.

If the board has a separate analog ground plane, this pin should be connected to this

ground plane. Otherwise, connect to GND.

PEN is a programming enable pin for the Serial Programming mode. By holding this pin

low during a Power-on Reset, the device will enter the Serial Programming mode. PEN

has no function during normal operation.

Clock Options

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which

can be configured for use as an on-chip Oscillator, as shown in Figure 2. Either a quartz

crystal or a ceramic resonator may be used.

Figure 2. Oscillator Connections

MAX 1 HC BUFFER

HC

C2

XTAL2

C1

XTAL1

GND

Note:

When using the MCU Oscillator as a clock for an external device, an HC buffer should be

connected as indicated in the figure.

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ATmega103(L)

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ATmega103(L)

External Clock

To drive the device from an external clock source, XTAL2 should be left unconnected

while XTAL1 is driven as shown in Figure 3.

Figure 3. External Clock Drive Configuration

XTAL2

XTAL1

GND

NC

EXTERNAL

OSCILLATOR

SIGNAL

Timer Oscillator

For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly

between the pins. No external capacitors are needed. The Oscillator is optimized for use

with a 32,768 Hz watch crystal. Applying an external clock source to TOSC1 is not

recommended.

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Architectural

Overview

Figure 4. The ATmega103(L) AVR RISC Architecture

AVR ATmega103(L) Architecture

Data Bus 8-bit

Program

Counter

Status

and Test

64K x 16

Program

Memory

32 x 8

General

Purpose

Registers

Instruction

Register

Instruction

Decoder

Peripherals

ALU

Control Lines

4K x 8

Data

SRAM

4K x 8

EEPROM

The AVR uses a Harvard architecture concept – with separate memories and buses for

program and data. The Program memory is accessed with a single-level pipeline. While

one instruction is being executed, the next instruction is pre-fetched from the Program

memory. This concept enables instructions to be executed in every clock cycle. The

Program memory is In-System Programmable Flash memory. With a few exceptions,

AVR instructions have a single 16-bit word format, meaning that every Program memory

address contains a single 16-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the Stack. The Stack is effectively allocated in the general data SRAM and,

consequently, the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The 16-bit Stack Pointer (SP) is read/write accessible in the

I/O space.

The 4000 bytes data SRAM can be easily accessed through the five different address-

ing modes supported in the AVR architecture.

A flexible interrupt module has its control registers in the I/O space with an additional

Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep-

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ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

arate Interrupt Vector in the Interrupt Vector table at the beginning of the

Program memory. The different interrupts have priority in accordance with their Interrupt

Vector position. The lower the Interrupt Vector address, the higher the priority.

The memory spaces in the AVR architecture are all linear and regular memory maps.

General Purpose

Register File

Figure 5 shows the structure of the 32 general purpose working registers in the CPU.

Figure 5. AVR CPU General Purpose Working Registers

7

0

Addr.

$00

R0

R1

$01

R2

$02

. . .

R13

R14

R15

R16

R17

. . .

$0D

$0E

$0F

$10

$11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

$1A

$1B

$1C

$1D

$1E

$1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

All the register operating instructions in the instruction set have direct and single-cycle

access to all registers. The only exception are the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the

LDI instruction for load immediate constant data. These instructions apply to the second

half of the registers in the Register File – R16..R31. The general SBC, SUB, CP, AND

and OR and all other operations between two registers or on a single register apply to

the entire Register File.

As shown in Figure 5, each register is also assigned a Data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any

register in the file.

The 4K bytes of SRAM available for general data are implemented as addresses $0060

to $0FFF.

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X-register, Y-register and Z-

register

The registers R26..R31 have some added functions to their general purpose usage.

These registers are address pointers for indirect addressing of the SRAM. The three

indirect address registers X, Y, and Z are defined as:

Figure 6. X-, Y-, and Z-registers

15

7

0

X-register

0

7

0

R27 ($1B)

R26 ($1A)

15

7

0

Y-register

Z-register

0

7

0

R29 ($1D)

R31 ($1F)

R28 ($1C)

R30 ($1E)

15

7

In the different addressing modes these address registers have functions as fixed dis-

placement, automatic increment and decrement (see the descriptions for the different

instructions).

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general

purpose working registers. Within a single clock cycle, ALU operations between regis-

ters in the Register File are executed. The ALU operations are divided into three main

categories: arithmetic, logical and bit functions.

ISP Flash Program

Memory

The ATmega103(L) contains 128K bytes of On-chip In-System Programmable Flash

memory for program storage. Since all instructions are single or double 16-bit words, the

Flash is organized as 64K x 16. The Flash memory has an endurance of at least 1000

write/erase cycles.

Constant tables can be allocated in the entire Program memory space (see the LPM –

Load Program Memory and ELPM – Extended Load Program Memory instruction

descriptions).

SRAM Data Memory

The ATmega103(L) supports two different configurations for the SRAM Data memory as

listed in Table 1.

Table 1. Memory Configurations

Configuration

Internal SRAM Data Memory

External SRAM Data Memory

A

B

4000

None

up to 64K

Note:

When using 64K of external SRAM, 60K will be available.

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ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 7. Memory Configurations

Memory Configuration A

Program Memory

Data Memory

$0000

32 Registers

64 I/O Registers

$0000 - $001F

$0020 - $005F

$0060

Internal SRAM

(4000 x 8)

$0FFF

Program Flash

(32K/64K x 16)

$7FFF/$FFFF

Memory Configuration B

Program Memory

Data Memory

32 Registers

$0000 - $001F

$0000

64 I/O Registers $0020 - $005F

$0060

Internal SRAM

(4000 x 8)

$0FFF

$1000

Program Flash

(32K/64K x 16)

External SRAM

(0 - 64K x 8)

$7FFF/

$FFFF

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The 4096 first Data memory locations address both the Register File, the I/O memory

and the internal Data SRAM. The first 96 locations address the Register File and I/O

memory, and the next 4000 locations address the internal Data SRAM.

An optional external Data SRAM can be used with the ATmega103(L). This SRAM will

occupy an area in the remaining address locations in the 64K address space. This area

starts at the address following the internal SRAM. If a 64K external SRAM is used, 4K of

the external memory is lost as the addresses are occupied by internal memory.

When the addresses accessing the SRAM memory space exceeds the internal Data

memory locations, the external Data SRAM is accessed using the same instructions as

for the internal Data memory access. When the internal Data memories are accessed,

the read and write strobe pins (RD and WR) are inactive during the whole access cycle.

External SRAM operation is enabled by setting the SRE bit in the MCUCR Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access

of the internal SRAM. This means that the commands LD, ST, LDS, STS, PUSH and

POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts,

subroutine calls and returns take two clock cycles extra because the 2-byte Program

Counter is pushed and popped. When external SRAM interface is used with wait state,

two additional clock cycles are used per byte. This has the following effect: Data transfer

instructions take two extra clock cycles, whereas interrupt, subroutine calls and returns

will need four clock cycles more than specified in the “Instruction Set Summary” on page

135.

The five different addressing modes for the Data memory cover: Direct, Indirect with

Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In

the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The Indirect with Displacement mode features 63 address locations reached from the

base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic Pre-decrement and Post-

increment, the address registers X, Y, and Z are decremented and incremented.

The entire Data address space including the 32 general purpose working registers and

the 64 I/O Registers are all accessible through all these addressing modes. See the

next section for a detailed description of the different addressing modes.

Program and Data

Addressing Modes

The ATmega103(L) AVR RISC microcontroller supports powerful and efficient address-

ing modes for access to the Program memory (Flash) and Data memory (SRAM,

Register File and I/O memory). This section describes the different addressing modes

supported by the AVR architecture. In the figures, OP means the operation code part of

the instruction word. To simplify, not all figures show the exact location of the address-

ing bits.

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ATmega103(L)

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ATmega103(L)

Register Direct, Single

Register Rd

Figure 8. Direct Single Register Addressing

REGISTER FILE

0

15

4

0

OP

d

31

The operand is contained in register d (Rd).

Register Direct, Two Registers Figure 9. Direct Register Addressing, Two Registers

Rd and Rr

REGISTER FILE

0

15

9

5 4

0

OP

r

d

r

31

Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d

(Rd).

I/O Direct

Figure 10. I/O Direct Addressing

I/O MEMORY

0

15

5

0

OP

n

P

63

Operand address is contained in six bits of the instruction word. n is the destination or

source register address.

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Data Direct

Figure 11. Direct Data Addressing

Data Space

$0000

20 19

31

16

0

OP

Rr/Rd

16 LSBs

15

$FFFF

A 16-bit Data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify

the destination or source register.

Data Indirect with

Displacement

Figure 12. Data Indirect with Displacement

Data Space

$0000

15

0

Y- OR Z-REGISTER

15

10

6 5

0

OP

n

a

$FFFF

Operand address is the result of the Y- or Z-register contents added to the address con-

tained in six bits of the instruction word.

Data Indirect

Figure 13. Data Indirect Addressing

Data Space

$0000

15

0

X-, Y- OR Z-REGISTER

$FFFF

Operand address is the contents of the X-, Y,- or the Z-register.

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ATmega103(L)

Data Indirect with Pre-

decrement

Figure 14. Data Indirect Addressing with Pre-decrement

Data Space

$0000

15

0

X-, Y- OR Z-REGISTER

-1

$FFFF

The X-, Y-, or the Z-register is decremented before the operation. Operand address is

the decremented contents of the X-, Y-, or the Z-register.

Data Indirect with Post-

increment

Figure 15. Data Indirect Addressing with Post-increment

Data Space

$0000

15

0

X-, Y- OR Z-REGISTER

1

$FFFF

The X-, Y-, or the Z-register is incremented after the operation. Operand address is the

contents of the X-, Y-, or the Z-register prior to incrementing.

Constant Addressing Using

the LPM and ELPM

Instructions

Figure 16. Code Memory Constant Addressing

PROGRAM MEMORY

$0000

15

1 0

Z-REGISTER

$7FFF/$FFFF

Constant byte address is specified by the Z-register contents. The 15 MSBs select word

address (0 - 32K), LSB selects Low Byte if cleared (LSB = 0) or High Byte if set (LSB =

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1). If ELPM is used, LSB of the RAM Page Z register (RAMPZ) is used to select low or

high memory page (RAMPZ0 = 0: Low Page, RAMPZ0 = 1: High Page).

Direct Program Address, JMP Figure 17. Direct Program Memory Addressing

and CALL

PROGRAM MEMORY

$0000

31

16

21 20

OP

16 LSBs

15

0

$7FFF/$FFFF

Program execution continues at the address immediate in the instruction words.

Indirect Program Addressing, Figure 18. Indirect Program Memory Addressing

IJMP and ICALL

PROGRAM MEMORY

$0000

15

0

Z-REGISTER

$7FFF/$FFFF

Program execution continues at address contained by the Z-register (i.e., the PC is

loaded with the contents of the Z-register).

Relative Program Addressing, Figure 19. Relative Program Memory Addressing

RJMP and RCALL

PROGRAM MEMORY

$0000

15

0

PC

1

15

12 11

0

OP

k

$7FFF/$FFFF

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ATmega103(L)

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ATmega103(L)

Program execution continues at address PC + k + 1. The relative address k is -2048 to

2047.

EEPROM Data Memory

The EEPROM memory is organized as a separate Data space in which single bytes can

be read and written. The EEPROM has an endurance of at least 100,000 write/erase

cycles. The access between the EEPROM and the CPU is described on page 57 speci-

fying the EEPROM Address Register, the EEPROM Data Register and the EEPROM

Control Register.

Memory Access Times

and Instruction

This section describes the general access timing concepts for instruction execution and

internal memory access.

Execution Timing

The AVR CPU is driven by the System Clock Ø, directly generated from the external

clock crystal for the chip. No internal clock division is used.

Figure 20 shows the parallel instruction fetches and instruction executions enabled by

the Harvard architecture and the fast-access Register File concept. This is the basic

pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results

for functions per cost, functions per clocks and functions per power unit.

Figure 20. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 21 shows the internal timing concept for the Register File. In a single clock cycle,

an ALU operation using two register operands is executed and the result is stored back

to the destination register.

Figure 21. Single Cycle ALU Operation

T1

T2

T3

T4

System Clock Ø

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

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The internal Data SRAM access is performed in two System Clock cycles as described

in Figure 22.

Figure 22. On-chip Data SRAM Access Cycles

T1

T2

T3

T4

System Clock Ø

Prev. Address

Address

Data

WR

Data

RD

See “Interface to External SRAM” on page 84. for a description of the access to the

external SRAM.

I/O Memory

The I/O space definition of the ATmega103(L) is shown in Table 2.

Table 2. ATmega103(L) I/O Space

I/O Address (SRAM

Address)

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

Name

SREG

SPH

Function

Status REGister

Stack Pointer High

SPL

Stack Pointer Low

XDIV

XTAL Divide Control Register

RAM Page Z Select Register

External Interrupt Control Register

External Interrupt MaSK Register

External Interrupt Flag Register

Timer/Counter Interrupt MaSK Register

Timer/Counter Interrupt Flag Register

MCU General Control Register

MCU Status Register

RAMPZ

EICR

EIMSK

EIFR

TIMSK

TIFR

MCUCR

MCUSR

TCCR0

TCNT0

OCR0

ASSR

TCCR1A

TCCR1B

Timer/Counter0 Control Register

Timer/Counter0 (8-bit)

Timer/Counter0 Output Compare Register

Asynchronous Mode Status Register

Timer/Counter1 Control Register A

Timer/Counter1 Control Register B

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ATmega103(L)

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ATmega103(L)

Table 2. ATmega103(L) I/O Space (Continued)

I/O Address (SRAM

Address)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$21 ($41)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

$07 ($27)

Name

Function

TCNT1H

TCNT1L

Timer/Counter1 High Byte

Timer/Counter1 Low Byte

OCR1AH Timer/Counter1 Output Compare Register A High Byte

OCR1AL Timer/Counter1 Output Compare Register A Low Byte

OCR1BH Timer/Counter1 Output Compare Register B High Byte

OCR1BL

ICR1H

ICR1L

TCCR2

TCNT2

OCR2

WDTCR

EEARH

EEARL

EEDR

EECR

PORTA

DDRA

PINA

Timer/Counter1 Output Compare Register B Low Byte

Timer/Counter1 Input Capture Register High Byte

Timer/Counter1 Input Capture Register Low Byte

Timer/Counter2 Control Register

Timer/Counter2 (8-bit)

Timer/Counter2 Output Compare Register

Watchdog Timer Control Register

EEPROM Address Register High

EERPOM Address Register Low

EEPROM Data Register

EEPROM Control Register

Data Register, Port A

Data Direction Register, Port A

Input Pins, Port A

PORTB

DDRB

PINB

Data Register, Port B

Data Direction Register, Port B

Input Pins, Port B

PORTC

PORTD

DDRD

PIND

Data Register, Port C

Data Register, Port D

Data Direction Register, Port D

Input Pins, Port D

SPDR

SPSR

SPCR

UDR

SPI I/O Data Register

SPI Status Register

SPI Control Register

UART I/O Data Register

USR

UART Status Register

UCR

UART Control Register

UBRR

ACSR

ADMUX

UART Baud Rate Register

Analog Comparator Control and Status Register

ADC Multiplexer Select Register

19

0945I–AVR–02/07

Table 2. ATmega103(L) I/O Space (Continued)

I/O Address (SRAM

Address)

$06 ($26)

$05 ($25)

$04 ($24)

$03 ($23)

$02 ($22)

$01 ($21)

$00 ($20)

Name

ADCSR

ADCH

ADCL

PORTE

DDRE

PINE

Function

ADC Control and Status Register

ADC Data Register High

ADC Data Register Low

Data Register, Port E

Data Direction Register, Port E

Input Pins, Port E

PINF

Input Pins, Port F

Note:

Reserved and unused locations are not shown in the table.

All the different ATmega103(L) I/Os and peripherals are placed in the I/O space. The dif-

ferent I/O locations are directly accessed by the IN and OUT instructions transferring

data between the 32 general purpose working registers and the I/O space. I/O Registers

within the address range $00 - $1F are directly bit-accessible using the SBI and CBI

instructions. In these registers, the value of single bits can be checked by using the

SBIS and SBIC instructions. Refer to the “Instruction Set Summary” on page 135 for

more details. When using the I/O specific instructions IN and OUT, the I/O Register

address $00 - $3F are used. When addressing I/O Registers as SRAM, $20 must be

added to this address. All I/O Register addresses throughout this document are shown

with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O Register, writing a one back into

any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-

isters $00 to $1F only.

The different I/O and peripherals control registers are explained in the following

sections.

Status Register – SREG

The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

$3F ($5F)

Read/Write

Initial Value

SREG

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The

individual interrupt enable control is then performed in separate control registers. If the

Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled

independent of the individual interrupt enable settings. The I-bit is cleared by hardware

after an interrupt has occurred and is set by the RETI instruction to enable subsequent

interrupts.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source

and destination for the operated bit. A bit from a register in the Register File can be cop-

20

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

ied into T by the BST instruction and a bit in T can be copied into a bit in a register in the

register file by the BLD instruction.

• Bit 5 – H: Half-carry Flag

The Half-carry Flag H indicates a Half-carry in some arithmetic operations. See the

instruction set description on page 135 for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-

ment Overflow Flag V. See the instruction set description on page 135 for detailed

information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See

the instruction set description on page 135 for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result from an arithmetical or logical operation.

See the Instruction set description on page 135 for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result from an arithmetical or logical operation. See the

instruction set description on page 135 for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetical or logical operation. See the

instruction set description on page 135 for detailed information.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine or restored when returning from an interrupt routine. This must be handled by

software.

Stack Pointer – SP

The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the

I/O space locations $3E ($5E) and $3D ($5D). As the ATmega103(L) supports up to

64K bytes memory, all 16 bits are used.

Bit

15

SP15

SP7

7

14

SP14

SP6

6

13

SP13

SP5

5

12

SP12

SP4

4

11

SP11

SP3

3

10

SP10

SP2

2

9

SP9

SP1

1

8

SP8

SP0

0

$3E ($5E)

$3D ($5D)

SPH

SPL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Stack Pointer points to the Data SRAM Stack area where the Subroutine and Inter-

rupt Stacks are located. This Stack space in the Data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above $60. The Stack Pointer is decremented by one when

data is pushed onto the Stack with the PUSH instruction and it is decremented by 2

when an address is pushed onto the Stack with subroutine calls and interrupts. The

Stack Pointer is incremented by 1 when data is popped from the Stack with the POP

21

0945I–AVR–02/07

instruction and it is incremented by 2 when an address is popped from the Stack with

return from subroutine RET or return from interrupt RETI.

RAM Page Z Select Register –

RAMPZ

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

RAMPZ0

R/W

$3B ($5B)

Read/Write

Initial Value

RAMPZ

R

0

R

0

R

0

R

0

R

0

R

0

R

0

The RAMPZ Register is normally used to select which 64K RAM page is accessed by

the Z pointer. As the ATmega103(L) does not support more than 64K of SRAM memory,

this register is used only to select which page in the Program memory is accessed when

the ELPM instruction is used. The different settings of the RAMPZ0 bit have the follow-

ing effects:

RAMPZ0 = 0: Program memory address $0000 - $7FFF (lower 64K bytes) is

accessed by ELPM

RAMPZ0 = 1: Program memory address $8000 - $FFFF (higher 64K bytes) is

accessed by ELPM

Note that LPM is not affected by the RAMPZ setting.

MCU Control Register –

MCUCR

The MCU Control Register contains control bits for general MCU functions.

Bit

7

6

SRW

R/W

0

5

SE

R/W

0

4

3

2

–

1

–

0

–

$35 ($55)

Read/Write

Initial Value

SRE

R/W

0

SM1

R/W

0

SM0

R/W

0

MCUCR

R

0

R

0

R

0

• Bit 7 – SRE: External SRAM Enable

When the SRE bit is set (one), the external Data SRAM is enabled, and the pin functions

AD0 - 7 (Port A), and A8 - 15 (Port C) are activated as the alternate pin functions. Then

the SRE bit overrides any pin direction settings in the respective Data Direction Regis-

ters. When the SRE bit is cleared (zero), the external Data SRAM is disabled and the

normal pin and data direction settings are used.

• Bit 6 – SRW: External SRAM Wait State

When the SRW bit is set (one), a one-cycle wait state is inserted in the external Data

SRAM access cycle. When the SRW bit is cleared (zero), the external Data SRAM

access is executed with a three-cycle scheme. See Figure 51 on page 85 and Figure 52

on page 85.

• Bit 5 – SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-

grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the

execution of the SLEEP instruction.

22

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

• Bits 4, 3 – SM1/SM0: Sleep Mode Select Bits 1 and 0

This bit selects between the three available sleep modes as shown in Table 3.

Table 3. Sleep Mode Select

SM1

SM0

Sleep Mode

Idle mode

0

1

0

1

0

1

Reserved

Power-down

Power-save

• Bits 2..0 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

XTAL Divide Control Register The XTAL Divide Control Register is used to divide the XTAL clock frequency by a num-

– XDIV

ber in the range 1 - 129. This feature can be used to decrease power consumption when

the requirement for processing power is low.

Bit

7

XDIVEN

R/W

0

6

XDIV6

R/W

0

5

XDIV5

R/W

0

4

XDIV4

R/W

0

3

XDIV3

R/W

0

2

XDIV2

R/W

0

1

XDIV1

R/W

0

XDIV0

R/W

0

$3C ($5C)

Read/Write

Initial Value

XDIV

• Bit 7 – XDIVEN: XTAL Divide Enable

When the XDIVEN bit is set (one), the clock frequency of the CPU and all peripherals is

divided by the factor defined by the setting of XDIV6 - XDIV0. This bit can be set and

cleared run-time to vary the clock frequency as suitable to the application.

• Bits 6..0 – XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0

These bits define the division factor that applies when the XDIVEN bit is set (one). If the

value of these bits is denoted d, the following formula defines the resulting CPU clock

frequency f_clk:

XTAL

129 – d

f

= ------------------

CLK

The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is

set to one, the value written simultaneously into XDIV6..XDIV0 is taken as the division

factor. When XDIVEN is cleared to zero, the value written simultaneously into

XDIV6..XDIV0 is rejected. As the divider divides the Master Clock Input to the MCU, the

speed of all peripherals is reduced when a division factor is used.

Reset and Interrupt

Handling

The ATmega103(L) provides 23 different interrupt sources. These interrupts and the

separate Reset Vector each have a separate Program Vector in the Program memory

space. All interrupts are assigned individual enable bits that must be set (one) together

with the I-bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are automatically defined as the

Reset and Interrupt Vectors. The complete list of vectors is shown in Table 4. The list

also determines the priority levels of the different interrupts. The lower the address, the

23

0945I–AVR–02/07

higher the priority level. RESET has the highest priority and next is INT0 (the External

Interrupt Request 0), etc.

Table 4. Reset and Interrupt Vectors

Program

Vector No.

Address

Source

Interrupt Definition

Hardware Pin, Power-on Reset and Watchdog

Reset

1

$0000

RESET

2

$0002

$0004

$0006

$0008

$000A

$000C

$000E

$0010

$0012

$0014

$0016

$0018

$001A

$001C

$001E

$0020

$0022

$0024

$0026

$0028

$002A

$002C

$002E

INT0

External Interrupt Request 0

External Interrupt Request 1

External Interrupt Request 2

External Interrupt Request 3

External Interrupt Request 4

External Interrupt Request 5

External Interrupt Request 6

External Interrupt Request 7

Timer/Counter2 Compare Match

Timer/Counter2 Overflow

3

INT1

4

INT2

5

INT3

6

INT4

7

INT5

8

INT6

9

INT7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

TIMER2 COMP

TIMER2 OVF

TIMER1 CAPT

TIMER1 COMPA

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

TIMER1 COMPB Timer/Counter1 Compare Match B

TIMER1 OVF

TIMER0 COMP

TIMER0 OVF

SPI, STC

Timer/Counter1 Overflow

Timer/Counter0 Compare Match

Timer/Counter0 Overflow

SPI Serial Transfer Complete

UART, Rx Complete

UART, RX

UART, UDRE

UART, TX

UART Data Register Empty

UART, Tx Complete

ADC

ADC Conversion Complete

EEPROM Ready

EE READY

ANALOG COMP

Analog Comparator

The most typical program setup for the Reset and Interrupt vector addresses are:

AddressLabels Code

Comments

$0000

$0002

$0004

$0006

$0008

$000A

$000C

$000E

$0010

jmp

RESET

; Reset Handler

; IRQ0 Handler

; IRQ1 Handler

; IRQ2 Handler

; IRQ3 Handler

; IRQ4 Handler

; IRQ5 Handler

; IRQ6 Handler

; IRQ7 Handler

EXT_INT0

EXT_INT1

EXT_INT2

EXT_INT3

EXT_INT4

EXT_INT5

EXT_INT6

EXT_INT7

24

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

$0012

$0014

$0016

$0018

$001A

$001C

$001E

$0020

$0022

$0024

$0026

$0028

$002A

$002C

$002E

;

jmp

TIM2_COMP

TIM2_OVF

TIM1_CAPT

TIM1_COMPA

TIM1_COMPB

TIM1_OVF

TIM0_COMP

TIM0_OVF

SPI_STC

; Timer2 Compare Handler

; Timer2 Overflow Handler

; Timer1 Capture Handler

; Timer1 Compare A Handler

; Timer1 Compare B Handler

; Timer1 Overflow Handler

; Timer0 Compare Handler

; Timer0 Overflow Handler

; SPI Transfer Complete Handler

; UART RX Complete Handler

; UDR Empty Handler

UART_RXC

UART_DRE

UART_TXC

ADC

; UART TX Complete Handler

; ADC Conversion Complete Handler

; EEPROM Ready Handler

EE_RDY

ANA_COMP

; Analog Comparator Handler

$0030 MAIN:

$0031

$0032

$0033

$0034

ldi

out

ldi

out

r16, high(RAMEND); Main program start

SPH,r16

r16, low(RAMEND)

SPL,r16

<instr> xxx

... ...

...

Reset Sources

The ATmega103(L) has three sources of reset:

•

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (V_POT).

External Reset. The MCU is reset when a low level is present on the RESET pin for

more than 50 ns.

Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and

the Watchdog is enabled.

During reset, all I/O Registers except the MCU Status Register are then set to their initial

values and the program starts execution from address $0000. The instruction placed in

address $0000 must be a JMP (absolute jump) instruction to the reset handling routine.

If the program never enables an interrupt source, the Interrupt Vectors are not used and

regular program code can be placed at these locations. The circuit diagram in Figure 23

shows the reset logic. Table 5 defines the timing and electrical parameters of the reset

circuitry.

25

0945I–AVR–02/07

Figure 23. Reset Logic

POR

Power-on Reset

VCC

RESET

PEN

Circuit

Reset Circuit

S

Q

Watchdog

Timer

D

E

Q

On-chip

RC Oscillator

R

Q

14-stage Ripple Counter

Q8

Q11 Q13

Delay Unit

XTAL1

26

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Table 5. Reset Characteristics (V_CC= 5.0V)

Symbol Parameter Condition Min

Power-on Reset Threshold

Typ

Max

Units

1.0

1.4

1.8

V

(rising)

(1)

V_POT

Power-on Reset Threshold

(falling)

0.4

0.6

0.8

V

V_RST

RESET Pin Threshold Voltage

V_CC/2

5

V

SUT = 00

CPU cycles

SUT = 01

SUT = 10

SUT = 11

0.4

3.2

12.8

0.5

4.0

16.0

0.6

4.8

19.2

T_TOUT

Reset Delay Time-out Period

ms

Note:

1. The Power-on Reset will not work unless the supply voltage has been below V_POT

(falling).

Power-on Reset

A Power-on Reset (POR) circuit ensures that the device is Reset from Power-on. As

shown in Figure 23, an internal timer clocked from the Watchdog Timer Oscillator pre-

vents the MCU from starting until after a certain period after V_CChas reached the Power-

on Threshold voltage (V_POT), regardless of the V_CCrise time (see Figure 24). The Fuse

bits SUT1 and SUT0 are used to select start-up time as indicated in Table 5. A “0” in the

table indicates that the fuse is programmed.

The user can select the start-up time according to typical Oscillator start-up time. The

number of WDT Oscillator cycles used for each Time-out except for SUT = 00 is shown

in Table 6. The frequency of the Watchdog Oscillator is voltage-dependent as shown in

“Typical Characteristics” on page 123.

Table 6. Number of Watchdog Oscillator Cycles

SUT 1/0

01

Time-out at V_CC= 5V

0.5 ms

Number of WDT Cycles

512

4K

10

4.0 ms

11

16.0 ms

16K

The setting SUT 1/0 = 00 starts the MCU after 5 CPU clock cycles, and can be used

when an external clock signal is applied to the XTAL1 pin. This setting does not use the

WDT Oscillator and enables very fast start-up from the sleep modes Power-down or

Power-save if the clock signal is present during sleep. For details, refer to the program-

ming specification starting on page 104.

If the built-in start-up delay is sufficient, RESET can be connected to V_CCdirectly or via

an external pull-up resistor. By holding the pin low for a period after V_CChas been

applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing

example of this.

27

0945I–AVR–02/07

Figure 24. MCU Start-up, RESET Tied to V_CC

.

V_POT

VCC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 25. MCU Start-up, RESET Controlled Externally

V_POT

VCC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

External Reset

An external reset is generated by a low level on the RESET pin. Reset pulses longer

than 50 ns will generate a reset even if the clock is not running. Shorter pulses are not

guaranteed to generate a reset. When the applied signal reaches the Reset Threshold

Voltage (V_RST) on its positive edge, the delay timer starts the MCU after the Time-out

period t_TOUThas expired.

Figure 26. External Reset during Operation

VCC

RESET

V_RST

t_TOUT

TIME-OUT

INTERNAL

RESET

28

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period

t_TOUT. Refer to page 55 for details on operation of the Watchdog.

Figure 27. Watchdog Reset during Operation

VCC

RESET

1 XTAL Cycle

WDT

TIME-OUT

t_TOUT

RESET

TIME-OUT

INTERNAL

RESET

MCU Status Register –

MCUSR

The MCU Status Register provides information on which reset source caused an MCU

reset.

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

0

$34 ($54)

Read/Write

Initial Value

EXTRF

R/W

PORF

R/W

MCUSR

R

0

R

0

R

0

R

0

R

0

R

0

See bit description

• Bits 7..2 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

• Bit 1 – EXTRF: External Reset Flag

After a Power-on Reset, this bit is undefined (X). It will be set by an external reset. A

Watchdog reset will leave this bit unchanged.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set by a Power-on Reset. A Watchdog Reset or an External Reset will leave

this bit unchanged.

To summarize, Table 7 shows the value of these two bits after the three modes of reset:

Table 7. PORF and EXTRF Values after Reset

Reset Source

Power-on Reset

External Reset

Watchdog Reset

EXTRF

undefined

1

PORF

1

unchanged

To make use of these bits to identify a reset condition, the user software should clear

both the PORF and EXTRF bits as early as possible in the program. Checking the

PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before

29

0945I–AVR–02/07

an external or Watchdog reset occurs, the source of reset can be found by using the fol-

lowing truth table, Table 8.

Table 8. Reset Source Identification

Reset Source

Watchdog Reset

Power-on Reset

External Reset

Power-on Reset

EXTRF

PORF

0

1

0

1

0

1

Interrupt Handling

The ATmega103(L) has two dedicated 8-bit Interrupt Mask Control Registers; EIMSK

(External Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register).

In addition, other enable and mask bits can be found in the peripheral control registers.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-

rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.

The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

When the Program Counter is vectored to the actual Interrupt Vector in order to execute

the interrupt handling routine, hardware clears the corresponding flag that generated the

interrupt. Some of the Interrupt Flags can also be cleared by writing a logical “1” to the

flag bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared

(zero), the Interrupt Flag will be set and remembered until the interrupt is enabled or the

flag is cleared by software.

If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared

(zero), the corresponding Interrupt Flag(s) will be set and remembered until the Global

Interrupt Enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag and will only be remembered for

as long as the interrupt condition is active.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine or restored when returning from an interrupt routine. This must be handled by

software.

External Interrupt Mask

Register – EIMSK

Bit

7

6

5

4

3

2

1

0

$39 ($59)

Read/Write

Initial Value

INT7

R/W

0

INT6

R/W

0

INT5

R/W

0

INT4

R/W

0

INT3

R/W

0

INT2

R/W

0

INT1

R/W

0

INT0

R/W

0

EIMSK

• Bits 7..4 – INT7 - INT4: External Interrupt Request 7 - 4 Enable

When an INT7 - INT4 bit is set (one) and the I-bit in the Status Register (SREG) is set

(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control

bits in the External Interrupt Control Register (EICR) define whether the external inter-

rupt is activated on rising or falling edge or is level-sensed. Activity on any of these pins

will trigger an interrupt request even if the pin is enabled as an output. This provides a

way of generating a software interrupt.

30

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

• Bits 3..0 – INT3 - INT0: External Interrupt Request 3 - 0 Enable

When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set

(one), the corresponding external pin interrupt is enabled. The external interrupts are

always low-level triggered interrupts. Activity on any of these pins will trigger an interrupt

request even if the pin is enabled as an output. This provides a way of generating a soft-

ware interrupt. When enabled, a level-triggered interrupt will generate an interrupt

request as long as the pin is held low.

External Interrupt Flag

Register – EIFR

Bit

7

INTF7

R/W

0

6

INTF6

R/W

0

5

INTF5

R/W

0

4

INTF4

R/W

0

3

–

2

–

1

–

0

–

$38 ($58)

Read/Write

Initial Value

EIFR

R

0

R

0

R

0

R

0

• Bits 7..4 – INTF7 - INTF4: External Interrupt 7 - 4 Flags

When an edge on the INT7 - INT4 pins triggers an interrupt request, the corresponding

Interrupt Flag, INTF7 - INTF4, becomes set (one). If the I-bit in SREG and the corre-

sponding interrupt enable bit, INT7 - INT4 in EIMSK, is set (one), the MCU will jump to

the Interrupt Vector. The flag is cleared when the corresponding interrupt routine is exe-

cuted. Alternatively, the flag is cleared by writing a logical “1” to it. These flags are

always cleared when INTF7 - INFT4 are configured as level interrupts.

• Bits 3..0 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

External Interrupt Control

Register – EICR

Bit

7

ISC71

R/W

0

6

ISC70

R/W

0

5

ISC61

R/W

0

4

ISC60

R/W

0

3

ISC51

R/W

0

2

ISC50

R/W

0

1

ISC41

R/W

0

ISC40

R/W

0

$3A ($5A)

Read/Write

Initial Value

EICR

• Bits 7..0 – ISCX1, ISCX0: External Interrupt 7 - 4 Sense Control Bits

The External Interrupts 7 - 4 are activated by the external pins INT7 - INT4 if the SREG

I-flag and the corresponding interrupt mask in the EIMSK are set. The level and edges

on the external pins that activate the interrupts are defined in Table 9.

Table 9. Interrupt Sense Control

ISCX1

ISCX0

Description

0

1

0

1

0

1

The low level of INTX generates an interrupt request.

Reserved

The falling edge of INTX generates an interrupt request.

The rising edge of INTX generates an interrupt request.

The value on the INTX pin is sampled before detecting edges. If edge interrupt is

selected, pulses that last longer than one CPU clock period will generate an interrupt.

Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock fre-

quency can be lower than the XTAL frequency if the XTAL divider is enabled. If low-level

interrupt is selected, the low level must be held until the completion of the currently exe-

31

0945I–AVR–02/07

cuting instruction to generate an interrupt. If enabled, a level-triggered interrupt will

generate an interrupt request as long as the pin is held low.

32

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Timer/Counter Interrupt Mask

Register – TIMSK

Bit

7

OCIE2

R/W

0

6

TOIE2

R/W

0

5

TICIE1

R/W

0

4

OCIE1A

R/W

0

3

OCIE1B

R/W

0

2

TOIE1

R/W

0

1

OCIE0

R/W

0

TOIE0

R/W

0

TIMSK

$37 ($57)

Read/Write

Initial Value

• Bit 7 – OCIE2: Timer/Counter2 Output Compare Interrupt Enable

When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at

vector $0012) is executed if a compare match in Timer/Counter2 occurs, i.e., when the

OCF2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector

$0014) is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is

set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Input Capture Event interrupt is enabled. The corresponding interrupt

(at vector $0016) is executed if a capture-triggering event occurs on pin 29, PD4(IC1),

i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register.

• Bit 4 – OCE1A: Timer/Counter1 Output Compare A Match Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare A Match interrupt is enabled. The corresponding interrupt (at

vector $0018) is executed if a Compare A Match in Timer/Counter1 occurs, i.e., when

the OCF1A bit is set in the Timer/Counter Interrupt Flag Register.

• Bit 3 – OCIE1B: Timer/Counter1 Output Compare B Match Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare B Match interrupt is enabled. The corresponding interrupt (at

vector $001A) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when

the OCF1B bit is set in the Timer/Counter Interrupt Flag Register.

• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector

$001C) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is

set in the Timer/Counter Interrupt Flag Register.

• Bit 1 – OCIE0: Timer/Counter0 Output Compare Interrupt Enable

When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt (at

vector $001E) is executed if a compare match in Timer/Counter0 occurs, i.e., when the

OCF0 bit is set in the Timer/Counter Interrupt Flag Register.

33

0945I–AVR–02/07

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector

$0020) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is

set in the Timer/Counter Interrupt Flag Register.

34

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Timer/Counter Interrupt Flag

Register – TIFR

Bit

7

OCF2

R/W

0

6

TOV2

R/W

0

5

4

OCF1A

R/W

0

3

OCF1B

R/W

0

2

TOV1

R/W

0

1

OCF0

R/W

0

TOV0

R/W

0

$36 ($56)

Read/Write

Initial Value

ICF1

R/W

0

TIFR

• Bit 7 – OCF2: Output Compare Flag 2:

The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and

the data in OCR2 – Output Compare Register 2. OCF2 is cleared by hardware when

executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by

writing a logical “1” to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2

Compare Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2 Output

Compare interrupt is executed.

• Bit 6 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV2 is cleared by writing a logical “1” to the flag. When the I-bit in SREG, and TOIE2

(Timer/Counter1 Overflow Interrupt Enable) and TOV2 are set (one), the

Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter2 advances from $00.

• Bit 5 – ICF1: Input Capture Flag 1

The ICF1 bit is set (one) to flag an Input Capture event, indicating that the

Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1

is cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit,

TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the

Timer/Counter1 Capture interrupt is executed.

• Bit 4 – OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1

and the data in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF1A is

cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A

(Timer/Counter1 Compare Interrupt Enable) and the OCF1A are set (one), the

Timer/Counter1 Compare A Match interrupt is executed.

• Bit 3 – OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1

and the data in OCR1B – Output Compare Register 1B. OCF1B is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF1B is

cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B

(Timer/Counter1 Compare Match Interrupt Enable) and the OCF1B are set (one), the

Timer/Counter1 Compare B Match interrupt is executed.

• Bit 2 – TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1

35

0945I–AVR–02/07

(Timer/Counter1 Overflow Interrupt Enable) and TOV1 are set (one), the

Timer/Counter1 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter1 advances from $0000.

• Bit 1 – OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and

the data in OCR0 – Output Compare Register 0. OCF0 is cleared by hardware when

executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by

writing a logical “1” to the flag. When the I-bit in SREG and OCIE0 (Timer/Counter2

Compare Interrupt Enable) and the OCF0 are set (one), the Timer/Counter0 Output

Compare interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0

(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the

Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter0 advances from $00.

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. Four clock cycles after the Interrupt Flag has been set, the Program Vector

address for the actual interrupt handling routine is executed. During this four-clock-cycle

period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer

is decremented by 2. The vector is normally a jump to the interrupt routine, and this

jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine (same as for a subroutine call routine) takes

four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is

popped back from the Stack, and the Stack Pointer is incremented by 2. When the AVR

exits from an interrupt, it will always return to the main program and execute one more

instruction before any pending interrupt is served.

Sleep Modes

To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a

SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register

select which sleep mode (Idle, Power-down, or Power-save) will be activated by the

SLEEP instruction, see Table 3 on page 23.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, exe-

cutes the interrupt routine and resumes execution from the instruction following SLEEP.

The contents of the Register File, SRAM, and I/O memory are unaltered. If a reset

occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

Idle Mode

When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the

Idle mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC,

Timer/Counters, Watchdog and the interrupt system to continue operating. This enables

the MCU to wake up from external triggered interrupts as well as internal ones like the

Timer Overflow and UART Receive Complete interrupts. If wake-up from the Analog

Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This

will reduce power consumption in Idle mode. When the MCU wakes up from Idle mode,

the CPU starts program execution immediately.

36

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Power-down Mode

When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the

Power-down mode. In this mode, the external Oscillator is stopped while the external

interrupts and the Watchdog (if enabled) continue operating. Only an External Reset, a

Watchdog Reset (if enabled), or an external level interrupt can wake up the MCU.

Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the

changed level must be held for some time to wake up the MCU. This makes the MCU

less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator

clock and if the input has the required level during this time, the MCU will wake up. The

period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of

the Watchdog Oscillator is voltage-dependent, as shown in “Typical Characteristics” on

page 123.

When waking up from Power-down mode, a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable

after having been stopped. The wake-up period is defined by the same SUT fuses that

define the Reset Time-out period. The wake-up period is equal to the clock reset period,

as shown in Table 5 on page 27.

If the wake-up condition disappears before the MCU wakes up and starts to execute,

e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be

executed.

Power-save Mode

When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the

Power-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set,

Timer/Counter0 will run during sleep. In addition to the Power-down wake-up sources,

the device can also wake up from either Timer Overflow or Output Compare event from

Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in

TIMSK. To ensure that the part executes the interrupt routine when waking up, also set

the Global Interrupt Enable bit i SREG.

When waking up from Power-save mode by an external interrupt, two instruction cycles

are executed before the Interrupt Flags are updated. When waking up by the asynchro-

nous timer, three instruction cycles are executed before the flags are updated. During

these cycles, the processor executes instructions, but the interrupt condition is not read-

able and the interrupt routine has not started yet. If the asynchronous timer is not

clocked asynchronously, Power-down mode is recommended instead of Power-save

mode because the contents of the registers in the asynchronous timer should be consid-

ered undefined after wake-up in Power-save mode if AS0 is 0.

37

0945I–AVR–02/07

Timer/Counters

The ATmega103(L) provides three general purpose Timer/Counters – two 8-bit T/Cs

and one 16-bit T/C. Timer/Counter0 optionally can be asynchronously clocked from an

external Oscillator. This Oscillator is optimized for use with a 32.768 kHz crystal,

enabling use of Timer/Counter0 as a Real Time Clock (RTC). Timer/Counter0 has its

own prescaler. Timer/Counters 1 and 2 have individual prescaling selection from the

same 10-bit prescaling timer. These Timer/Counters can either be used as a Timer with

an internal clock time base or as a counter with an external pin connection that triggers

the counting.

Timer/Counter

Prescalers

Figure 28. Prescaler for Timer/Counter1 and Timer/Counter2

CK

10-BIT T/C PRESCALER

T1

T2

0

CS20

CS21

CS22

CS10

CS11

CS12

TIMER/COUNTER2 CLOCK SOURCE

TCK2

TIMER/COUNTER1 CLOCK SOURCE

TCK1

For Timer/Counters 1 and 2, the four different prescaled selections are: CK/8, CK/64,

CK/256 and CK/1024, where CK is the CPU clock. Observe that CPU clock frequency

can be lower than the XTAL frequency if the XTAL divider is enabled. For

Timer/Counters 1 and 2, added selections as CK, external source and stop can be

selected as clock sources.

Figure 29. The Timer/Counter0 Prescaler

CK

PCK0

10-BIT T/C PRESCALER

TOSC1

AS0

CS00

CS01

CS02

TIMER/COUNTER0 CLOCK SOURCE

PCK0

38

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

The clock source for Timer/Counter0 prescaler is named PCK0. PCK0 is by default con-

nected to the main system clock CK. Observe that CPU clock frequency can be lower

than the XTAL frequency if the XTAL divider is enabled. By setting the AS0 bit in ASSR,

Timer/Counter0 prescaler is asynchronously clocked from the TOSC1 pin. This enables

use of Timer/Counter0 as a Real Time Clock (RTC). A crystal can be connected

between the TOSC1 and TOSC2 pins to serve as an independent clock source for

Timer/Counter0. This Oscillator is optimized for use with a 32.768 kHz crystal.

8-bit Timer/Counters

T/C0 and T/C2

Figure 30 shows the block diagram for Timer/Counter0. Figure 31 shows the block dia-

gram for Timer/Counter2.

Figure 30. Timer/Counter0 Block Diagram

T/C0 OVER- T/C0 COMPARE

FLOW IRQ

MATCH IRQ

8-BIT DATA BUS

8-BIT ASYNCH T/C0 DATA BUS

TIMER INT. MASK

REGISTER (TIMSK)

TIMER INT. FLAG

REGISTER (TIFR)

T/C0 CONTROL

REGISTER (TCCR0)

7

0

T/C CLEAR

TIMER/COUNTER0

(TCNT0)

T/C CLK SOURCE

UP/DOWN

CONTROL

LOGIC

PCK0

7

8-BIT COMPARATOR

7

OUTPUT COMPARE

REGISTER0 (OCR0)

ASYNCH. STATUS

REGISTER (ASSR)

CK

TCK0

SYNCH UNIT

39

0945I–AVR–02/07

Figure 31. Timer/Counter2 Block Diagram

T/C2 OVER- T/C2 COMPARE

FLOW IRQ MATCH IRQ

TIMER INT. MASK

REGISTER (TIMSK)

TIMER INT. FLAG

REGISTER (TIFR)

T/C2 CONTROL

REGISTER (TCCR2)

7

0

TIMER/COUNTER2

(TCNT2)

T/C CLEAR

CK

T/C CLK SOURCE

UP/DOWN

CONTROL

LOGIC

T2

7

0

8-BIT COMPARATOR

OUTPUT COMPARE

REGISTER2 (OCR2)

The 8-bit Timer/Counter0 can select clock source from PCK0 or prescaled PCK0. The 8-

bit Timer/Counter2 can select clock source from CK, prescaled CK or an external pin.

Both Timer/Counters can be stopped as described in the specification for the

Timer/Counter Control Registers – TCCR0 and TCCR2.

The different Status Flags (Overflow, Compare Match and Capture Event) are found in

the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the

Timer/Counter Control Registers – TCCR0 and TCCR2. The interrupt enable/disable

settings are found in the Timer/Counter Interrupt Mask Register (TIMSK).

When Timer/Counter2 is externally clocked, the external signal is synchronized with the

Oscillator frequency of the CPU. To assure proper sampling of the external clock, the

minimum time between two external clock transitions must be at least one internal CPU

clock period. The external clock signal is sampled on the rising edge of the internal CPU

clock.

The 8-bit Timer/Counters feature a high-resolution and a high-accuracy usage with the

lower prescaling opportunities. Similarly, the high prescaling opportunities make these

units useful for lower speed functions or exact timing functions with infrequent actions.

Both Timer/Counters support two Output Compare functions using the Output Compare

Registers (OCR0 and OCR2) as the data source to be compared to the Timer/Counter

contents. The Output Compare functions include optional clearing of the counter on

compare match and action on the Output Compare pins – PB4(OC0/PWM0) and

PB7(OC2/PWM2) – on compare match.

Timer/Counters 0 and 2 can also be used as 8-bit Pulse Width Modulators. In this mode

the Timer/Counter and the Output Compare Register serve as a glitch-free, stand-alone

PWM with centered pulses. Refer to page 43 for a detailed description of this function.

40

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Timer/Counter0 Control

Register – TCCR0

Bit

7

–

6

PWM0

R/W

0

5

COM01

R/W

0

4

COM00

R/W

0

3

CTC0

R/W

0

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

33 ($53)

Read/Write

Initial Value

TCCR0

R

0

Timer/Counter2 Control

Register – TCCR2

Bit

7

–

6

PWM2

R/W

0

5

COM21

R/W

0

4

COM20

R/W

0

3

CTC2

R/W

0

2

CS22

R/W

0

1

CS21

R/W

0

CS20

R/W

0

$25 ($45)

Read/Write

Initial Value

TCCR2

R

0

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the ATmega103(L) and always reads as zero.

• Bit 6 – PWM0/PWM2: Pulse Width Modulator Enable

When set (one), this bit enables PWM mode for Timer/Counter0 or Timer/Counter2.

This mode is described on page 43.

• Bits 5, 4 – COM01, COM00/COM21, COM20: Compare Output Mode, Bits 1 and 0

The COMn1 and COMn0 control bits determine any output pin action following a com-

pare match in Timer/Counter2. Any output pin actions affect pins PB4 (OC0/PWM0) or

PB7 (OC2/PWM2). Since this is an alternative function to an I/O port, the corresponding

direction control bit must be set (one) to control an output pin. The control configuration

is shown in Table 10.

Table 10. Compare Mode Select

COMn1

COMn0

Description

0

1

0

1

0

1

Timer/Counter disconnected from output pin OCn/PWMn

Toggle the OCn/PWMn output line.

Clear the OCn/PWMn output line (to zero).

Set the OCn/PWMn output line (to one).

Note:

n = 0 or 2

In PWM mode, these bits have a different function. Refer to Table 13 for a detailed

description.

• Bit 3 – CTC0/CTC2: Clear Timer/Counter on Compare Match

When the CTC0 or CTC2 control bit is set (one), the Timer/Counter is reset to $00 in the

CPU clock cycle after a compare match. If the control bit is cleared, the Timer continues

counting and is unaffected by a compare match. Since the compare match is detected in

the CPU clock cycle following the match, this function will behave differently when a

prescaling higher than 1 is used for the Timer. When a prescaling of 1 is used and the

Compare Register is set to C, the Timer will count as follows if CTC0/2 is set:

... | C-2 | C-1 | C | 0 | 1 | ...

When the prescaler is set to divide by 8, the Timer will count like this:

... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,

0, 0, 0, 0, 0, 0 | 1, 1, 1, ...

41

0945I–AVR–02/07

In PWM mode, this bit has no effect.

• Bits 2, 1, 0 – CS02, CS01, CS00/CS22, CS21, CS20: Clock Select Bits 2, 1 and 0

The Clock Select2 bits 2, 1 and 0 define the prescaling source of the Timer/Counter.

Table 11. Timer/Counter0 Prescale Select

CS02

CS01

CS00

Description

Timer/Counter0 is stopped.

PCK0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PCK0/8

PCK0/32

PCK0/64

PCK0/128

PCK0/256

PCK0/1024

Table 12. Timer/Counter2 Prescale Select

CS22

CS21

CS20

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Timer/Counter2 is stopped.

CK

CK/8

CK/64

CK/256

CK/1024

External Pin PD7(T2), falling edge

External Pin PD7(T2), rising edge

The Stop condition provides a Timer Enable/Disable function. The CK down divided

modes are scaled directly from the CK CPU clock. If the external pin modes are used for

Timer/Counter2, transitions on PD7/(T2) will clock the counter even if the pin is config-

ured as an output. This feature can give the user software control of the counting.

Timer/Counter0 – TCNT0

Timer/Counter2 – TCNT2

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$32 ($42)

Read/Write

Initial Value

LSB

R/W

0

TCNT0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$24 ($44)

Read/Write

Initial Value

LSB

R/W

0

TCNT2

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

42

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

These 8-bit registers contain the value of the Timer/Counters.

Both Timer/Counters are realized as up or up/down (in PWM mode) counters with read

and write access. If the Timer/Counter is written to and a clock source is selected, it con-

tinues counting in the timer clock cycle after it is preset with the written value.

Timer/Counter0 Output

Compare Register – OCR0

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$31 ($51)

Read/Write

Initial Value

LSB

R/W

0

OCR0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Timer/Counter2 Output

Compare Register – OCR2

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$23 ($43)

Read/Write

Initial Value

LSB

R/W

0

OCR2

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Registers are 8-bit read/write registers.

The Timer/Counter Output Compare Registers contain the data to be continuously com-

pared with the Timer/Counter. Actions on compare matches are specified in TCCR0 and

TCCR2. A compare match does only occur if the Timer/Counter counts to the OCR

value. A software write that sets the Timer/Counter and Output Compare Register to the

same value does not generate a compare match.

A compare match will set the Compare Interrupt Flag in the CPU clock cycle following

the compare event.

Timer/Counters 0 and 2 in

PWM Mode

When the PWM mode is selected, the Timer/Counter and the Output Compare Register

(OCR0 or OCR2) form an 8-bit, free-running, glitch-free and phase correct PWM with

outputs on the PB4(OC0/PWM0) or PB7(OC2/PWM2) pin. The Timer/Counter acts as

an up/down counter, counting up from $00 to $FF, where it turns and counts down again

to zero before the cycle is repeated. When the counter value matches the contents of

the Output Compare Register, the PB4(OC0/PWM0) or PB7(OC2/PWM2) pin is set or

cleared according to the settings of the COM01/COM00 or COM21/COM20 bits in the

Timer/Counter Control Registers TCCR0 and TCCR2. Refer to Table 13 for details.

Table 13. Compare Mode Select in PWM Mode

COMn1 COMn0 Effect on Compare/PWM Pin

0

1

Not connected

Cleared on compare match, up-counting. Set on compare match, down-

counting (non-inverted PWM).

1

0

Cleared on compare match, down-counting. Set on compare match, up-

counting (inverted PWM).

1

Note:

n = 0 or 2

Note that in PWM mode, the Output Compare Register is transferred to a temporary

location when written. The value is latched when the Timer/Counter reaches $FF. This

prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsyn-

chronized OCR0 or OCR2 write. See Figure 32 for an example.

43

0945I–AVR–02/07

Figure 32. Effects on Unsynchronized OCR Latching

Compare Value changes

Counter Value

Compare Value

PWM Output

Synchronized OCR Latch

Compare Value changes

Counter Value

Compare Value

PWM Output

Glitch

Unsynchronized OCR Latch

During the time between the write and the latch operation, a read from OCR0 or OCR2

will read the contents of the temporary location. This means that the most recently writ-

ten value always will read out of OCR0/2.

When the OCR Register (not the temporary register) is updated to $00 or $FF, the PWM

output changes to low or high immediately according to the settings of COM21/COM20

or COM11/COM10. This is shown in Table 14.

Table 14. PWM Outputs OCRn = $00 or $FF

COMn1

COMn0

OCRn

$00

Output PWMn

1

0

1

L

H

L

$FF

$00

$FF

Note:

n = 0 or 2

In PWM mode, the Timer Overflow Flag, TOV0 or TOV2, is set when the counter

advances from $00. Timer Overflow Interrupts 0 and 2 operate exactly as in normal

Timer/Counter mode, i.e., it is executed when TOV0 or TOV2 is set, provided that Timer

Overflow interrupt and Global Interrupts are enabled. This also applies to the Timer Out-

put Compare Flags and interrupts.

The frequency of the PWM will be Timer Clock Frequency divided by 510.

Asynchronous Status

Register – ASSR

Bit

7

–

6

–

5

–

4

–

3

2

1

0

AS0

R/W

0

TCN0UB

OCR0UB

TCR0UB

ASSR

$30 ($50)

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

44

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

• Bit 3 – AS0: Asynchronous Timer/Counter0

When set (one), Timer/Counter0 is clocked from the TOSC1 pin. When cleared (zero),

Timer/Counter0 is clocked from the internal system clock, CK. When the value of this bit

is changed, the contents of TCNT0 might get corrupted.

• Bit 2 – TCN0UB: Timer/Counter0 Update Busy

When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes

set (one). When TCNT0 has been updated from the temporary storage register, this bit

is cleared (zero) by hardware. A logical “0” in this bit indicates that TCNT0 is ready to be

updated with a new value.

• Bit 1 – OCR0UB: Output Compare Register0 Update Busy

When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes

set (one). When OCR0 has been updated from the temporary storage register, this bit is

cleared (zero) by hardware. A logical “0” in this bit indicates that OCR0 is ready to be

updated with a new value.

• Bit 0 – TCR0UB: Timer/Counter Control Register0 Update Busy

When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes

set (one). When TCCR0 has been updated from the temporary storage register, this bit

is cleared (zero) by hardware. A logical “0” in this bit indicates that TCCR0 is ready to be

updated with a new value.

If a write is performed to any of the three Timer/Counter0 Registers while its update

busy flag is set (one), the updated value might get corrupted and cause an unintentional

interrupt to occur.

When reading TCNT0, OCR0 and TCCR0, there is a difference in result. When reading

TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the

temporary storage register is read.

Asynchronous Operation of

Timer/Counter0

When Timer/Counter0 operates synchronously, all operations and timing are identical to

Timer/Counter2. During asynchronous operation, however, some considerations must

be taken.

•

WARNING: When switching between asynchronous and synchronous clocking of

Timer/Counter0, the Timer Registers TCNT0, OCR0 and TCCR0 might get

corrupted. The following is the safe procedure for switching clock source:

1. Disable the Timer0 interrupts OCIE0 and TOIE0.

2. Select clock source by setting ASO as appropriate.

3. Write new values to TCNT0, OCR0 and TCCR0.

4. If switching to asynchronous operation, wait for TCNT0UB, OCR0UB and

TCR0UB to be cleared.

5. Clear the Timer/Counter0 Interrupt Flags.

6. Enable interrupts if needed.

•

The Oscillator is optimized for use with a 32,768 Hz watch crystal. An external clock

signal applied to this pin goes through the same amplifier having a bandwidth of

256 kHz. The external clock signal should therefore be in the interval 0 Hz -

256 kHz. The frequency of the clock signal applied to the TOSC1 pin must be lower

than one fourth of the CPU main clock frequency. Observe that CPU clock

frequency can be lower than the XTAL frequency if the XTAL divider is enabled.

45

0945I–AVR–02/07

•

When writing to one of the registers TCNT0, OCR0 or TCCR0, the value is

transferred to a temporary register and latched after two positive edges on TOSC1.

The user should not write a new value before the contents of the temporary register

have been transferred to its destination. Each of the three mentioned registers have

their individual temporary register, which means that e.g., writing to TCNT0 does not

disturb an OCR0 write in progress. To detect that a transfer to the destination

register has taken place, an Asynchronous Status Register (ASSR) has been

implemented.

When entering Power-save mode after having written to TCNT0, OCR0 or TCCR0,

the user must wait until the written register has been updated if Timer/Counter0 is

used to wake up the device. Otherwise, the MCU will go to sleep before the changes

have had any effect. This is extremely important if the Output Compare0 interrupt is

used to wake up the device; Output Compare is disabled during write to OCR0 or

TCNT0. If the write cycle is not finished (i.e., the user goes to sleep before the

OCR0UB bit returns to zero), the device will never get a compare match and the

MCU will not wake up.

If Timer/Counter0 is used to wake up the device from Power-save mode,

precautions must be taken if the user wants to reenter Power-save mode: The

interrupt logic needs one TOSC1 cycle to get reset. If the time between wake-up

and reentering Power-save mode is less than one TOSC1 cycle, the interrupt will not

occur and the device will fail to wake up. If the user is in doubt whether the time

before re-entering Power-save is sufficient, the following algorithm can be used to

ensure that one TOSC1 cycle has elapsed:

1. Write a value to TCCR0, TCNT0 or OCR0.

2. Wait until the corresponding Update Busy Flag in ASSR returns to zero.

3. Enter Power-save mode.

•

When asynchronous operation is selected, the 32 kHz Oscillator for Timer/Counter0

is always running, except in Power-down mode. After a Power-up Reset or wake-up

from Power-down, the user should be aware of the fact that this Oscillator might take

as long as one second to stabilize. The user is advised to wait for at least one

second before using Timer/Counter0 after Power-up or wake-up from Power-down.

The content of all Timer/Counter0 Registers must be considered lost after a wake-

up from Power-down due to the unstable clock signal upon start-up, no matter

whether the Oscillator is in use or a clock signal is applied to the TOSC pin.

Description of wake-up from Power-save mode when the Timer is clocked

asynchronously: When the interrupt condition is met, the wake-up process is started

on the following cycle of the Timer clock, that is, the Timer is always advanced by at

least one before the processor can read the counter value. To execute the

corresponding Timer/Counter0 interrupt routine, the Global Interrupt bit in SREG

must have been set. Otherwise, the part will still wake up from Power-down, but

continues to execute the Sleep command. The Interrupt Flags are updated three

processor cycles after the processor clock has started. During these cycles, the

processor executes instructions, but the interrupt condition is not readable and the

interrupt routine has not started yet.

•

During asynchronous operation, the synchronization of the Interrupt Flags for the

asynchronous Timer takes three processor cycles plus one timer cycle. The Timer is

therefore advanced by at least one before the processor can read the Timer value

causing the setting of the Interrupt Flag. The Output Compare pin is changed on the

Timer clock, and is not synchronized to the processor clock.

•

After waking up from Power-save mode with the asynchronous Timer enabled, there

will be a short interval of which TCNT0 will read as the same value as before Power-

46

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

save mode was entered. After an edge on the asynchronous clock, TCNT0 will read

correctly. (The compare and overflow functions of the Timer are not affected by this

behavior.) Safe procedure to ensure correct value is read:

1. Write any value to either of the registers OCR0 or TCCR0

2. Wait for the corresponding Update Busy Flag to be cleared

3. Read TCNT0

Note that OCR0 and TCCR0 are never modified by hardware, and will always read

correctly.

16-bit Timer/Counter1

Figure 33 shows the block diagram for Timer/Counter1.

The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an exter-

nal pin. In addition, it can be stopped as described in the specification for the

Timer/Counter1 Control Register (TCCR1B). The different Status Flags (Overflow, Com-

pare Match and Capture Event) are found in the Timer/Counter Interrupt Flag Register

(TIFR). Control signals are found in the Timer/Counter1 Control Registers – TCCR1A

and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the

Timer/Counter Interrupt Mask Register (TIMSK).

When Timer/Counter1 is externally clocked, the external signal is synchronized with the

Oscillator frequency of the CPU. To assure proper sampling of the external clock, the

minimum time between two external clock transitions must be at least one internal CPU

clock period. The external clock signal is sampled on the rising edge of the internal CPU

clock.

The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage

with the lower prescaling opportunities. Similarly, the high prescaling opportunities

makes the Timer/Counter1 useful for lower speed functions or exact timing functions

with infrequent actions.

The Timer/Counter1 supports two Output Compare functions using the Output Compare

Registers 1A and 1B (OCR1A and OCR1B) as the data sources to be compared to the

Timer/Counter1 contents. The Output Compare functions include optional clearing of

the counter on Compare A Match, and actions on the Output Compare pins on both

compare matches.

47

0945I–AVR–02/07

Figure 33. Timer/Counter1 Block Diagram

T/C1 OVER-

FLOW IRQ

T/C1 COMPARE T/C1 COMPARE T/C1 INPUT

MATCHA IRQ MATCHB IRQ CAPTURE IRQ

TIMER INT. MASK

REGISTER (TIMSK)

TIMER INT. FLAG

REGISTER (TIFR)

T/C1 CONTROL

REGISTER A (TCCR1A)

T/C1 CONTROL

REGISTER B (TCCR1B)

15

8

7

0

T/C1 INPUT CAPTURE REGISTER (ICR1)

CK

CONTROL

LOGIC

T1

CAPTURE

TRIGGER

15

8

7

0

T/C CLEAR

T/C CLOCK SOURCE

UP/DOWN

TIMER/COUNTER1 (TCNT1)

8

7

15

8

7

0

16-BIT COMPARATOR

8

7

15

8

7

TIMER/COUNTER1 OUTPUT COMPARE REGISTER A

TIMER/COUNTER1 OUTPUT COMPARE REGISTER B

Timer/Counter1 can also be used as an 8-, 9- or 10-bit Pulse Width Modulator. In this

mode the counter and the OCR1A/OCR1B Registers serve as a dual glitch-free stand-

alone PWM with centered pulses. Refer to page 53 for a detailed description of this

function.

The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1

contents to the Input Capture Register (ICR1), triggered by an external event on the

Input Capture pin – PD4/(IC1). The actual capture event settings are defined by the

Timer/Counter1 Control Register (TCCR1B). In addition, the Analog Comparator can be

set to trigger the Input Capture. Refer to “Analog Comparator” on page 75 for details on

this. The ICP pin logic is shown in Figure 34.

Figure 34. ICP Pin Schematic Diagram

48

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

If the Noise Canceler function is enabled, the actual trigger condition for the capture

event is monitored over four samples, and all four must be equal to activate the capture

flag.

Timer/Counter1 Control

Register A – TCCR1A

Bit

7

COM1A1

R/W

6

COM1A0

R/W

5

COM1B1

R/W

4

COM1B0

R/W

3

–

2

–

1

PWM11

R/W

0

PWM10

R/W

0

TCCR1A

$2F ($4F)

Read/Write

Initial Value

R

0

R

0

• Bits 7..6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0

The COM1A1 and COM1A0 control bits determine any output pin action following a

compare match in Timer/Counter1. Any output pin actions affect pin OC1A – Output

Compare A pin 1. This is an alternative function to an I/O port, and the corresponding

direction control bit must be set (one) to control an output pin. The control configuration

is shown in Table 15

• Bits 5..4 – COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0

The COM1B1 and COM1B0 control bits determine any output pin action following a

compare match in Timer/Counter1. Any output pin actions affect pin OC1B – Output

Compare B. Since this is an alternative function to an I/O port, the corresponding direc-

tion control bit must be set (one) to control an output pin. The control configuration is

given in Table 15.

Table 15. Compare1 Mode Select

COM1X1

COM1X0

Description

0

1

0

1

0

1

Timer/Counter1 disconnected from output pin OC1X

Toggle the OC1X output line.

Clear the OC1X output line (to zero).

Set the OC1X output line (to one).

Note:

X = A or B.

In PWM mode, these bits have a different function. Refer to Table 16 for a detailed

description.

• Bits 3..2 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

• Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select Bits

These bits select PWM operation of Timer/Counter1 as specified in Table 18 on page

53. This mode is described on page 53.

Table 16. PWM Mode Select

PWM11

PWM10

Description

0

PWM operation of Timer/Counter1 is disabled.

49

0945I–AVR–02/07

Table 16. PWM Mode Select

PWM11

PWM10

Description

0

1

0

1

Timer/Counter1 is an 8-bit PWM.

Timer/Counter1 is a 9-bit PWM.

Timer/Counter1 is a 10-bit PWM.

Timer/Counter1 Control

Register B – TCCR1B

Bit

7

6

ICES1

R/W

0

5

–

4

–

3

CTC1

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

$2E ($4E)

Read/Write

Initial Value

ICNC1

R/W

0

TCCR1B

R

0

R

0

• Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)

When the ICNC1 bit is cleared (zero), the Input Capture Trigger Noise Canceler function

is disabled. The Input Capture is triggered at the first rising/falling edge sampled on the

Input Capture pin PD4(IC1) as specified. When the ICNC1 bit is set (one), four succes-

sive samples are measured on PD4(IC1), and all samples must be high/low according to

the Input Capture trigger specification in the ICES1 bit. The actual sampling frequency is

XTAL clock frequency.

• Bit 6 – ICES1: Input Capture1 Edge Select

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the

Input Capture Register (ICR1) on the falling edge of the Input Capture pin – PD4(IC1).

While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the

Input Capture Register on the rising edge of the Input Capture pin – PD4(IC1).

• Bits 5, 4 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

• Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match

When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock

cycle after a Compare A Match. If the CTC1 control bit is cleared, Timer/Counter1 con-

tinues counting and is unaffected by a compare match. Since the compare match is

detected in the CPU clock cycle following the match, this function will behave differently

when a prescaling higher than 1 is used for the Timer. When a prescaling of 1 is used

and the Compare A Register is set to C, the Timer will count as follows if CTC1 is set:

... | C-2 | C-1 | C | 0 | 1 | ...

When the prescaler is set to divide by 8, the Timer will count like this:

... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,

0, 0, 0, 0, 0, 0 | ...

In PWM mode, this bit has no effect.

50

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

• Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0

The lock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1.

Table 17. Clock1 Prescale Select

CS12

CS11

CS10

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Stop, the Timer/Counter1 is stopped.

CK

CK/8

CK/64

CK/256

CK/1024

External Pin T1, falling edge

External Pin T1, rising edge

The Stop condition provides a Timer Enable/Disable function. The CK down divided

modes are scaled directly from the CK CPU clock. If the external pin modes are used for

Timer/Counter1, transitions on PD6/(T1) will clock the counter even if the pin is config-

ured as an output. This feature can give the user software control of the counting.

Timer/Counter1 – TCNT1H

and TCNT1L

Bit

15

14

13

12

11

10

9

8

$2D ($4D)

$2C ($4C)

MSB

TCNT1H

TCNT1L

LSB

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial Value

R/W

0

This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To

ensure that both the high and low bytes are read and written simultaneously when the

CPU accesses these registers, the access is performed using an 8-bit temporary regis-

ter (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and

ICR1. If the main program and interrupt routines perform access to registers using

TEMP, interrupts must be disabled during access from the main program (and from

interrupt routines if interrupts are allowed from within interrupt routines).

•

TCNT1 Timer/Counter1 Write:

When the CPU writes to the High Byte TCNT1H, the written data is placed in the

TEMP Register. Next, when the CPU writes the Low Byte TCNT1L, this byte of data

is combined with the byte data in the TEMP Register, and all 16 bits are written to

the TCNT1 Timer/Counter1 Register simultaneously. Consequently, the High Byte

TCNT1H must be accessed first for a full 16-bit register write operation. When using

Timer/Counter1 as an 8-bit Timer, it is sufficient to write the Low Byte only.

•

TCNT1 Timer/Counter1 Read:

When the CPU reads the Low Byte TCNT1L, the data of TCNT1L is sent to the CPU

and the data of the High Byte TCNT1H is placed in the TEMP Register. When the

CPU reads the data in the High Byte TCNT1H, the CPU receives the data in the

TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a

51

0945I–AVR–02/07

full 16-bit register read operation. When using Timer/Counter1 as an 8-bit Timer, it

is sufficient to read the Low Byte only.

The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read

and write access. If Timer/Counter1 is written to and a clock source is selected, the

Timer/Counter1 continues counting in the clock cycle after it is preset with the written

value.

Timer/Counter1 Output

Compare Register – OCR1AH

and OCR1AL

Bit

15

14

13

12

11

10

9

8

$2B

$2A

MSB

OCR1AH

OCR1AL

LSB

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial Value

R/W

0

Timer/Counter1 Output

Compare Register – OCR1BH

and OCR1BL

Bit

15

14

13

12

11

10

9

8

$29

$28

MSB

OCR1BH

OCR1BL

LSB

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial Value

R/W

0

The Output Compare Registers are 16-bit read/write registers.

The Timer/Counter1 Output Compare Registers contain the data to be continuously

compared with Timer/Counter1. Actions on compare matches are specified in the

Timer/Counter1 Control and Status Registers. A compare match occurs only if

Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A

or OCR1B to the same value does not generate a compare match.

A compare match will set the Compare Interrupt Flag in the CPU clock cycle following

the compare event.

Since the Output Compare Registers (OCR1A and OCR1B) are 16-bit registers, a tem-

porary register TEMP is used when OCR1A/B are written to ensure that both bytes are

updated simultaneously. When the CPU writes the High Byte, OCR1AH or OCR1BH,

the data is temporarily stored in the TEMP Register. When the CPU writes the Low Byte,

OCR1AL or OCR1BL, the TEMP Register is simultaneously written to OCR1AH or

OCR1BH. Consequently, the High Byte OCR1AH or OCR1BH must be written first for a

full 16-bit register write operation.

The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program

and interrupt routines perform access to registers using TEMP, interrupts must be dis-

abled during access from the main program.

Timer/Counter1 Input Capture

Register – ICR1H and ICR1L

Bit

15

14

6

13

5

12

4

11

3

10

2

9

1

8

$27 ($37)

$26 ($36)

MSB

ICR1H

ICR1L

LSB

7

0

52

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

The Input Capture Register is a 16-bit read-only register.

When the rising or falling edge (according to the Input Capture edge setting (ICES1)) of

the signal at the Input Capture pin – PD4(IC1) – is detected, the current value of the

Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time,

the Input Capture Flag (ICF1) is set (one).

Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register TEMP

is used when ICR1 is read to ensure that both bytes are read simultaneously. When the

CPU reads the Low Byte ICR1L, the data is sent to the CPU and the data of the High

Byte ICR1H is placed in the TEMP Register. When the CPU reads the data in the High

Byte ICR1H, the CPU receives the data in the TEMP Register. Consequently, the Low

Byte ICR1L must be accessed first for a full 16-bit register read operation.

The TEMP Register is also used when accessing TCNT1, OCR1A and OCR1B. If the

main program and interrupt routines perform access to registers using TEMP, interrupts

must be disabled during access from the main program.

Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1, the Output Compare Register1A

(OCR1A) and the Output Compare Register1B (OCR1B) form a dual 8-, 9- or 10-bit,

free-running, glitch-free and phase-correct PWM with outputs on the PB5(OC1A) and

PB6(OC1B) pins. Timer/Counter1 acts as an up/down counter, counting up from $0000

to TOP (see Table 16), where it turns and counts down again to zero before the cycle is

repeated. When the counter value matches the contents of the 10 least significant bits of

OCR1A or OCR1B, the PB5(OC1A)/PB6(OC1B) pins are set or cleared according to the

settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1

Control Register, TCCR1A. Refer to Table 19 for details.

Table 18. Timer TOP Values and PWM Frequency

PWM Resolution

Timer TOP value

$00FF (255)

Frequency

f_TCK1/510

8-bit

9-bit

$01FF (511)

f_TCK1/1022

10-bit

$03FF (1023)

f_TCK1/2046

Table 19. Compare1 Mode Select in PWM Mode

COM1X1 COM1X0 Effect on OCX1

0

1

Not connected

Cleared on compare match, up-counting. Set on compare match,

down-counting (non-inverted PWM).

1

0

Cleared on compare match, down-counting. Set on compare match,

up-counting (inverted PWM).

1

Note:

X = A or B

Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written,

are transferred to a temporary location. They are latched when Timer/Counter1 reaches

53

0945I–AVR–02/07

the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the

event of an unsynchronized OCR1A/OCR1B write. See Figure 35 for an example.

Figure 35. Effects on Unsynchronized OCR1 Latching

Compare Value changes

Counter alue

V

Compare V

alue

Output OC1X

PWM

Synchronized

OCR1X Latch

Compare Value changes

Counter

Value

Compare Value

PWM Output OC1X

Glitch

Unsynchronized

OCR1X Latch

Note: X = A or B

During the time between the write and the latch operation, a read from OCR1A or

OCR1B will read the contents of the temporary location. This means that the most

recently written value always will read out of OCR1A/B.

When the OCR1A/OCR1B contains $0000 or TOP, the output OC1A/OC1B is updated

to low or high on the next compare match according to the settings of

COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 20.

Note:

If the Compare Register contains the TOP value and the prescaler is not in use

(CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-

counting and down-counting value is reached simultaneously. When the prescaler is in

use (CS12..CS10 ≠ 001 or 000), the PWM output goes active when the counter reaches

the TOP value, but the down-counting compare match is not interpreted to be reached

before the next time the counter reaches the TOP value, making a one-period PWM

pulse.

Table 20. PWM Outputs OCR1X = $0000 or TOP

COM1X1

COM1X0

OCR1X

$0000

TOP

Output OC1X

1

0

1

L

H

L

$0000

TOP

Note:

X = A or B

In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from

$0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode,

i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and Global

Interrupts are enabled. This does also apply to the Timer Output Compare1 flags and

interrupts.

54

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator. By controlling the

Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in

Table 21. See characterization data for typical values at other V_CClevels. The WDR

(Watchdog Reset) instruction resets the Watchdog Timer. From the Watchdog Reset,

eight different clock cycle periods can be selected to determine the reset period. If the

reset period expires without another Watchdog Reset, the ATmega103(L) resets and

executes from the Reset Vector. For timing details on the Watchdog Reset, refer to

page 29.

To prevent unintentional disabling of the Watchdog, a special turn-off procedure must

be followed when the Watchdog is disabled. Refer to the description of the Watchdog

Timer Control Register for details.

Figure 36. Watchdog Timer

Oscillator

1 MHz at V_CC= 5V

350 kHz at V_CC= 3V

Watchdog Timer Control

Register – WDTCR

Bit

7

–

6

–

5

–

4

WDTOE

R/W

0

3

WDE

R/W

0

2

WDP2

R/W

0

1

WDP1

R/W

0

WDP0

R/W

0

$21 ($41)

Read/Write

Initial Value

WDTCR

R

0

R

0

R

0

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set (one) when the WDE bit is cleared, Otherwise, the Watchdog will

not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.

Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is set (one), the Watchdog Timer is enabled and if the WDE is cleared

(zero), the Watchdog Timer function is disabled. WDE can only be cleared if the

WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-

dure must be followed:

55

0945I–AVR–02/07

1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must

be written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logical “0” to WDE. This disables the

Watchdog.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0

The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

Time-out periods are shown in Table 21.

Table 21. Watchdog Timer Prescale Select

Number of WDT

WDP2 WDP1 WDP0 Oscillator Cycles

Typical Time-out

at V_CC= 3.0V

Typical Time-out

at V_CC= 5.0V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16K cycles

47 ms

94 ms

0.19 s

0.38 s

0.75 s

1.5 s

15 ms

30 ms

60 ms

0.12 s

0,24 s

0.49 s

0.97 s

1.9 s

32K cycles

64K cycles

128K cycles

256K cycles

512K cycles

1,024K cycles

2,048K cycles

3.0 s

1

6.0 s

Note:

The frequency of the Watchdog Oscillator is voltage-dependent as shown in the Electri-

cal Characteristics section.

The WDR (Watchdog Reset) instruction should always be executed before the Watchdog

Timer is enabled. This ensures that the reset period will be in accordance with the

Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the

Watchdog Timer may not start counting from zero.

To avoid unintentional MCU Reset, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.

56

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

EEPROM Read/Write The EEPROM Access Registers are accessible in the I/O space.

Access

The write access time is in the range of 2.5 - 4 ms, depending on the V_CCvoltages. A

self-timing function lets the user software detect when the next byte can be written. A

special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to

accept new data.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed. When it is read, the CPU is halted for four clock cycles.

EEPROM Address Register –

EEARH, EEARL

Bit

15

14

13

12

11

EEAR11

EEAR3

3

10

EEAR10

EEAR2

2

9

EEAR9

EEAR1

1

8

EEAR8

EEAR0

0

$1F ($3F)

$1E ($3E)

–

EEARH

EEARL

EEAR7

EEAR6

EEAR5

EEAR4

7

R

6

R

5

R

4

R

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The EEPROM Address Registers (EEARH and EEARL) specify the EEPROM address

in the 4 KB EEPROM space. The EEPROM Data bytes are addressed linearly between

0 and 4095.

EEPROM Data Register –

EEDR

Bit

7

6

5

4

3

2

1

0

$1D ($3D)

Read/Write

Initial Value

MSB

R/W

0

LSB

R/W

0

EEDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7..0 – EEDR7..0: EEPROM Data:

For the EEPROM write operation, the EEDR Register contains the data to be written to

the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-

ation, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

EEPROM Control Register –

EECR

Bit

7

–

6

–

5

–

4

–

3

EERIE

R/W

0

2

EEMWE

R/W

0

1

EEWE

R/W

0

EERE

R/W

0

$1C ($3C)

Read/Write

Initial Value

EECR

R

0

R

0

R

0

R

0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and will always be read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is

enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt

constantly generates an interrupt request when EEWE is cleared (zero).

57

0945I–AVR–02/07

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be

written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the

selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE

has been set (one) by software, hardware clears the bit to zero after four clock cycles.

See the description of the EEWE bit for a EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable signal (EEWE) is the write strobe to the EEPROM. When

address and data are correctly set up, the EEWE bit must be set to write the value into

the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, oth-

erwise no EEPROM write takes place. The following procedure should be followed

when writing the EEPROM (the order of steps 2 and 3 is unessential):

1. Wait until EEWE becomes zero.

2. Write new EEPROM address to EEAR (optional).

3. Write new EEPROM Data to EEDR (optional).

4. Write a logical “1” to the EEMWE bit in EECR (to be able to write an logical “1” to

the EEMWE bit, the EEWE bit must be written to zero in the same cycle).

5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.

Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM access, the EEAR and EEDR Registers will

be modified, causing the interrupted EEPROM access to fail. It is recommended to have

the Global Interrupt Flag cleared during the four last steps to avoid these problems.

When the write access time (typically 2.5 ms at V_CC= 5V or 4 ms at V_CC= 2.7V) has

elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit

and wait for a zero before writing the next byte. When EEWE has been set, the CPU is

halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable signal (EERE) is the read strobe to the EEPROM. When

the correct address is set up in the EEAR Register, the EERE bit must be set. When the

EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register.

The EEPROM read access takes one instruction and there is no need to poll the EERE

bit. When EERE has been set, the CPU is halted for four cycles before the next instruc-

tion is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation

is in progress when new data or address is written to the EEPROM I/O Registers, the

write operation will be interrupted and the result is undefined.

58

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Prevent EEPROM

Corruption

During periods of low V_CC, the EEPROM Data can be corrupted because the supply volt-

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board-level systems using the EEPROM and the same design solutions

should be applied.

An EEPROM Data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequence to the EEPROM requires a minimum voltage to

operate correctly. Second, the CPU itself can execute instructions incorrectly if the sup-

ply voltage for executing instructions is too low.

EEPROM Data corruption can easily be avoided by following these design recommen-

dations (one is sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This is best done by an external low V_CCReset Protection circuit, often

referred to as a Brown-out Detector (BOD). Please refer to application note “AVR

180” for design considerations regarding Power-on Reset and low-voltage

detection.

2. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the EEPROM Registers from unintentional writes.

3. Store constants in Flash memory if the ability to change memory contents from

software is not required. Flash memory cannot be updated by the CPU and will

not be subject to corruption.

59

0945I–AVR–02/07

Serial Peripheral

Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between the ATmega103(L) and peripheral devices or between several AVR devices.

The ATmega103(L) SPI features include the following:

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Four Programmable Bit Rates

• End-of-Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode (Slave Mode only)

Figure 37. SPI Block Diagram

The interconnection between Master and Slave CPUs with SPI is shown in Figure 38.

The PB1 (SCK) pin is the clock output in the Master mode and is the clock input in the

Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock

generator, and the data written shifts out of the PB2 (MOSI) pin and into the PB2 (MOSI)

pin of the Slave CPU. After shifting one byte, the SPI clock generator stops, setting the

End-of-Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR

Register is set, an interrupt is requested. The Slave Select input, PB0(SS), is set low to

select an individual Slave SPI device. The two Shift Registers in the Master and the

Slave can be considered as one distributed 16-bit circular Shift Register. This is shown

in Figure 38. When data is shifted from the Master to the Slave, data is also shifted in

the opposite direction, simultaneously. This means that during one shift cycle, data in

the Master and the Slave are interchanged.

60

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 38. SPI Master-Slave Interconnection

MSB

MASTER

LSB

MSB

SLAVE

LSB

MISO MISO

8-BIT SHIFT REGISTER

MOSI MOSI

SCK

SS

SCK

SS

SPI

CLOCK GENERATOR

V_CC

The system is single-buffered in the transmit direction and double-buffered in the

receive direction. This means that characters to be transmitted cannot be written to the

SPI Data Register before the entire shift cycle is completed. When receiving data, how-

ever, a received byte must be read from the SPI Data Register before the next byte has

been completely shifted in. Otherwise, the first byte is lost.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is

overridden according to the following table:

Table 22. SPI Pin Overrides

MOSI

MISO

SCK

SS

Direction, Master SPI

User Defined

Input

Direction, Slave SPI

Input

User Defined

Input

User Defined

Input

Note:

See “Alternate Functions of Port B” on page 89 for a detailed description and how to

define the direction of the user-defined SPI pins.

SS Pin Functionality

When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine

the direction of the SS pin. If SS is configured as an output, the pin is a general output

pin that does not affect the SPI system. If SS is configured as an input, it must be held

high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry

when the SPI is configured as Master with the SS pin defined as an input, the SPI sys-

tem interprets this as another Master selecting the SPI as a Slave and starts to send

data to it. To avoid bus contention, the SPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a

result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in

SREG is set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmittal is used in Master mode and there exists a

possibility that SS is driven low, the interrupt should always check that the MSTR bit is

still set. Once the MSTR bit has been cleared by a Slave Select, it must be set by the

user to re-enable SPI Master mode.

When the SPI is configured as a Slave, the SS pin is always input. When SS is held low,

the SPI is activated and MISO becomes an output if configured so by the user. All other

pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, which

means that it will not receive incoming data. Note that the SPI logic will be reset once

61

0945I–AVR–02/07

the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI

will stop sending and receiving immediately and both data received and data sent must

be considered as lost.

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data that

are determined by control bits CPHA and CPOL. The SPI data transfer formats are

shown in Figure 39 and Figure 40.

Figure 39. SPI Transfer Format with CPHA = 0 and DORD = 0

SCK CYCLE #

(FOR REFERENCE)

1

2

3

4

5

6

7

8

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

(FROM MASTER)

MSB

6

5

4

3

2

1

LSB

MISO

(FROM SLAVE)

MSB

6

2

*

SS (TO SLAVE)

SAMPLE

* Not defined but normally MSB of character just received.

Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0

SCK CYCLE #

(FOR REFERENCE)

1

2

3

4

5

6

7

8

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MSB

6

5

4

3

2

1

LSB

(FROM MASTER)

MISO

(FROM SLAVE)

6

4

1

LSB

*

SS (TO SLAVE)

SAMPLE

* Not defined but normally LSB of previously transmitted character.

SPI Control Register – SPCR

Bit

7

6

5

DORD

R/W

0

4

MSTR

R/W

0

3

CPOL

R/W

0

2

CPHA

R/W

0

1

0

SPR0

R/W

0

$0D ($2D)

Read/Write

Initial Value

SPIE

R/W

0

SPE

R/W

0

SPR1

R/W

0

SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set

and the Global Interrupts are enabled.

• Bit 6 – SPE: SPI Enable

When the SPE bit is set (one), the SPI is enabled and SS, MOSI, MISO and SCK are

connected to pins PB0, PB1, PB2 and PB3.

62

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

• Bit 5 – DORD: Data Order

When the DORD bit is set (one), the LSB of the data word is transmitted first.

When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared

(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be

cleared and SPIF in SPSR will become set. The user will then have to set MSTR to re-

enable SPI Master mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is

low when idle. Refer to Figure 39 and Figure 40 for additional information.

• Bit 2 – CPHA: Clock Phase

Refer to Figure 39 or Figure 40 for the functionality of this bit.

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and

SPR0 have no effect on the Slave. The relationship between SCK and the CPU Clock

frequency (f_cl) is shown in Table 23.

Table 23. Relationship between SCK and the Oscillator Frequency

SPR1

SPR0

SCK Frequency

f_cl/4

0

1

0

1

0

1

f_cl/16

f_cl/64

f_cl/128

Note:

Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL

divider is enabled.

SPI Status Register – SPSR

Bit

7

SPIF

R

6

5

–

4

–

3

–

2

–

1

–

0

–

$0E

WCOL

SPSR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-

ated if SPIE in SPCR is set (one) and Global Interrupts are enabled. SPIF is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively, the

SPIF bit is cleared by first reading the SPI Status Register with SPIF set (one), then

accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write Collision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.

The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-

ister with WCOL set (one), and then accessing the SPI Data Register.

63

0945I–AVR–02/07

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and will always read as zero.

64

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

SPI Data Register – SPDR

Bit

7

6

5

4

3

2

1

0

$0F ($2F)

Read/Write

Initial Value

MSB

R/W

X

LSB

R/W

X

SPDR

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Undefined

The SPI Data Register is a read/write register used for data transfer between the Regis-

ter File and the SPI Shift Register. Writing to the register initiates data transmission.

Reading the register causes the Shift Register Receive buffer to be read.

65

0945I–AVR–02/07

UART

The ATmega103(L) features a full duplex (separate Receive and Transmit Registers)

Universal Asynchronous Receiver and Transmitter (UART). The main features are:

• Baud Rate Generator that can Generate a large Number of Baud Rates (bps)

• High Baud Rates at Low XTAL Frequencies

• 8 or 9 Bits Data

• Noise Filtering

• OverRun Detection

• Framing Error Detection

• False Start Bit Detection

• Three separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

Data Transmission

A block schematic of the UART Transmitter is shown in Figure 41.

Data transmission is initiated by writing the data to be transmitted to the UART I/O Data

Register, UDR. Data is transferred from UDR to the Transmit Shift Register when:

•

A new character has been written to UDR after the stop bit from the previous

character has been shifted out. The Shift Register is loaded immediately.

•

A new character has been written to UDR before the stop bit from the previous

character has been shifted out. The Shift Register is loaded when the stop bit of the

character currently being transmitted has been shifted out.

If the 10(11)-bit Transmit Shift Register is empty, data is transferred from UDR to the

Shift Register. At this time the UDRE (UART Data Register Empty) bit in the UART Sta-

tus Register, USR, is set. When this bit is set (one), the UART is ready to receive the

next character. Writing to UDR clears UDRE. At the same time as the data is transferred

from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit)

and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART

Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit

Shift Register.

66

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 41. UART Transmitter

DATA BUS

/16

BAUD x 16

BAUD RATE

XTAL

UART I/O DATA

REGISTER (UDR)

GENERATOR

STORE UDR

SHIFT ENABLE

PIN CONTROL

LOGIC

1

BAUD

10(11)-BIT TX

SHIFT REGISTER

TXD

CONTROL LOGIC

IDLE

UART CONTROL

REGISTER (UCR)

UART STATUS

REGISTER (USR)

DATA BUS

UDRE

IRQ

TXC

IRQ

On the baud rate clock following the transfer operation to the Shift Register, the start bit

is shifted out on the TXD pin, followed by the data, LSB first. When the stop bit has been

shifted out, the Shift Register is loaded if any new data has been written to the UDR dur-

ing the transmission. During loading, UDRE is set. If there is no new data in the UDR

Register to send when the stop bit is shifted out, the UDRE Flag will remain set. In this

case, after the stop bit has been present on TXD for one bit length, the TX Complete

Flag (TXC) in USR is set.

The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is

cleared (zero), the PE1 pin can be used for general I/O. When TXEN is set, the UART

Transmitter will be connected to PE1, which is forced to be an output pin regardless of

the setting of the DDE1 bit in DDRE.

67

0945I–AVR–02/07

Data Reception

Figure 42. UART Receiver

DATA BUS

UART I/O DATA

REGISTER (UDR)

XTAL

BAUD X 16

BAUD

BAUD RATE

/16

GENERATOR

STORE UDR

PIN CONTROL

LOGIC

DATA RECOVERY

LOGIC

10(11)-BIT RX

SHIFT REGISTER

RXD

UART CONTROL

REGISTER (UCR)

UART STATUS

REGISTER (USR)

DATA BUS

RXC

IRQ

The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times

the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as

the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample

1 denote the first zero-sample. Following the 1-to-0 transition, the Receiver samples the

RXD pin at samples 8, 9, and 10. If two or more of these three samples are found to be

logical “1”s, the start bit is rejected as a noise spike and the Receiver starts looking for

the next 1-to-0 transition.

If, however, a valid start bit is detected, sampling of the data bits following the start bit is

performed. These bits are also sampled at samples 8, 9 and 10. The logical value found

in at least two of the three samples is taken as the bit value. All bits are shifted into the

Transmitter Shift Register as they are sampled. Sampling of an incoming character is

shown in Figure 43.

68

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 43. Sampling Received Data

RXD

START BIT

D0

D1

D2

D3

D4

D5

D6

D7

STOP BIT

RECEIVER

SAMPLING

When the stop bit enters the Receiver, the majority of the three samples must be one to

accept the stop bit. If two or more samples are logical “0”s, the Framing Error (FE) Flag

in the UART Status Register (USR) is set when the received byte is transferred to UDR.

Before reading the UDR Register, the user should always check the FE bit to detect

Framing Errors. FE is cleared when UDR is read.

Whether or not a valid stop bit is detected at the end of a character reception cycle, the

data is transferred to UDR and the RXC Flag in USR is set. UDR is in fact two physically

separate registers, one for transmitted data and one for received data. When UDR is

read, the Receive Data Register is accessed, and when UDR is written, the Transmit

Data Register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Con-

trol Register, UCR is set), the RXB8 bit in UCR is loaded with bit 9 in the Transmit Shift

Register when data is transferred to UDR.

If, after having received a character, the UDR Register has not been accessed since the

last receive, the OverRun (OR) flag in USR is set. This means that the new data trans-

ferred to the Shift Register could not be transferred to UDR and is lost. The OR bit is

buffered, and is available when the valid data byte in UDR has been read. The user

should always check the OR after reading from the UDR Register in order to detect any

OverRuns if the baud rate is high or CPU load is high.

When the RXEN bit in the UCR Register is cleared (zero), the Receiver is disabled. This

means that the PE0 pin can be used as a general I/O pin. When RXEN is set, the UART

Receiver will be connected to PE0, which is forced to be an input pin regardless of the

setting of the DDE0 bit in DDRE. When PE0 is forced to input by the UART, the

PORTE0 bit can still be used to control the pull-up resistor on the pin.

When the CHR9 bit in the UCR Register is set, transmitted and received characters are

9 bits long plus start and stop bits. The 9th data bit to be transmitted is the TXB8 bit in

UCR Register. This bit must be set to the wanted value before a transmission is initated

by writing to the UDR Register.

69

0945I–AVR–02/07

UART Control

UART I/O Data Register – UDR

Bit

7

6

5

4

3

2

1

0

$0C ($2C)

Read/Write

Initial Value

MSB

R/W

0

LSB

R/W

0

UDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The UDR Register is actually two physically separate registers sharing the same I/O

address. When writing to the register, the UART Transmit Data Register is written.

When reading from UDR, the UART Receive Data Register is read.

UART Status Register – USR

Bit

7

RXC

R

6

5

UDRE

R

4

FE

R

3

OR

R

2

–

1

–

0

–

$0B ($2B)

Read/Write

Initial Value

TXC

R/W

0

USR

R

0

R

0

R

0

1

0

The USR Register is a read-only register providing information on the UART Status.

• Bit 7 – RXC: UART Receive Complete

This bit is set (one) when a received character is transferred from the Receiver Shift

Register to UDR. The bit is set regardless of any detected framing errors. When the

RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when

RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception

is used, the UART Receive Complete Interrupt routine must read UDR in order to clear

RXC, otherwise a new interrupt will occur once the interrupt routine terminates.

• Bit 6 – TXC: UART Transmit Complete

This bit is set (one) when the entire character (including the stop bit) in the Transmit

Shift Register has been shifted out and no new data has been written to the UDR. This

flag is especially useful in half-duplex communications interfaces, where a transmitting

application must enter Receive mode and free the communications bus immediately

after completing the transmission.

When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete

interrupt to be executed. TXC is cleared by hardware when executing the corresponding

interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical

“1” to the bit.

• Bit 5 – UDRE: UART Data Register Empty

This bit is set (one) when a character written to UDR is transferred to the Transmit Shift

Register. Setting of this bit indicates that the Transmitter is ready to receive a new char-

acter for transmission.

When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be exe-

cuted as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven

data transmittal is used, the UART Data Register Empty Interrupt routine must write

UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt rou-

tine terminates.

UDRE is set (one) during reset to indicate that the Transmitter is ready.

70

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

• Bit 4 – FE: Framing Error

This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom-

ing character is zero.

The FE bit is cleared when the stop bit of received data is one.

• Bit 3 – OR: OverRun

This bit is set if an OverRun condition is detected, i.e., when a character already present

in the UDR Register is not read before the next character is transferred from the

Receiver Shift Register. The OR bit is buffered, which means that it will be set once the

valid data still in UDRE is read.

The OR bit is cleared (zero) when data is received and transferred to UDR.

• Bits 2..0 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and will always read as zero.

UART Control Register – UCR

Bit

7

RXCIE

R/W

0

6

TXCIE

R/W

0

5

UDRIE

R/W

0

4

RXEN

R/W

0

3

TXEN

R/W

0

2

CHR9

R/W

0

1

RXB8

R

0

TXB8

W

$0A ($2A)

Read/Write

Initial Value

UCR

1

0

• Bit 7 – RXCIE: RX Complete Interrupt Enable

When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Com-

plete Interrupt routine to be executed, provided that global interrupts are enabled.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Com-

plete Interrupt routine to be executed, provided that global interrupts are enabled.

• Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable

When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data

Register Empty Interrupt routine to be executed, provided that global interrupts are

enabled.

• Bit 4 – RXEN: Receiver Enable

This bit enables the UART Receiver when set (one). When the Receiver is disabled, the

RXC, OR and FE Status Flags cannot become set. If these flags are set, turning off

RXEN does not cause them to be cleared.

• Bit 3 – TXEN: Transmitter Enable

This bit enables the UART Transmitter when set (one). When disabling the Transmitter

while transmitting a character, the Transmitter is not disabled before the character in the

Shift Register plus any following character in UDR has been completely transmitted.

• Bit 2 – CHR9: 9-bit Characters

When this bit is set (one), transmitted and received characters are nine bits long, plus

start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in

UCR, respectively. The ninth data bit can be used as an extra stop bit or a parity bit.

71

0945I–AVR–02/07

• Bit 1 – RXB8: Receive Data Bit 8

When CHR9 is set (one), RXB8 is the ninth data bit of the received character.

• Bit 0 – TXB8: Transmit Data Bit 8

When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted.

72

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Baud Rate Generator

The baud rate generator is a frequency divider that generates baud rates according to

the following equation:

f

CK

BAUD = --------------------------------------

16(UBRR + 1)

•

BAUD = baud rate

_CK= CPU clock frequency

UBRR = contents of the UART Baud Rate Register, UBRR (0 - 255)

f

For standard crystal frequencies, the most commonly used baud rates can be generated

by using the UBRR settings in Table 24. Observe that CPU clock frequency can be

lower than the XTAL frequency if the XTAL divider is enabled. UBRR values that yield an

actual baud rate differing less than 2% from the target baud rate are in boldface in the

table. However, using baud rates that have more than 1% error is not recommended.

High error ratings give less noise resistance.

73

0945I–AVR–02/07

Table 24. UBRR Settings at Various CPU Frequencies

Baud Rate

2400

%Error

0.2

%Error

0.0

%Error

0.2

%Error

0.0

1 MHz

1.8432 MHz

2 MHz

2.4576 MHz

UBRR=

25

12

6

47

23

11

7

51

25

12

8

6

3

63

31

15

10

7

UBRR=

4800

9600

0.2

0.0

33.3 UBRR=

0.2

0.0

3.1

0.0

6.3

0.0

12.5

0.0

25.0

7.5 UBRR=

7.8 UBRR=

22.9 UBRR=

7.8 UBRR=

22.9 UBRR=

84.3 UBRR=

3

2

1

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

22.9 UBRR=

7.8 UBRR=

14400

19200

28800

38400

57600

76800

115200

5

3

2

1

0

4

3

2

1

2

1

0

1

UBRR=

0

0.0

Baud Rate

2400

%Error

0.0

%Error

0.0

3.2768 MHz

3.6864 MHz

4 MHz

4.608 MHz

UBRR=

84

42

20

13

10

6

4

3

2

1

0.4

0.8

1.6

95

47

23

15

11

7

103

51

25

16

12

8

0.2

119

59

29

19

14

9

4800

9600

0.0

6.7

0.0

6.7

2.1 UBRR=

UBRR=

14400

19200

28800

38400

57600

76800

115200

3.1 UBRR=

UBRR=

0.2

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

1.6

6.3 UBRR=

12.5 UBRR=

6

3

2

1

7

4

3

2

5

3

2

1

20.0

0.0

Baud Rate

2400

%Error

0.2

%Error

0.0

%Error

-

7.3728 MHz

8 MHz

9.216 MHz

11.059 MHz

UBRR= 287

UBRR=

191

95

47

31

23

15

11

7

0.0

207

103

51

34

25

16

12

8

239

119

59

39

29

19

14

9

UBRR=

4800

9600

0.2

0.8

0.2

0.0

6.7 UBRR=

143

71

47

35

23

17

11

8

0.0

14400

19200

28800

38400

57600

76800

115200

2.1 UBRR=

UBRR=

0.2

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

6

3

7

4

5

3

UBRR=

0.0

5

UART Baud Rate Register –

UBRR

Bit

7

6

5

4

3

2

1

0

$09 ($29)

MSB

LSB

R/W

0

UBRR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The UBRR is an 8-bit read/write register that specifies the UART baud rate according to

the description on the previous page.

74

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Analog Comparator

The analog comparator compares the input values on the positive input PE2 (AC+) and

negative input PE3 (AC-). When the voltage on the positive input PE2 (AC+) is higher

than the voltage on the negative input PE3 (AC-), the Analog Comparator Output (ACO)

is set (one). The output of the comparator can be set to trigger the Timer/Counter1 Input

Capture function. In addition, the comparator can trigger a separate interrupt, exclusive

to the analog comparator. The user can select interrupt triggering on comparator output

rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown

in Figure 44.

Figure 44. Analog Comparator Block Diagram

VCC

ACD

ACIE

PE2

(AC+)

ANALOG

COMPARATOR

IRQ

+

-

INTERRUPT

SELECT

PE3

(AC-)

ACI

ACIS1 ACIS0

ACIC

ACO

TO T/C1 CAPTURE

TRIGGER MUX

Analog Comparator Control

and Status Register – ACSR

Bit

7

6

–

5

ACO

R

4

3

2

ACIC

R/W

0

1

0

ACIS0

R/W

0

$08 ($28)

ACD

R/W

0

ACI

R/W

0

ACIE

R/W

0

ACIS1

R/W

0

ACSR

Read/Write

Initial Value

R

0

X

• Bit 7 – ACD: Analog Comparator Disable

When this bit is set (one), the power to the analog comparator is switched off. This bit

can be set at any time to turn off the analog comparator. This will reduce power con-

sumption in active and Idle mode. When changing the ACD bit, the Analog Comparator

interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise, an interrupt can

occur when the bit is changed.

• Bit 6 – Res: Reserved Bit

This bit is a reserved bit in the ATmega103(L) and will always read as zero.

• Bit 5 – ACO: Analog Comparator Output

ACO is directly connected to the comparator output.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set (one) when a comparator output event triggers the interrupt mode defined

by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit

is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-

75

0945I–AVR–02/07

ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a

logical “1” to the flag. Observe, however, that if another bit in this register is modified

using the SBI or CBI instruction, ACI will be cleared if it has become set before the

operation.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana-

log Comparator interrupt is activated. When cleared (zero), the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When set (one), this bit enables the Input Capture function in Timer/Counter1 to be trig-

gered by the analog comparator. The comparator output is, in this case, directly

connected to the Input Capture front-end logic, making the comparator utilize the noise

canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When

cleared (zero), no connection between the analog comparator and the Input Capture

function is given. To make the comparator trigger the Timer/Counter1 Input Capture

interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator inter-

rupt. The different settings are shown in Table 25.

Table 25. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle

Reserved

Comparator Interrupt on Falling Output Edge

Comparator Interrupt on Rising Output Edge

When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be dis-

abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise, an interrupt

can occur when the bits are changed.

Caution: Using the SBI or CBI instruction on other bits than ACI in this register will write

a one back into ACI if it is read as set, thus clearing the flag.

76

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Analog-to-Digital

Converter

Feature list:

• 10-bit Resolution

2 LSB Absolute Accuracy

•

• 0.5 LSB Integral Non-linearity

• 70 - 280 µs Conversion Time

• Up to 14 kSPS

• 8 Multiplexed Input Channels

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

The ATmega103(L) features a 10-bit successive approximation ADC. The ADC is con-

nected to an 8-channel Analog Multiplexer, which allows each pin of Port F to be used

as an input for the ADC. The ADC contains a Sample and Hold Amplifier, which ensures

that the input voltage to the ADC is held at a constant level during conversion. A block

diagram of the ADC is shown in Figure 45.

The ADC has two separate analog supply voltage pins, AV_CCand AGND. AGND must

be connected to GND, and the voltage on AV_CCmust not differ more than ± 0.3V from

V

_CC. See the section “ADC Noise Canceling Techniques” on page 82 on how to connect

these pins.

An external reference voltage must be applied to the AREF pin. This voltage must be in

the range AGND - AV_CC

.

Figure 45. Analog-to-Digital Converter Block Schematic

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

External

Reference

Voltage

9

0

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL & STATUS

REGISTER (ADCSR)

ADC DATA REGISTER

(ADCH/ADCL)

10-BIT DAC

CONVERSION LOGIC

8-

Analog

Inputs

CHANNEL

MUX

-

+

SAMPLE & HOLD

COMPARATOR

77

0945I–AVR–02/07

Operation

The ADC operates in Single Conversion mode, and each conversion will have to be ini-

tiated by the user.

The ADC is enabled by writing a logical “1” to the ADC Enable bit, ADEN in ADCSR.

The first conversion that is started after enabling the ADC will be preceded by a dummy

conversion to initialize the ADC. To the user, the only difference will be that this conver-

sion takes 13 more ADC clock pulses than a normal conversion (see Figure 48).

A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC.

This bit will stay high as long as the conversion is in progress and be set to zero by hard-

ware when the conversion is completed. If a different data channel is selected while a

conversion is in progress, the ADC will finish the current conversion before performing

the channel change.

As the ADC generates a 10-bit result, two Data Registers, ADCH and ADCL, must be

read to get the result when the conversion is complete. Special data protection logic is

used to ensure that the contents of the Data Registers belong to the same result when

they are read. This mechanism works as follows:

When reading data, ADCL must be read first. Once ADCL is read, ADC access to Data

Registers is blocked. This means that if ADCL has been read, and a conversion com-

pletes before ADCH is read, none of the registers are updated and the result from the

conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers

is re-enabled.

The ADC has its own interrupt, ADIF, which can be triggered when a conversion com-

pletes. When ADC access to the Data Registers is prohibited between reading of ADCL

and ADCH, the interrupt will trigger even if the result is lost.

Prescaling

Figure 46. ADC Prescaler

Reset

ADEN

CK

7-BIT ADC PRESCALER

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

The ADC contains a prescaler, which divides the system clock to an acceptable ADC

clock frequency. The ADC accepts input clock frequencies in the range 50 - 200 kHz.

Applying a higher input frequency will result in poorer accuracy (see “ADC DC Charac-

teristics” on page 83).

The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input fre-

quency from any XTAL frequency above 100 kHz. The prescaler starts counting from

the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler

78

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

keeps running for as long as the ADEN bit is set and is continuously reset when ADEN

is low.

When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at

the following falling edge of the ADC clock cycle. The actual sample-and-hold takes

place one ADC clock cycle after the start of the conversion. The result is ready and writ-

ten to the ADC Result Register after 13 cycles. The ADC needs two more clock cycles

before a new conversion can be started. If ADSC is set high in this period, the ADC will

start the new conversion immediately. For a summary of conversion times, see Table

26.

Figure 47. ADC Timing Diagram, First Conversion

Cycle number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

1

2

ADC clock

ADEN

ADSC

Hold strobe

ADIF

ADCH

ADCL

MSB of result

LSB of result

Second

Conversion

Dummy Conversion

Actual Conversion

Table 26. ADC Conversion Time

Sample

Cycle

Number

Result Ready

(Cycle

Number)

Total

Conversion

Time (Cycles)

Total

Conversion

Time (µs)

Condition

1st Conversion

Single Conversion

14

1

26

13

28

15

140 - 560

75 - 300

Figure 48. ADC Timing Diagram

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1

2

Cycle number

ADC clock

ADSC

Hold strobe

ADIF

ADCH

MSB of result

LSB of result

ADCL

One Conversion

Next Conversion

79

0945I–AVR–02/07

ADC Noise Canceler

Function

The ADC features a noise canceler that enables conversion during Idle mode to reduce

noise induced from the CPU core. To make use of this feature, the following procedure

should be used:

1. Turn off the ADC by clearing ADEN.

2. Turn on the ADC and simultaneously start a conversion by setting ADEN and

ADSC. This starts a dummy conversion that will be followed by a valid

conversion.

3. Within 14 ADC clock cycles, enter Idle mode.

4. If no other interrupts occur before the ADC conversion completes, the ADC inter-

rupt will wake up the MCU and execute the ADC conversion complete interrupt

routine.

ADC Multiplexer Select

Register – ADMUX

Bit

7

–

6

–

5

–

4

–

3

–

2

MUX2

R/W

0

1

MUX1

R/W

0

MUX0

R/W

0

$07 ($27)

Read/Write

Initial Value

ADMUX

R

0

R

0

R

0

R

0

R

0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

• Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2 - 0

The value of these three bits selects which analog input 7 - 0 is connected to the ADC.

ADC Control and Status

Register – ADCSR

Bit

7

ADEN

R/W

0

6

ADSC

R/W

0

5

–

4

ADIF

R/W

0

3

ADIE

R/W

0

2

ADPS2

R/W

0

1

ADPS1

R/W

0

ADPS0

R/W

0

$06 ($26)

Read/Write

Initial Value

ADCSR

R

0

• Bit 7 – ADEN: ADC Enable

Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is

turned off. Turning the ADC off while a conversion is in progress will terminate this

conversion.

• Bit 6 – ADSC: ADC Start Conversion

A logical “1” must be written to this bit to start each conversion. The first time ADSC has

been written after the ADC has been enabled, or if ADSC is written at the same time as

the ADC is enabled, a dummy conversion will precede the initiated conversion. This

dummy conversion performs initialization of the ADC.

ADSC remains high during the conversion. ADSC goes low after the conversion is com-

plete, but before the result is written to the ADC Data Registers. This allows a new

conversion to be initiated before the current conversion is complete. The new conver-

sion will then start immediately after the current conversion completes. When a dummy

conversion precedes a real conversion, ADSC will stay high until the real conversion

completes.

Writing a zero to this bit has no effect.

80

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

• Bit 5 – Res: Reserved Bit

This bit is reserved in the ATmega103(L). Warning: When writing ADCSR, a logical “0”

must be written to this bit.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set (one) when an ADC conversion is complete and the result is written to the

ADC Data Registers are updated. The ADC Conversion Complete interrupt is executed

if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when

executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by

writing a logical “1” to the flag. Beware that if doing a Read-Modify-Write on ADCSR, a

pending interrupt can be disabled. This also applies if the SBI and CBI instructions are

used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com-

plete interrupt is activated.

• Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input

clock to the ADC.

Table 27. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Invalid

2

4

8

16

32

64

128

ADC Data Register – ADCL

and ADCH

Bit

15

14

13

12

11

10

9

8

$05 ($25)

$04 ($24)

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

When an ADC conversion is complete, the result is found in these two registers. It is

essential that both registers are read and that ADCL is read before ADCH.

81

0945I–AVR–02/07

ADC Noise Canceling

Techniques

Digital circuitry inside and outside the ATmega103(L) generates EMI, which might affect

the accuracy of analog measurements. If conversion accuracy is critical, the noise level

can be reduced by applying the following techniques:

1. The analog part of the ATmega103(L) and all analog components in the applica-

tion should have a separate analog ground plane on the PCB. This ground plane

is connected to the digital ground plane via a single point on the PCB.

2. Keep analog signal paths as short as possible. Make sure analog tracks run over

the analog ground plane, and keep them well away from high-speed switching

digital tracks.

3. The AV_CCpin on the ATmega103(L) should have its own decoupling capacitor as

shown in Figure 49.

4. Use the ADC Noise Canceler function to reduce induced noise from the CPU.

5. If some Port F pins are used as digital inputs, it is essential that these do not

switch while a conversion is in progress.

Figure 49. ADC Power Connections

(AD0) PA0 51

VCC

52

GND 53

(ADC7) PF7 54

(ADC6) PF6 55

(ADC5) PF5 56

(ADC4) PF4 57

(ADC3) PF3 58

(ADC2) PF2 59

(ADC1) PF1

(ADC0) PF0

60

61

62

63

64

AREF

AGND

AVCC

10nF

Analog Ground Plane

1

82

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

ADC DC Characteristics

TA = -40°C to 85°C

Symbol Parameter

Condition

Min

Typ

Max

Units

Resolution

10

Bits

Absolute

accuracy

VREF = 4V, V_CC= 4V

ADC clock = 200 kHz

1

4

2

LSB

µs

Absolute

accuracy

VREF = 4V, V_CC= 4V

ADC clock = 1 MHz

Absolute

accuracy

VREF = 4V, V_CC= 4V

ADC clock = 2 MHz

16

0.5

1

Integral

Non-linearity

VREF > 2V

Differential

Non-linearity

Zero Error

(Offset)

Conversion

Time

70

50

280

200

Clock

Frequency

kHz

Analog

Supply

Voltage

AV_CC

V_REF

R_REF

R_AIN

V_CC- 0.3⁽¹⁾

V_CC+ 0.3⁽²⁾

V

Reference

Voltage

2

6

AV_CC

Reference

Input

Resistance

10

13

kΩ

MΩ

Analog Input

Resistance

100

Notes: 1. Minimum for AV_CCis 2.7V.

2. Maximum for AV_CCis 6.0V.

83

0945I–AVR–02/07

Interface to External

SRAM

The interface to the SRAM consists of:

Port A: multiplexed low-order address bus and data bus

Port C: high-order address bus

The ALE pin: address latch enable

The RD and WR pin: read and write strobes

The external data SRAM is enabled by setting the external SRAM enable bit (SRE) of

the MCU Control Register (MCUCR) and will override the setting of the Data Direction

Register (DDRA). When the SRE bit is cleared (zero), the external data SRAM is dis-

abled and the normal pin and data direction settings are used. When SRE is cleared

(zero), the address space above the internal SRAM boundary is not mapped into the

internal SRAM as AVR parts do not have an interface to the external SRAM.

When ALE goes from high to low, there is a valid address on Port A. ALE is low during a

data transfer. RD and WR are active when accessing the external SRAM only.

When the external SRAM is enabled, the ALE signal may have short pulses when

accessing the internal RAM, but the ALE signal is stable when accessing the external

SRAM.

Figure 50 shows how to connect an external SRAM to the AVR using eight latches that

are transparent when G is high.

By default, the external SRAM access is a three-cycle scheme as depicted in Figure 51.

When one extra wait state is needed in the access cycle, set the SRW bit (one) in the

MCUCR Register. The resulting access scheme is shown in Figure 52. In both cases,

note that Port A is data bus in one cycle only. As soon as the data access finishes, Port

A becomes a low-order address bus again.

Note:

If a read is followed by a write, or vice versa, there is no extra insertion of wait states in

between. The user may insert a NOP between consecutive read and write operations to

the external RAM, because such short time for releasing the bus is difficult to obtain with-

out making bus contention.

For details on the timing for the SRAM interface, please refer to Figure 79, Table 45,

Table 46, Table 47, and Table 48 in the section “DC Characteristics” on page 118 and

refer to “Architectural Overview” on page 8 for a description of the memory map, includ-

ing address space for SRAM.

Figure 50. External SRAM Connected to the AVR

D[7:0]

Port A

ALE

D

G

Q

A[7:0]

SRAM

AVR

A[15:8]

Port C

RD

WR

84

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 51. External SRAM Access Cycle without Wait States

T1

T2

T3

System Clock Ø

ALE

Prev. Address

Address

Data

Address [15..8]

Data / Address [7..0]

WR

Prev. Address

Address

Prev. Address Address

Data

Data / Address [7..0]

RD

Figure 52. External SRAM Access Cycle with Wait State

T1

T2

T3

T4

System Clock Ø

ALE

Prev. Address

Address

Address [15..8]

Data / Address [7..0]

WR

Prev. Address

Address

Data

Add

.

r

Prev. Address Address

Data

Add.

Data / Address [7..0]

RD

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0945I–AVR–02/07

I/O Ports

All AVR ports have true Read-Modify-Write functionality when used as general digital

I/O ports. This means that the direction of one port pin can be changed without uninten-

tionally changing the direction of any other pin with the SBI and CBI instructions. The

same applies for changing drive value (if configured as output) or enabling/disabling of

pull-up resistors (if configured as input).

Port A

Port A is an 8-bit bi-directional I/O port with internal pull-ups.

Three I/O memory address locations are allocated for Port A, one each for the Data

Register – PORTA, $1B($3B), Data Direction Register – DDRA, $1A($3A) and the Port

A Input Pins – PINA, $19($39). The Port A Input Pins address is read-only, while the

Data Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port A output buffers can

sink 20 mA and thus drive LED displays directly. When pins PA0 to PA7 are used as

inputs and are externally pulled low, they will source current if the internal pull-up resis-

tors are activated.

The Port A pins have alternate functions related to the optional external data SRAM.

Port A can be configured to be the multiplexed low-order address/data bus during

accesses to the byte.

When Port A is set to the alternate function by the SRE (External SRAM Enable) bit in

the MCUCR (MCU Control Register), the alternate settings override the Data Direction

Register.

Port A Data Register – PORTA

Bit

7

PORTA7

R/W

0

6

PORTA6

R/W

0

5

PORTA5

R/W

0

4

PORTA4

R/W

0

3

PORTA3

R/W

0

2

PORTA2

R/W

0

1

PORTA1

R/W

0

PORTA0

R/W

0

PORTA

DDRA

PINA

$1B ($3B)

Read/Write

Initial Value

Port A Data Direction Register

– DDRA

Bit

7

DDA7

R/W

0

6

DDA6

R/W

0

5

DDA5

R/W

0

4

DDA4

R/W

0

3

DDA3

R/W

0

2

DDA2

R/W

0

1

DDA1

R/W

0

DDA0

R/W

0

$1A ($3A)

Read/Write

Initial Value

Port A Input Pins Address –

PINA

Bit

7

PINA7

R

6

PINA6

R

5

PINA5

R

4

PINA4

R

3

PINA3

R

2

PINA2

R

1

PINA1

R

0

PINA0

R

$19 ($39)

Read/Write

Initial Value

N/A

The Port A Input Pins address (PINA) is not a register; this address enables access to

the physical value on each Port A pin. When reading PORTA the Port A Data Latch is

read and when reading PINA, the logical values present on the pins are read.

Port A as General Digital I/O

All eight pins in Port A have equal functionality when used as digital I/O pins.

PAn, general I/O pin: The DDAn bit in the DDRA Register selects the direction of this

pin. If DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero),

PAn is configured as an input pin. If PORTAn is set (one) when the pin configured as an

input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, POR-

TAn has to be cleared (zero) or the pin has to be configured as an output pin. The port

86

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Table 28. DDAn Effects on Port A Pins

DDAn

PORTAn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PAn will source current if ext. pulled low.

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 7,6...0, pin number

Port A Schematics

Note that all port pins are synchronized. The synchronization latch is, however, not

shown in the figure.

Figure 53. Port A Schematic Diagrams (Pins PA0 - PA7)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDAn

C

WD

RESET

R

Q

D

PAn

PORTAn

C

RL

WP

RP

WP:

WD:

RL:

RP:

RD:

WRITE PORTA

WRITE DDRA

READ PORTA LATCH

READ PORTA PIN

READ DDRA

SRE

R

SRE: EXT. SRAM ENABLE

A:

D:

W:

R:

n:

ADDRESS

DATA

W

Dn

WRITE

READ

0-7

An

Port B

Port B is an 8-bit bi-directional I/O port with internal pull-ups.

Three I/O memory address locations are allocated for Port B, one each for the Data

Register – PORTB, $18($38), Data Direction Register – DDRB, $17($37) and the Port B

Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the Data

Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port B output buffers can

sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as

87

0945I–AVR–02/07

inputs and are externally pulled low, they will source current if the internal pull-up resis-

tors are activated.

The Port B pins with alternate functions are shown in Table 29.

Table 29. Port B Pin Alternate Functions

Port Pin

PB0

Alternate Functions

SS (SPI Slave Select input)

PB1

SCK (SPI Bus Serial Clock)

PB2

MOSI (SPI Bus Master Output/Slave Input)

PB3

MISO (SPI Bus Master Input/Slave Output)

PB4

OC0/PWM0 (Output Compare and PWM Output for Timer/Counter0)

OC1A/PWM1A (Output Compare and PWM Output A for Timer/Counter1)

OC1B/PWM1B (Output Compare and PWM Output B for Timer/Counter1)

OC2/PWM2 (Output Compare and PWM Output for Timer/Counter2)

PB5

PB6

PB7

When the pins are used for the alternate function, the DDRB and PORTB Registers

have to be set according to the alternate function description.

Port B Data Register – PORTB

Bit

7

PORTB7

R/W

0

6

PORTB6

R/W

0

5

PORTB5

R/W

0

4

PORTB4

R/W

0

3

PORTB3

R/W

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

PORTB0

R/W

0

PORTB

DDRB

PINB

$18 ($38)

Read/Write

Initial Value

Port B Data Direction Register

– DDRB

Bit

7

DDB7

R/W

0

6

DDB6

R/W

0

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

$17 ($37)

Read/Write

Initial Value

Port B Input Pins Address –

PINB

Bit

7

PINB7

R

6

PINB6

R

5

PINB5

R

4

PINB4

R

3

PINB3

R

2

PINB2

R

1

PINB1

R

0

PINB0

R

$16 ($36)

Read/Write

Initial Value

N/A

The Port B Input Pins address (PINB) is not a register; this address enables access to

the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is

read and when reading PINB, the logical values present on the pins are read.

Port B as General Digital I/O

All eight pins in Port B have equal functionality when used as digital I/O pins.

PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this

pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero),

PBn is configured as an input pin. If PORTBn is set (one) when the pin configured as an

input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the

PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The

port pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

88

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Table 30. DDBn Effects on Port B Pins

DDBn

PORTBn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PBn will source current if ext. pulled low

Push-pull Zero Output

Output

No

Push-pull One Output

Note:

n: 7,6...0, pin number

Alternate Functions of Port B The alternate pin configuration is as follows:

• OC2/PWM2, Bit 7

OC2/PWM2, Output Compare output for Timer/Counter2 or PWM output when

Timer/Counter2 is in PWM mode. The pin has to be configured as an output to serve

this function.

• OC1B/PWM1B, Bit 6

OC1B/PWM1B, Output Compare output B for Timer/Counter1 or PWM output B when

Timer/Counter1 is in PWM mode. The pin has to be configured as an output to serve

this function.

• OC1A/PWM1A, Bit 5

OC1A/PWM1A, Output Compare output A for Timer/Counter1 or PWM output A when

Timer/Counter1 is in PWM mode. The pin has to be configured as an output to serve

this function.

• OC0/PWM0, Bit 4

OC0/PWM0, Output Compare output for Timer/Counter0 or PWM output when

Timer/Counter0 is in PWM mode. The pin has to be configured as an output to serve

this function.

• MISO – Port B, Bit 3

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is

enabled as a Master, this pin is configured as an input regardless of the setting of

DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by

DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB3 bit. See the description of the SPI port for further details.

• MOSI – Port B, Bit 2

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is

enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2.

When the SPI is enabled as a Master, the data direction of this pin is controlled by

DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB2 bit. See the description of the SPI port for further details.

• SCK – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is

enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1.

When the SPI is enabled as a Master, the data direction of this pin is controlled by

89

0945I–AVR–02/07

DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB1 bit. See the description of the SPI port for further details.

• SS – Port B, Bit 0

SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured

as an input regardless of the setting of DDB0. As a Slave, the SPI is activated when this

pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is

controlled by DDB0. When the pin is forced to be an input, the pull-up can still be con-

trolled by the PORTB0 bit. See the description of the SPI port for further details.

Port B Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not

shown in the figures.

Figure 54. Port B Schematic Diagram (Pin PB0)

90

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 55. Port B Schematic Diagram (Pin PB1)

Figure 56. Port B Schematic Diagram (Pin PB2)

91

0945I–AVR–02/07

Figure 57. Port B Schematic Diagram (Pin PB3)

Figure 58. Port B Schematic Diagram (Pin PB4)

RD

MOS

PULL-

UP

RESET

R

DDB4

C

Q

D

WD

RESET

R

Q

D

PB4

PORTB4

C

RL

RP

WP

COM01

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

WP:

WD:

RL:

RP:

RD:

OUTPUT

MODE SELECT

COMP. MATCH 0

92

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 59. Port B Schematic Diagram (Pins PB5 and PB6)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDBn

C

WD

RESET

R

Q

D

PBn

PORTBn

C

RL

WP

RP

COM1X0

COM1X1

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

5, 6

WP:

WD:

RL:

RP:

RD:

n:

OUTPUT

MODE SELECT

COMP. MATCH 1X

A, B

X:

Figure 60. Port B Schematic Diagram (Pin PB7)

RD

MOS

PULL-

UP

RESET

R

DDB7

C

Q

D

WD

RESET

R

Q

D

PB7

PORTB7

C

RL

RP

WP

COM20

COM21

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

WP:

WD:

RL:

RP:

RD:

OUTPUT

MODE SELECT

COMP. MATCH 2

93

0945I–AVR–02/07

Port C

Port C is an 8-bit output port.

The Port C pins have alternate functions related to the optional external data SRAM.

When using the device with external SRAM, Port C outputs the high-order address byte

during accesses to external Data memory. When a reset condition becomes active, the

port pins are not tri-stated, but the pins will assume their initial value after two stable

clock cycles.

The Port C Data Register –

PORTC

Bit

7

PORTC7

R/W

0

6

PORTC6

R/W

0

5

PORTC5

R/W

0

4

PORTC4

R/W

0

3

PORTC3

R/W

0

2

PORTC2

R/W

0

1

PORTC1

R/W

0

PORTC0

R/W

0

PORTC

$15 ($35)

Read/Write

Initial Value

Port C Schematics

Figure 61. Port C Schematic Diagram (Pins PC0 - PC7)

RESET

R

Q

D

PCn

PORTCn

C

RL

WP

WRITE PORTC

WP:

RL:

A:

SRE:

n:

READ PORTC LATCH

SRAM ADDRESS

EXTERNAL SRAM ENABLE

0-7

SRE

An

Port D

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.

Three I/O memory address locations are allocated for the Port D, one each for the Data

Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D

Input Pins – PIND, $10($30). The Port D Input Pins address is read-only, while the Data

Register and the Data Direction Register are read/write.

The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally

pulled low will source current if the pull-up resistors are activated.

Some Port D pins have alternate functions as shown in Table 31.

Table 31. Port D Pin Alternate Functions

Port Pin

PD0

Alternate Function

INT0 (External Interrupt0 Input)

INT1 (External Interrupt1 Input)

INT2 (External Interrupt2 Input)

INT3 (External Interrupt3 Input)

IC1 (Timer/Counter1 Input Capture Trigger)

T1 (Timer/Counter1 Clock Input)

T2 (Timer/Counter2 Clock Input)

PD1

PD2

PD3

PD4

PD6

PD7

94

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

When the pins are used for the alternate function, the DDRD and PORTD Registers

have to be set according to the alternate function description.

Port D Data Register – PORTD

Bit

7

PORTD7

R/W

0

6

PORTD6

R/W

0

5

PORTD5

R/W

0

4

PORTD4

R/W

0

3

PORTD3

R/W

0

2

PORTD2

R/W

0

1

PORTD1

R/W

0

PORTD0

R/W

0

PORTD

DDRD

PIND

$12

Read/Write

Initial Value

Port D Data Direction Register

– DDRD

Bit

7

DDD7

R/W

0

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

$11

Read/Write

Initial Value

Port D Input Pins Address –

PIND

Bit

7

PIND7

R

6

PIND6

R

5

PIND5

R

4

PIND4

R

3

PIND3

R

2

PIND2

R

1

PIND1

R

0

PIND0

R

$10

Read/Write

Initial Value

N/A

The Port D Input Pins address (PIND) is not a register, and this address enables access

to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch

is read, and when reading PIND, the logical values present on the pins are read.

Port D as General Digital I/O

PDn, General I/O pin: The DDDn bit in the DDRD Register selects the direction of this

pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero),

PDn is configured as an input pin. If PDn is set (one) when configured as an input pin

the MOS pull-up resistor is activated. To switch the pull-up resistor off the PDn has to be

cleared (zero) or the pin has to be configured as an output pin. The port pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Table 32. DDDn Bits on Port D Pins

DDDn

PORTDn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PDn will source current if ext. pulled low.

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 7,6...0, pin number

Alternate Functions of Port D The alternate pin functions of Port D are:

• INT0..INT3 – Port D, Bits 0..3

External Interrupt sources 0 - 3. The PD0 - PD3 pins can serve as external active low

interrupt sources to the MCU. The internal pull-up MOS resistors can be activated as

described above. See the interrupt description for further details, and how to enable the

sources.

95

0945I–AVR–02/07

• IC1 – Port D, Bit 4

IC1, Input Capture pin for Timer/Counter1. When a positive or negative (selectable)

edge is applied to this pin, the contents of Timer/Counter1 is transferred to the

Timer/Counter1 Input Capture Register. The pin has to be configured as an input to

serve this function. See the Timer/Counter1 description on how to operate this function.

The internal pull-up MOS resistor can be activated as described above.

• T1 – Port D, Bit 6

T1, Timer/Counter1 counter source. See the Timer description for further details.

• T2 – Port D, Bit 7

T2, Timer/Counter2 counter source. See the Timer description for further details.

Port D Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not

shown in the figures.

Figure 62. Port D Schematic Diagram (Pins PD0, PD1, PD2 and PD3)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDDn

C

WD

RESET

R

Q

D

PDn

PORTDn

C

RL

RP

WP

WP: WRITE PORTD

WD: WRITE DDRD

INTn

RL: READ PORTD LATCH

RP: READ PORTD PIN

RD: READ DDRD

n:

0, 1, 2, 3

96

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 63. Port D Schematic Diagram (Pin PD4)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDD4

C

WD

RESET

R

Q

D

PD4

PORTD4

C

RL

WP

RP

WP: WRITE PORTD

WD: WRITE DDRD

0

1

NOISE CANCELER

ICNC1

EDGE SELECT

ICES1

ICF1

RL:

RP:

READ PORTD LATCH

READ PORTD PIN

RD: READ DDRD

ACIC: COMPARATOR IC ENABLE

ACO: COMPARATOR OUTPUT

ACIC

ACO

Figure 64. Port D Schematic Diagram (Pin PD5)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDD5

C

WD

RESET

R

Q

D

PD5

PORTD5

C

RL

WP

RP

WP: WRITE PORTD

WD: WRITE DDRD

RL: READ PORTD LATCH

RP: READ PORTD PIN

RD: READ DDRD

97

0945I–AVR–02/07

Figure 65. Port D Schematic Diagram (Pins PD6 and PD7)

RD

MOS

PULL-

UP

RESET

R

DDDn

C

Q

D

WD

RESET

R

Q

D

PDn

PORTDn

C

RL

WP

RP

WP: WRITE PORTD

WD: WRITE DDRD

RL: READ PORTD LATCH

RP: READ PORTD PIN

RD: READ DDRD

TIMERm CLOCK

SOURCE MUX

SENSE CONTROL

n:

m:

6, 7

1, 2

CSm0

CSm2 CSm1

Port E

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors.

Three I/O memory address locations are allocated for the Port E, one each for the Data

Register – PORTE, $03($23), Data Direction Register – DDRE, $02($22) and the Port E

Input Pins – PINE, $01($21). The Port E Input Pins address is read-only, while the Data

Register and the Data Direction Register are read/write.

The Port E output buffers can sink 20 mA. As inputs, Port E pins that are externally

pulled low will source current if the pull-up resistors are activated.

All Port E pins have alternate functions as shown in Table 33.

Table 33. Port E Pin Alternate Functions

Port Pin

PE0

Alternate Function

PDI/RXD (Programming Data Input or UART Receive Pin)

PDO/TXD (Programming Data Output or UART Transmit Pin)

AC+ (Analog Comparator Positive Input)

AC- (Analog Comparator Negative Input)

INT4 (External Interrupt4 Input)

PE1

PE2

PE3

PE4

PE5

INT5 (External Interrupt5 Input)

PE6

INT6 (External Interrupt6 Input)

PE7

INT7 (External Interrupt7 Input)

When the pins are used for the alternate function, the DDRE and PORTE Registers

have to be set according to the alternate function description.

98

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Port E Data Register – PORTE

Bit

7

PORTE7

R/W

0

6

PORTE6

R/W

0

5

PORTE5

R/W

0

4

PORTE4

R/W

0

3

PORTE3

R/W

0

2

PORTE2

R/W

0

1

PORTE1

R/W

0

PORTE0

R/W

0

PORTE

DDRE

PINE

$03 ($23)

Read/Write

Initial Value

Port E Data Direction Register

– DDRE

Bit

7

DDE7

R/W

0

6

DDE6

R/W

0

5

DDE5

R/W

0

4

DDE4

R/W

0

3

DDE3

R/W

0

2

DDE2

R/W

0

1

DDE1

R/W

0

DDE0

R/W

0

$02 ($22)

Read/Write

Initial Value

Port E Input Pins Address –

PINE

Bit

7

PINE7

R

6

PINE6

R

5

PINE5

R

4

PINE4

R

3

PINE3

R

2

PINE2

R

1

PINE1

R

0

PINE0

R

$01 ($21)

Read/Write

Initial Value

N/A

The Port E Input Pins address (PINE) is not a register; this address enables access to

the physical value on each Port E pin. When reading PORTE, the Port E Data Latch is

read and when reading PINE, the logical values present on the pins are read.

Port E as General Digital I/O

Alternate Functions of Port E

0945I–AVR–02/07

PEn, general I/O pin: The DDEn bit in the DDRE Register selects the direction of this

pin. If DDEn is set (one), PEn is configured as an output pin. If DDEn is cleared (zero),

PEn is configured as an input pin. If PEn is set (one) when configured as an input pin,

the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PEn has to

be cleared (zero) or the pin has to be configured as an output pin.The port pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Table 34. DDEn Bits on Port E Pins

DDEn

PORTEn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PDn will source current if ext. pulled low.

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 7,6...0, pin number

The alternate pin functions of Port E are:

• PDI/RXD – Port E, Bit 0

PDI, Serial Programming Data Input. During Serial Program downloading, this pin is

used as data input line for the ATmega103(L).

RXD, UART Receive Pin. Receive Data (Data input pin for the UART). When the UART

Receiver is enabled, this pin is configured as an input regardless of the value of DDRD0.

When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the

internal pull-up.

• PDO/TXD – Port E, Bit 1

PDO, Serial Programming Data Output. During Serial Program downloading, this pin is

used as data output line for the ATmega103(L).

99

TXD, UART Transmit Pin.

• AC+ – Port E, Bit 2

AC+, Analog Comparator Positive Input. This pin is directly connected to the positive

input of the analog comparator.

• AC- – Port E, Bit 3

AC-, Analog Comparator Negative Input. This pin is directly connected to the negative

input of the analog comparator.

• INT4..INT7 – Port E, Bits 4 - 7

INT4..INT7, External Interrupt sources 4 - 7: The PE4 - PE7 pins can serve as external

interrupt sources to the MCU. Interrupts can be triggered by low level or positive or neg-

ative edge on these pins. The internal pull-up MOS resistors can be activated as

described above. See the interrupt description for further details, and how to enable the

sources.

Port E Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not

shown in the figures.

Figure 66. Port E Schematic Diagram (Pin PE0)

100

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 67. Port E Schematic Diagram (Pin PE1)

Figure 68. Port E Schematic Diagram (Pin PE2)

RD

MOS

PULL-

UP

RESET

Q

D

DDE2

C

WD

RESET

Q

D

PE2

PORTE2

C

RL

WP

RP

AC+

TO COMPARATOR

WP: WRITE PORTE

WD: WRITE DDRE

RL: READ PORTE LATCH

RP: READ PORTE PIN

RD: READ DDRE

101

0945I–AVR–02/07

Figure 69. Port E Schematic Diagram (Pin PE3)

RD

MOS

PULL-

UP

RESET

Q

D

DDE3

C

WD

RESET

Q

D

PE3

PORTE3

C

RL

WP

RP

AC-

TO COMPARATOR

WP: WRITE PORTE

WD: WRITE DDRE

RL: READ PORTE LATCH

RP: READ PORTE PIN

RD: READ DDRE

Figure 70. Port E Schematic Diagram (Pins PE4, PE5, PE6 and PE7)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDEn

C

WD

RESET

R

Q

D

PEn

PORTEn

C

RL

WP

RP

WP: WRITE PORTE

WD: WRITE DDRE

SENSE CONTROL

INTn

RL: READ PORTE LATCH

RP: READ PORTE PIN

RD: READ DDRE

n:

4, 5, 6, 7

ISCn1

ISCn0

102

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Port F

Port F is an 8-bit input port.

One I/O memory location is allocated for Port F, the Port F Input Pins – PINF, $00 ($20).

All Port F pins are connected to the analog multiplexer, which further is connected to the

A/D converter. The digital input function of Port F can be used together with the A/D

converter, allowing the user to use some pins of Port F and digital inputs and other as

analog inputs, at the same time.

Port F Input Pins Address –

PINF

Bit

7

PINF7

R

6

PINF6

R

5

PINF5

R

4

PINF4

R

3

PINF3

R

2

PINF2

R

1

PINF1

R

0

PINF0

R

$00 ($20)

Read/Write

Initial Value

PINF

N/A

The Port F Input Pins address (PINF) is not a register; this address enables access to

the physical value on each Port F pin.

Figure 71. Port F Schematic Diagram (Pins PF7 - PF0)

RP

PFn

AINn

TO ADC MUX

RP: READ PORTF PIN

n:

0 - 7

103

0945I–AVR–02/07

Memory

Programming

Program and Data

Memory Lock Bits

The ATmega103(L) MCU provides two Lock bits that can be left unprogrammed (“1”) or

can be programmed (“0”) to obtain the additional features listed in Table 35. The Lock

bits can only be erased to “1” with the Chip Erase command.

Table 35. Lock Bit Protection Modes

Memory Lock Bits

Protection Type

Mode

LB1

1

LB2

1

2

3

No memory lock features enabled.

0

1

Further programming of the Flash and EEPROM is disabled.⁽¹⁾

0

Same as mode 2, and verify is also disabled.

Note:

1. In Parallel mode, programming of the Fuse bits are also disabled. Program the Fuse

bits before programming the Lock bits.

Fuse Bits

The ATmega103(L) has four Fuse bits, SPIEN, SUT1..0 and EESAVE.

•

When the SPIEN Fuse is programmed (“0”), Serial Program and Data Downloading

is enabled. Default value is programmed (“0”). The SPIEN Fuse is not accessible in

Serial Programming mode.

When EESAVE is programmed, the EEPROM memory is preserved through the

Chip Erase cycle. Default value is unprogrammed (“1”). The EESAVE Fuse bit

cannot be programmed if any of the Lock bits are programmed.

SUT1..0 Fuses: Determine the MCU start-up time. See Table 5 on page 27 for

further details. Default value is unprogrammed (“11”), which gives a nominal start-up

time of 16 ms.

The status of the Fuse bits is not affected by Chip Erase.

Signature Bytes

All Atmel microcontrollers have a 3-byte signature code that identifies the device. This

code can be read in both Serial and Parallel mode. The three bytes reside in a separate

address space.

For the ATmega103 they are:

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $97 (indicates 128K bytes Flash memory)

3. $002: $01 (indicates ATmega103 when signature byte $001 is $97)

Programming the Flash

and EEPROM

Atmel’s ATmega103(L) offers 128K bytes of In-System Reprogrammable Flash memory

and 4K bytes of EEPROM Data memory.

The ATmega103(L) is shipped with the On-chip Flash Program and EEPROM Data

memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed.

This device supports a Parallel Programming mode and a Serial Programming mode.

The +12V supplied to the RESET pin in Parallel Programming mode is used for pro-

gramming enable only, and no current of significance is drawn by this pin. The Serial

Programming mode provides a convenient way to download program and data into the

ATmega103(L) inside the user’s system.

104

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

The Flash Program memory array on the ATmega103(L) is organized as 512 pages of

256 bytes each. When programming the Flash, the Program data is latched into a page

buffer. This allows one page of program data to be programmed simultaneously in either

Programming mode.

The EEPROM Data memory array on the ATmega103(L) is programmed byte-by-byte in

either Programming mode. An auto-erase cycle is provided within the self-timed

EEPROM write instruction in the Serial Programming mode.

During programming, the supply voltage must be in accordance with Table 36.

Table 36. Supply Voltage during Programming

Part

Serial Programming

4.0 - 5.0V

Parallel Programming

4.0 - 5.0V

ATmega103

ATmega103L

3.2 - 3.6V

3.2 - 5.0V

Parallel Programming

This section describes how to Parallel Program and verify Flash Program memory,

EEPROM Data memory, Lock bits and Fuse bits in the ATmega103(L). Pulses are

assumed to be at least 500 ns unless otherwise noted.

Signal Names

In this section, some pins of the ATmega103(L) are referenced by signal names describ-

ing their function during parallel programming (see Figure 72 and Table 37). Pins not

described in Table 37 are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-

tive pulse. The bit coding is shown in Table 38.

When pulsing WR or OE, the command loaded determines the action executed. The

command is a byte where the different bits are assigned functions, as shown in Table

39.

Figure 72. Parallel Programming

ATmega103(L)

V_CC

VCC

PD1

PD2

PD3

PD4

PD5

PD6

PA0

RDY/BSY

OE

PB7 - PB0

DATA

WR

BS1

XA0

XA1

PAGEL

+12V

RESET

PD7

XTAL1

GND

105

0945I–AVR–02/07

.

Table 37. Pin Name Mapping

Signal Name in

Programming Mode Pin Name I/O Function

0: Device is busy programming, 1: Device is ready

for new command

RDY/BSY

PD1

O

OE

PD2

PD3

I

Output Enable (active low)

Write Pulse (active low)

WR

Byte Select 1 (“0” selects Low Byte, “1” selects

High Byte)

BS1

PD4

I

XA0

XA1

PD5

PD6

I

XTAL Action Bit 0

XTAL Action Bit 1

BS2

PD7

Byte Select 2 (always low)

Program Memory Page Load

PAGEL

DATA

PA0

PB7 - 0

I/O Bi-directional Data Bus (output when OE is low)

Table 38. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0

1

0

1

0

1

Load Flash or EEPROM Address (High or low address byte determined by BS1)

Load Data (High or low data byte for Flash determined by BS1)

Load Command

No Action, Idle

Table 39. Command Byte Bit Coding

Command Byte

1000 0000

Command Executed

Chip Erase

0100 0000

Write Fuse Bits

Write Lock Bits

Write Flash

0010 0000

0001 0000

0001 0001

Write EEPROM

Read Signature Bytes

Read Lock and Fuse Bits

Read Flash

0000 1000

0000 0100

0000 0010

0000 0011

Read EEPROM

106

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Enter Programming Mode

The following algorithm puts the device in Parallel Programming mode:

1. Apply supply voltage according to Table 36, between V_CCand GND.

2. Set RESET and BS1 pins to “0” and wait at least 100 ns.

3. Apply 11.5 - 12.5V to RESET. Any activity on BS1 within 100 ns after +12V has

been applied to RESET will cause the device to fail entering Programming mode.

Chip Erase

The Chip Erase will erase the Flash and EEPROM memories, and Lock bits. The Lock

bits are not reset until the Program memory has been completely erased. The Fuse bits

are not changed. A chip erase must be performed before the Flash or EEPROM is

reprogrammed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a t_{WLWH_CE}wide negative pulse to execute Chip Erase. See Table 40 for

t_{WLWH_CE}value. Chip Erase does not generate any activity on the RDY/BSY pin.

Table 40. Minimum WR Pulse Width for Chip Erase

Symbol

3.2V

3.6V

4.0V

5.0V

t_{WLWH_CE}

56 ms

43 ms

35 ms

22 ms

Programming the Flash

The Flash is organized as 512 pages of 256 bytes each. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to

be programmed simultaneously. The following procedure describes how to program the

entire Flash memory:

A: Load Command “Write Flash”.

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B: Load Address Low Byte.

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address Low Byte ($00 - $FF)

4. Give XTAL1 a positive pulse. This loads the address Low Byte.

C: Load Data Low Byte.

1. Set BS1 to “0”. This selects low data.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data Low Byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the data byte.

D: Latch Data Low Byte.

1. Give PAGEL a positive pulse. This latches the data Low Byte.

(See Figure 73 for signal waveforms.)

107

0945I–AVR–02/07

E: Load Data High Byte.

1. Set BS1 to “1”. This selects high data.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data High Byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the data High Byte.

F: Latch Data High Byte.

1. Give PAGEL a positive pulse. This latches the data High Byte.

G: Repeat B through F 128 times to fill the page buffer.

H: Load Address High Byte.

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address High Byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address High Byte.

I: Program Page.

1. Give WR a negative pulse. This starts programming of the entire page of data.

RDY/BSY goes low.

2. Wait until RDY/BSY goes high.

(See Figure 74 for signal waveforms.)

J: End Page Programming.

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA = “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command and the internal write sig-

nals are reset.

K: Repeat A through J 512 times or until all data has been programmed.

Figure 73. Programming the Flash Waveforms

DATA

$10

ADDR. LOW

ADDR. HIGH

DATA LOW

XA1

XA2

BS1

XTAL1

WR

RDY/BSY

RESET

+12V

OE

BS2

PAGEL

108

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 74. Programming the Flash Waveforms (Continued)

DATA

DATA HIGH

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET

OE

+12V

PAGEL

BS2

Programming the EEPROM

The programming algorithm for the EEPROM data memory is as follows (refer to “Pro-

gramming the Flash” on page 107 for details on command, address and data loading):

1. A: Load Command “0001 0001”.

2. H: Load Address High Byte ($00 - $0F).

3. B: Load Address Low Byte ($00 - $FF).

4. E: Load Data Low Byte ($00 - $FF).

L: Write Data Low Byte.

1. Set BS to “0”. This selects low data.

2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY

goes low.

3. Wait until RDY/BSY goes high to program the next byte.

(See Figure 75 for signal waveforms.)

The loaded command and address are retained in the device during programming. For

efficient programming, the following should be considered:

•

The command needs only be loaded once when writing or reading multiple memory

locations.

Address High Byte needs only be loaded before programming a new 256-word page

in the EEPROM.

Skip writing the data value $FF that is the contents of the entire EEPROM after a

chip erase.

These considerations also apply to Flash, EEPROM and signature bytes reading.

109

0945I–AVR–02/07

Figure 75. Programming the EEPROM Waveforms

$11

DATA

ADDR. HIGH

ADDR. LOW DATA LOW

XA1

XA2

BS1

XTAL1

WR

RDY/BSY

RESET

+12V

OE

BS2

PAGEL

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the

Flash” on page 107 for details on command and address loading):

1. A: Load Command “0000 0010”.

2. H: Load Address High Byte ($00 - $FF).

3. B: Load Address Low Byte ($00 - $FF).

4. Set OE to “0”, and BS1 to “0”. The Flash word Low Byte can now be read at

DATA.

5. Set BS to “1”. The Flash word High Byte can now be read at DATA.

6. Set OE to “1”.

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” on page 107 for details on command and address loading):

1. A: Load Command “0000 0011”.

2. H: Load Address High Byte ($00 - $0F).

3. B: Load Address ($00 - $FF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at

DATA.

5. Set OE to “1”.

Programming the Fuse Bits

The algorithm for programming the Fuse bits is as follows (refer to “Programming the

Flash” on page 107 for details on command and data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

Bit 5 = SPIEN Fuse bit

Bit 3 = EESAVE Fuse bit

Bit 2 = always “1”

110

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Bit 1 = SUT1 Fuse bit

Bit 0 = SUT0 Fuse bit

Bit 7, 6, 4, 2 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3. Give WR a t_{WLWH_PFB}wide negative pulse to execute the programming. t_{WLWH_PFB}is

found in Table 41. Programming the Fuse bits does not generate any activity on

the RDY/BSY pin.

Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the

Flash” on page 107 for details on command and data loading):

1. A: Load Command “0010 0000”.

2. D: Load Data Low Byte. Bit n = “0” programs the Lock bit.

Bit 2 = Lock Bit2

Bit 1 = Lock Bit1

Bit 7 - 3, 0 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3. L: Write Data Low Byte.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock

Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming

the Flash” on page 107 for details on command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, and BS to “0”. The status of the Fuse bits can now be read at

DATA (“0” means programmed).

Bit 5 = SPIEN Fuse bit

Bit 3 = EESAVE Fuse bit

Bit 1 = SUT1 Fuse bit

Bit 0 = SUT0 Fuse bit

Set OE to “0”, and BS to “1”. The status of the Lock bits can now be read at DATA

(“0” means programmed).

Bit 2 = Lock Bit2

Bit 1 = Lock Bit1

3. Set OE to “1”.

Reading the Signature Bytes

The algorithm for reading the signature bytes is as follows (refer to “Programming the

Flash” on page 107 for details on command and address loading):

1. A: Load Command “0000 1000”.

2. C: Load Address Low Byte ($00 - $02).

Set OE to “0”, and BS to “0”. The selected signature byte can now be read at DATA.

3. Set OE to “1”.

111

0945I–AVR–02/07

Parallel Programming

Characteristics

Figure 76. Parallel Programming Timing

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDX

Data & Contol

(DATA, XA0/1, BS1)

t_BVXH

t_PLBXt_BVWL

t_RHBX

PAGEL

t_PHPL

t_WLWH

WR

t_PLWL

t_WHRL

RDY/BSY

t_WLRH

t_OHDZ

OE

t_XLOL

t_OLDV

DATA

Table 41. Parallel Programming Characteristics T_A= 25°C 10%, V_CC= 5V 10%

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

250

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Valid before XTAL1 High

XTAL1 Pulse Width High

11.5

I_PP

µA

ns

ms

ns

ms

t_DVXH

t_XHXL

67

t_XLDX

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

t_XLWL

t_BVXH

t_PHPL

BS1 Valid before XTAL1 High

PAGEL Pulse Width High

t_PLBX

BS1 Hold after PAGEL Low

PAGEL Low to WR Low

t_PLWL

t_BVWL

t_RHBX

t_WLWH

t_WHRL

t_WLRH

t_XLOL

BS1 Valid to WR Low

BS1 Hold after RDY/BSY High

WR Pulse Width Low⁽¹⁾

WR High to RDY/BSY Low⁽²⁾

WR Low to RDY/BSY High⁽²⁾

XTAL1 Low to OE Low

20

0.5

67

0.7

0.9

t_OLDV

t_OHDZ

t_{WLWH_CE}

t_{WLWH_PFB}

OE Low to DATA Valid

20

OE High to DATA Tri-stated

WR Pulse Width Low for Chip Erase

WR Pulse Width Low for Progr. the Fuse Bits

20

15

5

10

1.0

1.5

1.8

Notes: 1. Use t_{WLWH_CE}for Chip Erase and t_{WLWH_PFB}for programming the fuse bits.

2. If t_WLWHis held longer than t_WLRH, no RDY/BSY pulse will be seen.

112

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial inter-

face while RESET is pulled to GND, or when PEN is low during Power-on Reset. The

serial interface consists of pins SCK, RXD/PDI (input) and TXD/PDO (output). After

RESET is set low, the Programming Enable instruction needs to be executed first before

program/erase instructions can be executed.

For the EEPROM, an auto-erase cycle is provided within the self-timed Write instruction

and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-

tion turns the content of every memory location in both the Program and EEPROM

arrays into $FF.

The Program and EEPROM memory arrays have separate address spaces: $0000 to

$FFFF for Program memory and $0000 to $0FFF for EEPROM memory.

Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected

across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock

(SCK) input are defined as follows:

Low: > 2 XTAL1 clock cycles

High: > 2 XTAL1 clock cycles

Figure 77. Serial Programming

ATmega103(L)

VCC

INSTR. IN

DATA OUT

CLOCK IN

PE0 (PD1/RXD)

PE1 (PD0/TXD)

PB1 (SCK)

XTAL1

RESET

GND

Note:

Instruction in and data out is not using the SPI pins as on other AVR devices. SCK uses

the SPI pin as usual.

Serial Programming

Algorithm

When writing serial data to the ATmega103(L), data is sampled by the ATmega

103/103L on the rising edge of SCK. When reading data from the ATmega103(L), data

is clocked on the falling edge of SCK. See Figure 78 for an explanation. To program and

verify the ATmega103(L) in the Serial Programming mode, the following sequence is

recommended (See 4-byte instruction formats in Table 44.):

1. Power-up sequence: Apply power between V_CCand GND while RESET and SCK

are set to “0”. The RESET signal must be kept low during the complete serial

programming session. If a crystal is not connected across pins XTAL1 and

XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer

cannot guarantee that SCK is held low during Power-up. In this case, RESET

must be given a positive pulse of at least two XTAL1 cycles duration after SCK

has been set to “0”.

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0945I–AVR–02/07

As an alternative to using the RESET signal, PEN can be held low during Power-

on Reset while SCK is set to “0”. In this case, only the PEN value at Power-on

Reset is important. If a crystal is not connected across pins XTAL1 and XTAL2,

apply a clock signal to the XTAL1 pin. If the programmer cannot guarantee that

SCK is held low during power-up, the PEN method cannot be used. The device

must be powered down in order to commence normal operation when using this

method.

2. Wait for at least 20 ms and enable serial programming by sending the Program-

ming Enable serial instruction to pin PE0(PDI/RXD).

3. The serial programming instructions will not work if the communication is out of

synchronization. When in sync, the second byte ($53) will echo back when issu-

ing the third byte of the Programming Enable instruction. Whether the echo is

correct or not, all four bytes of the instruction must be transmitted. If the $53 did

not echo back, give SCK a positive pulse and issue a new Programming Enable

instruction. If the $53 is not seen within 32 attempts, there is no functional device

connected.

4. If a chip erase is performed (must be done to erase the Flash), wait at least (2 x

t

_{WD_FLASH}), give RESET a positive pulse of at least two XTAL1 cycles duration

after SCK has been set to “0”, and start over from step 2.

5. The Flash is programmed one page at a time. The memory page is loaded one

byte at a time by supplying the 7 LSB of the address and data together with the

Load Program Memory Page instruction. The Program Memory Page is stored

by loading the Write Program Memory Page instruction with the 9 MSB of the

address. The next page can be written after t_{WD_FLASH}, i.e., writing 256 bytes

takes t_{WD_FLASH}. Accessing the serial programming interface before the Flash

write operation completes can result in incorrect programming.

6. The EEPROM array is programmed one byte at a time by supplying the address

and data together with the appropriate Write instruction. An EEPROM memory

location is first automatically erased before new data is written. If polling is not

used, the user must wait at least t_{WD_EEPROM}before issuing the next byte. (Please

refer to Table 42.)

7. Any memory location can be verified by using the Read instruction, which

returns the content at the selected address at serial output PE1(PDO/TXD).

8. At the end of the programming session, RESET can be set high to commence

normal operation.

9. Power-off sequence (if needed): Set XTAL1 to “0” (if a crystal is not used). Set

RESET to “1”. Turn V_CCpower off.

Table 42 shows the actual delays used in this section.

Please note: The MISO pin is not high-Z during serial programming.

Data Polling for the EEPROM

When a new EEPROM byte has been written and is being programmed into the

EEPROM, reading the address location being programmed will first give the value P1

(please refer to Table 43) until the auto-erase is finished, and then the value P2.

At the time the device is ready for a new EEPROM byte, the programmed value will read

correctly. This is used to determine when the next byte can be written. This will not work

for the values P1 and P2, so when programming these values, the user will have to wait

for at least the prescribed time t_{WD_EEPROM}(please refer to Table 42) before programming

the next byte. As a chip-erased device contains $FF in all locations, programming of

addresses that are meant to contain $FF can be skipped. This does not apply if the

EEPROM is reprogrammed without chip erasing the device.

114

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Data polling is not implemented for the Flash.

Table 42. Minimum Wait Delay before Writing the Next Flash or EEPROM Location

Symbol

3.2V

56 ms

9 ms

3.6V

43 ms

7 ms

4.0V

35 ms

6 ms

5.0V

22 ms

4 ms

(Note:)

t_{WD_FLASH}

t_{WD_EEPROM}

Note: Per page.

Table 43. Read Back Value during EEPROM Polling

Part/Revision

P1

P2

TBD

Note:

See Errata sheet for latest information.

115

0945I–AVR–02/07

Table 44. Serial Programming Instruction Set

Instruction Format

Byte 2 Byte 3

Instruction

Byte 1

Byte 4

Operation

Programming Enable

1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable serial programming while

RESET is low.

Chip Erase

1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip erase EEPROM and Flash.

Read Program Memory

0010 H000 aaaa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from

Program memory at word address a:b.

Load Program Memory Page 0100 H000 xxxx xxxx xbbb bbbb iiii iiii Write H (high or low) data i to Program

memory page at word address b.

Write Program Memory Page 0100 1100 aaaa aaaa bxxx xxxx xxxx xxxx Write Program memory page at

address a:b.

Read EEPROM Memory

Write EEPROM Memory

Read Lock Bits

1010 0000 xxxx aaaa bbbb bbbb oooo oooo Read data o from EEPROM memory

at address a:b.

1100 0000 xxxx aaaa bbbb bbbb iiii iiii Write data i to EEPROM memory at

address a:b.

0101 1000 xxxx xxxx xxxx xxxx xxxx x21x Read Lock bits. “0” = programmed,

“1” = unprogrammed.

Write Lock Bits

1010 1100 1111 1211 xxxx xxxx xxxx xxxx Write Lock bits. Set bits 1,2 = “0” to

Program Lock bits.

Read Fuse Bits

0101 0000 xxxx xxxx xxxx xxxx xx5x 6143 Read Fuse bits. “0” = programmed,

“1” = unprogrammed.

Write Fuse Bits

1010 1100 1011 6143 xxxx xxxx xxxx xxxx Write Fuse bits. Set bit 6,4,3 = “0” to

program, “1” to unprogram.

Read Signature Byte

0011 0000 xxxx xxxx xxxx xxbb oooo oooo Read signature byte o at address b.

Note:

a = address high bits

b = address low bits

H = 0 – Low byte, 1 – High byte

o = data out

i = data in

x = don’t care

1 = Lock Bit 1

2 = Lock Bit 2

3 = SUT0 Fuse

4 = SUT1 Fuse

5 = SPIEN Fuse

6 = EESAVE Fuse

116

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 78. Serial Programming Waveforms

SERIAL DATA INPUT

PE0(PDI/RXD)

MSB

LSB

SERIAL DATA OUTPUT

PE1(PDO/TXD)

MSB

SERIAL CLOCK INPUT

PB1(SCK)

SAMPLE

117

0945I–AVR–02/07

Electrical Characteristics

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................. -40°C to +105°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin except RESET

with Respect to Ground...............................-1.0V to V_CC+ .5V

Voltage on RESET with Respect to Ground ...-1.0V to + 13.0V

Maximum Operating Voltage ............................................ 6.6V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND........................................ 400.0 mA

DC Characteristics

T_A= -40°C to 85°C, V_CC= 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted)

Symbol

V_IL

Parameter

Condition

Except (XTAL)

XTAL

Min

-0.5

Typ

Max

Units

(1)

Input Low Voltage

Input High Voltage

0.3 V_CC

V

V_IL1

-0.5

0.2 V_CC- 0.1⁽¹⁾

(2)

V_IH

Except (XTAL, RESET)

XTAL

0.6 V_CC

0.7 V_CC

V_CC+ 0.5

V_IH1

V_IH2

V_CC+ 0.5

(2)

RESET

0.85 V_CC

V_CC+ 0.5

Output Low Voltage⁽³⁾

Ports A, B, C, D, E

I_OL= 20 mA, V_CC= 5V

I_OL= 10 mA, V_CC= 3V

0.6

0.5

V

V_OL

Output High Voltage⁽⁴⁾

Ports A, B, C, D, E

I_OH= -3 mA, V_CC= 5V

I_OH= -1.5 mA, V_CC= 3V

4.3

2.2

V

V_OH

I_IL

Input Leakage

Current I/O Pin

V_CC= 6V, Pin Low

(absolute value)

8.0

µA

I_IH

Input Leakage

Current I/O Pin

V_CC= 6V, Pin High

(absolute value)

µA

RRST

R_I/O

Reset Pull-up

I/O Pin Pull-up

100

35

500

120

5.0

kΩ

Active 4 MHz, V_CC= 3V

Idle 4 MHz, V_CC= 3V

mA

2.0

Power-down⁽⁵⁾, V_CC= 3V

WDT Enabled

40.0

25.0

35.0

µA

I_CC

Power Supply Current

Power-down⁽⁵⁾, V_CC= 3V

WDT Disabled

Power-save⁽⁵⁾, V_CC= 3V

WDT Disabled

118

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

DC Characteristics (Continued)

T_A= -40°C to 85°C, V_CC= 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min

Typ

Max

Units

Analog Comp

Input Offset V

V_CC= 5V

V_IN= V_CC/2

V_ACIO

40

mV

Analog Comp

Input Leakage A

V_CC= 5V

V_IN= V_CC/2

I_ACLK

t_ACPD

-50

50

nA

ns

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 4.0V

750

500

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.

2. “Min” means the lowest value where the pin is guaranteed to be read as high.

3. Although each I/O port can sink more than the test conditions (20 mA at V_CC= 5V, 10 mA at V_CC= 3V) under steady-state

conditions (non-transient), the following must be observed:

1] The sum of all I_OL, for all ports, should not exceed 400 mA.

2] The sum of all I_OL, for ports A0 - A7, ALE, C3 - C7 should not exceed 100 mA.

3] The sum of all I_OL, for ports C0 - C2, RD, WR, D0 - D7, XTAL2 should not exceed 100 mA.

4] The sum of all I_OL, for ports B0 - B7, should not exceed 100 mA.

5] The sum of all I_OL, for ports E0 - E7, should not exceed 100 mA.

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (3 mA at V_CC= 5V, 1.5 mA at V_CC= 3V) under steady-state

conditions (non-transient), the following must be observed:

1] The sum of all I_OH, for all ports, should not exceed 400 mA.

2] The sum of all I_OH, for ports A0 - A7, ALE, C3 - C7 should not exceed 100 mA.

3] The sum of all I_OH, for ports C0 - C2, RD, WR, D0 - D7, XTAL2 should not exceed 100 mA.

4] The sum of all I_OH, for ports B0 - B7, should not exceed 100 mA.

5] The sum of all I_OH, for ports E0 - E7, should not exceed 100 mA.

If I_OHexceeds the test condition, V_OHmay exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

5. Minimum V_CCfor Power-down is 2V.

119

0945I–AVR–02/07

External Data Memory Timing

Table 45. External Data Memory Characteristics, 4.0 - 6.0 Volts, No Wait State

6 MHz Oscillator

Variable Oscillator

Symbol

1/t_CLCL

t_LHLL

Parameter

Min

Max

Min

Max

Unit

MHz

ns

0

1

2

Oscillator Frequency

ALE Pulse Width

0.0

6.0

48.3

43.3

77.3

0.5 t_CLCL- 35.0⁽¹⁾

0.5 t_CLCL- 40.0⁽¹⁾

0.5 t_CLCL- 10.0⁽²⁾

t_AVLL

Address Valid A to ALE Low

ns

3a t_{LLAX_ST}

Address Hold after ALE Low,

ST/STD/STS Instructions

ns

3b t_{LLAX_LD}

Address Hold after ALE Low,

LD/LDD/LDS Instructions

15.0

ns

4

5

6

7

8

9

t_AVLLC

t_AVRL

t_AVWL

t_LLWL

t_LLRL

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

ALE Low to RD Low

43.3

136.7

215.0

146.7

70.0

0.5 t_CLCL- 40.0⁽¹⁾

1.0 t_CLCL- 30.0

1.5 t_CLCL- 35.0⁽¹⁾

1.0 t_CLCL- 20.0

0.5 t_CLCL- 20.0⁽²⁾

70.0

ns

186.7

1.0 t_CLCL+ 20.0

0.5 t_CLCL+ 20.0⁽²⁾

t_DVRH

Data Setup to RD High

Read Low to Data Valid

Data Hold after RD High

RD Pulse Width

10 t_RLDV

11 t_RHDX

12 t_RLRH

13 t_DVWL

14 t_WHDX

15 t_DVWH

16 t_WLWH

136.7

1.0 t_CLCL- 30.0

0.0

146.7

53.3

0.0

1.0 t_CLCL- 20.0

0.5 t_CLCL- 30.0⁽²⁾

0.0

Data Setup to WR Low

Data Hold after WR High

Data Valid to WR High

WR Pulse Width

146.7

63.3

1.0 t_CLCL- 20.0

0.5 t_CLCL- 20.0⁽¹⁾

Table 46. External Data Memory Characteristics, 4.0 - 6.0 Volts, 1 Cycle Wait State

6 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

6.0

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

303.4

2.0 t_CLCL- 30.0

313.4

230.0

2.0 t_CLCL- 20.0

1.5 t_CLCL- 20.0⁽²⁾

ns

Data Valid to WR High

WR Pulse Width

ns

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

120

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Table 47. External Data Memory Characteristics, 2.7 - 3.6 Volts, No Wait State

4 MHz Oscillator

Variable Oscillator

Symbol

1/t_CLCL

t_LHLL

Parameter

Min

Max

Min

Max

Unit

MHz

ns

0

1

2

Oscillator Frequency

ALE Pulse Width

0.0

4.0

65.0

75.0

0.5 t_CLCL- 60.0⁽¹⁾

0.5 t_CLCL- 50.0⁽¹⁾

t_AVLL

Address Valid A to ALE Low

ns

(2)

3a t_{LLAX_ST}

Address Hold after ALE Low,

ST/STD/STS Instructions

125.0

0.5 t_CLCL

ns

3b t_{LLAX_LD}

Address Hold after ALE Low,

LD/LDD/LDS Instructions

15.0

ns

4

5

6

7

8

9

t_AVLLC

t_AVRL

t_AVWL

t_LLWL

t_LLRL

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

ALE Low to RD Low

60.0

205.0

325.0

230.0

105.0

115.0

0.5 t_CLCL- 65.0⁽¹⁾

1.0 t_CLCL- 45.0

1.5 t_CLCL- 65.0⁽¹⁾

1.0 t_CLCL- 20.0

ns

270.0

145.0

1.0 t_CLCL+ 20.0

0.5 t_CLCL- 20.0⁽²⁾0.5 t_CLCL+ 20.0⁽²⁾

t_DVRH

Data Setup to RD High

Read Low to Data Valid

Data Hold after RD High

RD Pulse Width

115.0

1.0 t_CLCL- 40.0

0.0

10 t_RLDV

11 t_RHDX

12 t_RLRH

13 t_DVWL

14 t_WHDX

15 t_DVWH

16 t_WLWH

210.0

0.0

230.0

90.0

0.0

1.0 t_CLCL- 20.0

0.5 t_CLCL- 35.0⁽¹⁾

0.0

Data Setup to WR Low

Data Hold after WR High

Data Valid to WR High

WR Pulse Width

230.0

100.0

1.0 t_CLCL- 20.0

0.5 t_CLCL- 25.0⁽²⁾

Table 48. External Data Memory Characteristics, 2.7 - 3.6 Volts, 1 Cycle Wait State

4 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

4.0

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

460.0

2.0 t_CLCL- 40.0

480.0

350.0

2.0 t_CLCL- 20.0

1.5 t_CLCL- 25.0⁽²⁾

ns

Data Valid to WR High

ns

WR Pulse Width

ns

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

121

0945I–AVR–02/07

Figure 79. External RAM Timing

T1

0

T2

T3

T4

System Clock Ø

ALE

1

4

7

6

Prev. Address

Address

Address [15..8]

2

13

15

Prev. Address

Address

3b

Data

16

Addr.

14

Data / Address [7..0]

3a

WR

11

Prev. Address

Address

Data

Addr.

Data / Address [7..0]

5

10

9

RD

8

12

Note: Clock cycle T3 is only present when external SRAM Wait State is enabled.

External Clock Drive

Waveforms

Figure 80. External Clock Drive Waveforms

VIH1

VIL1

Table 49. External Clock Drive

Symbol

1/t_CLCL

t_CLCL

Parameter

Oscillator Frequency

Clock Period

High Time

V_CC= 2.7V to 3.6V

V_CC= 4.0V to 5.5V

Units

0.0

4.0

0.0

167.0

67.0

6.0

MHz

ns

250.0

100.0

t_CHCX

t_CLCX

ns

Low Time

ns

t_CLCH

Rise Time

1.6

0.5

µs

t_CHCL

Fall Time

µs

Note:

See “External Data Memory Timing” on page 120. for a description of how the duty cycle

influences the timing for the external Data memory.

122

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Typical

Characteristics

The following charts show typical behavior. These figures are not tested during manu-

facturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. All pins on Port F are pulled high

externally. A sine wave generator with rail-to-rail output is used as clock source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage,

operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and

ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as C_L•

V

_CC• f, where C_L= load capacitance, V_CC= operating voltage and f = average switching

frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaran-

teed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog

Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif-

ferential current drawn by the Watchdog Timer.

Figure 81. Active Supply Current vs. Frequency

ACTIVE SUPPLY CURRENT vs. FREQUENCY

T_A= 25˚C

50

V_cc= 6V

45

V_cc= 5.5V

40

V_cc= 5V

35

V_cc= 4.5V

30

25

20

15

10

5

V_cc= 4V

V_cc= 3.6V

V_cc= 3.3V

V_cc= 3.0V

V_cc= 2.7V

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Frequency (MHz)

123

0945I–AVR–02/07

Figure 82. Active Supply Current vs. V_CC

ACTIVE SUPPLY CURRENT vs. V

cc

FREQUENCY = 4 MHz

25

20

15

10

5

T_A= 25˚C

T_A= 85˚C

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 83. Idle Supply Current vs. Frequency

IDLE SUPPLY CURRENT vs. FREQUENCY

T_A= 25˚C

18

16

14

12

10

8

V_cc= 6V

V_cc= 5.5V

V_cc= 5V

V_cc= 4.5V

V_cc= 4V

V_cc= 3.6V

6

V_cc= 3.3V

V_cc= 3.0V

4

V_cc= 2.7V

2

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Frequency (MHz)

124

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 84. Idle Supply Current vs. V_CC

IDLE SUPPLY CURRENT vs. V

cc

FREQUENCY = 4 MHz

7

6

5

4

3

2

1

0

T_A= 85˚C

T_A= 25˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 85. Power-down Supply Current vs. V_CC

POWER-DOWN SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER DISABLED

70

60

50

40

30

20

10

0

T_A= 85˚C

T_A= 70˚C

T_A= 45˚C

T_A= 25˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

125

0945I–AVR–02/07

Figure 86. Power-down Supply Current vs. V_CC

POWER-DOWN SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER ENABLED

250

200

150

100

50

T_A= 85˚C

T_A= 25˚C

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 87. Power-save Supply Current vs. V_CC

POWER SAVE SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER DISABLED

80

70

60

50

40

30

20

10

0

T_A= 85˚C

T_A= 25˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

126

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 88. Analog Comparator Current vs. V_CC

ANALOG COMPARATOR CURRENT vs. V

cc

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T_A= 25˚C

T_A= 85˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Analog comparator offset voltage is measured as absolute offset.

Figure 89. Analog Comparator Offset Voltage vs. Common Mode Voltage

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

V_cc= 5V

18

16

14

12

10

8

T_A= 25˚C

T_A= 85˚C

6

4

2

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Common Mode Voltage (V)

127

0945I–AVR–02/07

Figure 90. Analog Comparator Offset Voltage vs. Common Mode Voltage

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

V_cc= 2.7V

10

8

T_A= 25˚C

6

T_A= 85˚C

4

2

0

0.5

1

1.5

2

2.5

3

Common Mode Voltage (V)

Figure 91. Analog Comparator Input Leakage Current

ANALOG COMPARATOR INPUT LEAKAGE CURRENT

V_CC= 6V

T_A= 25˚C

60

50

40

30

20

10

0

-10

0

0.5

1

1.5

2

2.5

3

3.5

V (V)

4

4.5

5

5.5

6

6.5

7

IN

128

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 92. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. V

cc

1600

1400

1200

1000

800

600

400

200

0

T_A= 25˚C

T_A= 85˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Sink and source capabilities of I/O ports are measured on one pin at a time.

Figure 93. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_cc= 5V

120

T_A= 25˚C

100

T_A= 85˚C

80

60

40

20

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_OP(V)

129

0945I–AVR–02/07

Figure 94. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_cc= 2.7V

30

25

20

15

10

5

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

V_OP(V)

Figure 95. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_cc= 5V

70

60

50

40

30

20

10

0

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

V_OL(V)

130

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 96. I/O Pin Source Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_cc= 5V

20

18

16

14

12

10

8

T_A= 25˚C

T_A= 85˚C

6

4

2

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_OH(V)

Figure 97. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_cc= 2.7V

25

20

15

10

5

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

V_OL(V)

131

0945I–AVR–02/07

Figure 98. I/O Pin Source Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_cc= 2.7V

6

5

4

3

2

1

0

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

V_OH(V)

Figure 99. I/O Pin Input Threshold Voltage vs. V_CC

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

cc

T_A= 25˚C

2.5

2

1.5

1

0.5

0

2.7

4.0

5.0

V_cc

132

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Figure 100. I/O Pin Input Hysteresis vs. V_CC

I/O PIN INPUT HYSTERESIS vs. V

cc

T_A= 25˚C

0.18

0.16

0.14

0.12

0.1

0.08

0.06

0.04

0.02

0

2.7

4.0

5.0

V_cc

133

0945I–AVR–02/07

Register Summary

Address

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$21 ($47)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

$07 ($27)

$06 ($26)

$05 ($25)

$04 ($24)

$03 ($23)

$02 ($22)

$01 ($21)

$00 ($20)

Name

SREG

Bit7

I

Bit6

T

Bit5

H

Bit4

S

Bit3

V

Bit2

N

Bit1

Z

Bit0

C

Page

page 20

page 21

page 23

page 22

page 31

page 30

page 31

page 33

page 35

page 22

page 29

page 41

page 42

page 43

page 44

page 49

page 50

page 51

page 52

page 41

page 42

page 43

page 55

page 57

page 86

page 88

page 94

page 95

page 65

page 63

page 62

page 70

page 71

page 74

page 75

page 80

page 81

page 99

page 103

SPH

SP15

SP7

XDIVEN

–

SP14

SP6

SP13

SP5

SP12

SP4

SP11

SP3

XDIV3

–

SP10

SP2

XDIV2

–

SP9

SP1

XDIV1

–

SP8

SPL

SP0

XDIV

XDIV6

–

XDIV5

–

XDIV4

–

XDIV0

RAMPZ0

ISC40

INT0

–

RAMPZ

EICR

ISC71

INT7

INTF7

OCIE2

OCF2

SRE

–

ISC70

INT6

INTF6

TOIE2

TOV2

SRW

–

ISC61

INT5

INTF5

TICIE1

ICF1

SE

ISC60

INT4

INTF4

OCIE1A

OCF1A

SM1

ISC51

INT3

–

ISC50

INT2

–

ISC41

INT1

–

EIMSK

EIFR

TIMSK

TIFR

OCIE1B

OCF1B

SM0

–

TOIE1

TOV1

–

OCIE0

OCF0

–

TOIE0

TOV0

–

MCUCR

MCUSR

TCCR0

TCNT0

OCR0

ASSR

–

EXTRF

CS01

PORF

CS00

–

PWM0

COM01

COM00

CTC0

CS02

Timer/Counter0 (8-bit)

Timer/Counter0 Output Compare Register

–

COM1B1

–

COM1B0

–

AS0

–

TCN0UB

–

OCR0UB

PWM11

CS11

TCR0UB

PWM10

CS10

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

TCCR2

TCNT2

OCR2

WDTCR

EEARH

EEARL

EEDR

EECR

PORTA

DDRA

PINA

COM1A1

ICNC1

COM1A0

ICES1

CTC1

CS12

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Output Compare Register A High Byte

Timer/Counter1 – Output Compare Register A Low Byte

Timer/Counter1 – Output Compare Register B High Byte

Timer/Counter1 – Output Compare Register B Low Byte

Timer/Counter1 – Input Capture Register High Byte

Timer/Counter1 – Input Capture Register Low Byte

–

PWM2

COM21

COM20

CTC2

CS22

CS21

CS20

Timer/Counter2 (8-bit)

Timer/Counter2 Output Compare Register

–

WDTOE

–

WDE

WDP2

WDP1

WDP0

EEAR11

EEAR10

EEAR9

EEAR8

EEPROM Address Register L

EEPROM Data Register

–

EERIE

PORTA3

DDA3

EEMWE

PORTA2

DDA2

EEWE

PORTA1

DDA1

EERE

PORTA0

DDA0

PORTA7

DDA7

PORTA6

DDA6

PORTA5

DDA5

PORTA4

DDA4

PINA7

PORTB7

DDB7

PINA6

PINA5

PINA4

PINA3

PINA2

PINA1

PINA0

PORTB

DDRB

PINB

PORTB6

DDB6

PORTB5

DDB5

PORTB4

DDB4

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

PINB7

PORTC7

PORTD7

DDD7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

PORTC

PORTD

DDRD

PIND

PORTC6

PORTD6

DDD6

PORTC5

PORTD5

DDD5

PORTC4

PORTD4

DDD4

PORTC3

PORTD3

DDD3

PORTC2

PORTD2

DDD2

PORTC1

PORTD1

DDD1

PORTC0

PORTD0

DDD0

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

SPDR

SPSR

SPI Data Register

SPIF

SPIE

WCOL

SPE

–

SPCR

UDR

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

UART I/O Data Register

USR

RXC

TXC

UDRE

UDRIE

FE

OR

–

UCR

RXCIE

TXCIE

RXEN

TXEN

CHR9

RXB8

TXB8

UBRR

ACSR

ADMUX

ADCSR

ADCH

ADCL

UART Baud Rate Register

ACD

–

ACO

–

ACI

–

ACIE

–

ACIC

MUX2

ADPS2

–

ACIS1

MUX1

ADPS1

ADC9

ACIS0

MUX0

ADPS0

ADC8

ADEN

–

ADSC

–

ADIF

–

ADIE

–

ADC7

PORTE7

DDE7

PINE7

PINF7

ADC6

PORTE6

DDE6

PINE6

PINF6

ADC5

PORTE5

DDE5

PINE5

PINF5

ADC4

PORTE4

DDE4

PINE4

PINF4

ADC3

PORTE3

DDE3

PINE3

PINF3

ADC2

PORTE2

DDE2

PINE2

PINF2

ADC1

ADC0

PORTE

DDRE

PINE

PORTE1

DDE1

PORTE0

DDE0

PINE1

PINF1

PINE0

PINF0

PINF

Note:

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written. Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instruc-

tions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and

SBI instructions work with registers $00 to $1F only.

134

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add Two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry Two Registers

Add Immediate to Word

Subtract Two Registers

Subtract Constant from Register

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Rd ← Rd v K

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd, K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd - 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

JMP

k

Direct Jump

PC ← k

3

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd, Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd - Rr

None

Z,N,V,C,H

None

1/2/3

1

Rd, Rr

CPC

Rd, Rr

Compare with Carry

Rd - Rr - C

1

CPI

Rd, K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (P(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ← PC + k + 1

if (SREG(s) = 0) then PC ← PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V = 0) then PC ← PC + k + 1

if (N ⊕ V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-flag Set

k

Branch if T-flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

DATA TRANSFER INSTRUCTIONS

ELPM

Extended Load Program Memory

Move between Registers

Load Immediate

R0 ← (Z + RAMPZ)

Rd ← Rr

None

3

1

MOV

LDI

Rd, Rr

Rd, K

Rd ← K

135

0945I–AVR–02/07

Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

LD

Rd, X

Load Indirect

Rd ← (X)

None

2

3

1

2

LD

Rd, X+

Rd, -X

Rd, Y

Load Indirect and Post-increment

Load Indirect and Pre-decrement

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, -Y

Rd, Y+q

Rd, Z

Load Indirect and Post-increment

Load Indirect and Pre-decrement

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-increment

Load Indirect and Pre-decrement

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z + 1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

LD

LDD

LDS

ST

Rd ← (k)

X, Rr

(X) ← Rr

ST

X+, Rr

-X, Rr

Y, Rr

Store Indirect and Post-increment

Store Indirect and Pre-decrement

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

-Y, Rr

Store Indirect and Post-increment

Store Indirect and Pre-decrement

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

Y+q, Rr

Z, Rr

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q, Rr

k, Rr

Store Indirect and Post-increment

Store Indirect and Pre-decrement

Store Indirect with Displacement

Store Direct to SRAM

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

IN

(k) ← Rr

Load Program Memory

R0 ← (Z)

Rd, P

P, Rr

Rr

In Port

Rd ← P

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

P, b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)

Z,C,N,V

Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n = 0..6

Z,C,N,V

Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit Load from T to Register

Set Carry

T

None

C

Clear Carry

C ← 0

C

Set Negative Flag

N ← 1

N

Clear Negative Flag

Set Zero Flag

N ← 0

N

Z ← 1

Z

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

SET

CLT

T ← 1

T

Clear T in SREG

T ← 0

T

SEH

CLH

NOP

SLEEP

WDR

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

H ← 1

H

H ← 0

H

None

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WD Timer)

Watchdog Reset

136

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Ordering Information

Speed (MHz)

Power Supply

Ordering Code

Package

Operation Range

4

2.7 - 3.6V

ATmega103L-4AC

64A

Commercial

(0°C to 70°C)

ATmega103L-4AI

ATmega103-6AC

ATmega103-6AI

64A

Industrial

(-40°C to 85°C)

6

4.0 - 5.5V

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

64A

137

0945I–AVR–02/07

Packaging Information

64A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0°~7°

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.95

15.75

13.90

15.75

13.90

0.30

0.09

0.45

–

0.15

1.00

16.00

14.00

16.00

14.00

–

1.05

16.25

D1

E

14.10 Note 2

16.25

Notes:

E1

B

14.10 Note 2

0.45

1.This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

64A

R

B

138

ATmega103(L)

0945I–AVR–02/07

ATmega103(L)

Table of Contents

Features................................................................................................. 1

Pin Configuration .................................................................................................. 2

Description............................................................................................ 3

Block Diagram ...................................................................................................... 4

Pin Descriptions.................................................................................................... 5

Clock Options ....................................................................................................... 6

Architectural Overview......................................................................... 8

General-purpose Register File.............................................................................. 9

ALU – Arithmetic Logic Unit................................................................................ 10

ISP Flash Program Memory ............................................................................... 10

SRAM Data Memory........................................................................................... 10

Program and Data Addressing Modes................................................................ 12

EEPROM Data Memory...................................................................................... 17

Memory Access Times and Instruction Execution Timing .................................. 17

I/O Memory......................................................................................................... 18

Reset and Interrupt Handling.............................................................................. 23

Sleep Modes....................................................................................................... 36

Timer/Counters ................................................................................... 38

Timer/Counter Prescalers................................................................................... 38

8-bit Timer/Counters T/C0 and T/C2 .................................................................. 39

16-bit Timer/Counter1......................................................................................... 47

Watchdog Timer.................................................................................. 55

EEPROM Read/Write Access............................................................. 57

Prevent EEPROM Corruption............................................................................. 59

Serial Peripheral Interface – SPI........................................................ 60

Data Modes ........................................................................................................ 62

UART.................................................................................................... 66

Data Transmission.............................................................................................. 66

Data Reception................................................................................................... 68

UART Control ..................................................................................................... 70

Analog Comparator ............................................................................ 75

Analog-to-Digital Converter............................................................... 77

Feature list:......................................................................................................... 77

Operation............................................................................................................ 78

Prescaling........................................................................................................... 78

ADC Noise Canceler Function............................................................................ 80

ADC Noise Canceling Techniques ..................................................................... 82

i

0945I–AVR–02/07

ADC DC Characteristics ..................................................................................... 83

Interface to External SRAM................................................................ 84

I/O Ports............................................................................................... 86

Port A.................................................................................................................. 86

Port B.................................................................................................................. 87

Port C.................................................................................................................. 94

Port D.................................................................................................................. 94

Port E.................................................................................................................. 98

Port F................................................................................................................ 103

Memory Programming...................................................................... 104

Program and Data Memory Lock Bits............................................................... 104

Fuse Bits........................................................................................................... 104

Signature Bytes ................................................................................................ 104

Programming the Flash and EEPROM............................................................. 104

Parallel Programming ....................................................................................... 105

Parallel Programming Characteristics .............................................................. 112

Serial Downloading........................................................................................... 113

Electrical Characteristics................................................................. 118

Absolute Maximum Ratings*............................................................................. 118

DC Characteristics............................................................................................ 118

External Data Memory Timing .......................................................................... 120

External Clock Drive Waveforms...................................................................... 122

Typical Characteristics .................................................................... 123

Register Summary............................................................................ 134

Instruction Set Summary ................................................................. 135

Ordering Information........................................................................ 137

Packaging Information..................................................................... 138

64A ................................................................................................................... 138

Table of Contents .................................................................................. i

ii

ATmega103(L)

0945I–AVR–02/07

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT

OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

ers, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of oth-

ers.

0945I–AVR–02/07


型号：	ATMEGA103_07
厂家：	ATMEL
描述：	8-bit Microcontroller with 128K Bytes In-System Programmable Flash 8位微控制器，带有128K字节的系统内可编程闪存闪存微控制器
文件：	总141页 (文件大小：2195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA103_07 [ATMEL]

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