ATMEGA128(L) [ETC]
ATmega128(L) Preliminary Summary [Updated 9/03. 23 Pages] ; ATmega128的( L)初步总结[ 9/03更新。 23页]\n![ATMEGA128(L)](http://pdffile.icpdf.com/pdf1/p00008/img/icpdf/ATMEG_38373_icpdf.jpg)
型号: | ATMEGA128(L) |
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描述: | ATmega128(L) Preliminary Summary [Updated 9/03. 23 Pages]
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Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
– 128K Bytes of In-System Reprogrammable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
– 4K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 4K Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
Capture Mode
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
ATmega128
ATmega128L
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
Preliminary
Summary
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
• I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad MLF
• Operating Voltages
– 2.7 - 5.5V for ATmega128L
– 4.5 - 5.5V for ATmega128
• Speed Grades
Rev. 2467IS–AVR–09/03
– 0 - 8 MHz for ATmega128L
– 0 - 16 MHz for ATmega128
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
Pin Configurations
Figure 1. Pinout ATmega128
PEN
RXD0/(PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
1
2
3
4
5
6
7
8
9
48 PA3 (AD3)
47 PA4 (AD4)
46 PA5 (AD5)
45 PA6 (AD6)
44 PA7 (AD7)
43 PG2(ALE)
42 PC7 (A15)
41 PC6 (A14)
40 PC5 (A13)
39 PC4 (A12)
38 PC3 (A11)
37 PC2 (A10)
36 PC1 (A9)
35 PC0 (A8)
34 PG1(RD)
33 PG0(WR)
(IC3/INT7) PE7
(SS) PB0 10
(SCK) PB1 11
(MOSI) PB2 12
(MISO) PB3 13
(OC0) PB4 14
(OC1A) PB5 15
(OC1B) PB6 16
Overview
The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the sys-
tem designer to optimize power consumption versus processing speed.
2
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
Block Diagram
Figure 2. Block Diagram
PF0 - PF7
PA0 - PA7
PC0 - PC7
VCC
GND
PORTA DRIVERS
PORTF DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
CALIB. OSC
INTERNAL
OSCILLATOR
ADC
AGND
AREF
OSCILLATOR
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
JTAG TAP
TIMING AND
CONTROL
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
ON-CHIP DEBUG
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
TIMER/
COUNTERS
GENERAL
PURPOSE
REGISTERS
X
Y
Z
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
PEN
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
TWO-WIRE SERIAL
INTERFACE
SPI
USART0
USART1
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REG. DATA DIR.
PORTG
REG. PORTG
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PORTE DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
3
2467IS–AVR–09/03
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega128 provides the following features: 128K bytes of In-System Programma-
ble Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53
general purpose I/O lines, 32 general purpose working registers, Real Time Counter
(RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte
oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential
input stage with programmable gain, programmable Watchdog Timer with Internal Oscil-
lator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for
accessing the On-chip Debug system and programming and six software selectable
power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-
down mode saves the register contents but freezes the Oscillator, disabling all other
chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asyn-
chronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all
I/O modules except Asynchronous Timer and ADC, to minimize switching noise during
ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while
the rest of the device is sleeping. This allows very fast start-up combined with low power
consumption. In Extended Standby mode, both the main Oscillator and the Asynchro-
nous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is
a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega128 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
ATmega103 and
ATmega128
Compatibility
The ATmega128 is a highly complex microcontroller where the number of I/O locations
supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure back-
ward compatibility with the ATmega103, all I/O locations present in ATmega103 have
the same location in ATmega128. Most additional I/O locations are added in an
Extended I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM
space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD
instructions only, not by using IN and OUT instructions. The relocation of the internal
RAM space may still be a problem for ATmega103 users. Also, the increased number of
interrupt vectors might be a problem if the code uses absolute addresses. To solve
these problems, an ATmega103 compatibility mode can be selected by programming
the fuse M103C. In this mode, none of the functions in the Extended I/O space are in
use, so the internal RAM is located as in ATmega103. Also, the Extended Interrupt vec-
tors are removed.
4
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
The ATmega128 is 100% pin compatible with ATmega103, and can replace the
ATmega103 on current Printed Circuit Boards. The application note “Replacing
ATmega103 by ATmega128” describes what the user should be aware of replacing the
ATmega103 by an ATmega128.
ATmega103 Compatibility
Mode
By programming the M103C fuse, the ATmega128 will be compatible with the
ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. How-
ever, some new features in ATmega128 are not available in this compatibility mode,
these features are listed below:
•
One USART instead of two, Asynchronous mode only. Only the eight least
significant bits of the Baud Rate Register is available.
•
One 16 bits Timer/Counter with two compare registers instead of two 16-bit
Timer/Counters with three compare registers.
•
•
•
•
•
•
•
Two-wire serial interface is not supported.
Port C is output only.
Port G serves alternate functions only (not a general I/O port).
Port F serves as digital input only in addition to analog input to the ADC.
Boot Loader capabilities is not supported.
It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
The External Memory Interface can not release any Address pins for general I/O,
neither configure different wait-states to different External Memory Address
sections.
In addition, there are some other minor differences to make it more compatible to
ATmega103:
•
•
•
•
Only EXTRF and PORF exists in MCUCSR.
Timed sequence not required for Watchdog Time-out change.
External Interrupt pins 3 - 0 serve as level interrupt only.
USART has no FIFO buffer, so data overrun comes earlier.
Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in
ATmega128.
Pin Descriptions
VCC
Digital supply voltage.
Ground.
GND
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega128 as listed
on page 69.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
5
2467IS–AVR–09/03
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega128 as listed
on page 70.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the ATmega128 as listed on page
73. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not
tri-stated when a reset condition becomes active.
Port D (PD7..PD0)
Port E (PE7..PE0)
Port F (PF7..PF0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega128 as listed
on page 74.
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega128 as listed
on page 77.
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes
active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resis-
tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset
occurs.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input Port only.
Port G (PG4..PG0)
Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port G output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port G pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features.
6
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
The port G pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
In ATmega103 compatibility mode, these pins only serves as strobes signals to the
external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to
PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active,
even if the clock is not running. PG3 and PG4 are oscillator pins.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
19 on page 48. Shorter pulses are not guaranteed to generate a reset.
XTAL1
XTAL2
AVCC
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-
nected to VCC through a low-pass filter.
AREF
PEN
AREF is the analog reference pin for the A/D Converter.
PEN is a programming enable pin for the SPI Serial Programming mode. By holding this
pin low during a Power-on Reset, the device will enter the SPI Serial Programming
mode. PEN has no function during normal operation.
7
2467IS–AVR–09/03
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
($FF)
..
Reserved
Reserved
Reserved
UCSR1C
UDR1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
($9E)
($9D)
($9C)
($9B)
($9A)
($99)
($98)
($97)
($96)
UMSEL1
UPM11
UPM10
USBS1
UCSZ11
UCSZ10
UCPOL1
190
188
188
189
192
192
USART1 I/O Data Register
UCSR1A
UCSR1B
UBRR1L
UBRR1H
Reserved
Reserved
UCSR0C
Reserved
Reserved
Reserved
Reserved
UBRR0H
Reserved
Reserved
Reserved
TCCR3C
TCCR3A
TCCR3B
TCNT3H
TCNT3L
OCR3AH
OCR3AL
OCR3BH
OCR3BL
OCR3CH
OCR3CL
ICR3H
RXC1
TXC1
UDRE1
UDRIE1
FE1
DOR1
UPE1
U2X1
MPCM1
TXB81
RXCIE1
TXCIE1
RXEN1
TXEN1
UCSZ12
RXB81
USART1 Baud Rate Register Low
–
–
–
–
USART1 Baud Rate Register High
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
($95)
($94)
($93)
($92)
($91)
–
UMSEL0
UPM01
UPM00
USBS0
UCSZ01
UCSZ00
UCPOL0
190
192
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
($90)
($8F)
($8E)
($8D)
($8C)
–
–
–
–
USART0 Baud Rate Register High
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FOC3A
COM3A1
ICNC3
FOC3B
COM3A0
ICES3
FOC3C
COM3B1
–
–
–
–
–
135
130
134
136
136
136
136
137
137
137
137
137
137
($8B)
($8A)
($89)
($88)
($87)
($86)
($85)
($84)
($83)
($82)
($81)
($80)
($7F)
($7E)
COM3B0
WGM33
COM3C1
WGM32
COM3C0
CS32
WGM31
CS31
WGM30
CS30
Timer/Counter3 – Counter Register High Byte
Timer/Counter3 – Counter Register Low Byte
Timer/Counter3 – Output Compare Register A High Byte
Timer/Counter3 – Output Compare Register A Low Byte
Timer/Counter3 – Output Compare Register B High Byte
Timer/Counter3 – Output Compare Register B Low Byte
Timer/Counter3 – Output Compare Register C High Byte
Timer/Counter3 – Output Compare Register C Low Byte
Timer/Counter3 – Input Capture Register High Byte
Timer/Counter3 – Input Capture Register Low Byte
ICR3L
Reserved
Reserved
ETIMSK
ETIFR
–
–
–
–
–
–
–
–
–
–
–
–
OCIE3A
OCF3A
–
–
OCIE3B
OCF3B
–
–
TOIE3
TOV3
–
–
–
($7D)
($7C)
($7B)
($7A)
–
–
TICIE3
ICF3
–
OCIE3C
OCIE1C
138
139
–
–
–
–
OCF3C
OCF1C
Reserved
TCCR1C
OCR1CH
OCR1CL
Reserved
Reserved
Reserved
TWCR
–
–
–
–
FOC1A
FOC1B
FOC1C
–
–
–
135
136
136
($79)
($78)
($77)
($76)
($75)
Timer/Counter1 – Output Compare Register C High Byte
Timer/Counter1 – Output Compare Register C Low Byte
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
($74)
($73)
($72)
($71)
($70)
($6F)
($6E)
($6D)
($6C)
($6B)
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
205
207
207
206
205
39
TWDR
Two-wire Serial Interface Data Register
TWAR
TWA6
TWS7
TWA5
TWS6
TWA4
TWS5
TWA3
TWS4
TWA2
TWS3
TWA1
–
TWA0
TWGCE
TWPS0
TWSR
TWPS1
TWBR
Two-wire Serial Interface Bit Rate Register
Oscillator Calibration Register
OSCCAL
Reserved
XMCRA
XMCRB
Reserved
EICRA
–
–
–
–
–
SRW01
–
–
SRW00
XMM2
–
–
SRW11
XMM1
–
–
–
SRL2
SRL1
SRL0
29
31
XMBK
–
–
–
–
XMM0
–
–
–
–
–
($6A)
($69)
($68)
($67)
($66)
($65)
($64)
($63)
ISC31
ISC30
ISC21
ISC20
–
ISC11
–
ISC10
–
ISC01
–
ISC00
–
86
Reserved
SPMCSR
Reserved
Reserved
PORTG
DDRG
–
–
–
SPMIE
RWWSB
–
RWWSRE
–
BLBSET
–
PGWRT
–
PGERS
–
SPMEN
–
279
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTG4
DDG4
PING4
PORTF4
PORTG3
DDG3
PING3
PORTF3
PORTG2
DDG2
PING2
PORTF2
PORTG1
DDG1
PING1
PORTF1
PORTG0
DDG0
PING0
PORTF0
85
85
85
84
–
–
–
–
–
–
PING
($62)
PORTF
PORTF7
PORTF6
PORTF5
8
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
($61)
DDRF
Reserved
SREG
DDF7
–
DDF6
–
DDF5
–
DDF4
–
DDF3
–
DDF2
–
DDF1
–
DDF0
–
85
($60)
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
I
T
H
S
V
N
Z
C
9
12
SPH
SP15
SP7
SP14
SP6
SP13
SP5
XDIV5
–
SP12
SP4
SP11
SP3
SP10
SP2
SP9
SP8
SPL
SP1
SP0
12
XDIV
XDIVEN
–
XDIV6
–
XDIV4
–
XDIV3
–
XDIV2
–
XDIV1
–
XDIV0
RAMPZ0
ISC40
INT0
41
RAMPZ
EICRB
EIMSK
EIFR
12
ISC71
INT7
INTF7
OCIE2
OCF2
SRE
JTD
ISC70
INT6
INTF6
TOIE2
TOV2
SRW10
–
ISC61
INT5
INTF5
TICIE1
ICF1
SE
ISC60
INT4
INTF4
OCIE1A
OCF1A
SM1
ISC51
INT3
INTF3
OCIE1B
OCF1B
SM0
ISC50
INT2
INTF
TOIE1
TOV1
SM2
BORF
CS02
ISC41
INT1
INTF1
OCIE0
OCF0
IVSEL
EXTRF
CS01
87
88
INTF0
TOIE0
TOV0
IVCE
PORF
CS00
88
TIMSK
TIFR
105, 138, 158
105, 139, 159
29, 42, 60
51, 255
100
MCUCR
MCUCSR
TCCR0
TCNT0
OCR0
–
JTRF
COM00
WDRF
WGM01
FOC0
WGM00
COM01
Timer/Counter0 (8 Bit)
Timer/Counter0 Output Compare Register
102
102
ASSR
–
–
–
COM1B1
–
–
AS0
TCN0UB
COM1C0
CS12
OCR0UB
WGM11
CS11
TCR0UB
WGM10
CS10
103
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
ICR1H
ICR1L
COM1A1
ICNC1
COM1A0
ICES1
COM1B0
WGM13
COM1C1
WGM12
130
134
Timer/Counter1 – Counter Register High Byte
Timer/Counter1 – Counter Register Low Byte
136
136
Timer/Counter1 – Output Compare Register A High Byte
Timer/Counter1 – Output Compare Register A Low Byte
Timer/Counter1 – Output Compare Register B High Byte
Timer/Counter1 – Output Compare Register B Low Byte
Timer/Counter1 – Input Capture Register High Byte
Timer/Counter1 – Input Capture Register Low Byte
136
136
136
136
137
137
TCCR2
TCNT2
OCR2
FOC2
WGM20
COM21
COM20
WGM21
OCDR3
CS22
CS21
CS20
156
Timer/Counter2 (8 Bit)
158
Timer/Counter2 Output Compare Register
IDRD/
OCDR7
158
$22 ($42)
OCDR
OCDR6
OCDR5
OCDR4
OCDR2
OCDR1
OCDR0
252
$21 ($41)
$20 ($40)
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2B)
$0A ($2A)
$09 ($29)
$08 ($28)
$07 ($27)
$06 ($26)
$05 ($25)
$04 ($24)
$03 ($23)
$02 ($22)
WDTCR
SFIOR
EEARH
EEARL
EEDR
–
TSM
–
–
–
–
–
–
–
WDCE
WDE
WDP2
PUD
WDP1
PSR0
WDP0
53
–
–
ACME
PSR321
69, 106, 143, 227
EEPROM Address Register High
19
19
EEPROM Address Register Low Byte
EEPROM Data Register
20
EECR
–
–
–
–
EERIE
PORTA3
DDA3
EEMWE
PORTA2
DDA2
EEWE
PORTA1
DDA1
EERE
PORTA0
DDA0
20
PORTA
DDRA
PORTA7
DDA7
PORTA6
DDA6
PORTA5
DDA5
PORTA4
DDA4
83
83
PINA
PINA7
PINA6
PORTB6
DDB6
PINA5
PORTB5
DDB5
PINA4
PORTB4
DDB4
PINA3
PINA2
PINA1
PINA0
83
PORTB
DDRB
PORTB7
DDB7
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
83
83
PINB
PINB7
PINB6
PORTC6
DDC6
PINB5
PORTC5
DDC5
PINB4
PORTC4
DDC4
PINB3
PINB2
PINB1
PINB0
83
PORTC
DDRC
PINC
PORTC7
DDC7
PORTC3
DDC3
PORTC2
DDC2
PORTC1
DDC1
PORTC0
DDC0
83
83
PINC7
PINC6
PORTD6
DDD6
PINC5
PORTD5
DDD5
PINC4
PORTD4
DDD4
PINC3
PORTD3
DDD3
PINC2
PINC1
PINC0
PORTD0
DDD0
84
PORTD
DDRD
PIND
PORTD7
DDD7
PORTD2
DDD2
PORTD1
DDD1
84
84
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
84
SPDR
SPI Data Register
SPIF
168
168
166
188
188
189
192
227
243
244
246
246
84
SPSR
WCOL
SPE
–
–
–
–
–
SPI2X
SPR0
SPCR
SPIE
DORD
MSTR
CPOL
CPHA
SPR1
UDR0
USART0 I/O Data Register
UCSR0A
UCSR0B
UBRR0L
ACSR
RXC0
TXC0
UDRE0
UDRIE0
FE0
DOR0
UPE0
U2X0
MPCM0
TXB80
RXCIE0
TXCIE0
RXEN0
TXEN0
UCSZ02
RXB80
USART0 Baud Rate Register Low
ACD
REFS1
ADEN
ACBG
REFS0
ADSC
ACO
ADLAR
ADFR
ACI
MUX4
ADIF
ACIE
MUX3
ADIE
ACIC
MUX2
ADPS2
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
ADMUX
ADCSRA
ADCH
ADC Data Register High Byte
ADC Data Register Low byte
ADCL
PORTE
DDRE
PORTE7
DDE7
PORTE6
DDE6
PORTE5
DDE5
PORTE4
DDE4
PORTE3
DDE3
PORTE2
DDE2
PORTE1
DDE1
PORTE0
DDE0
84
9
2467IS–AVR–09/03
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
$01 ($21)
$00 ($20)
PINE
PINF
PINE7
PINF7
PINE6
PINF6
PINE5
PINF5
PINE4
PINF4
PINE3
PINF3
PINE2
PINF2
PINE1
PINF1
PINE0
PINF0
84
85
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
10
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
ADIW
SUB
SUBI
SBC
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
Rd ← Rd Rr
Z,N,V
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd ← Rd • ($FF - K)
Rd ← Rd + 1
Z,N,V
INC
Z,N,V
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
TST
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Z,N,V
CLR
Rd
Rd ← Rd Rd
Rd ← $FF
Z,N,V
SER
Rd
Set Register
None
MUL
MULS
MULSU
FMUL
FMULS
FMULSU
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
JMP
k
k
Direct Jump
PC ← k
3
RCALL
ICALL
CALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
k
Direct Subroutine Call
Subroutine Return
PC ← k
4
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1 / 2 / 3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N V= 0) then PC ← PC + k + 1
if (N V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
Rr, b
P, b
P, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
k
k
11
2467IS–AVR–09/03
Instruction Set Summary (Continued)
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRIE
BRID
k
k
Branch if Interrupt Enabled
Branch if Interrupt Disabled
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
1 / 2
1 / 2
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
-
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
LD
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
LD
LDD
LD
Rd ← (Z)
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
LD
LDD
LDS
ST
Rd ← (k)
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
ELPM
ELPM
ELPM
SPM
IN
(k) ← Rr
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Extended Load Program Memory
Extended Load Program Memory
Extended Load Program Memory and Post-Inc
Store Program Memory
In Port
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
R0 ← (RAMPZ:Z)
Rd ← (RAMPZ:Z)
Rd ← (RAMPZ:Z), RAMPZ:Z ← RAMPZ:Z+1
(Z) ← R1:R0
Rd, Z
Rd, Z+
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd
Rd ← STACK
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CBI
I/O(P,b) ← 0
None
LSL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Z
I
Clear Carry
C ← 0
Set Negative Flag
Clear Negative Flag
Set Zero Flag
N ← 1
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
I ← 1
CLI
I ← 0
I
SES
CLS
S ← 1
S
S
S ← 0
12
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
Instruction Set Summary (Continued)
Mnemonics
Operands
Description
Operation
Flags
#Clocks
SEV
CLV
SET
CLT
SEH
CLH
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
V
V
T
T
H
H
1
1
1
1
1
1
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
13
2467IS–AVR–09/03
Ordering Information
Speed (MHz)
Power Supply
Ordering Code
Package
Operation Range
8
2.7 - 5.5V
ATmega128L-8AC
ATmega128L-8MC
64A
Commercial
(0oC to 70oC)
64M1
ATmega128L-8AI
ATmega128L-8MI
64A
Industrial
(-40oC to 85oC)
64M1
16
4.5 - 5.5V
ATmega128-16AC
ATmega128-16MC
64A
Commercial
(0oC to 70oC)
64M1
ATmega128-16AI
ATmega128-16MI
64A
Industrial
(-40oC to 85oC)
64M1
Note:
1. The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
Package Type
64A
64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (MLF)
64M1
14
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
Packaging Information
64A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.30
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
14.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64A
B
R
15
2467IS–AVR–09/03
64M1
D
Marked Pin# 1 ID
E
SEATING PLANE
C
A1
TOP VIEW
A
0.08
C
L
Pin #1 Corner
SIDE VIEW
D2
1
2
3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.80
–
MAX
1.00
0.05
0.28
NOM
0.90
NOTE
SYMBOL
E2
A
A1
b
0.02
0.23
0.25
D
9.00 BSC
5.40
D2
E
5.20
5.20
0.35
5.60
5.60
0.45
9.00 BSC
5.40
e
b
E2
e
BOTTOM VIEW
0.50 BSC
0.40
L
Note: JEDEC Standard MO-220, Fig. 1, VMMD.
01/15/03
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm
Micro Lead Frame Package (MLF)
64M1
C
R
16
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
Erratas
The revision letter in this section refers to the revision of the ATmega128 device.
ATmega128 Rev. H
There are no errata for this revision of ATmega128. However, a proposal for solving
problems regarding the JTAG instruction IDCODE is presented below.
IDCODE masks data from TDI input
The public but optional JTAG instruction IDCODE is not implemented correctly
according to IEEE1149.1; a logic one is scanned into the shift register instead of the
TDI input while shifting the Device ID Register. Hence, captured data from the pre-
ceding devices in the boundary scan chain are lost and replaced by all-ones, and
data to succeeding devices are replaced by all-ones during Update-DR.
If ATmega128 is the only device in the scan chain, the problem is not visible.
Problem Fix / Workaround
Select the Device ID Register of the ATmega128 (Either by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller) to read
out the contents of its Device ID Register and possibly data from succeeding
devices of the scan chain. Note that data to succeeding devices cannot be entered
during this scan, but data to preceding devices can. Issue the BYPASS instruction
to the ATmega128 to select its Bypass Register while reading the Device ID Regis-
ters of preceding devices of the boundary scan chain. Never read data from
succeeding devices in the boundary scan chain or upload data to the succeeding
devices while the Device ID Register is selected for the ATmega128. Note that the
IDCODE instruction is the default instruction selected by the Test-Logic-Reset state
of the TAP-controller.
Alternative Problem Fix / Workaround
If the Device IDs of all devices in the boundary scan chain must be captured simul-
taneously (for instance if blind interrogation is used), the boundary scan chain can
be connected in such way that the ATmega128 is the fist device in the chain.
Update-DR will still not work for the succeeding devices in the boundary scan chain
as long as IDCODE is present in the JTAG Instruction Register, but the Device ID
registered cannot be uploaded in any case.
ATmega128 Rev. G
There are no errata for this revision of ATmega128. However, a proposal for solving
problems regarding the JTAG instruction IDCODE is presented below.
IDCODE masks data from TDI input
The public but optional JTAG instruction IDCODE is not implemented correctly
according to IEEE1149.1; a logic one is scanned into the shift register instead of the
TDI input while shifting the Device ID Register. Hence, captured data from the pre-
ceding devices in the boundary scan chain are lost and replaced by all-ones, and
data to succeeding devices are replaced by all-ones during Update-DR.
If ATmega128 is the only device in the scan chain, the problem is not visible.
Problem Fix / Workaround
Select the Device ID Register of the ATmega128 (Either by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller) to read
out the contents of its Device ID Register and possibly data from succeeding
devices of the scan chain. Note that data to succeeding devices cannot be entered
during this scan, but data to preceding devices can. Issue the BYPASS instruction
to the ATmega128 to select its Bypass Register while reading the Device ID Regis-
ters of preceding devices of the boundary scan chain. Never read data from
17
2467IS–AVR–09/03
succeeding devices in the boundary scan chain or upload data to the succeeding
devices while the Device ID Register is selected for the ATmega128. Note that the
IDCODE instruction is the default instruction selected by the Test-Logic-Reset state
of the TAP-controller.
Alternative Problem Fix / Workaround
If the Device IDs of all devices in the boundary scan chain must be captured simul-
taneously (for instance if blind interrogation is used), the boundary scan chain can
be connected in such way that the ATmega128 is the fist device in the chain.
Update-DR will still not work for the succeeding devices in the boundary scan chain
as long as IDCODE is present in the JTAG Instruction Register, but the Device ID
registered cannot be uploaded in any case.
ATmega128 Rev. F
There are no errata for this revision of ATmega128. However, a proposal for solving
problems regarding the JTAG instruction IDCODE is presented below.
IDCODE masks data from TDI input
The public but optional JTAG instruction IDCODE is not implemented correctly
according to IEEE1149.1; a logic one is scanned into the shift register instead of the
TDI input while shifting the Device ID Register. Hence, captured data from the pre-
ceding devices in the boundary scan chain are lost and replaced by all-ones, and
data to succeeding devices are replaced by all-ones during Update-DR.
If ATmega128 is the only device in the scan chain, the problem is not visible.
Problem Fix / Workaround
Select the Device ID Register of the ATmega128 (Either by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller) to read
out the contents of its Device ID Register and possibly data from succeeding
devices of the scan chain. Note that data to succeeding devices cannot be entered
during this scan, but data to preceding devices can. Issue the BYPASS instruction
to the ATmega128 to select its Bypass Register while reading the Device ID Regis-
ters of preceding devices of the boundary scan chain. Never read data from
succeeding devices in the boundary scan chain or upload data to the succeeding
devices while the Device ID Register is selected for the ATmega128. Note that the
IDCODE instruction is the default instruction selected by the Test-Logic-Reset state
of the TAP-controller.
Alternative Problem Fix / Workaround
If the Device IDs of all devices in the boundary scan chain must be captured simul-
taneously (for instance if blind interrogation is used), the boundary scan chain can
be connected in such way that the ATmega128 is the fist device in the chain.
Update-DR will still not work for the succeeding devices in the boundary scan chain
as long as IDCODE is present in the JTAG Instruction Register, but the Device ID
registered cannot be uploaded in any case.
18
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
Datasheet Change
Log for ATmega128
Please note that the referring page numbers in this section are referred to this docu-
ment. The referring revision in this section are referring to the document revision.
Changes from Rev.
2467H-02/03 to Rev.
2467I-09/03
1. Updated note in “XTAL Divide Control Register – XDIV” on page 41.
2. Updated “JTAG Interface and On-chip Debug System” on page 46.
3. Updated values for VBOT (BODLEVEL = 1) in Table 19 on page 48.
4. Updated “Test Access Port – TAP” on page 247 regarding JTAGEN.
5. Updated description for the JTD bit on page 256.
6. Added a note regarding JTAGEN fuse to Table 119 on page 290.
7. Updated RPU values in “DC Characteristics” on page 321.
8. Added a proposal for solving problems regarding the JTAG instruction
IDCODE in “Erratas” on page 17.
Changes from Rev.
2467G-09/02 to Rev.
2467H-02/03
1. Corrected the names of the two Prescaler bits in the SFIOR Register.
2. Added Chip Erase as a first step under “Programming the Flash” on page 318
and “Programming the EEPROM” on page 319.
3. Removed reference to the “Multipurpose Oscillator” application note and the
“32 kHz Crystal Oscillator” application note, which do not exist.
4. Corrected OCn waveforms in Figure 52 on page 122.
5. Various minor Timer1 corrections.
6. Added information about PWM symmetry for Timer0 and Timer2.
7. Various minor TWI corrections.
8. Added reference to Table 125 on page 293 from both SPI Serial Programming
and Self Programming to inform about the Flash Page size.
9. Added note under “Filling the Temporary Buffer (Page Loading)” on page 282
about writing to the EEPROM during an SPM Page load.
10. Removed ADHSM completely.
11. Added section “EEPROM Write During Power-down Sleep Mode” on page 23.
12. Updated drawings in “Packaging Information” on page 15.
Changes from Rev.
2467F-09/02 to Rev.
2467G-09/02
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
19
2467IS–AVR–09/03
Changes from Rev.
2467E-04/02 to Rev.
2467F-09/02
1. Added 64-pad MLF Package and updated “Ordering Information” on page 14.
2. Added the section “Using all Locations of External Memory Smaller than 64
KB” on page 31.
3. Added the section “Default Clock Source” on page 35.
4. Renamed SPMCR to SPMCSR in entire document.
5. When using external clock there are some limitations regards to change of
frequency. This is descried in “External Clock” on page 40 and Table 132,
“External Clock Drive,” on page 323.
6. Added a sub section regarding OCD-system and power consumption in the
section “Minimizing Power Consumption” on page 45.
7. Corrected typo (WGM-bit setting) for:
“Fast PWM Mode” on page 95 (Timer/Counter0).
“Phase Correct PWM Mode” on page 97 (Timer/Counter0).
“Fast PWM Mode” on page 150 (Timer/Counter2).
“Phase Correct PWM Mode” on page 152 (Timer/Counter2).
8. Corrected Table 81 on page 192 (USART).
9. Corrected Table 103 on page 261 (Boundary-Scan)
10. Updated Vil parameter in “DC Characteristics” on page 321.
Changes from Rev.
2467D-03/02 to Rev.
2467E-04/02
1. Updated the Characterization Data in Section “ATmega128 Typical Character-
istics – Preliminary Data” on page 333.
2. Updated the following tables:
Table 19 on page 48, Table 20 on page 52, Table 68 on page 157, Table 103 on
page 261, and Table 136 on page 327.
3. Updated Description of OSCCAL Calibration Byte.
In the data sheet, it was not explained how to take advantage of the calibration
bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following
sections:
Improved description of “Oscillator Calibration Register – OSCCAL” on page 39 and
“Calibration Byte” on page 291.
Changes from Rev.
2467C-02/02 to Rev.
2467D-03/02
1. Added more information about “ATmega103 Compatibility Mode” on page 5.
2. Updated Table 2, “EEPROM Programming Time,” on page 21.
3. Updated typical Start-up Time in Table 7 on page 35, Table 9 and Table 10 on
page 37, Table 12 on page 38, Table 14 on page 39, and Table 16 on page 40.
4. Updated Table 22 on page 54 with typical WDT Time-out.
20
ATmega128(L)
2467IS–AVR–09/03
ATmega128(L)
5. Corrected description of ADSC bit in “ADC Control and Status Register A –
ADCSRA” on page 244.
6. Improved description on how to do a polarity check of the ADC diff results in
“ADC Conversion Result” on page 241.
7. Corrected JTAG version numbers in “JTAG Version Numbers” on page 254.
8. Improved description of addressing during SPM (usage of RAMPZ) on
“Addressing the Flash During Self-Programming” on page 280, “Performing
Page Erase by SPM” on page 282, and “Performing a Page Write” on page
282.
9. Added not regarding OCDEN Fuse below Table 119 on page 290.
10. Updated Programming Figures:
Figure 135 on page 292 and Figure 144 on page 304 are updated to also reflect that
AVCC must be connected during Programming mode. Figure 139 on page 299
added to illustrate how to program the fuses.
11. Added
a
note regarding usage of the PROG_PAGELOAD and
PROG_PAGEREAD instructions on page 310.
12. Added Calibrated RC Oscillator characterization curves in section
“ATmega128 Typical Characteristics – Preliminary Data” on page 333.
13. Updated “Two-wire Serial Interface” section.
More details regarding use of the TWI Power-down operation and using the TWI as
master with low TWBRR values are added into the data sheet. Added the note at
the end of the “Bit Rate Generator Unit” on page 203. Added the description at the
end of “Address Match Unit” on page 204.
14. Added a note regarding usage of Timer/Counter0 combined with the clock.
See “XTAL Divide Control Register – XDIV” on page 41.
Changes from Rev.
2467B-09/01 to Rev.
2467C-02/02
1. Corrected Description of Alternate Functions of Port G
Corrected description of TOSC1 and TOSC2 in “Alternate Functions of Port G” on
page 81.
2. Added JTAG Version Numbers for rev. F and rev. G
Updated Table 100 on page 254.
3
Added Some Preliminary Test Limits and Characterization Data
Removed some of the TBD's in the following tables and pages:
Table 19 on page 48, Table 20 on page 52, “DC Characteristics” on page 321,
Table 132 on page 323, Table 135 on page 325, and Table 136 on page 327.
4. Corrected “Ordering Information” on page 14.
5. Added some Characterization Data in Section “ATmega128 Typical Character-
istics – Preliminary Data” on page 333.
21
2467IS–AVR–09/03
6. Removed Alternative Algortihm for Leaving JTAG Programming Mode.
See “Leaving Programming Mode” on page 318.
7. Added Description on How to Access the Extended Fuse Byte Through JTAG
Programming Mode.
See “Programming the Fuses” on page 320 and “Reading the Fuses and Lock Bits”
on page 320.
22
ATmega128(L)
2467IS–AVR–09/03
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